Address allocation device, power distribution cabinet, address allocation method and storage medium

Abstract

The embodiment of the invention provides an address allocation device, a power distribution cabinet, an address allocation method and a storage medium. The address allocation apparatus includes: a gateway configured to generate an address signal enabling address allocation; the address distribution line is coupled to the gateway to receive the address signal, and a plurality of switches are arranged in the address distribution line; a plurality of connection units arranged in series along the address distribution line and each adapted to be connected to one bus device, each of the plurality of switches being located within one of the plurality of connection units, each of the plurality of connection units further adapted to: couple the address distribution line to the bus device, an on-off state of a switch located in the connection unit is controlled according to a switch control signal from a bus device to which the connection unit is connected so as to control transmission of an address signal to a downstream connection unit. According to the embodiment of the invention, the address of the bus equipment can be quickly allocated, so that the debugging and maintenance time of a system can be shortened.

Description

Technical Field

[0001] Example embodiments of the present disclosure generally relate to the field of electrical equipment, and in particular, to an address allocation device, a power distribution cabinet, an address allocation method, and a storage medium. Background Art

[0002] In a fieldbus-based device communication system, each device needs to have a unique identification number, that is, a communication address. The purpose of this design is to ensure that devices can communicate and interact accurately. By assigning a unique communication address to each device, the system can easily identify and locate the bus device and send instructions to it or obtain data. The existence of this independent identification enables the system to achieve accurate and reliable point-to-point or many-to-many communication. Summary of the invention

[0003] Embodiments of the present disclosure provide an address allocation device, a power distribution cabinet, an address allocation method, and a storage medium.

[0004] In a first aspect of the present disclosure, an address allocation device is provided. The device includes: a gateway configured to generate an address signal enabling address allocation; an address allocation line coupled to the gateway to receive the address signal, wherein a plurality of switches are arranged in the address allocation line; a plurality of connection units arranged in series along the address allocation line and respectively adapted to be connected to a bus device, wherein each of the plurality of switches is located in one of the plurality of connection units, and each of the plurality of connection units is further adapted to: couple the address allocation line to the bus device to which the connection unit is connected, and control the on / off state of the switch located in the connection unit among the plurality of switches according to a switch control signal from the bus device to which the connection unit is connected, so as to control the transmission of the address signal to a downstream connection unit among the plurality of connection units, wherein the downstream connection unit is located downstream of the connection unit relative to the gateway.

[0005] In some embodiments of the first aspect, each connection unit among the multiple connection units is further adapted to: in response to the switch control signal being in a first control signal, place the switch within the connection unit in an open state to prevent the address signal from being transmitted to a downstream connection unit; and in response to the switch control signal being in a second control signal different from the first control signal, place the switch within the connection unit in a closed state to allow the address signal to be transmitted to the downstream connection unit.

[0006] In some embodiments of the first aspect, each switch of the plurality of switches is a normally closed switch, the second control signal maintains the normally closed switch in a closed state, and the first control signal opens the normally closed switch.

[0007] In some embodiments of the first aspect, the apparatus further comprises: a communication data line connected to the gateway and connected in parallel with the address allocation line, and wherein each connection unit of the plurality of connection units is further adapted to couple the communication data line to a bus device to which the connection unit is connected.

[0008] In some embodiments of the first aspect, the gateway is further configured to: send the first address to be assigned through the communication data line when the address signal is valid; and send the second address to be assigned through the communication data line in response to determining that the first address has been assigned.

[0009] In some embodiments of the first aspect, the communication data line includes: a transmit data line adapted to transmit data from the gateway; and a receive data line adapted to transmit data to the gateway.

[0010] In a second aspect of the present disclosure, a power distribution cabinet is provided. The power distribution cabinet comprises: an address allocation device according to the first aspect; and at least one bus device, each of the at least one bus device is connected to a connection unit among a plurality of connection units, and is configured to set a switch control signal provided to the connection unit to which the bus device is connected based on the address allocation state of the bus device.

[0011] In some embodiments of the second aspect, each bus device in at least one bus device is further configured to: in response to the bus device not being assigned an address by the gateway, set the switch control signal to a first control signal so that the switch in the connection unit to which it is connected is in an open state; and in response to the bus device being assigned an address by the gateway, set the switch control signal to a second control signal different from the first control signal so that the switch in the connection unit to which it is connected is in a closed state.

[0012] In some embodiments of the second aspect, each bus device in the at least one bus device is further configured to: in response to the bus device having a preset address, set the switch control signal to the first control signal.

[0013] In some embodiments of the second aspect, each of the at least one bus device is further configured to: in response to receiving an address signal via a connection unit to which the bus device is connected, perform address allocation for the bus device according to communication with a gateway.

[0014] In some embodiments of the second aspect, each bus device in at least one bus device is further configured to: receive an address to be assigned from a gateway via the connection unit to which it is connected; set the bus device to have the address in response to receiving the address signal; and send an affirmative reply to the gateway via the connection unit to which it is connected that the address has been assigned.

[0015] In a third aspect of the present disclosure, an address allocation method is provided. The address allocation method includes: obtaining an address allocation state, the address allocation state indicating whether a bus device is allocated an address by a gateway; and based on the address allocation state, setting a switch control signal provided to a connection unit to which the bus device is connected, the switch control signal being used to control the on / off state of a switch in the connected connection unit to control the transmission of an address signal generated by the gateway to a downstream connection unit along an address allocation line, wherein the downstream connection unit is arranged in series with the connected connection unit along the address allocation line and is located downstream of the connected connection unit relative to the gateway.

[0016] In some embodiments of the third aspect, setting a switch control signal provided to a connection unit to which a bus device is connected includes: in response to the bus device not being assigned an address by a gateway, setting the switch control signal to a first control signal so that a switch in the connection unit to which the bus device is connected is in an open state; and in response to the bus device being assigned an address by a gateway, setting the switch control signal to a second control signal different from the first control signal so that the switch in the connection unit to which the bus device is connected is in a closed state.

[0017] In some embodiments of the third aspect, setting a switch control signal provided to a connection unit to which the bus device is connected includes: in response to the bus device having a preset address, setting the switch control signal to a first control signal.

[0018] In some embodiments of the third aspect, the address allocation method further includes: in response to receiving an address signal via a connection unit to which the bus device is connected, performing address allocation for the bus device according to communication with a gateway.

[0019] In some embodiments of the third aspect, performing address allocation for a bus device based on communication with a gateway includes: receiving an address to be allocated from the gateway via a connection unit to which it is connected; setting the bus device to have an address in response to receiving the address signal; and sending an affirmative reply to the gateway via the connection unit to which it is connected that the address has been allocated.

[0020] In a fourth aspect of the present disclosure, a machine-readable storage medium is provided, wherein a program is stored on the machine-readable storage medium, and the program can be executed by a processor to implement the method of the third aspect.

[0021] It will be understood from the following description that, according to an embodiment of the present disclosure, a method for automatically allocating a location-dependent bus address is provided for a bus device. The on-off state of a switch in a connection unit is controlled according to a switch control signal from the bus device, thereby automatically allocating an address to the bus device. In this way, the address allocation and topology of the bus device can be constructed quickly and efficiently. This greatly shortens the debugging and maintenance time of the system. Other benefits will be described below in conjunction with the corresponding embodiments.

[0022] It should be understood that the contents described in this content section are not intended to limit the key features or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein:

[0024] Figure 1 A schematic diagram showing a structure of a part of a power distribution cabinet including an address allocation device and a bus device according to some embodiments of the present disclosure is shown;

[0025] Figure 2A A schematic diagram of a topological structure of a power distribution cabinet according to some embodiments of the present disclosure is shown;

[0026] Figure 2B A schematic diagram of bus composition in an address allocation device according to some embodiments of the present disclosure is shown;

[0027] Figure 2C A schematic diagram of a connection unit according to some embodiments of the present disclosure is shown;

[0028] FIG. 3A to FIG. 3D A schematic diagram illustrating an example process of address allocation according to some embodiments of the present disclosure; and

[0029] Figure 4 A flow chart illustrating an example method of address allocation according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0030] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0031] In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may be included below. The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may be included below.

[0032] As briefly mentioned above, bus devices need to have unique communication addresses to achieve reliable communication. In some address allocation schemes, the communication address of each bus device is specified by manual intervention or operation, such as through physical switches, dip switches, adjustment knobs, human-machine interface (HMI, for example, using a touch screen, input device, etc.) menu settings, etc. However, when the number of bus devices is large, a lot of manpower is required to set the address.

[0033] In other address allocation schemes, an automatic address allocation mechanism based on bus data interaction is defined through the bus protocol, and addresses are allocated to bus devices based on such a mechanism. However, such a mechanism depends on a specific protocol, and the allocated addresses have certain uncertainties. It is difficult to ensure that the address allocated to the same bus device is the same each time, which brings certain troubles to the upper system in identifying the bus device.

[0034] In the power distribution system, especially the low-voltage power distribution system, the bus devices are located in the dedicated distribution cabinet in the low-voltage power distribution system. The location of the bus devices in the distribution cabinet is fixed. Such bus devices are connected using the fieldbus, and then the gateway performs protocol conversion and connects to the edge control system. The edge control system usually needs to establish a virtual model of the bus devices in the distribution cabinet so that users can match the virtual model with the actual bus devices. Therefore, it becomes very valuable to assign communication addresses based on the device location and automatically and quickly establish communication connections.

[0035] In order to solve or at least partially solve the problem of address allocation of bus devices, an embodiment of the present disclosure provides an address allocation device and an allocation scheme thereof. In the address allocation device, the on-off state of the switch in the connection unit is controlled according to the switch control signal from the bus device, so as to achieve automatic address allocation for the bus device.

[0036] According to an embodiment of the present disclosure, an address allocation device includes a gateway configured to generate an address signal enabling address allocation. The address allocation device also includes an address allocation line coupled to the gateway to receive the address signal. A plurality of switches are provided in the address allocation line. The address allocation device also includes a plurality of connection units, which are arranged in series along the address allocation line and are respectively suitable for connecting to a bus device. Each of the plurality of switches is located in one of the plurality of connection units. Each connection unit couples the address allocation line to the bus device to which the connection unit is connected, and controls the on-off state of the switch located in the connection unit among the plurality of switches according to a switch control signal from the bus device to which the connection unit is connected, so as to control the transmission of the address signal to the downstream connection unit of the connection unit. The downstream connection unit is located downstream of the connection unit relative to the gateway. In this way, the address allocation and topology of the bus device can be constructed quickly and efficiently. This greatly shortens the debugging and maintenance time of the system.

[0037] Some example embodiments of the present disclosure will be described below with reference to the accompanying drawings. Please note that in some descriptions of the embodiments, certain specific values ​​may be involved in order to better help readers understand. These values ​​are exemplary and may vary according to specific application scenarios, and do not limit the scope of the present disclosure in any way.

[0038] The following will be combined Figure 1 A schematic diagram of a power distribution cabinet including an address allocation device according to some embodiments of the present disclosure is described, combined with Figure 2A and Figure 2B To describe an example topology of a power distribution cabinet including an address distribution device, and in combination FIG. 3A to FIG. 3D To describe an example process of address allocation.

[0039] First reference Figure 1 According to some embodiments of the present disclosure, the address allocation device may be implemented in the power distribution cabinet 100. The address allocation device may include a plurality of connection units 120. The connection unit 120 may include, for example, a slot, an interface, or a port to connect to the bus device 110. The bus device 110 may include various suitable devices required in the power distribution cabinet. In some embodiments, the bus device 110 may be implemented in a drawer form, such as Figure 1 As shown, it can also be called a drawer. Correspondingly, the power distribution cabinet 100 can also be called a drawer cabinet. For example, in a low-voltage power distribution system, the address allocation device can be arranged in the low-voltage power distribution cabinet.

[0040] The plurality of connection units 120, for example, constitute a part of a backplane connector. The plurality of bus devices 110 are physically connected together through the backplane connector so that the bus devices 110 can share power and data signals. In addition, the backplane connector also provides mechanical stability and reliability, ensuring that each bus device is correctly inserted and in good contact.

[0041] The address allocation device may also include a gateway ( Figure 1 (not shown). The gateway may be implemented by hardware devices or software and is used for functions such as address allocation and conversion, data processing and analysis, protocol conversion, and routing selection.

[0042] In some embodiments, the power distribution cabinet 100 may further include a housing, a guide rail, or a partition. The housing is made of, for example, metal or synthetic material to protect the bus device 110 and the connection unit 120 from physical damage, dust, moisture, and other environmental factors. The guide rail is made of, for example, steel so that the bus device 110 can be smoothly pushed in and out. Figure 1 The internal space (not shown) is made of metal or synthetic material, for example, and is used to divide and organize the internal space so as to better accommodate the bus device 110.

[0043] It should be understood that Figure 1 The structure of the power distribution cabinet in which the address distribution device can be arranged is only exemplary and is not intended to limit the scope of the present disclosure. In the embodiments of the present disclosure, the power distribution cabinet can have any suitable structure.

[0044] Figure 2A and Figure 2B A schematic diagram of the topology structure of the address allocation device 201 according to some embodiments of the present disclosure is shown. The address allocation device 201 includes a gateway 210, a plurality of bus devices 110 (such as bus device 110-1, bus device 110-2, ..., bus device 110-4, which may be collectively or individually referred to as bus devices 110), a plurality of connection units 120 (such as connection unit 120-1, connection unit 120-2, ..., connection unit 120-N, which may be collectively or individually referred to as connection unit 120), and a bus 220 coupled to the gateway 210.

[0045] A plurality of connection units 120 are arranged in series along the bus 220 and are respectively suitable for connecting to one bus device 110. For example, the connection unit 120-1 is connected to the bus device 110-1, the connection device 120-2 is connected to the bus device 110-2, the connection unit 120-3 is connected to the bus device 110-3, and so on. These connection units 120 are connected in series through the bus 220, thereby forming a T-type topology with the bus device 110. In an embodiment of the present disclosure, the connection unit 120 is suitable for connecting to the bus device 110, but in some cases, it is not required that each connection unit 120 is connected to the bus device 110. It will be understood from the description below that in some embodiments, when one or more connection units 120 are not connected to any bus device 110 (for example, in Figure 2A In the case that the connection unit 120-4 is not connected to the bus device 110 or the bus device 110 to which it is connected fails, the address allocation device or the power distribution cabinet according to the disclosed embodiment can operate normally.

[0046] refer to Figure 2A , the gateway 210 is configured to generate an address signal. Such an address signal is used to enable address allocation. The address signal can be any suitable type of signal, and the embodiments of the present disclosure are not limited in this respect. For example, when the address signal is at a high level, the gateway 210 enters an address allocation state, so that a communication address (hereinafter referred to as the address) can be allocated to the bus device 110. Upon receiving the address signal, the bus device 120 sets the address according to the communication with the gateway 210. Exemplarily, the gateway 210 can be a motor control center (MCC) head device.

[0047] refer to Figure 2B The bus 220 includes an address allocation line 222. The address allocation line 222 is coupled to the gateway 210 so as to receive an address signal. In this case, the connection units 120 are arranged in series along the address allocation line 222.

[0048] A plurality of switches 228 (such as switch 228-1, switch 228-2, ..., switch 228-N, which may be collectively or individually referred to as 228) are provided in the address allocation line 222. The plurality of switches 228 are respectively arranged in a plurality of connection units 120, that is, one switch 228 is located in one connection unit 120.

[0049] The connection unit 120 is configured to couple the address allocation line 222 to the bus device 110 , and control the on-off state of the switch 228 according to a switch control signal from the bus device 110 .

[0050] exist Figure 2BIn the example of FIG. 1 , the gateway 210 includes an address port Addr. The bus device 110 includes an address port Addr and a control port Imhib. The address port Addr of each bus device 110 and the address port Addr of the gateway 210 are connected to the address allocation line 222. Accordingly, Figure 2C As shown, the connection unit 120 includes an address port Addr to couple the address port Addr of the bus device 110 to the address allocation line 220. The control port Imhib of each bus device 110 is respectively connected to the address allocation line 220 via the control port Imhib of the connection unit 120 (such as Figure 2C As shown in FIG. 1 , the switch 228 is coupled to the connected connection unit 110 to control the on / off state of the switch 228 through a switch control signal.

[0051] As an example, the bus device 110-1 is always connected to the gateway 210 through the address allocation line 222, so that the address signal from the gateway 210 can be received. If the bus device 110-1 controls the switch 228-1 to be closed through the switch control signal, the bus device 110-2 can be connected to the gateway 210 through the address allocation line 222 via the switch 228-1, so that the address signal from the gateway 210 can be received. If the bus device 110-2 controls the switch 228-2 to be closed through the switch control signal, the bus device 110-3 can be connected to the gateway 210 through the address allocation line 222 via the switch 228-2 and the switch 228-1, so that the address signal from the gateway 210 can be received. In this way, the address signal sent by the gateway 210 can be controlled to be transmitted to the downstream connection unit 120 along the address allocation line 222.

[0052] In an embodiment of the present disclosure, a downstream connection unit 120 of a connection unit 120 is located downstream of the connection unit 120 relative to the gateway 210 (i.e., the signal source) on the transmission path of the address signal. For example, connection units 120-2 to 120-N are downstream connection units of connection unit 120-1. When switch 228-1 is closed, the address signal can be transmitted to connection unit 120-2 via connection unit 120-1. Connection units 120-3 to 120-N are downstream connection units of connection unit 120-2. When both switch 228-1 and switch 228-2 are closed, the address signal continues to be transmitted to connection unit 120-3 via connection unit 120-1 and connection unit 120-2. And so on.

[0053] In some embodiments, if the switch control signal is a certain control signal (also referred to as a first control signal), the control switch 228 is in an open state to prevent the address signal from being transmitted to the downstream connection unit. If the switch control signal is another control signal (also referred to as a second control signal), the control switch 228 is in a closed state to allow the address signal to be transmitted to the downstream connection unit. That is, the first control signal can control the switch 228 to be opened, and the second control signal different from the first control signal can control the switch 228 to be closed.

[0054] The switch control signal may be a signal of any suitable type. For example, the switch control signal may be a pulse signal, and accordingly, the first control signal and the second control signal may have different pulse waveforms. For another example, the first control signal and the second control signal may have different levels.

[0055] As an example, the level of the switch control signal for controlling a certain type of switch 228 includes a high level and a low level. If the switch control signal is at a high level, the switch is disconnected, and the address signal can only be transmitted to the connection unit 120 where the switch 228 is located. If the switch control signal is at a low level, the switch is closed, and the address signal can continue to be transmitted to another connection unit 120 in the downstream direction via the connection unit 120 where the switch 228 is located.

[0056] In some embodiments, switch 228 may be a normally closed switch. Figure 2A In the example, the address allocation device 201 includes multiple connection units 120. In some cases, these connection units 120 are not all connected to the bus device 110, for example, the connection unit 120-4. When the bus device 110 is not connected, the switch 228 in the connection unit 120-4 remains in a closed state, and the address signal can continue to be transmitted to the connection unit 120 in the downstream direction via the connection unit 120-4. That is, when the connection unit 120 is connected to the bus device 110, the address signal can be controlled to be transmitted to each connection unit 120 in sequence, so that the gateway 210 can allocate addresses to the bus devices 110 coupled to the connection unit 120. When the connection unit 120 is not connected to the bus device 110, since there is no need to perform address allocation, it is sufficient to ensure that the address signal passes directly.

[0057] In this embodiment, by using a normally closed switch, it is not required that each connection unit 120 is connected to the bus device 110, and the address allocation can be ensured to be carried out normally. This improves the flexibility of the arrangement of each bus device 110 in the power distribution cabinet. In addition, in the case of a failure of the connected bus device 110, the address allocation and subsequent communication can also be carried out normally. In this way, the reliability of the address allocation device and the power distribution cabinet can be improved.

[0058] In some embodiments, in order to transmit address data to the bus device 110, the bus 220 in the address allocation device 110 also includes a communication data line. One end of the communication data line is connected to the gateway 210 and is connected in parallel with the address allocation line 222. The connection unit 120 couples such a communication data line to the bus device 110 connected thereto. Thus, the gateway 210 can establish a communication link with each bus device 110 through the communication data line. The on-off state of the switch 228 in each connection unit 120 is controlled so that when the bus device 110 is connected to the address allocation line 222 in turn, the gateway 210 can allocate addresses to these bus devices 110 in turn.

[0059] In some embodiments, reference Figure 2B , the communication data line may include a transmission data line 226 and a reception data line 224. One end of the transmission data line 226 is connected to the transmission port Tx of the gateway 210, and is coupled to the transmission port Tx of each bus device 110 via the transmission port Tx of each connection unit 120. Thus, the gateway 210 can send data, such as an address to be assigned, to each bus device 110 via the transmission data line 226. One end of the reception data line 224 is connected to the reception port Rx of the gateway 210, and is coupled to the reception port Rx of each bus device 110 via the reception port Rx of each connection unit 120. Thus, the gateway 210 can receive data from each bus device 110 via the reception data line 224, such as a reply to the address assignment.

[0060] In some embodiments, when the address signal is valid (for example, the address signal is at a preset level, the address signal has a predetermined waveform, or the gateway 210 sends an address signal), the gateway 210 may send the address to be assigned, also referred to as the first address, through the send data line 226 in the communication data line. When it is determined that the address has been assigned, the next address to be assigned, also referred to as the second address, is sent through the send data line 226 in the communication data line. And so on, until addresses are assigned to all bus devices 110 connected to the address allocation line 222. For example, the gateway 210 broadcasts address data (for example, including the first address to be assigned) to each bus device 110 through the send data line 226. In this case, all bus devices 110 can receive the address data, but only the bus device 110 that is connected to the address allocation line 222 and receives the address signal can respond, such as setting its own address, sending an affirmative reply, etc. The following will refer to FIG. 3A to FIG. 3D Describe the process of address allocation.

[0061] FIG. 3A to FIG. 3DA schematic diagram of an example process of address allocation according to some embodiments of the present disclosure is shown. In this example, all bus devices 110 are set with a default address. When the address allocation device 201 is initially powered on, each bus device 110 controls the switch 228 to be disconnected through a switch control signal in response to having a default address, that is, in response to not being assigned an address by the gateway 210. For example, all bus devices 110 can assert a switch control signal to prohibit the transmission of an address signal.

[0062] exist Figure 3A In the example, the address signal is valid (for example, the gateway 210 sets the address signal to a high level or the address signal has a predetermined waveform), and the gateway 210 is in an address allocation state. At this time, only the bus device 110-1 can receive the address signal of the gateway 210, and the bus devices 110-2 to 110-N are all disconnected from the gateway 210 and cannot receive the address signal.

[0063] exist Figure 3B In the example of , the gateway 210 broadcasts the first address to be assigned to each bus device 110 via the transmit data line 226. Since the bus device 110-1 can receive the address signal of the gateway 210, it knows that the gateway 210 is in the address assignment state. The bus device 110-1 can set the first address received from the transmit data line 226 as its own address, and send a positive reply to the gateway 210 via the receive data line 224 that the first address has been assigned.

[0064] exist Figure 3C In the example, since the address has been assigned, the bus device 110-1 controls the switch 228-1 to close through the switch control signal so that the address signal is transmitted downstream. For example, the bus device 110-1 can release the switch control signal.

[0065] Accordingly, after receiving the affirmative reply that the first address has been assigned, the gateway 210 broadcasts the second address to be assigned through the sending data line 226. At this time, both the bus device 110-1 and the bus device 110-2 can receive the address signal of the gateway 210. Since the bus device 110-1 has set the first address, it will no longer compete for the second address. For example, the bus device 110-1 compares the current address with the default address, and if it is not the default address, it determines that it has set a valid address. The bus device 110-2 can set the second address received from the sending data line 226 to its own address, and send an affirmative reply that the second address has been assigned to the gateway 210 through the receiving data line 224. Since the address has been assigned, the bus device 110-2 controls the switch 228-2 to be closed through the switch control signal, so that the address signal is transmitted in the downstream direction. For example, the bus device 110-2 can release the switch control signal.

[0066] Repeat the above example process, the gateway 210 sequentially assigns addresses to each bus device 110. The bus device 110 whose address has been set controls the switch 228 to close through the switch control signal. Figure 3D In the example of , after receiving the positive reply that the N-1th address has been assigned, the gateway 210 broadcasts the Nth address to be assigned through the transmit data line 226. At this time, the first N-1 bus devices 110 have been set with addresses. The bus device 110-N can set the Nth address received from the transmit data line 226 as its own address, and send a positive reply to the gateway 210 through the receive data line 224 that the Nth address has been assigned. At this point, all bus devices 110 have changed from having the same default address to having a unique address. The gateway 210 can establish a communication connection with each bus device 110 based on the address.

[0067] The present disclosure also provides a power distribution cabinet. The power distribution cabinet may include an address allocation device 201 and at least one bus device 110. The bus device 110 is connected to a connection unit 120 in the address allocation device 201. The bus device 110 is configured to set a switch control signal provided to the connection unit 120 based on its own address allocation state.

[0068] In some embodiments, if the bus device 110 is not assigned an address by the gateway 210, the bus device 110 sets the switch control signal to a first control signal so that the switch 228 in the connected connection unit 110 is in an open state. In such a case, if the bus device 110 receives an address signal and address data, it can set its own address. If the bus device 110 has been assigned an address by the gateway 210, the bus device 110 sets the switch control signal to a second control signal so that the switch 228 in the connected connection unit 110 is in a closed state. In such a case, the gateway 210 will not be affected to continue to assign addresses to the bus device 120 connected to the downstream connection unit 110.

[0069] In some embodiments, if the bus device 110 has a preset address, such as a default address, the bus device 110 sets the switch control signal to the first control signal so that the switch 228 in the connection unit 110 connected to the bus device 110 is in an off state. In this case, when the gateway 210 assigns an address, it will not compete with other bus devices 120 for the address. That is, it is guaranteed that only one bus device 110 that has not been assigned an address can receive the address signal and address data and set its own address.

[0070] In some embodiments, the bus device 110 may perform address allocation for itself in response to the received address signal according to the communication with the gateway 210. For example, when the address signal is valid, the bus device 110 receives the address signal from the address allocation line 222 and determines that the gateway 210 is in the address allocation state. The bus device 110 receives the address data to be allocated from the communication data line and sets its own address.

[0071] In some embodiments, the bus device 110 receives the address to be assigned from the gateway 210. When determining that the address signal is valid, the bus device 110 sets the received address to be assigned as its own address. In addition, the bus device 110 sends a positive reply to the gateway 210 via the connection unit 120 to which it is connected that the address to be assigned has been assigned.

[0072] In summary, the present disclosure provides an address allocation device and a power distribution cabinet that can automatically allocate addresses to bus devices. The on / off state of the switch in the connection unit can be controlled according to the switch control signal from the bus device, thereby achieving automatic address allocation for the bus device. As a result, the debugging and maintenance time of the system can be shortened.

[0073] Figure 4 4 is a flowchart of an exemplary method 400 of an address allocation device according to some embodiments of the present disclosure. The method 400 may be implemented, for example, at the bus device 110, for example, by a microcontroller unit of the bus device 110. Figure 2A and Figure 2B Method 400 is described. It should be understood that method 400 may include additional acts not shown and / or may omit acts shown, and the scope of the present disclosure is not limited in this respect.

[0074] In box 410, the bus device 110 obtains an address allocation state. The address allocation state indicates whether the bus device has been assigned an address by the gateway. In box 420, the bus device 110 sets a switch control signal provided to the connection unit to which the bus device is connected based on the address allocation state. The switch control signal is used to control the on-off state of the switch in the connection unit to which the bus device is connected to control the transmission of the address signal generated by the gateway to the downstream connection unit along the address allocation line. The downstream connection unit is arranged in series with the connection unit to which it is connected along the address allocation line, and is located downstream of the connection unit to which it is connected relative to the gateway.

[0075] In some embodiments, in response to the bus device not being assigned an address by the gateway, the bus device 110 sets the switch control signal to a first control signal so that the switch in the connected connection unit is in an open state; and in response to the bus device being assigned an address by the gateway, the bus device 110 sets the switch control signal to a second control signal different from the first control signal so that the switch in the connected connection unit is in a closed state.

[0076] In some embodiments, in response to the bus device having a preset address, the bus device 110 sets the switch control signal to the first control signal.

[0077] In some embodiments, the bus device 110 performs address allocation for the bus device according to communication with the gateway in response to receiving an address signal via a connection unit to which the bus device is connected.

[0078] In some embodiments, the bus device 110 receives an address to be assigned from the gateway via the connected connection unit; in response to receiving the address signal, sets the bus device to have the address; and sends an affirmative reply to the gateway via the connected connection unit that the address is assigned.

[0079] According to an exemplary implementation of the present disclosure, a machine-readable storage medium is also provided, on which machine-executable instructions are stored, wherein the machine-executable instructions are executed by a processor to implement the method described above. According to an exemplary implementation of the present disclosure, a program product is also provided, which is tangibly stored on a non-transitory machine-readable medium and includes machine-executable instructions, and the machine-executable instructions are executed by a processor to implement the method described above.

[0080] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices, equipment and program products implemented according to the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by machine-readable program instructions.

[0081] These machine-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, a server, a single-chip microcomputer and its cluster or other programmable data processing device, so as to produce a machine, so that when these instructions are executed by the machine, the programmable data processing device and / or other equipment, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These machine-readable program instructions can also be stored in a machine-readable storage medium, and these instructions make the machine, the programmable data processing device and / or other equipment work in a specific way, so that the machine-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0082] Machine-readable program instructions may be loaded onto a machine, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the machine, other programmable data processing apparatus, or other device to produce a machine-implemented process, thereby causing the instructions executed on the machine, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0083] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and program product according to multiple implementations of the present disclosure. In this regard, each square frame in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of a module, program segment or instruction comprises one or more executable instructions for realizing the logical function of the specification. In some implementations as replacements, the function marked in the square frame can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square frames can actually be executed substantially in parallel, and they can also be executed in the opposite order sometimes, depending on the function involved. It should also be noted that each square frame in the block diagram and / or flow chart, and the combination of the square frames in the block diagram and / or flow chart can be realized by a special hardware-based system that performs the function or action of the specification, or can be realized by a combination of special hardware and machine instructions.

[0084] The above descriptions of various implementations of the present disclosure are exemplary, non-exhaustive, and not limited to the disclosed implementations. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described implementations. The selection of terms used herein is intended to best explain the principles of the implementations, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the various implementations disclosed herein.

Claims

1. An address allocation device, comprising: a gateway configured to generate an address signal to enable address allocation; an address distribution line coupled to the gateway to receive the address signal, wherein a plurality of switches are disposed in the address distribution line; A plurality of connection units are arranged in series along the address allocation line and are respectively adapted to be connected to a bus device, wherein each of the plurality of switches is located in one of the plurality of connection units, and Each connection unit of the plurality of connection units is further adapted to: coupling the address assignment line to the bus device to which the connection unit is connected, and The on / off state of a switch located in the connection unit among the multiple switches is controlled according to a switch control signal from the bus device to which it is connected, so as to control the transmission of the address signal to a downstream connection unit among the multiple connection units, wherein the downstream connection unit is located downstream of the connection unit relative to the gateway.

2. The address allocation device according to claim 1, wherein each connection unit of the plurality of connection units is further adapted to: In response to the switch control signal being in the first control signal, the switch in the connection unit is in an open state to prevent the address signal from being transmitted to the downstream connection unit; and In response to the switch control signal being in a second control signal different from the first control signal, the switch in the connection unit is closed so that the address signal is transmitted to the downstream connection unit. 3 . The address allocation device according to claim 2 , wherein each of the plurality of switches is a normally closed switch, the second control signal maintains the normally closed switch in a closed state, and the first control signal opens the normally closed switch.

4. The address allocation device according to claim 1, further comprising: a communication data line connected to the gateway and connected in parallel with the address assignment line, and Each connection unit of the plurality of connection units is further adapted to couple the communication data line to a bus device to which the connection unit is connected.

5. The address allocation device according to claim 4, wherein the gateway is further configured to: When the address signal is valid, sending a first address to be assigned through the communication data line; and In response to determining that the first address has been assigned, a second address to be assigned is sent via the communication data line.

6. The address allocation device according to claim 4, wherein the communication data line comprises: A sending data line, suitable for transmitting data from the gateway; as well as A receive data line adapted to transmit data destined for the gateway.

7. A power distribution cabinet, comprising: The address allocation device according to any one of claims 1 to 6; as well as At least one bus device, each of the at least one bus device is connected to one connection unit among the plurality of connection units, and is configured to set the switch control signal provided to the connection unit to which the bus device is connected based on the address allocation state of the bus device.

8. The power distribution cabinet according to claim 7, wherein each bus device in the at least one bus device is further configured as: In response to the bus device not being assigned an address by the gateway, setting the switch control signal to a first control signal so that the switch in the connected connection unit is in an off state; and In response to the bus device being assigned an address by the gateway, the switch control signal is set to a second control signal different from the first control signal, so that the switch in the connected connection unit is in a closed state. 9 . The power distribution cabinet according to claim 8 , wherein each of the at least one bus device is further configured to: in response to the bus device having a preset address, set the switch control signal to the first control signal.

10. The power distribution cabinet according to claim 7, wherein each bus device in the at least one bus device is further configured to: In response to receiving the address signal via a connection unit to which the bus device is connected, address allocation for the bus device is performed according to communication with the gateway.

11. The power distribution cabinet according to claim 10, wherein each bus device in the at least one bus device is further configured to: receiving, via the connected connection unit, an address to be assigned from the gateway; In response to receiving the address signal, setting the bus device to have the address; as well as A positive reply that the address is assigned is sent to the gateway via the connected connection unit.

12. An address allocation method, comprising: Acquire an address allocation status, where the address allocation status indicates whether the bus device has been allocated an address by the gateway; as well as Based on the address allocation state, a switch control signal provided to the connection unit to which the bus device is connected is set, wherein the switch control signal is used to control the on / off state of the switch in the connection unit to which the bus device is connected so as to control the transmission of the address signal generated by the gateway to the downstream connection unit along the address allocation line, The downstream connection unit is arranged in series with the connected connection unit along the address allocation line and is located downstream of the connected connection unit relative to the gateway.

13. The method according to claim 12, wherein setting a switch control signal provided to a connection unit to which the bus device is connected comprises: In response to the bus device not being assigned an address by the gateway, setting the switch control signal to a first control signal so that the switch in the connected connection unit is in an off state; as well as In response to the bus device being assigned an address by the gateway, the switch control signal is set to a second control signal different from the first control signal, so that the switch in the connected connection unit is in a closed state.

14. The method according to claim 13, wherein setting a switch control signal provided to a connection unit to which the bus device is connected comprises: In response to the bus device having a preset address, the switch control signal is set to the first control signal.

15. The method according to claim 12, further comprising: In response to receiving the address signal via a connection unit to which the bus device is connected, address allocation for the bus device is performed according to communication with the gateway.

16. The method of claim 15, wherein performing address assignment for the bus device based on communication with the gateway comprises: receiving, via the connected connection unit, an address to be assigned from the gateway; In response to receiving the address signal, setting the bus device to have the address; as well as A positive reply that the address is assigned is sent to the gateway via the connected connection unit.

17. A computer-readable storage medium having a computer program stored thereon, wherein the computer program can be executed by a processor to implement the method according to any one of claims 12 to 16.

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