Memory, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a memory, a manufacturing method thereof and electronic equipment, the memory comprises a substrate, an inner electrode, an outer electrode and a dielectric substance layer, the inner electrode, the outer electrode and the dielectric substance layer are located on the substrate, and the dielectric substance layer is located between the inner electrode and the outer electrode and used for insulation; the inner electrode comprises a first sub-electrode and a second sub-electrode which are oppositely arranged, the first sub-electrode is provided with a first surface and a second surface which are opposite to each other, and the second sub-electrode is provided with a third surface and a fourth surface which are opposite to each other; the first surface and the second surface of the first sub-electrode are at least partially coated by the outer electrode, and the third surface and the fourth surface of the second sub-electrode are at least partially coated by the outer electrode. The area of the inner electrode of the memory provided by the embodiment of the invention is relatively large, so that more charges can be stored.

Description

Technical Field

[0001] The embodiments of the present application relate to but are not limited to the field of design and manufacture of semiconductor devices, and in particular to a memory and a manufacturing method thereof and an electronic device. Background Art

[0002] Semiconductor storage can be divided into volatile memory (Random Access Memory, RAM) and non-volatile memory based on application. RAM includes dynamic random access memory (Dynamic Random Access Memory, DRAM) and static random access memory (Static Random-Access Memory, SRAM). Non-volatile memory includes read-only memory (Read-Only Memory, ROM) and non-ROM.

[0003] Taking DRAM as an example, the conventional DRAM has multiple repeated "memory cells", each of which has a capacitor and a transistor. The capacitor can store 1 bit of data, and after charging and discharging, the amount of charge stored in the capacitor can correspond to the binary data "1" and "0" respectively. The transistor is the switch that controls the charging and discharging of the capacitor.

[0004] In order to reduce the cost of products as much as possible, people hope to make as many storage units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimization solutions to meet people's needs for current products. Summary of the invention

[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0006] The embodiments of the present application provide a memory device and a method for manufacturing the same, and an electronic device. The internal electrode of the memory device has a larger area and can store more charges.

[0007] The present application provides a memory, the memory comprising: a substrate and an inner electrode, an outer electrode, and a dielectric layer located on the substrate, the dielectric layer being located between the inner electrode and the outer electrode for insulation;

[0008] The inner electrode comprises a first sub-electrode and a second sub-electrode arranged opposite to each other, the first sub-electrode has a first surface and a second surface opposite to each other, and the second sub-electrode has a third surface and a fourth surface opposite to each other;

[0009] The first surface and the second surface of the first sub-electrode are both at least partially covered by the external electrode, and the third surface and the fourth surface of the second sub-electrode are both at least partially covered by the external electrode.

[0010] Exemplarily, the first sub-electrode and the second sub-electrode may be connected together to form a first annular body, and the inner circumference and the outer circumference of the first annular body are at least partially covered by the outer electrode.

[0011] Exemplarily, the outer electrode covering the first sub-electrode and the outer electrode covering the second sub-electrode may be an integrated structure.

[0012] Exemplarily, the outer electrode forms a second annular body within the first annular body of the inner electrode, and the second annular body has a conductive material inside.

[0013] Exemplarily, the memory further comprises: a plurality of memory cells distributed in different layers, stacked in a direction perpendicular to the substrate and periodically distributed; each layer comprises a plurality of columns of memory cells, and the memory cells comprise transistors;

[0014] Exemplarily, the channel region of the transistor may extend along a first direction parallel to the substrate;

[0015] The cross-sectional profile of the inner electrode on a plane perpendicular to the substrate and parallel to the first direction is a ring.

[0016] Exemplarily, the memory may further include: a word line extending in a direction perpendicular to the substrate and passing through the memory cells at different layers.

[0017] Exemplarily, the memory may further include: a bit line extending along a second direction parallel to the substrate.

[0018] Exemplarily, transistors of two columns of memory cells located in the same layer and adjacent to each other in the first direction may be connected to the same bit line, and the direction of the columns is the same as the second direction.

[0019] Exemplarily, the semiconductor layer of the transistor is electrically connected to the internal electrode via a conductive layer, and a material of the conductive layer is the same as a material of the bit line.

[0020] Exemplarily, the semiconductor layer includes a bottom, a middle and a top in sequence along a direction away from the substrate, and the dimensions of the top and the bottom in a direction parallel to the substrate are larger than the dimension of the middle in the direction parallel to the substrate.

[0021] Exemplarily, the word line has a protruding portion at a position close to the semiconductor layer of each of the transistors, and the protruding portion extends in a direction parallel to the substrate.

[0022] The embodiment of the present application also provides a method for manufacturing a memory, wherein the memory comprises: a plurality of memory cells distributed in different layers, stacked in a direction perpendicular to a substrate and periodically distributed, wherein the memory cells comprise transistors and capacitors;

[0023] The manufacturing method comprises:

[0024] Alternatingly depositing a first insulating layer and a first conductive layer on a substrate in sequence to obtain a stacked structure;

[0025] Performing patterned etching on the stacked structure, wherein each patterned first conductive layer includes a bit line and a plurality of conductive portions spaced apart and distributed on at least one side of the bit line, wherein the conductive portion includes a first electrode and a second electrode of the transistor;

[0026] Etching and removing a portion of the conductive portion away from the bit line, so as to expose a side surface of a first insulating layer at a set depth in the patterned stack structure;

[0027] Depositing a first sub-electrode and a second sub-electrode opposite to each other on the exposed side surface of the first insulating layer in the patterned stack structure, wherein the first sub-electrode and the second sub-electrode constitute an inner electrode of the capacitor; the first sub-electrode and the second sub-electrode each have two opposite surfaces;

[0028] A dielectric layer and an outer electrode are sequentially deposited on two opposite surfaces of the first sub-electrode and the second sub-electrode, respectively. The inner electrode, the outer electrode and the dielectric layer constitute the capacitor.

[0029] Exemplarily, the memory may further include a plurality of bit lines distributed in different layers and extending along a second direction parallel to the substrate, and the same bit line is connected to two adjacent columns of memory cells located in the same layer, and two adjacent columns of memory cells in different layers connected by the plurality of bit lines stacked and distributed in a direction perpendicular to the substrate constitute a memory repetition unit;

[0030] Patterning the stacked structure may include:

[0031] The stack structure is patterned and etched along a direction toward the substrate, so that a first groove extending along a first direction parallel to the substrate and a second groove extending along the second direction are formed in the stack structure; the first groove separates each of the first conductive layers into a bit line and a plurality of conductive portions spaced apart on at least one side of the bit line, and the second groove is used to separate two adjacent storage repetitive units in the first direction; and there are two spaced apart first grooves in the first direction between two adjacent second grooves.

[0032] Exemplarily, depositing a first sub-electrode and a second sub-electrode opposite to each other on the exposed side surface of the first insulating layer in the patterned stack structure may include:

[0033] Depositing a second conductive layer on the exposed side surface of the first insulating layer in the patterned stacked structure and on the inner wall of the first groove, and connecting the second conductive layer between two adjacent first insulating layers in the patterned stacked structure to form a ring;

[0034] Filling each of the first trenches and each of the gaps between the second conductive layers with a first insulating layer;

[0035] The first insulating layer in a partial area of ​​the first groove close to the second groove and the second conductive layer on the inner wall of the first groove are etched away, and the annular second conductive layer located between two adjacent first insulating layers remains, wherein the second conductive layers located on opposite sides of the two adjacent first insulating layers serve as the first sub-electrode and the second sub-electrode, respectively, and the first sub-electrode and the second sub-electrode are connected together to form a first annular body.

[0036] Exemplarily, sequentially depositing a dielectric layer and an external electrode on two opposite surfaces of the first sub-electrode and the second sub-electrode respectively may include:

[0037] A dielectric layer and an outer electrode are sequentially deposited on the inner circumference and the outer circumference of the first annular body, respectively, so that the inner circumference and the outer circumference of the first annular body are at least partially covered by the outer electrode.

[0038] Exemplarily, the manufacturing method may further include, after patterning and etching the stacked structure and before etching away a portion of the conductive portion away from the bit line, performing the following process:

[0039] depositing a second insulating layer on an inner wall of the first trench;

[0040] Filling the first trench with a first insulating layer, and exposing the first insulating layer in the patterned stacked structure in the second trench;

[0041] performing a transverse etching on the first insulating layer exposed in the patterned stack structure in the second trench, so as to expose a side surface of the first conductive layer at a certain depth in the patterned stack structure;

[0042] Depositing the second insulating layer on the inner wall of the second trench and filling the second trench with the first insulating layer;

[0043] The first insulating layer and the second insulating layer are removed by etching in a partial area of ​​the first trench close to the second trench, and the first trench exposes the first conductive layer in the patterned stacked structure.

[0044] Exemplarily, depositing a second insulating layer on an inner wall of the first trench, filling the first trench with the first insulating layer, and exposing the first insulating layer in the patterned stacked structure in the second trench may include:

[0045] Depositing a second insulating layer on inner walls of the first trench and the second trench, and filling the first trench and the second trench with the first insulating layer;

[0046] Etching and removing the first insulating layer in the second trench;

[0047] The second insulating layer on the inner wall of the second trench is removed by etching to expose the first insulating layer in the patterned stack structure.

[0048] Exemplarily, etching and removing the first insulating layer and the second insulating layer in a partial area of ​​the first trench close to the second trench, so that the first trench exposes the first conductive layer in the patterned stacked structure, may include:

[0049] Etching and removing the first insulating layer in a partial area of ​​the first trench near the second trench, exposing the second insulating layer on a partial inner wall of the first trench, and exposing the second insulating layer in the second trench near a side of the bit line;

[0050] The second insulating layer exposed on the inner wall of the first trench and the second insulating layer exposed in the second trench are removed by etching, so that a portion of the sidewall of the first trench exposes the first conductive layer in the patterned stacked structure.

[0051] An embodiment of the present application also provides an electronic device, which includes the memory provided in the above embodiment of the present application.

[0052] The memory of the embodiment of the present application adopts an internal electrode with a bipolar plate structure, which increases the area of ​​the internal electrode, allowing the internal electrode to store more charges, thereby improving the performance of the memory.

[0053] The manufacturing method of the memory of the embodiment of the present application first removes the first conductive layer located in the capacitor area (i.e., the area used to form the capacitor later) to expose the side of the set depth of the patterned first insulating layer, and then deposits the second conductive layer as the first sub-electrode and the second sub-electrode on the exposed side of the two adjacent patterned first insulating layers, respectively, to obtain an inner electrode with a bipolar plate structure (i.e., the inner electrode includes the first sub-electrode and the second sub-electrode). Among them, the first sub-electrode has a first surface and a second surface opposite to each other, the second sub-electrode has a third surface and a fourth surface opposite to each other, and the first surface, the second surface, the third surface and the fourth surface can all store charges. Therefore, compared with the inner electrode of the unipolar plate structure, the inner electrode obtained by the manufacturing method of the embodiment of the present application can have more area to store charges, thereby improving the performance of the memory.

[0054] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or understood by practicing the present application. The objects and advantages of the present application can be realized and obtained by the structures particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0056] Figure 1A A schematic longitudinal section diagram of a memory provided for an exemplary embodiment of the present application;

[0057] Figure 1B for Figure 1A A schematic longitudinal section view of the memory device shown at another angle;

[0058] Figure 2A A schematic cross-sectional view of a memory provided for an exemplary embodiment of the present application;

[0059] Figure 2B for Figure 2A A schematic longitudinal cross-sectional view of the memory in the a-a' direction is shown;

[0060] Figure 2C for Figure 2A A schematic longitudinal section diagram of the memory in the direction bb' is shown;

[0061] Figure 2D for Figure 2A A schematic longitudinal section diagram of the memory in the c-c' direction is shown;

[0062] Figure 2E for Figure 2AA schematic longitudinal section diagram of the memory in the d-d' direction is shown;

[0063] Figure 3 A process flow chart of a method for manufacturing a memory provided for an exemplary embodiment of the present application;

[0064] Figure 4A A schematic longitudinal cross-sectional view in the a-a' direction of a memory manufacturing method according to an exemplary embodiment of the present application after a stacking structure is formed;

[0065] Figure 4B for Figure 4A A schematic longitudinal section diagram of the memory in the direction bb' is shown;

[0066] Figure 4C for Figure 4A A schematic longitudinal section diagram of the memory in the c-c' direction is shown;

[0067] Figure 4D for Figure 4A A schematic longitudinal section diagram of the memory in the d-d' direction is shown;

[0068] Figure 5A A schematic longitudinal cross-sectional view of a memory manufacturing method according to an exemplary embodiment of the present application after forming a first trench and a second trench in the aa' direction;

[0069] Figure 5B for Figure 5A A schematic longitudinal section diagram of the memory in the direction bb' is shown;

[0070] Figure 5C for Figure 5A A schematic longitudinal section diagram of the memory in the c-c' direction is shown;

[0071] Figure 5D for Figure 5A A schematic longitudinal section diagram of the memory in the d-d' direction is shown;

[0072] Fig. 6A A schematic longitudinal cross-sectional view in the aa' direction after a first insulating layer is filled in a first trench and a second trench according to a method for manufacturing a memory according to an exemplary embodiment of the present application;

[0073] Figure 6B for Fig. 6A A schematic longitudinal section diagram of the memory in the direction bb' is shown;

[0074] Figure 6C for Fig. 6A A schematic longitudinal section diagram of the memory in the c-c' direction is shown;

[0075] Fig.6D for Fig. 6A A schematic longitudinal section diagram of the memory in the d-d' direction is shown;

[0076] Fig. 7A A schematic longitudinal cross-sectional view in the aa' direction of a method for manufacturing a memory according to an exemplary embodiment of the present application after removing the second insulating layer in the second trench;

[0077] Figure 7B for Fig. 7A A schematic longitudinal section diagram of the memory in the direction bb' is shown;

[0078] Figure 7C for Fig. 7A A schematic longitudinal section diagram of the memory in the c-c' direction is shown;

[0079] Fig.7D for Fig. 7A A schematic longitudinal section diagram of the memory in the d-d' direction is shown;

[0080] Fig. 8A A schematic longitudinal cross-sectional view in the aa' direction after removing a first insulating layer at a certain depth in a patterned stack structure according to a method for manufacturing a memory according to an exemplary embodiment of the present application;

[0081] Figure 8B for Fig. 8A A schematic longitudinal section diagram of the memory in the direction bb' is shown;

[0082] Figure 8C for Fig. 8A A schematic longitudinal section diagram of the memory in the c-c' direction is shown;

[0083] Fig.8D for Fig. 8A A schematic longitudinal section diagram of the memory in the d-d' direction is shown;

[0084] Fig. 9A A schematic longitudinal cross-sectional view in the aa' direction after removing a first insulating layer at a certain depth in a patterned stack structure according to a method for manufacturing a memory according to an exemplary embodiment of the present application;

[0085] Fig. 9B for Fig. 9A A schematic longitudinal section diagram of the memory in the direction bb' is shown;

[0086] Fig. 9C for Fig. 9A A schematic longitudinal section diagram of the memory in the c-c' direction is shown;

[0087] Fig.9D for Fig. 9A A schematic longitudinal section diagram of the memory in the d-d' direction is shown;

[0088] Fig. 10A A schematic longitudinal cross-sectional view in the aa' direction of a memory manufacturing method according to an exemplary embodiment of the present application after removing a first insulating layer from a partial region of a first trench close to a second trench;

[0089] Fig. 10B for Fig. 10A A schematic longitudinal section diagram of the memory in the direction bb' is shown;

[0090] Fig. 10C for Fig. 10A A schematic longitudinal section diagram of the memory in the c-c' direction is shown;

[0091] Fig. 10D for Fig. 10A A schematic longitudinal section diagram of the memory in the d-d' direction is shown;

[0092] Fig.11A A schematic longitudinal cross-sectional view of a method for manufacturing a memory according to an exemplary embodiment of the present application after removing the second insulating layer exposed by the first trench and the second trench in the aa' direction;

[0093] Fig. 11B for Fig.11A A schematic longitudinal section diagram of the memory in the direction bb' is shown;

[0094] Fig. 11C for Fig.11A A schematic longitudinal section diagram of the memory in the c-c' direction is shown;

[0095] Fig.11D for Fig.11A A schematic longitudinal section diagram of the memory in the d-d' direction is shown;

[0096] Fig. 12A A schematic longitudinal cross-sectional view in the a-a' direction of a method for manufacturing a memory according to an exemplary embodiment of the present application after forming a second conductive layer;

[0097] Fig. 12B for Fig. 12A A schematic longitudinal section diagram of the memory in the direction bb' is shown;

[0098] Fig. 12C for Fig. 12A A schematic longitudinal section diagram of the memory in the c-c' direction is shown;

[0099] Fig.12D for Fig. 12A A schematic longitudinal section diagram of the memory in the d-d' direction is shown;

[0100] Fig.13AA schematic longitudinal cross-sectional view in the aa' direction of a memory manufacturing method according to an exemplary embodiment of the present application after removing the second conductive layer exposed on the inner wall of the first trench;

[0101] Fig. 13B for Fig.13A A schematic longitudinal section diagram of the memory in the direction bb' is shown;

[0102] Fig. 13C for Fig.13A A schematic longitudinal section diagram of the memory in the c-c' direction is shown;

[0103] Fig.13D for Fig.13A A schematic longitudinal section diagram of the memory in the d-d' direction is shown;

[0104] Fig.14A A schematic longitudinal cross-sectional view in the aa' direction of a method for manufacturing a memory according to an exemplary embodiment of the present application after forming a third electrode of a capacitor;

[0105] Fig. 14B for Fig.14A A schematic longitudinal section diagram of the memory in the direction bb' is shown;

[0106] Fig. 14C for Fig.14A A schematic longitudinal section diagram of the memory in the c-c' direction is shown;

[0107] Fig.14D for Fig.14A A schematic longitudinal section diagram of the memory in the d-d' direction is shown;

[0108] Fig.15A A schematic longitudinal cross-sectional view in the a-a' direction of a method for manufacturing a memory according to an exemplary embodiment of the present application after forming a capacitor;

[0109] Fig. 15B for Fig.15A A schematic longitudinal section diagram of the memory in the direction bb' is shown;

[0110] Fig. 15C for Fig.15A A schematic longitudinal section diagram of the memory in the c-c' direction is shown;

[0111] Fig.15D for Fig.15A A schematic longitudinal section diagram of the memory in the d-d' direction is shown;

[0112] Fig.16A A schematic longitudinal cross-sectional view of a memory manufacturing method according to an exemplary embodiment of the present application after forming a through hole K in the a-a' direction;

[0113] Fig. 16B for Fig.16A A schematic longitudinal section diagram of the memory in the direction bb' is shown;

[0114] Fig. 16C for Fig.16A A schematic longitudinal section diagram of the memory in the c-c' direction is shown;

[0115] Fig.16D for Fig.16A A schematic longitudinal section diagram of the memory in the d-d' direction is shown;

[0116] Fig.17A It is a schematic longitudinal cross-sectional view in the a-a' direction after a semiconductor layer is deposited in a through hole K according to a method for manufacturing a memory according to an exemplary embodiment of the present application;

[0117] Fig. 17B for Fig.17A A schematic longitudinal section diagram of the memory in the direction bb' is shown;

[0118] Fig. 17C for Fig.17A A schematic longitudinal section diagram of the memory in the c-c' direction is shown;

[0119] Fig.17D for Fig.17A A schematic longitudinal section diagram of the memory in the d-d' direction is shown;

[0120] Fig.18A A schematic longitudinal cross-sectional view in the a-a' direction of a method for manufacturing a memory according to an exemplary embodiment of the present application after removing the semiconductor layer of the parasitic MOS region;

[0121] Fig.18B for Fig.18A A partial enlarged view of

[0122] Fig. 18C for Fig.18A A schematic longitudinal section diagram of the memory in the direction bb' is shown;

[0123] Fig.18D for Fig.18A A schematic longitudinal section diagram of the memory in the c-c' direction is shown;

[0124] Fig.18E for Fig.18A The memory shown is a schematic longitudinal cross-sectional view along the d-d' direction. DETAILED DESCRIPTION

[0125] In order to make the purpose, technical solution and advantages of the present application more clear, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.

[0126] The embodiments of the present application are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present application are not limited to the shapes or values ​​shown in the drawings.

[0127] The ordinal numbers such as "first" and "second" in this application are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0128] In this application, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on this application. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

[0129] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0130] In this application, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, a channel region refers to a region where current mainly flows.

[0131] In the present application, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present application, unless otherwise specified, the "source electrode" and the "drain electrode" may be interchanged.

[0132] In the present disclosure, "electrical connection" or "connection" includes situations where constituent elements are connected together through an element having some electrical function, such as electrical signal connection (coupled connection, such as coupled to), or physical direct connection. There is no particular limitation on "element having some electrical function" as long as it can transfer electrical signals between connected constituent elements. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0133] In this application, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

[0134] In some embodiments of the present application, "film" and "layer" can be interchanged. For example, "first conductive layer" can sometimes be replaced by "conductive film". Similarly, "insulating film" can sometimes be replaced by "insulating layer".

[0135] In the embodiments of the present application, "A and B are an integrated structure" may mean that there is no obvious boundary interface such as a fault or gap in the microstructure. Generally, a film layer patterned on a film layer to form a connection is an integrated structure. For example, A and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process, or B is directly grown on A by epitaxy, and the materials of the two may not be exactly the same.

[0136] In the present application, spacing can be understood as being separated, and can be achieved by a physical structural disconnection or an electrical characteristic disconnection. For example, the semiconductor layer between the effective channels corresponding to the two transistors is modified to achieve insulation to achieve electrical spacing between the two channels.

[0137] In this application, "pore size" refers to the average pore size measured at multiple locations.

[0138] The capacitor structure in common DRAM devices is a dielectric layer sandwiched between two upper and lower conductive plates, where the lower plates of different capacitors are designed independently, each of which is connected to the drain electrode of a transistor device, while the upper plates of different capacitors are continuous and generally used for grounding. A larger plate area in the capacitor structure can store more charge, thereby bringing better device performance. Therefore, people hope to increase the plate area of ​​the capacitor as much as possible.

[0139] An embodiment of the present application provides a memory. Figure 1A A schematic longitudinal section diagram of a memory provided for an exemplary embodiment of the present application; Figure 1B for Figure 1A A schematic longitudinal section view of the memory shown at another angle.

[0140] like Figure 1A and Figure 1B As shown, exemplarily, the memory includes: a substrate and an inner electrode 43, an outer electrode 44, and a dielectric layer 45 located on the substrate, wherein the dielectric layer 45 is located between the inner electrode 43 and the outer electrode 44 for insulation;

[0141] The inner electrode 43 includes a first sub-electrode 431 and a second sub-electrode 432 that are opposite to each other. The first sub-electrode 431 has a first surface 4311 and a second surface 4312 that are opposite to each other. The second sub-electrode 432 has a third surface 4321 and a fourth surface 4322 that are opposite to each other.

[0142] The first surface 4311 and the second surface 4312 of the first sub-electrode 431 are at least partially covered by the external electrode 44 , and the third surface 4321 and the fourth surface 4322 of the second sub-electrode 432 are at least partially covered by the external electrode 44 .

[0143] Exemplarily, "at least partially encapsulated" includes full encapsulation or partial encapsulation. Figure 1A From the perspective shown, the first surface 4311, the second surface 4312, the third surface 4321 and the fourth surface 4322 are all partially covered by the external electrode 44; Figure 1B From the perspective shown, the first surface 4311 , the second surface 4312 , the third surface 4321 , and the fourth surface 4322 are all completely covered by the external electrode 44 .

[0144] The memory of the embodiment of the present application adopts an internal electrode with a bipolar plate structure, which increases the area of ​​the internal electrode, allowing the internal electrode to store more charges, thereby improving the performance of the memory.

[0145] For example, Figure 1AAs shown, the first sub-electrode 431 and the second sub-electrode 432 are connected together to form a first annular body 46 , and the inner circumference and the outer circumference of the first annular body 46 are both covered by the outer electrode 44 .

[0146] When the first sub-electrode and the second sub-electrode of the inner electrode are connected together to form a first ring body, the inner electrode can have more area to store charges and the occupied area of ​​the inner electrode of the same area can be reduced, so that more storage units can be formed in a limited area, thereby improving the integration of the memory.

[0147] For example, Figure 1A and Figure 1B As shown, the outer electrode 44 covering the first sub-electrode 431 and the outer electrode 44 covering the second sub-electrode 432 may be an integrated structure.

[0148] For example, Figure 1A As shown, the outer electrode 44 forms a second annular body 441 in the first annular body 46 of the inner electrode 43, and the second annular body 441 has a conductive material 442 inside, and the second annular body 441 and the conductive material 442 constitute the outer electrode 44. Exemplarily, the material of the dielectric layer can be silicon oxide or a High-K dielectric material, that is, a dielectric material with a dielectric constant K ≥ 3.9. The High-K dielectric material can include but is not limited to at least one of the following: aluminum oxide (Al2O3), hafnium oxide.

[0149] Exemplarily, the storage device may be a capacitor.

[0150] Figure 2A A schematic cross-sectional view of a memory provided for an exemplary embodiment of the present application; Figure 2B for Figure 2A A schematic longitudinal cross-sectional view of the memory in the a-a' direction is shown; Figure 2C for Figure 2A A schematic longitudinal section diagram of the memory in the direction bb' is shown; Figure 2D for Figure 2A A schematic longitudinal section diagram of the memory in the c-c' direction is shown; Figure 2E for Figure 2A The memory shown is a schematic longitudinal cross-sectional view along the d-d' direction.

[0151] like FIG. 2A to FIG. 2E As shown, the memory may further include a plurality of storage units 60;

[0152] The memory cells 60 are distributed in different layers, stacked and periodically distributed along a direction perpendicular to the substrate 10; each layer includes multiple columns of memory cells 60, and the memory cells 60 include transistors 61 and capacitors 62. The capacitors 62 may include the inner electrodes 43, outer electrodes 44 and dielectric layers 45 as described above.

[0153] For example, FIG. 2A to FIG. 2E As shown, the cross-sectional profile of the internal electrode 43 on a plane perpendicular to the substrate 10 and parallel to the first direction is annular.

[0154] For example, FIG. 2A to FIG. 2E As shown, the transistor 61 includes a first electrode 41 , a second electrode 42 , a semiconductor layer 80 located between the first electrode 41 and the second electrode 42 , and a gate electrode 71 . The semiconductor layer 80 and the gate electrode 71 are insulated from each other by a gate insulating layer 72 and a first insulating layer 11 .

[0155] For example, Figure 2B and Figure 2D As shown, the semiconductor layers 80 of transistors located at different layers are distributed alternately.

[0156] For example, FIG. 2A to FIG. 2E As shown, the channel region of the transistor 61 extends along a first direction parallel to the substrate 10 , that is, the channel between the first electrode 41 and the second electrode 42 may be a horizontal channel.

[0157] A horizontal channel is a channel in which the carrier transmission direction is in a plane parallel to the substrate, but the carrier transmission direction is not limited to one direction. In practical applications, the carrier transmission direction extends in one direction as a whole, but locally, it is related to the shape of the semiconductor layer. In other words, a horizontal channel does not mean that it must extend in one direction in the horizontal plane, and may extend in different directions. For example, when the semiconductor layer is annular, the source contact area and the drain contact area on the annular semiconductor layer are part of the ring. At this time, the carriers extend from the source contact area to the drain contact area in one direction as a whole, and may not be in a certain direction locally. Of course, the carrier transmission direction in a plane parallel to the substrate is also a macroscopic concept, and is not limited to being absolutely parallel to the substrate. The present application protects the channel between the first electrode and the second electrode as a channel that is not perpendicular to the substrate.

[0158] For example, Figure 2A As shown, the semiconductor layer 80 of the same transistor may surround its gate electrode 71 .

[0159] Here, surrounding can be understood as partially surrounding or completely surrounding. In some embodiments, such as Figure 2AAs shown, the surrounding can be a full surrounding, that is, at least the entire side wall of the gate electrode 71 is surrounded by the semiconductor layer 80, and the cross section of the semiconductor layer 80 after the surrounding is a closed ring. The cross section is intercepted along a direction perpendicular to the substrate and parallel to the first direction. In some embodiments, the surrounding can be a partial surrounding, that is, part of the side wall of the gate electrode 71 is surrounded by the semiconductor layer 80, and the cross section after the surrounding is not closed, but presents a ring shape. For example, a ring with an opening or two independent semiconductor layers. For example, the opposite side surfaces of the gate electrode 71 are surrounded by the semiconductor layer 80, and the cross section of the semiconductor layer 80 is a ring with two openings.

[0160] For example, Figure 2A As shown, the memory may further include: a word line 70; the word line 70 extends in a direction perpendicular to the substrate 10. The stacked memory cells 60 of different layers may share a word line 70 extending in a direction perpendicular to the substrate 10, that is, the word line 70 may run through the memory cells 60 of different layers.

[0161] For example, Figure 2B and Figure 2D As shown, the semiconductor layers 80 corresponding to transistors of different layers may be located on the sidewalls of the word lines 70 and respectively located in different regions extending in a direction perpendicular to the substrate 10 .

[0162] For example, Figure 2B and Figure 2D As shown, the gate electrodes 71 of transistors in different layers may be part of the word lines 70 , and the word lines 70 are exposed between the semiconductor layers 80 that are spaced apart.

[0163] For example, Figure 2A and Figure 2B As shown, the memory may further include: a bit line 31; the bit line 31 extends along a second direction parallel to the substrate 10, and the second direction intersects the first direction.

[0164] Exemplarily, the first direction and the second direction may be perpendicular to each other. For example, the first direction may be Figure 2A The a-a' direction or the b-b' direction shown in FIG. 1 , the second direction may be as follows Figure 2A The c-c' direction or the d-d' direction shown.

[0165] For example, Figure 2A and Figure 2B As shown, the transistors 61 of two columns of memory cells 60 located in the same layer and adjacent to each other in the second direction are connected to the same bit line 31 , and the direction of the columns is the same as the second direction.

[0166] For example, Figure 2A and Figure 2B As shown, the bit line 31 is connected to the first electrodes 41 of two adjacent columns of transistors in the same layer. The first electrodes 41 and the bit line 31 of two adjacent columns of transistors in the same layer can be an integrated structure, or it can be understood that the first electrode 41 and the bit line 31 can be shared.

[0167] For example, Figure 2A As shown, the external electrodes 44 of the capacitors in the same layer and the same column can be an integrated structure. In addition, the external electrodes 44 of the capacitors in the same column of different layers can be an integrated structure.

[0168] Exemplarily, the dielectric layers of the capacitors in the same column of different layers may be of an integrated structure. Exemplarily, the semiconductor layer and the inner electrode of the transistor may be electrically connected via a conductive layer, and the material of the conductive layer is the same as that of the bit line. Figure 2A and Figure 2B As shown, the semiconductor layer 80 is electrically connected to the internal electrode 43 through the first conductive layer where the second electrode 42 is located. The first conductive layer also includes the bit line 31, that is, the second electrode 42 and the bit line 31 are located in the same conductive layer and are made of the same material.

[0169] For example, Figure 2D As shown, the semiconductor layer 80 includes a bottom 81, a middle portion 82 and a top 83 in sequence along a direction away from the substrate 10. The dimensions of the top 83 and the bottom 81 in a direction parallel to the substrate 10 are larger than the dimension of the middle portion 82 in a direction parallel to the substrate 10, that is, the orthographic projection of the middle portion 82 on the substrate 10 falls within the range of the orthographic projections of the top 83 and the bottom 81 on the substrate 10.

[0170] Exemplarily, the word line 70 has a protruding portion 74 at a position close to the semiconductor layer 80 of each of the transistors, and the protruding portion 74 extends in a direction parallel to the substrate 10 .

[0171] In the present application, the semiconductor layer 80 can be understood as a semiconductor material, and its shape and structure are not emphasized here, but only its function is emphasized. For example, the material of the semiconductor layer can be a material such as silicon or polysilicon with a band gap less than 1.65eV, or a wide band gap material, such as a metal oxide material with a band gap greater than 1.65eV.

[0172] For example, the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may contain compounds of other elements, such as N, Si, etc., and may contain other small amounts of doping elements.

[0173] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InW O, IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials. As long as the leakage current of the transistor can meet the requirements, the specific adjustment can be made according to the actual situation.

[0174] These materials have a wider band gap and a lower leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10A to 15A, thereby improving the operating performance of the dynamic memory.

[0175] The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic proportion in the material and the film quality of the material.

[0176] Exemplarily, the material of the bit line can be selected from any one or more of other metal materials with similar properties such as tungsten, molybdenum, cobalt, etc. The bit line can be a single-layer or multi-layer structure, for example, a multi-layer structure formed of titanium (Ti), titanium nitride (TiN) and tungsten (W).

[0177] Exemplarily, the electrode material of the gate electrode may be any one or more of the following different types of materials:

[0178] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

[0179] It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as metal oxide materials with high conductivity such as indium tin oxide ITO, indium zinc oxide IZO, indium oxide InO, etc.; for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc.;

[0180] Of course, it can also be polysilicon material; it can also be conductive material doped semiconductor material, such as conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc.; other materials that embody conductivity, etc.

[0181] Exemplarily, the material of the gate insulating layer may include one or more layers of Low-K and / or High-K dielectric materials, or include two or more regions with different dielectric constants K. The characteristics of the gate insulating layer of the present application will be exemplarily described below.

[0182] Low-K materials, such as silicon oxide.

[0183] High-K materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, oxides of one or more of hafnium, aluminum, lanthanum, zirconium, etc. may be included. Exemplarily, for example, at least one of the following may be included but is not limited to: high-K materials such as hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), and zirconium oxide (ZrO2).

[0184] The above-mentioned memory cell may be a memory cell including a transistor, wherein the transistor may be an access transistor, and the memory cell may further include other components, such as a read transistor and a storage node in a 2T0C memory cell.

[0185] Exemplarily, the memory may be a 3D memory, such as a 3D DRAM or the like. The 3D memory may be a 1T1C or 2T1C structure.

[0186] An embodiment of the present application also provides a method for manufacturing a memory, wherein the memory comprises: a plurality of memory cells distributed in different layers, stacked in a direction perpendicular to a substrate and periodically distributed, wherein the memory cells comprise transistors and capacitors. Figure 3 A process flow chart of a method for manufacturing a memory provided for an exemplary embodiment of the present application.

[0187] like Figure 3 As shown, the manufacturing method comprises:

[0188] Alternatingly depositing a first insulating layer and a first conductive layer on a substrate in sequence to obtain a stacked structure;

[0189] Performing patterned etching on the stacked structure, wherein each patterned first conductive layer includes a bit line and a plurality of conductive portions spaced apart and distributed on at least one side of the bit line, wherein the conductive portion includes a first electrode and a second electrode of the transistor;

[0190] Etching and removing a portion of the conductive portion away from the bit line, so as to expose a side surface of a first insulating layer at a set depth in the patterned stack structure;

[0191] Depositing a first sub-electrode and a second sub-electrode opposite to each other on the exposed side surface of the first insulating layer in the patterned stack structure, wherein the first sub-electrode and the second sub-electrode constitute an inner electrode of the capacitor; the first sub-electrode and the second sub-electrode each have two opposite surfaces;

[0192] A dielectric layer and an outer electrode are sequentially deposited on two opposite surfaces of the first sub-electrode and the second sub-electrode, respectively. The inner electrode, the outer electrode and the dielectric layer constitute the capacitor.

[0193] The manufacturing method of the memory of the embodiment of the present application first removes the first conductive layer located in the capacitor area (i.e., the area used to form the capacitor later) to expose the side of the set depth of the patterned first insulating layer, and then deposits the second conductive layer as the first sub-electrode and the second sub-electrode on the exposed side of the two adjacent patterned first insulating layers, respectively, to obtain an inner electrode with a bipolar plate structure (i.e., the inner electrode includes the first sub-electrode and the second sub-electrode). Among them, the first sub-electrode has a first surface and a second surface opposite to each other, the second sub-electrode has a third surface and a fourth surface opposite to each other, and the first surface, the second surface, the third surface and the fourth surface can all store charges. Therefore, compared with the inner electrode of the unipolar plate structure, the inner electrode obtained by the manufacturing method of the embodiment of the present application can have more area to store charges, thereby improving the performance of the memory.

[0194] Exemplarily, the memory may further include a plurality of bit lines distributed in different layers and extending along a second direction parallel to the substrate, and the same bit line is connected to two adjacent columns of memory cells located in the same layer, and two adjacent columns of memory cells in different layers connected by the plurality of bit lines stacked and distributed in a direction perpendicular to the substrate constitute a memory repetition unit;

[0195] Patterning the stacked structure may include:

[0196] The stack structure is patterned and etched along a direction toward the substrate, so that a first groove extending along a first direction parallel to the substrate and a second groove extending along the second direction are formed in the stack structure; the first groove separates each of the first conductive layers into a bit line and a plurality of conductive portions spaced apart on at least one side of the bit line, and the second groove is used to separate two adjacent storage repetitive units in the first direction; and there are two spaced apart first grooves in the first direction between two adjacent second grooves.

[0197] Exemplarily, depositing a first sub-electrode and a second sub-electrode opposite to each other on the exposed side surface of the first insulating layer in the patterned stack structure may include:

[0198] Depositing a second conductive layer on the exposed side surface of the first insulating layer in the patterned stacked structure and on the inner wall of the first groove, and connecting the second conductive layer between two adjacent first insulating layers in the patterned stacked structure to form a ring;

[0199] Filling each of the first trenches and each of the gaps between the second conductive layers with a first insulating layer;

[0200] The first insulating layer in a partial area of ​​the first groove close to the second groove and the second conductive layer on the inner wall of the first groove are etched away, and the annular second conductive layer located between two adjacent first insulating layers remains, wherein the second conductive layers located on opposite sides of the two adjacent first insulating layers serve as the first sub-electrode and the second sub-electrode, respectively, and the first sub-electrode and the second sub-electrode are connected together to form a first annular body.

[0201] Exemplarily, sequentially depositing a dielectric layer and an external electrode on two opposite surfaces of the first sub-electrode and the second sub-electrode respectively may include:

[0202] A dielectric layer and an outer electrode are sequentially deposited on the inner circumference and the outer circumference of the first annular body, respectively, so that the inner circumference and the outer circumference of the first annular body are at least partially covered by the outer electrode.

[0203] When the first sub-electrode and the second sub-electrode of the inner electrode are connected together to form a first ring body, the inner electrode can have more area to store charges, and the occupied area of ​​the inner electrode can be reduced within the same area, so that more storage units can be formed in a limited area, thereby improving the integration of the memory.

[0204] Exemplarily, the manufacturing method may further include, after patterning and etching the stacked structure and before etching away a portion of the conductive portion away from the bit line, performing the following process:

[0205] depositing a second insulating layer on an inner wall of the first trench;

[0206] Filling the first trench with a first insulating layer, and exposing the first insulating layer in the patterned stacked structure in the second trench;

[0207] performing a transverse etching on the first insulating layer exposed in the patterned stack structure in the second trench, so as to expose a side surface of the first conductive layer at a certain depth in the patterned stack structure;

[0208] Depositing the second insulating layer on the inner wall of the second trench and filling the second trench with the first insulating layer;

[0209] The first insulating layer and the second insulating layer are removed by etching in a partial area of ​​the first trench close to the second trench, and the first trench exposes the first conductive layer in the patterned stacked structure.

[0210] Exemplarily, depositing a second insulating layer on an inner wall of the first trench, filling the first trench with the first insulating layer, and exposing the first insulating layer in the patterned stacked structure in the second trench may include:

[0211] Depositing a second insulating layer on inner walls of the first trench and the second trench, and filling the first trench and the second trench with the first insulating layer;

[0212] Etching and removing the first insulating layer in the second trench;

[0213] The second insulating layer on the inner wall of the second trench is removed by etching to expose the first insulating layer in the patterned stack structure.

[0214] Exemplarily, etching and removing the first insulating layer and the second insulating layer in a partial area of ​​the first trench close to the second trench, so that the first trench exposes the first conductive layer in the patterned stacked structure, may include:

[0215] Etching and removing the first insulating layer in a partial area of ​​the first trench near the second trench, exposing the second insulating layer on a partial inner wall of the first trench, and exposing the second insulating layer in the second trench near a side of the bit line;

[0216] The second insulating layer exposed on the inner wall of the first trench and the second insulating layer exposed in the second trench are removed by etching, so that a portion of the sidewall of the first trench exposes the first conductive layer in the patterned stacked structure.

[0217] The memory provided in the above embodiment of the present application can be obtained by the above manufacturing method.

[0218] The technical solution of the embodiment of the present application is further explained below through the manufacturing process of the memory of the exemplary embodiment. The "patterned etching" mentioned in this embodiment includes deposition of film layers, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which is a mature preparation process in the relevant technology. The "photolithography" process mentioned in this embodiment includes coating of film layers, mask exposure and development, which is a mature preparation process in the relevant technology. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, etc., coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here.

[0219] FIG. 4A to FIG. 18E Schematic diagrams of longitudinal sections and partial enlarged diagrams of a device structure obtained in different directions during an intermediate process of a method for manufacturing a memory according to an exemplary embodiment of the present application.

[0220] like FIG. 4A to FIG. 18E As shown, exemplarily, the method for manufacturing the memory may include the following processes.

[0221] S10: providing a substrate 10, and alternately depositing a first insulating layer 11 and a first conductive layer 12 on the substrate 10 in sequence to obtain a stacked structure consisting of the first insulating layer 11 and the first conductive layer 12 distributed in layers, wherein the top layer of the stacked structure is the first insulating layer 11, such as 4A to 4D shown.

[0222] Exemplarily, the material of the first insulating layer may be a low-K dielectric material, ie, a dielectric material with a dielectric constant K<3.9, including but not limited to silicon oxides, such as silicon dioxide (SiO2) or other silicon-containing film layers.

[0223] Exemplarily, the material of the first conductive layer may be any one or more of conductive metal, conductive metal nitride and polysilicon (Poly); the conductive metal includes but is not limited to tungsten (W), cobalt (Co), titanium (Ti) and the like.

[0224] Exemplarily, the first conductive layer may be a single layer or a multilayer structure, for example, a multilayer structure formed of Ti, TiN and W. For example, Ti, TiN and W may be deposited in sequence on the side of the first insulating layer 11 away from the substrate 10 to form a first conductive layer of a multilayer structure. Providing TiN between the side of W close to the substrate 10 and the first insulating layer 11 can prevent W from being oxidized by the oxygen-containing first insulating layer 11, so the film layer formed by TiN can be called an anti-oxidation layer. Of course, the first insulating layer may be an oxygen-free film layer, and then the first conductive layer does not need to be added with an anti-oxidation layer.

[0225] For example, Ti may be deposited by a chemical vapor deposition (CVD) process, TiN may be deposited by an atomic layer deposition (ALD) process, and W may be deposited by a CVD or ALD process. After each deposition of a tungsten layer, a chemical mechanical polishing (CMP) process may be used to planarize the tungsten layer and control its thickness.

[0226] Exemplarily, the substrate 10 may be a supporting structure, such as a silicon substrate, or a supporting structure on which other film layers or functional functions or circuits are already distributed, and the device involved in the inventive construction of the embodiment of the present application is arranged on the upper main surface of the supporting structure.

[0227] 4A to 4D The stacking structure shown in the figure includes four first insulating layers 11 and three first conductive layers 12, which is only an example. In other embodiments, the stacking structure may include more or fewer first insulating layers 11 and first conductive layers 12 that are alternately arranged.

[0228] S20: performing pattern etching on the stacked structure.

[0229] Exemplarily, step S20 may include: depositing a second insulating layer 13 on the surface of the stacking structure; defining a photolithography pattern using a photolithography method, and pattern-etching the second insulating layer 13 and the stacking structure along a direction toward the substrate 10, so that a plurality of first grooves 21 extending along a first direction and a plurality of second grooves 22 extending along a second direction are formed in the stacking structure; the plurality of first grooves 21 are spaced apart in the second direction, and there are two spaced apart first grooves 21 between two adjacent second grooves 22 in the first direction; the first direction intersects with the second direction, and the alternatingly stacked patterned first insulating layers 11 and patterned first conductive layers 12 constitute a patterned stacking structure.

[0230] The first trench 21 spaces the first conductive layer 12 into bit lines 31 to be formed, a plurality of spaced-apart first conductive portions 32, and a plurality of spaced-apart second conductive portions 33. That is, the patterned first conductive layer 12 includes bit lines 31, first conductive portions 32, and second conductive portions 33. Among them, the bit lines 31 connect the first conductive portions 32 and the second conductive portions 33. The plurality of spaced-apart first conductive portions 32 and the plurality of spaced-apart second conductive portions 33 are respectively located on both sides of the bit lines 31. The bit lines 31, the plurality of first conductive portions 32, and the plurality of second conductive portions 33 can form a "丰" character-shaped structure. The bit lines 31 serve as the main trunk of the "丰" character-shaped structure, and the plurality of first conductive portions 32 and the plurality of second conductive portions 33 serve as the branches of the "丰" character-shaped structure. The first conductive portion 32 can extend along the first direction, the second conductive portion 33 can extend along the first direction, and the bit lines 31 can extend along the second direction. The same bit line can be connected to adjacent two columns of memory cells in the same layer to be formed. The adjacent two columns of memory cells connected by a plurality of bit lines stacked along the direction perpendicular to the substrate constitute a memory repeating unit. The second trench 22 is used to space apart adjacent two memory repeating units in the first direction. The pattern of the patterned first insulating layer 11 is the same as the pattern of the patterned first conductive layer 12, as FIG. 5A to FIG. 5D shown.

[0231] One end of the first conductive portion 32 connected to the bit line 31 serves as the first electrode of the transistor to be formed subsequently. That is, the bit line 31 and the first electrode of the transistor connected thereto are of an integral structure, or the bit line 31 and the first electrode of the transistor connected thereto are shared. One end of the first conductive portion 32 away from the bit line 31 forms a second electrode of a transistor by disconnecting from the bit line 31 subsequently. One end of the second conductive portion 33 away from the bit line 31 forms a second electrode of an adjacent another transistor by disconnecting from the bit line 31 subsequently. One end of the second conductive portion 33 connected to the bit line 31 serves as the first electrode of the transistor or the bit line 31 is shared as the first electrode of the transistor.

[0232] Exemplarily, the first direction and the second direction can both be parallel to the substrate 10. For example, the first direction can be the a-a' direction or the b-b' direction as Figure 2A shown, and the second direction can be the c-c' direction or the d-d' direction as Figure 2A shown.

[0233] Exemplarily, as FIG. 5A to FIG. 5D shown, the depth of the first trench 21 can be greater than the depth of the second trench 22. For example, the first trench 21 can be extended into the substrate 10, and the second trench 22 exposes the surface of the substrate 10.

[0234] Exemplarily, the material of the second insulating layer may be any one or more of silicon oxide (e.g., SiO2), silicon oxynitride (SiON), silicon nitride (SiN), and silicon carbonitride (SiCN), and the material of the second insulating layer is different from that of the first insulating layer, so that when one of the insulating layers is subsequently etched and removed, the first insulating layer and the second insulating layer may have different etching rates, thereby removing the insulating layer that is desired to be removed. For example, in this embodiment, the material of the first insulating layer may be silicon oxide, and the material of the second insulating layer may be silicon nitride.

[0235] S30: depositing a second insulating layer 13 on the inner walls (including the side walls and the bottom wall) of the first trench 21 and the second trench 22 and the top surface of the patterned stack structure, and filling the first insulating layer 11 in the first trench 21 and the second trench 22, and then planarizing the first insulating layer 11 on the top surface of the substrate 10 by a CMP process until the second insulating layer 13 on the top surface of the substrate 10 is exposed, such as FIG. 6A to FIG. 6D shown.

[0236] S40: etching and removing the first insulating layer 11 in the second trench 22, such as FIG. 7A to FIG. 7D shown.

[0237] Exemplarily, in step S40 , dry etching may be used to remove the first insulating layer 11 in the second trench 22 .

[0238] S50: etching and removing the second insulating layer 13 on the inner wall of the second groove 22, exposing the first insulating layer 11 in the patterned stacking structure and the first insulating layer 11 in the first groove 21; performing transverse etching on the exposed first insulating layer 11 in the second groove 22, removing the first insulating layer 11 to a certain depth, so as to expose the end surface of the first conductive layer 12 at a corresponding depth in the patterned stacking structure, such as FIG. 8A to FIG. 8D shown.

[0239] For example, in step S50 , wet etching may be used to remove the second insulating layer 13 on the inner wall of the second trench 22 , and / or wet etching may be used to remove the first insulating layer 11 at a certain depth in the patterned stacked structure.

[0240] S60: depositing a second insulating layer 13 on the inner wall (including the side wall and the bottom wall) of the second groove 22, so that the exposed end surface of the first conductive layer 12 of the patterned stacked structure is covered by the second insulating layer 13, and the exposed side surface and top surface of the first insulating layer 11 in the first groove 21 are covered by the second insulating layer 13, and the first insulating layer 11 is filled in the second groove 22. The second insulating layer 13 deposited in this step can be used as an isolation layer between storage repeating units and a support layer of the capacitor to be formed. The first insulating layer 11 deposited in this step can be used as a barrier layer when the second insulating layer 13 is subsequently etched, such as 9A to 9D shown.

[0241] S70: removing the first insulating layer 11 in a partial area of ​​the first trench 21 close to the second trench 22, such as FIG. 10A to FIG. 10D shown.

[0242] Exemplarily, step S70 may include: removing the first insulating layer 11 from a partial area of ​​the first trench 21 near the second trench 22 by dry etching, exposing the second insulating layer 13 on a portion of the inner wall of the first trench 21, and exposing the second insulating layer 13 on the side of the second trench 22 near the bit line, and the second insulating layer 13 on the bottom wall of the first trench 21 originally covered by the first insulating layer 11 is also completely or partially etched away; wherein the length of the etched first insulating layer 11 in the first direction is equal to the desired length of the internal electrode 43 of the capacitor to be formed.

[0243] S80: etching and removing the second insulating layer 13 exposed on the inner wall of the first trench 21 and the second insulating layer 13 exposed in the second trench 22. FIG. 11A to FIG. 11D shown.

[0244] Exemplarily, step S80 may include: removing the second insulating layer 13 exposed on the sidewall of the first trench 21 and the second insulating layer 13 exposed in the second trench 22 by wet etching, so that part of the sidewall of the first trench 21 exposes the first conductive layer 12 in the patterned stacked structure.

[0245] like Fig. 11B As shown, due to the presence of the first insulating layer 11 on the side wall of the second trench 22, the first insulating layer 11 can act as a barrier layer in S80 to protect the second insulating layer 13 on the side wall of the second trench 22 away from the bit line from being etched away, and can subsequently serve as a support layer for supporting the storage repetitive unit to improve the structural stability of the memory.

[0246] like Fig.11A , Fig. 11C and Fig.11DAs shown, due to the presence of the first insulating layer 11 on the surface of the substrate 10, the second insulating layer 13 on the surface of the substrate 10 covered by the first insulating layer 11 will not be etched away, and can serve as a supporting layer (or frame) to provide support for the storage unit, thereby improving the structural stability of the storage unit.

[0247] S90: performing transverse etching on the first conductive layer 12 exposed on the side wall of the first trench 21, so as to expose the side of the first insulating layer 11 in the patterned stacking structure away from one end of the bit line at a set depth, wherein the set depth is the length of the inner electrode of the capacitor to be formed; depositing the second conductive layer 14 on the exposed side of the first insulating layer 11 in the patterned stacking structure and on the inner wall of the first trench 21, and connecting the second conductive layer 14 between two adjacent first insulating layers 11 in the patterned stacking structure to form a ring, wherein the second conductive layer 14 between two adjacent first insulating layers 11 is connected to the first conductive layer 12, such as FIG. 12A to FIG. 12D shown.

[0248] Exemplarily, in step S90 , wet etching may be used to laterally etch the exposed first conductive layer 12 , and the etching agent used in the wet etching is SC1 solution (a mixed solution of ammonia water and hydrogen peroxide).

[0249] Exemplarily, the material of the second conductive layer may be any one or more of a conductive metal, a nitride of a conductive metal, and polysilicon (Poly); the conductive metal includes but is not limited to tungsten (W), cobalt (Co), titanium (Ti), etc., and the material of the second conductive layer may be the same as or different from the material of the first conductive layer. The second conductive layer may be a single-layer or multi-layer structure. In this exemplary embodiment, the first conductive layer may be a three-layer structure consisting of Ti, TiN, and W, and the second conductive layer may be a double-layer structure consisting of Ti and TiN.

[0250] S100: fill the gaps between the first trenches 21 and the second conductive layers 14 with the first insulating layer 11; etch and remove the first insulating layer 11 in a portion of the first trench 21 near the second trench 22 and the second conductive layer 14 on the inner wall of the first trench 21, such as FIG. 13A to FIG. 13D shown.

[0251] Exemplarily, step S100 may include:

[0252] S101: filling the first trenches 21 and the gaps between the second conductive layers 14 with the first insulating layer 11, and planarizing them with a CMP process;

[0253] S102: dry etching is used to remove the first insulating layer 11 in a partial area of ​​the first trench 21 near the second trench 22, exposing the second conductive layer 14 on the inner wall of the first trench 21, that is, the first insulating layer 11 removed is the first insulating layer 11 deposited after the second conductive layer 14; then wet etching is used to remove the second conductive layer 14 exposed on the inner wall of the first trench 21, and the annular second conductive layer 14 located between the two adjacent first insulating layers 11 remains, wherein the second conductive layer 14 located on the opposite sides of the two adjacent first insulating layers 11 respectively serves as the first sub-electrode 431 and the second sub-electrode 432, and the first sub-electrode 431 and the second sub-electrode 432 are connected together to form a ring-shaped inner electrode 43; after the second conductive layer 14 on the side wall of the first trench 21 is etched, the first insulating layer 11 is exposed on the side wall of the first trench 21, such as FIG. 13A to FIG. 13D shown.

[0254] S110: The first insulating layer 11 exposed on the side wall of the first trench 21 is laterally etched to remove the first insulating layer 11 between the second conductive layers 14 spaced apart in a direction perpendicular to the substrate 10. After the first insulating layer 11 is removed, the first sub-electrode 431 and the second sub-electrode 432 of the inner electrode 43 are exposed on their two opposite surfaces. The exposed surfaces of the first sub-electrode 431 and the second sub-electrode 432 are connected together to form the inner and outer peripheral surfaces of the annular inner electrode 43. FIG. 14A to FIG. 14D shown.

[0255] like Fig.14A As shown, the longitudinal cross-sectional profile of the inner electrode 43 of the capacitor in the first direction may be annular.

[0256] S120: depositing a dielectric layer 45 and a conductive film layer on the substrate 10 in sequence to cover the exposed inner and outer surfaces of the annular inner electrode 43, wherein the conductive film layer covering the inner and outer surfaces of the annular inner electrode 43 is used to form an outer electrode 44, and the inner electrode 43, the outer electrode 44 and the dielectric layer 45 between the inner electrode 43 and the outer electrode 44 constitute a capacitor; and filling the blank space of the first groove 21 and the gap of the capacitor with a third conductive layer 15, such as FIG. 15A to FIG. 15D shown.

[0257] Exemplarily, the material of the outer electrode 44 may be any one or more of a conductive metal, a nitride of a conductive metal, and polysilicon (Poly); the conductive metal includes but is not limited to tungsten (W), cobalt (Co), titanium (Ti), etc., and the material of the outer electrode 44 and the inner electrode may be the same or different. The outer electrode 44 may be a single-layer or multi-layer structure, for example, it may include a second annular body formed of a double-layer structure of Ti and TiN and a conductive material polysilicon in the second annular body.

[0258] Exemplarily, the material of the third conductive layer may be any one or more of a conductive metal, a nitride of a conductive metal, and polysilicon (Poly); the conductive metal includes but is not limited to tungsten (W), cobalt (Co), titanium (Ti), etc., and the material of the third conductive layer may be the same as or different from the material of the first conductive layer. The third conductive layer may be a single-layer or multi-layer structure. In this exemplary embodiment, the first conductive layer may be a three-layer structure composed of Ti, TiN and W, and the third conductive layer may be a single-layer structure formed of polysilicon (Poly).

[0259] S130 : etching the patterned stacked structure along a direction toward the substrate 10 to form a through hole K penetrating each patterned first conductive layer 12 .

[0260] Exemplarily, step S130 may include:

[0261] S131: disconnecting the dielectric layer 45 and the conductive film layer (including the conductive film layer and the third conductive layer deposited when forming the external electrode) covering the patterned stacked structure on the top surface of the substrate 10 to prevent the capacitor from being connected to the subsequently formed word line, and then sequentially depositing the first insulating layer 11 and the second insulating layer 13 on the surface of the substrate 10;

[0262] S132: Etching the patterned stacked structure along the direction toward the substrate 10 to form a through hole K penetrating each patterned first conductive layer 12, such as FIG. 16A to FIG. 16D shown.

[0263] Exemplarily, step S132 may use photolithography and dry etching to form the through hole K. The through hole K obtained in step S132 may have substantially the same aperture in the first conductive layer and the first insulating layer in the patterned stacked structure, and the through hole K may extend in a direction perpendicular to the substrate 10 and expose the substrate 10 .

[0264] S133 : expanding the through hole K laterally, so that the first conductive portion 32 and the second conductive portion 33 are respectively disconnected by the through hole K to form the first electrode 41 and the second electrode 42 of the transistor.

[0265] Exemplarily, step S133 may include: performing lateral etching on the first conductive layer 12 in the patterned stacked structure in the through hole K, so that the through hole K penetrates the first conductive portion 32 and the second conductive portion 33 in the second direction, but the through hole K does not penetrate the first conductive portion 32 and the second conductive portion 33 in the first direction, thereby separating the first conductive portion 32 into the first electrode 41 and the second electrode 42 of a transistor, and separating the second conductive portion 33 into the first electrode 41 and the second electrode 42 of another adjacent transistor. After expansion, the aperture of the through hole K in the first conductive layer 12 is larger than the aperture of the through hole K in the first insulating layer 11, and the orthographic projection of the through hole K in the first insulating layer 11 on the substrate 10 falls within the range of the orthographic projection of the through hole K in the first conductive layer 12 on the substrate 10.

[0266] S140: a semiconductor layer 80 and a gate insulating layer 72 covering the inner wall of the through hole K are sequentially deposited on the substrate 10, and a gate electrode material is filled in the through hole K to form a gate electrode layer 73, such as FIG. 17A to FIG. 17D shown.

[0267] In this embodiment, the material of the semiconductor layer 80 may be IGZO, the material of the gate insulating layer 72 may be Al 2 O 3 , and the material of the gate electrode layer 73 may be ITO.

[0268] S150 : removing the semiconductor layer 80 of the parasitic MOS region 200 .

[0269] Due to the connection of the semiconductor layer 80 between the two transistors stacked in the direction perpendicular to the substrate 10, a parasitic MOS tube (parasitic MOS for short) will be formed, which will affect the performance of the memory. Therefore, the semiconductor layer 80 located in the parasitic MOS area 200 should be removed, and only the semiconductor layer 80 located in the channel area 300 should be retained.

[0270] Exemplarily, step S150 may include: removing the gate electrode layer 73, the gate insulating layer 72 and the semiconductor layer 80 on the inner wall of a partial area of ​​the through hole K by wet etching, and retaining only the gate electrode layer 73, the gate insulating layer 72 and the semiconductor layer 80 on the side walls of the partial through hole extending into the first electrode 41 and the second electrode 42; exemplarily, oxalic acid may be used as an etching agent to etch the gate electrode layer 73 of ITO material, and hydrochloric acid may be used as an etching agent to etch the gate insulating layer 72 of Al2O3 material and the semiconductor layer 80 of IGZO material; hydrochloric acid has a low etching rate for ITO, which can prevent the gate electrode layer 73 of ITO material from being over-etched.

[0271] S160 : forming a word line 70 in the through hole K.

[0272] Exemplarily, step S160 may include:

[0273] S161: depositing a first insulating layer 11 filling the through hole K on the substrate 10 to cover the semiconductor layer 80 and the gate insulating layer 72 exposed in the channel region 300; then wet etching the first insulating layer 11 to expose at least a portion of the gate electrode layer 73, and the first insulating layer 11 covering the semiconductor layer 80 and the gate insulating layer 72 is still retained, as shown in FIG. FIG. 18A to FIG. 18E As shown;

[0274] S162: Fill the through hole K with the gate electrode material, and the gate electrode material in each through hole K forms a word line 70 that penetrates each patterned first conductive layer; the area of ​​the word line 70 between the first electrode 41 and the second electrode 42 is used as the gate electrode 71 of the transistor, and the semiconductor layer 80 in the channel area between the first electrode 41 and the second electrode 42 is used to form a channel of the transistor, and the semiconductor layer 80 surrounds the gate electrode 71, and the first electrode 41, the second electrode 42, the semiconductor layer 80 between the first electrode 41 and the second electrode 42, and the gate electrode 71 constitute a transistor;

[0275] S163: Then, the gate electrode material on the surface of the substrate 10 is planarized by a CMP process until the second insulating layer 13 on the surface of the substrate 10 is exposed, and the following is obtained: FIG. 2A to FIG. 2E Memory shown.

[0276] An embodiment of the present application also provides an electronic device, which includes the memory provided in the above embodiment of the present application.

[0277] Exemplarily, the electronic device may be: a storage device, a smart phone, a computer, a tablet, an artificial intelligence device, a wearable device, or a mobile power source, etc. The storage device may include a memory in a computer, etc., which is not limited here.

[0278] Although the embodiments disclosed in this application are as above, the contents described are only embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any technician in the field to which this application belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be based on the scope defined in the attached claims.

Claims

1. A memory, characterized in that: include: A substrate and an inner electrode, an outer electrode, and a dielectric layer located on the substrate, wherein the dielectric layer is located between the inner electrode and the outer electrode for insulation; The inner electrode comprises a first sub-electrode and a second sub-electrode arranged opposite to each other, the first sub-electrode has a first surface and a second surface opposite to each other, and the second sub-electrode has a third surface and a fourth surface opposite to each other; The first surface and the second surface of the first sub-electrode are both at least partially covered by the external electrode, and the third surface and the fourth surface of the second sub-electrode are both at least partially covered by the external electrode.

2. The memory according to claim 1, characterized in that: The first sub-electrode and the second sub-electrode are connected together to form a first annular body, and the inner circumference and the outer circumference of the first annular body are at least partially covered by the outer electrode.

3. The memory according to claim 2, characterized in that: The outer electrode covering the first sub-electrode and the outer electrode covering the second sub-electrode are an integrated structure.

4. The memory according to claim 2, characterized in that: The outer electrode forms a second annular body within the first annular body of the inner electrode, and the second annular body has a conductive material inside.

5. The memory according to any one of claims 1 to 4, characterized in that: Also includes: A plurality of memory cells are distributed in different layers, stacked along a direction perpendicular to the substrate and distributed periodically; each layer includes a plurality of columns of memory cells, and the memory cells include transistors.

6. The memory according to claim 5, characterized in that: The channel region of the transistor extends along a first direction parallel to the substrate; The cross-sectional profile of the inner electrode on a plane perpendicular to the substrate and parallel to the first direction is a ring.

7. The memory according to claim 6, characterized in that: Also includes: A word line extending in a direction perpendicular to the substrate and passing through the memory cells of different layers; and / or, A bit line extends along a second direction parallel to the substrate; transistors of two columns of memory cells located in the same layer and adjacent to each other in the first direction are connected to the same bit line, and the direction of the columns is the same as the second direction.

8. The memory according to claim 7, characterized in that: The semiconductor layer of the transistor is electrically connected to the internal electrode through a conductive layer, and the material of the conductive layer is the same as that of the bit line.

9. The memory according to claim 8, characterized in that: The semiconductor layer includes a bottom, a middle and a top in sequence along a direction away from the substrate, and the dimensions of the top and the bottom in a direction parallel to the substrate are larger than the dimension of the middle in the direction parallel to the substrate.

10. The memory according to claim 7, characterized in that: The word line has a protruding portion at a position close to the semiconductor layer of each of the transistors, and the protruding portion extends in a direction parallel to the substrate.

11. A method for manufacturing a memory, characterized in that: The memory comprises: a plurality of storage units distributed in different layers, stacked along a direction perpendicular to a substrate and periodically distributed, wherein the storage units comprise transistors and capacitors; The manufacturing method comprises: Alternatingly depositing a first insulating layer and a first conductive layer on a substrate in sequence to obtain a stacked structure; Performing patterned etching on the stacked structure, wherein each patterned first conductive layer includes a bit line and a plurality of conductive portions spaced apart and distributed on at least one side of the bit line, wherein the conductive portion includes a first electrode and a second electrode of the transistor; Etching and removing a portion of the conductive portion away from the bit line, so as to expose a side surface of a first insulating layer at a set depth in the patterned stack structure; Depositing a first sub-electrode and a second sub-electrode opposite to each other on the exposed side surface of the first insulating layer in the patterned stack structure, wherein the first sub-electrode and the second sub-electrode constitute an inner electrode of the capacitor; the first sub-electrode and the second sub-electrode each have two opposite surfaces; A dielectric layer and an outer electrode are sequentially deposited on two opposite surfaces of the first sub-electrode and the second sub-electrode, respectively. The inner electrode, the outer electrode and the dielectric layer constitute the capacitor.

12. The manufacturing method according to claim 11, characterized in that: The memory further comprises a plurality of bit lines distributed in different layers and extending along a second direction parallel to the substrate, and the same bit line is connected to two adjacent columns of memory cells located in the same layer, and the two adjacent columns of memory cells in different layers connected by the plurality of bit lines stacked and distributed in a direction perpendicular to the substrate constitute a memory repetition unit; Patterning the stacked structure includes: Performing patterned etching on the stack structure along a direction toward the substrate, so that a first groove extending along a first direction parallel to the substrate and a second groove extending along the second direction are formed in the stack structure; The first grooves separate each of the first conductive layers into bit lines and a plurality of conductive portions spaced apart on at least one side of the bit lines; the second grooves are used to separate two adjacent storage repetitive units in the first direction; and there are two spaced apart first grooves between two adjacent second grooves in the first direction.

13. The manufacturing method according to claim 12, characterized in that: Depositing a first sub-electrode and a second sub-electrode opposite to each other on the exposed side surface of the first insulating layer in the patterned stack structure, comprising: Depositing a second conductive layer on the exposed side surface of the first insulating layer in the patterned stacked structure and on the inner wall of the first groove, and connecting the second conductive layers between two adjacent first insulating layers in the patterned stacked structure to form a ring shape; Filling each of the first trenches and each of the gaps between the second conductive layers with a first insulating layer; The first insulating layer in a partial area of ​​the first groove close to the second groove and the second conductive layer on the inner wall of the first groove are etched away, and the annular second conductive layer located between two adjacent first insulating layers remains, wherein the second conductive layers located on opposite sides of the two adjacent first insulating layers serve as the first sub-electrode and the second sub-electrode, respectively, and the first sub-electrode and the second sub-electrode are connected together to form a first annular body.

14. The manufacturing method according to claim 13, characterized in that: A dielectric layer and an external electrode are sequentially deposited on two opposite surfaces of the first sub-electrode and the second sub-electrode, respectively, including: A dielectric layer and an outer electrode are sequentially deposited on the inner circumference and the outer circumference of the first annular body, respectively, so that the inner circumference and the outer circumference of the first annular body are at least partially covered by the outer electrode.

15. The manufacturing method according to any one of claims 12 to 14, characterized in that: The method further includes performing the following process after patterning and etching the stack structure and before etching away a portion of the conductive portion away from the bit line: depositing a second insulating layer on an inner wall of the first trench; Filling the first trench with a first insulating layer, and exposing the first insulating layer in the patterned stacked structure in the second trench; performing a transverse etching on the first insulating layer exposed in the patterned stack structure in the second trench, so as to expose a side surface of the first conductive layer at a certain depth in the patterned stack structure; Depositing the second insulating layer on the inner wall of the second trench and filling the second trench with the first insulating layer; The first insulating layer and the second insulating layer are removed by etching in a partial area of ​​the first trench close to the second trench, and the first trench exposes the first conductive layer in the patterned stacked structure.

16. The manufacturing method according to claim 15, characterized in that: Depositing a second insulating layer on the inner wall of the first trench, filling the first trench with the first insulating layer, and exposing the first insulating layer in the patterned stacked structure in the second trench, comprising: Depositing a second insulating layer on inner walls of the first trench and the second trench, and filling the first trench and the second trench with the first insulating layer; Etching and removing the first insulating layer in the second trench; Etching and removing the second insulating layer on the inner wall of the second trench to expose the first insulating layer in the patterned stacked structure; and / or, The first insulating layer and the second insulating layer are removed by etching from a portion of the first trench near the second trench, so that the first trench exposes the first conductive layer in the patterned stacked structure, including: Etching and removing the first insulating layer in a partial area of ​​the first trench near the second trench, exposing the second insulating layer on a partial inner wall of the first trench, and exposing the second insulating layer in the second trench near a side of the bit line; The second insulating layer exposed on the inner wall of the first trench and the second insulating layer exposed in the second trench are removed by etching, so that a portion of the sidewall of the first trench exposes the first conductive layer in the patterned stacked structure.

17. An electronic device, characterized in that: Comprising a memory according to any one of claims 1 to 10.

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