Semiconductor structure, semiconductor device and manufacturing method thereof, and electronic equipment

Abstract

The invention discloses a semiconductor structure, a semiconductor device, a manufacturing method of the semiconductor device and electronic equipment, and the semiconductor structure comprises a first electrode which is used for being connected with a bit line; the second electrode comprises a surrounding part and an extending part, and the extending part extends in the direction perpendicular to the substrate; the semiconductor layer extends in the direction perpendicular to the substrate, and at least part of the side wall of the semiconductor layer is surrounded by the surrounding part; at least part of the side wall of the gate electrode is surrounded by the semiconductor layer, and a gate insulation layer used for insulation is arranged between the gate electrode and the semiconductor layer. According to the semiconductor structure, the contact area of the second electrode and the semiconductor layer is large, and the carrier transmission efficiency of the channel region is high.

Description

Technical Field

[0001] The embodiments of the present application relate to but are not limited to the field of design and manufacturing of semiconductor devices, and in particular to a semiconductor structure, a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] Semiconductor storage can be divided into volatile memory (Random Access Memory, RAM) and non-volatile memory based on application. RAM includes dynamic random access memory (Dynamic Random Access Memory, DRAM) and static random access memory (Static Random-Access Memory, SRAM). Non-volatile memory includes read-only memory (Read-Only Memory, ROM) and non-ROM.

[0003] Taking DRAM as an example, the conventional DRAM has multiple repeated "memory cells", each of which has a capacitor and a transistor. The capacitor can store 1 bit of data, and after charging and discharging, the amount of charge stored in the capacitor can correspond to the binary data "1" and "0" respectively. The transistor is the switch that controls the charging and discharging of the capacitor.

[0004] In order to improve the performance of semiconductor memory devices as much as possible, the industry has proposed various semiconductor structure designs and process optimization solutions to meet people's needs for current products. Summary of the invention

[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0006] The embodiment of the present application provides a semiconductor structure, a semiconductor device and a manufacturing method thereof, and an electronic device. The contact area between the second electrode and the semiconductor layer of the semiconductor structure is large, and the carrier transmission efficiency in the channel region is high.

[0007] An embodiment of the present application provides a semiconductor structure, wherein the semiconductor structure comprises:

[0008] A first electrode, used to be connected to a bit line;

[0009] A second electrode comprising a surrounding portion and an extending portion; the extending portion extends in a direction perpendicular to the substrate;

[0010] A semiconductor layer extending in a direction perpendicular to the substrate; at least a portion of a sidewall of the semiconductor layer is surrounded by the surrounding portion;

[0011] A gate electrode, at least a portion of the sidewall of the gate electrode is surrounded by the semiconductor layer, and a gate insulating layer for insulation is arranged between the gate electrode and the semiconductor layer.

[0012] Exemplarily, the first electrode and the second electrode are spaced apart from each other in a direction perpendicular to the substrate.

[0013] Exemplarily, the surrounding portion of the second electrode has an opening, the surrounding portion of the second electrode has an opening, and the semiconductor layer passes through the opening in a direction perpendicular to the substrate.

[0014] Exemplarily, the gate electrode extends in a direction perpendicular to the substrate, an end surface of the gate electrode facing away from the substrate is used for connecting to a word line, and an end surface of the gate electrode close to the substrate is surrounded by the semiconductor layer.

[0015] Exemplarily, the semiconductor layer surrounding the gate electrode constitutes a hollow cylindrical structure; the cylindrical structure has side surfaces, a bottom surface and an opening, the side surfaces are surrounded and contacted by the surrounding portion of the second electrode, the bottom surface is in contact with the first electrode, the area on the side surface of the cylindrical structure located between the first electrode and the second electrode is a channel region, the channel region extends in a direction perpendicular to the substrate, and the gate electrode is filled in the cylindrical structure.

[0016] Exemplarily, the material of the semiconductor layer is a metal oxide semiconductor material.

[0017] An embodiment of the present application also provides a semiconductor device, which includes a memory cell. The memory cell includes the semiconductor structure provided in the embodiment of the present application above, a plurality of bit lines, and a plurality of word lines, wherein the bit line is connected to the first electrode of the semiconductor structure, and the word line is connected to the gate electrode of the semiconductor structure.

[0018] For example,

[0019] The bit line may extend in a first direction parallel to the substrate.

[0020] Exemplarily, first electrodes of transistors of a column of memory cells spaced apart from each other along the first direction may be connected to the same bit line.

[0021] Exemplarily, the word line extends along a second direction which may be parallel to the substrate, and the second direction intersects the first direction.

[0022] Exemplarily, gate electrodes of transistors of a row of memory cells spaced apart along the second direction may be connected to the same word line.

[0023] The present application also provides a method for manufacturing a semiconductor device, the method comprising:

[0024] Depositing a first conductive layer on a substrate, and pattern-etching the first conductive layer to form a plurality of bit lines extending along a first direction and spaced apart in a second direction, wherein the first direction intersects the second direction;

[0025] Depositing an insulating layer and a second conductive layer in sequence on a side of the bit line away from the substrate;

[0026] Performing patterned etching on the second conductive layer to form a plurality of electrode regions distributed in an array along the first direction and the second direction;

[0027] Performing patterning on the electrode region to form a semiconductor layer extending in a direction perpendicular to the substrate, a gate electrode, and a gate insulating layer located between the semiconductor layer and the gate electrode;

[0028] An extension portion extending in a direction perpendicular to the substrate is formed on one side of each patterned electrode region, and the patterned electrode region and the extension portion are connected together to form a second electrode; the bit line is shared as a first electrode and the second electrode, the semiconductor layer and the gate electrode constitute a transistor.

[0029] Exemplarily, patterning and etching the second conductive layer to form a plurality of electrode regions distributed in an array along the first direction and the second direction may include:

[0030] Performing patterned etching on the second conductive layer, wherein the patterned second conductive layer includes a plurality of conductive regions distributed at intervals, and an orthographic projection of each bit line on the substrate and an orthographic projection of each conductive region of the patterned second conductive layer on the substrate have an overlapping area;

[0031] Depositing the insulating layer covering each of the conductive regions on the substrate;

[0032] The conductive region is pattern-etched to form a plurality of electrode regions that are spaced apart and distributed in an array along the first direction and the second direction.

[0033] Exemplarily, patterning the electrode region to form a semiconductor layer extending in a direction perpendicular to the substrate, a gate electrode, and a gate insulating layer located between the semiconductor layer and the gate electrode may include:

[0034] Performing patterned etching on the electrode region to form a first through hole penetrating the electrode region and extending in a direction perpendicular to the substrate, wherein the first through hole exposes the bit line, and an orthographic projection of the first through hole on the substrate falls within a range of an orthographic projection of the bit line on the substrate;

[0035] A semiconductor layer and a gate insulating layer are sequentially deposited on the inner wall of the first through hole, and a gate electrode is deposited in the first through hole.

[0036] Exemplarily, the width of the electrode region in parallel to the second direction is W1, the width of the bit line corresponding to the electrode region in the second direction is W2, and the aperture of the first through hole is D;

[0037] D≤W2<W1.

[0038] Exemplarily, the manufacturing method may further include, after forming the gate electrode, performing the following process:

[0039] Depositing an insulating layer covering the gate electrode and the semiconductor layer on the substrate;

[0040] Etching the insulating layer covering the gate electrode to expose the gate electrode;

[0041] Depositing a gate electrode material on the substrate to cover the exposed gate electrode;

[0042] The insulating layer and gate electrode material on the surface of the substrate are pattern-etched to form a word line connected to an end of the gate electrode away from the substrate.

[0043] Exemplarily, forming an extension portion extending in a direction perpendicular to the substrate on one side of each patterned electrode region includes:

[0044] Depositing an insulating layer covering the word line on the surface of the substrate;

[0045] Etching the insulating layer between two adjacent gate electrodes to form a second through hole in the insulating layer that exposes the electrode region of the second conductive layer, and making the orthographic projection of the second through hole on the substrate be within the range of the orthographic projection of the exposed electrode region on the substrate;

[0046] The second conductive layer is filled in the second through hole to obtain an extension portion located in the second through hole.

[0047] An embodiment of the present application further provides an electronic device, which includes the semiconductor structure or the semiconductor device provided in the above embodiment of the present application.

[0048] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or understood by practicing the present application. The objects and advantages of the present application can be realized and obtained by the structures particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0050] Figure 1A A schematic cross-sectional view of a semiconductor structure of an exemplary embodiment of the present application;

[0051] Figure 1B for Figure 1A A schematic longitudinal cross-sectional view of the semiconductor structure shown in the a-a' direction;

[0052] Figure 1C for Figure 1A A schematic longitudinal cross-sectional view of the semiconductor structure shown in the c-c' direction;

[0053] Figure 2A A cross-sectional view of a semiconductor device according to an exemplary embodiment of the present application;

[0054] Figure 2B for Figure 2A A schematic longitudinal cross-sectional view of the semiconductor device shown in the a-a' direction;

[0055] Figure 2C for Figure 2A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0056] Figure 2D for Figure 2A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0057] Figure 2E for Figure 2A A schematic longitudinal cross-sectional view of the semiconductor device shown in the d-d' direction;

[0058] Figure 3 A process flow chart of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application;

[0059] Figure 4A A schematic longitudinal cross-sectional view in the a-a' direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after forming a first conductive layer;

[0060] Figure 4B for Figure 4AA schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0061] Figure 4C for Figure 4A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0062] Figure 4D for Figure 4A A schematic longitudinal cross-sectional view of the semiconductor device shown in the d-d' direction;

[0063] Figure 5A A schematic longitudinal cross-sectional view in the aa' direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after forming a bit line;

[0064] Figure 5B for Figure 5A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0065] Figure 5C for Figure 5A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0066] Figure 5D for Figure 5A A schematic longitudinal cross-sectional view of the semiconductor device shown in the d-d' direction;

[0067] Fig. 6A A schematic longitudinal cross-sectional view in the a-a' direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after forming a second conductive layer;

[0068] Figure 6B for Fig. 6A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0069] Figure 6C for Fig. 6A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0070] Fig.6D for Fig. 6A A schematic longitudinal cross-sectional view of the semiconductor device shown in the d-d' direction;

[0071] Fig. 7A A schematic longitudinal cross-sectional view in the aa' direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after pattern etching is performed on the second conductive layer;

[0072] Figure 7B for Fig. 7A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0073] Figure 7C for Fig. 7A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0074] Fig.7D for Fig. 7A A schematic longitudinal cross-sectional view of the semiconductor device shown in the d-d' direction;

[0075] Fig. 8A A schematic longitudinal cross-sectional view in the a-a' direction after a first insulating layer is deposited on a conductive region in a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application;

[0076] Figure 8B for Fig. 8A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0077] Figure 8C for Fig. 8A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0078] Fig.8D for Fig. 8A A schematic longitudinal cross-sectional view of the semiconductor device shown in the d-d' direction;

[0079] Fig. 9A A schematic longitudinal cross-sectional view in the aa' direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after forming an electrode region;

[0080] Fig. 9B for Fig. 9A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0081] Fig. 9C for Fig. 9A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0082] Fig.9D for Fig. 9A A schematic longitudinal cross-sectional view of the semiconductor device shown in the d-d' direction;

[0083] Fig. 10A A schematic longitudinal cross-sectional view in the a-a' direction after a first insulating layer is deposited on an electrode region in a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application;

[0084] Fig. 10B for Fig. 10A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0085] Fig. 10C for Fig. 10AA schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0086] Fig. 10D for Fig. 10A A schematic longitudinal cross-sectional view of the semiconductor device shown in the d-d' direction;

[0087] Fig.11A A schematic longitudinal cross-sectional view of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after forming a through hole K in the aa' direction;

[0088] Fig. 11B for Fig.11A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0089] Fig. 11C for Fig.11A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0090] Fig.11D for Fig.11A A schematic longitudinal cross-sectional view of the semiconductor device shown in the d-d' direction;

[0091] Fig. 12A It is a schematic longitudinal cross-sectional view in the a-a' direction after a gate electrode is layered in a through hole K according to a method for manufacturing a semiconductor device of an exemplary embodiment of the present application;

[0092] Fig. 12B for Fig. 12A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0093] Fig. 12C for Fig. 12A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0094] Fig.12D for Fig. 12A A schematic longitudinal cross-sectional view of the semiconductor device shown in the d-d' direction;

[0095] Fig.13A A schematic longitudinal cross-sectional view in the a-a' direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after forming a word line;

[0096] Fig. 13B for Fig.13A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0097] Fig. 13C for Fig.13A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0098] Fig.13D for Fig.13A A schematic longitudinal cross-sectional view of the semiconductor device shown in the d-d' direction;

[0099] Fig.14A A schematic longitudinal cross-sectional view of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after forming a second through hole K2 in the aa' direction;

[0100] Fig. 14B for Fig.14A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0101] Fig. 14C for Fig.14A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0102] Fig.14D for Fig.14A The semiconductor device shown is a schematic longitudinal cross-sectional view along the d-d' direction.

[0103] The meanings of the symbols in the accompanying drawings are:

[0104] 10-substrate; 11-insulating layer; 12-first conductive layer; 13-second conductive layer; 21-first electrode; 22-second electrode; 221-surrounding portion; 222-extending portion; 23-electrode region; 30-semiconductor layer; 40-word line; 41-gate electrode; 42-gate insulating layer; 50-bit line; 60-memory cell; 61-transistor; K1-first through hole; K2-second through hole. DETAILED DESCRIPTION

[0105] In order to make the purpose, technical solution and advantages of the present application more clear, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.

[0106] The embodiments of the present application are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present application are not limited to the shapes or values ​​shown in the drawings.

[0107] The ordinal numbers such as "first" and "second" in this application are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0108] In this application, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on this application. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

[0109] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0110] In this application, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, a channel region refers to a region where current mainly flows.

[0111] In the present application, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present application, unless otherwise specified, the "source electrode" and the "drain electrode" may be interchanged.

[0112] In the present disclosure, "electrical connection" or "connection" includes situations where constituent elements are connected together through an element having some electrical function, such as electrical signal connection (coupled connection, such as coupled to), or physical direct connection. There is no particular limitation on "element having some electrical function" as long as it can transfer electrical signals between connected constituent elements. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0113] In this application, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

[0114] In some embodiments of the present application, "film" and "layer" can be interchanged. For example, "conductive layer" can sometimes be replaced with "conductive film". Similarly, "insulating film" can sometimes be replaced with "insulating layer".

[0115] The term "A and B are arranged in the same layer" in this application means that A and B are distributed on the same horizontal plane, or although not on the same horizontal plane, they are in different areas of the same support surface. In one embodiment, A and B are formed simultaneously by subjecting the same film layer to the same patterning process.

[0116] In the present application, "A and B are an integrated structure" may mean that there is no obvious boundary interface such as a fault or gap in the microstructure. Generally, a film layer patterned on a film layer to form a connection is an integrated structure. For example, A and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process, or B is directly grown on A by epitaxy, and the materials of the two may not be exactly the same.

[0117] In this application, "pore size" refers to the average pore size measured at multiple locations.

[0118] In the present application, the spacing distribution can be understood as separate distribution, which can be achieved by physical structure disconnection or electrical characteristic disconnection. For example, the semiconductor layer between the effective channels corresponding to the two transistors is modified to achieve insulation to achieve electrical spacing between the two channels.

[0119] An embodiment of the present application provides a semiconductor structure.

[0120] Figure 1A A schematic cross-sectional view of a semiconductor structure of an exemplary embodiment of the present application; Figure 1B for Figure 1A A schematic longitudinal cross-sectional view of the semiconductor structure shown in the a-a' direction; Figure 1C for Figure 1A The semiconductor structure shown is a schematic longitudinal cross-sectional view along the c-c' direction.

[0121] like Figures 1A to 1CAs shown, the semiconductor structure of the embodiment of the present application is disposed on a substrate 10 , and the semiconductor structure includes a first electrode 21 , a second electrode 22 , a semiconductor layer 30 and a gate electrode 41 .

[0122] The first electrode 21 is used to connect to the bit line 50;

[0123] The second electrode 22 includes a surrounding portion 221 and an extending portion 222; the surrounding portion 221 is used to connect to the semiconductor layer 30; the extending portion 222 extends in a direction perpendicular to the substrate 10, and is used to connect to an external circuit (for example, it can be a capacitor in a 1T1C or 2T1C memory cell, or include a read transistor and a storage node in a 1T0C or 2T0C memory cell);

[0124] The semiconductor layer 30 extends in a direction perpendicular to the substrate 10 , and at least a portion of the sidewall of the semiconductor layer 30 is surrounded by the surrounding portion 221 of the second electrode 22 ;

[0125] At least a portion of the sidewall of the gate electrode 41 is surrounded by the semiconductor layer 30 , and a gate insulating layer 42 for insulation is disposed between the gate electrode 41 and the semiconductor layer 30 .

[0126] The second electrode of the semiconductor structure of the embodiment of the present application includes a surrounding portion, and the surrounding portion adopts a surrounding structure surrounding the semiconductor layer, which can increase the contact area between the second electrode and the semiconductor layer, thereby improving the carrier transmission efficiency in the channel region.

[0127] For example, Figure 1B As shown, the semiconductor layer 30 is in contact with the surrounding portion 221 of the second electrode 22 .

[0128] like Figure 1B and Figure 1C As shown, the first electrode 21 and the second electrode 22 are spaced apart in a direction perpendicular to the substrate 10, that is, the first electrode 21 and the second electrode 22 are not on the same horizontal plane. Figure 1B and Figure 1C In the embodiment, the first electrode 21 is located below the second electrode 22, that is, the distance between the first electrode 21 and the substrate 10 is smaller than the distance between the extension portion 222 of the second electrode 22 and the substrate.

[0129] like Figures 1A to 1CAs shown, the surrounding portion 221 of the second electrode 22 has an opening, and the semiconductor layer 30 passes through the opening in a direction perpendicular to the substrate 10. Exemplarily, the semiconductor layer 30 passes through the opening from the first electrode 21 and is surrounded by the surrounding portion 221 in the corresponding area of ​​the opening. Here, the semiconductor layer 30 being "surrounded" by the surrounding portion 221 can be understood as being partially surrounded or fully surrounded. In some embodiments, the surrounding can be fully surrounded, that is, at least the entire side wall of the semiconductor layer 30 is surrounded by the surrounding portion 221, and the cross-section of the surrounding portion 221 after being surrounded is a closed ring, and the cross-section is parallel to the substrate. As shown in FIG. Figure 1A As shown, the entire circumferential sidewall of the semiconductor layer 30 is surrounded by the surrounding portion 221, and this surrounding also belongs to full surrounding. In some embodiments, the surrounding can be partial surrounding, that is, part of the sidewall of the semiconductor layer 30 is surrounded by the surrounding portion 221, and the cross-section after surrounding is not closed, but presents a ring shape. For example, a ring with an opening or two independent semiconductor layers. For example, the opposite side surfaces of the semiconductor layer 30 are surrounded by the surrounding portion 221, and the cross-section of the surrounding portion 221 is a ring with two openings.

[0130] It can be understood that “fully surrounding” means completely surrounding in the circumferential direction, and does not limit the extension degree of the surrounding portion in the vertical direction of the semiconductor layer.

[0131] like Figure 1A As shown, the sidewall of the gate electrode 41 is completely surrounded by the semiconductor layer 30, that is, the cross section of the region surrounding the gate electrode 41 in the semiconductor layer 30 is a closed ring, and the cross section is parallel to the substrate. In other embodiments, only part of the sidewall of the gate electrode 41 may be surrounded by the semiconductor layer 30, that is, the cross section of the region surrounding the gate electrode 41 in the semiconductor layer 30 is not closed, but presents a ring shape.

[0132] like Figure 1B and Figure 1C As shown, one end surface of the gate electrode 41 is used to be connected to the word line 40 , and the other end surface may be surrounded by the semiconductor layer 30 .

[0133] like Figure 1B and Figure 1C As shown, the gate electrode 41 extends in a direction perpendicular to the substrate 10, one end surface of the gate electrode 41 facing away from the substrate 10 is used to connect to the word line 40, and one end surface of the gate electrode 41 close to the substrate 10 is surrounded by the semiconductor layer 30. Figures 1A to 1C As shown, the semiconductor layer 30 surrounding the gate electrode 41 forms a hollow cylindrical structure; the cylindrical structure has a side surface, a bottom surface and an opening, the side surface is surrounded and contacted by the surrounding portion 221 of the second electrode 22, the bottom surface is in contact with the first electrode, and the area on the side of the cylindrical structure located between the first electrode and the second electrode is the channel region.

[0134] like Figure 1B and Figure 1C As shown, the gate insulating layer 42 is located on the inner wall of the tubular structure, and the gate electrode 41 is filled in the tubular structure.

[0135] like Figures 1A to 1C As shown, the side surfaces of the semiconductor layer 30 having a hollow cylindrical structure include four surfaces that are opposite to each other, that is, the four side surfaces of the semiconductor layer 30 can all transmit carriers, thereby increasing the on-state current of the semiconductor device.

[0136] like Figure 1B and Figure 1C As shown, the end surface of the gate electrode 41 extends through the opening of the tubular structure to the bottom surface of the tubular structure, and the gate electrode 41 is insulated from the tubular structure by a gate insulating layer 42 .

[0137] For example, the bit line 50 may extend along a first direction parallel to the substrate 10, and the first direction may be as follows: Figure 1A a-a' direction shown.

[0138] like Figure 1B and Figure 1C As shown, the first electrode 21 and the bit line 50 of the semiconductor structure can be an integrated structure, or the first electrode 21 and part of the bit line 50 can be shared, that is, the area where the bit line 50 contacts the semiconductor layer 30 can be shared as the first electrode 21 .

[0139] For example, the word line 40 may extend along a second direction parallel to the substrate 10; the second direction parallel to the substrate 10 may be understood as a lateral direction, for example, Figure 1A c-c' direction shown.

[0140] The substrate in the embodiment of the present application can be a supporting structure, such as a silicon substrate, or a supporting structure on which other film layers or functions or circuits are already distributed. The device involved in the inventive structure of the embodiment of the present application is arranged on the upper main surface of the supporting structure.

[0141] The semiconductor layer 30 can be understood as a semiconductor material, and its shape and structure are not emphasized here, but only its function is emphasized.

[0142] In an exemplary embodiment of the present application, the material of the semiconductor layer may be a material such as silicon or polysilicon with a band gap less than 1.65 eV, or a wide band gap material such as a metal oxide material with a band gap greater than 1.65 eV.

[0143] For example, the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may contain compounds of other elements, such as N, Si, etc., and may contain other small amounts of doping elements.

[0144] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InW O, IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials. As long as the leakage current of the transistor can meet the requirements, the specific adjustment can be made according to the actual situation.

[0145] These materials have a wide band gap and a low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A, thereby the operating performance of the semiconductor device can be improved, for example, the semiconductor device can have a longer refresh time.

[0146] The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic proportion in the material and the film quality of the material.

[0147] In an exemplary embodiment of the present application, the electrode material of the gate electrode may be any one or more of the following different types of materials:

[0148] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

[0149] It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as metal oxide materials with high conductivity such as indium tin oxide ITO, indium zinc oxide IZO, indium oxide InO, etc.; for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc.;

[0150] Of course, it can also be polysilicon material; it can also be conductive material doped semiconductor material, such as conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc.; other materials that embody conductivity, etc.

[0151] In an exemplary embodiment of the present application, the material of the gate insulating layer may include one or more layers of Low-K and / or High-K dielectric materials, or include two or more regions with different dielectric constants K. The characteristics of the gate insulating layer of the present application will be exemplarily described below;

[0152] Among them, Low-K materials, such as silicon oxide;

[0153] High-K materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, oxides of one or more of hafnium, aluminum, lanthanum, zirconium, etc. may be included. For example, at least one of the following may be included but is not limited to: hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other high-K materials.

[0154] An embodiment of the present application also provides a semiconductor device.

[0155] Figure 2A A cross-sectional view of a semiconductor device according to an exemplary embodiment of the present application; Figure 2B for Figure 2A A schematic longitudinal cross-sectional view of the semiconductor device shown in the a-a' direction; Figure 2C for Figure 2A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction; Figure 2D for Figure 2A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction; Figure 2E for Figure 2A The semiconductor device shown is a schematic longitudinal cross-sectional view along the d-d' direction.

[0156] like FIG. 2A to FIG. 2EAs shown, the semiconductor device includes at least one memory cell 60 located on a substrate 10, the memory cell 60 includes a transistor 61, and the transistor 61 includes a first electrode 21, a second electrode 22, a semiconductor layer 30 and a gate electrode 41;

[0157] Wherein, the first electrode 21 is used to connect with the bit line 50;

[0158] The second electrode 22 includes a surrounding portion 221 and an extending portion 222; the surrounding portion 221 is used to connect to the semiconductor layer 30; the extending portion 222 extends in a direction perpendicular to the substrate 10, and is used to connect to an external circuit (for example, a capacitor in a 1T1C or 2T1C memory cell, or a read transistor and a storage node in a 1T0C or 2T0C memory cell);

[0159] The semiconductor layer 30 extends in a direction perpendicular to the substrate 10 , and at least a portion of the sidewall of the semiconductor layer 30 is surrounded by the extension portion 222 of the second electrode 22 ;

[0160] At least a portion of the sidewall of the gate electrode 41 is surrounded by the semiconductor layer 30 , and a gate insulating layer 42 for insulation is disposed between the gate electrode 41 and the semiconductor layer 30 .

[0161] Illustratively, the transistor 61 in the semiconductor device may be a semiconductor structure as provided in the above embodiment of the present application.

[0162] Exemplarily, the first electrode 21 and the second electrode 22 are spaced apart from each other in a direction perpendicular to the substrate 10 .

[0163] Exemplarily, the surrounding portion 221 of the second electrode 22 has an opening, and the semiconductor layer 30 passes through the opening in a direction perpendicular to the substrate 10 . For example, the semiconductor layer 30 passes through the opening from the first electrode 21 and is surrounded by the surrounding portion 221 in a region corresponding to the opening.

[0164] Exemplarily, at least a portion of the sidewall of the gate electrode 41 is surrounded by the semiconductor layer 30 . For example, the entire sidewall of the gate electrode 41 is completely surrounded by the semiconductor layer 30 .

[0165] Exemplarily, an end surface of the gate electrode 41 may be surrounded by the semiconductor layer 30 .

[0166] Exemplarily, the semiconductor layer 30 surrounding the gate electrode 41 forms a hollow cylindrical structure; the cylindrical structure has side surfaces, a bottom surface and an opening, the side surfaces are surrounded and contacted by the surrounding portion 221 of the second electrode 22, the bottom surface is in contact with the first electrode, and the area on the side surface of the cylindrical structure located between the first electrode and the second electrode is a channel region.

[0167] Exemplarily, an end surface of the gate electrode 41 extends through the opening of the tubular structure to the bottom surface of the tubular structure, and the gate electrode 41 is insulated from the tubular structure by a gate insulating layer 42 .

[0168] For example, Figure 2A As shown, the semiconductor device includes a plurality of memory cells 60, and the plurality of memory cells 60 are distributed in an array on a substrate 10 along a first direction and a second direction parallel to the substrate 10. The first direction and the second direction intersect each other, for example, the first direction and the second direction may be perpendicular to each other. For example, the first direction may be as follows Figure 1A The a-a' direction or the b-b' direction shown in FIG. 1 , the second direction may be as follows Figure 1A The c-c' direction or the d-d' direction shown.

[0169] For example, Figures 2A to 2E As shown, the semiconductor device may further include a bit line 50 , and the bit line 50 is connected to the first electrode 21 of the transistor.

[0170] For example, Figure 2B As shown, the first electrode 21 of the transistor and the bit line 50 connected thereto may be an integrated structure, or the first electrode 21 and the bit line 50 connected thereto may be shared.

[0171] For example, Figure 2B As shown, the bit line 50 may extend along the first direction; the first electrodes 21 of transistors of a column of memory cells spaced apart along the first direction may be connected to the same bit line 50 .

[0172] Exemplarily, the material of the bit line can be selected from any one or more of other metal materials with similar properties such as tungsten, molybdenum, cobalt, etc. The bit line can be a single-layer or multi-layer structure, for example, a multi-layer structure formed of titanium (Ti), titanium nitride (TiN) and tungsten (W).

[0173] For example, Figures 2A to 2E As shown, the semiconductor device may further include a word line 40 , and the word line 40 is connected to a gate electrode 41 of the transistor.

[0174] For example, Figure 2B As shown, the word line 40 may extend along the second direction; the gate electrodes 41 of transistors of a row of memory cells spaced apart along the second direction may be connected to the same word line 40 , or the gate electrodes 41 may be regarded as part of the word line 40 .

[0175] The above-mentioned memory cell may be a memory cell including a transistor, wherein the transistor may be an access transistor, and the memory cell may further include other components, such as a capacitor in a 1T1C or 2T1C memory cell, or a read transistor and a storage node in a 1T0C or 2T0C memory cell.

[0176] Exemplarily, the storage cell may further include a capacitor, which includes an inner electrode, an outer electrode and a dielectric layer located between the inner electrode and the outer electrode, the inner electrode of the capacitor being connected to a second electrode of a transistor located in the same storage cell, for example, to an extension of the second electrode.

[0177] The material of the dielectric layer may be silicon oxide or a High-K dielectric material, that is, a dielectric material with a dielectric constant K ≥ 3.9. The High-K dielectric material may include but is not limited to at least one of the following: aluminum oxide (Al 2 O 3 ), hafnium oxide.

[0178] Exemplarily, the semiconductor device may be a memory, such as a DRAM, etc. The memory may have a 1T1C or 2T1C structure, or may have a 1T0C or 2T0C (including a read transistor and a write transistor) structure.

[0179] The embodiment of the present application also provides a method for manufacturing a semiconductor device. The semiconductor device provided in the embodiment of the present application as above can be manufactured by this method.

[0180] Figure 3 The present invention is a process flow chart of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application.

[0181] like Figure 3 As shown, the manufacturing method comprises:

[0182] Depositing a first conductive layer on a substrate, and pattern-etching the first conductive layer to form a plurality of bit lines extending along a first direction and spaced apart in a second direction, wherein the first direction intersects the second direction;

[0183] Depositing an insulating layer and a second conductive layer in sequence on a side of the bit line away from the substrate;

[0184] Performing patterned etching on the second conductive layer to form a plurality of electrode regions distributed in an array along the first direction and the second direction;

[0185] Performing patterning on the electrode region to form a semiconductor layer extending in a direction perpendicular to the substrate, a gate electrode, and a gate insulating layer located between the semiconductor layer and the gate electrode;

[0186] An extension portion extending in a direction perpendicular to the substrate is formed on one side of each patterned electrode region, and the patterned electrode region and the extension portion are connected together to form a second electrode; the bit line is shared as a first electrode and the second electrode, the semiconductor layer and the gate electrode constitute a transistor.

[0187] Exemplarily, patterning and etching the second conductive layer to form a plurality of electrode regions distributed in an array along the first direction and the second direction may include:

[0188] Performing patterned etching on the second conductive layer, wherein the patterned second conductive layer includes a plurality of conductive regions distributed at intervals, and making the orthographic projection of each bit line on the substrate fall within the range of the orthographic projection of each conductive region of the patterned second conductive layer on the substrate;

[0189] Depositing the insulating layer covering each of the conductive regions on the substrate;

[0190] The conductive region is pattern-etched to form a plurality of electrode regions that are spaced apart and distributed in an array along the first direction and the second direction.

[0191] Exemplarily, patterning the electrode region to form a semiconductor layer extending in a direction perpendicular to the substrate, a gate electrode, and a gate insulating layer located between the semiconductor layer and the gate electrode may include:

[0192] Performing patterned etching on the electrode region to form a first through hole penetrating the electrode region and extending in a direction perpendicular to the substrate, wherein the first through hole exposes the bit line, and an orthographic projection of the first through hole on the substrate falls within a range of an orthographic projection of the bit line on the substrate;

[0193] A semiconductor layer and a gate insulating layer are sequentially deposited on the inner wall of the first through hole, and a gate electrode is deposited in the first through hole.

[0194] Exemplarily, the width of the electrode region in parallel to the second direction is W1, the width of the bit line corresponding to the electrode region in the second direction is W2, and the aperture of the first through hole is D;

[0195] D≤W2<W1.

[0196] Exemplarily, the manufacturing method may further include, after forming the gate electrode, performing the following process:

[0197] Depositing an insulating layer covering the gate electrode and the semiconductor layer on the substrate;

[0198] Etching the insulating layer covering the gate electrode to expose the gate electrode;

[0199] Depositing a gate electrode material on the substrate to cover the exposed gate electrode;

[0200] The insulating layer and gate electrode material on the surface of the substrate are pattern-etched to form a word line connected to an end of the gate electrode away from the substrate.

[0201] Exemplarily, forming an extension portion extending in a direction perpendicular to the substrate on one side of each patterned electrode region includes:

[0202] Depositing an insulating layer covering the word line on the surface of the substrate;

[0203] Etching the insulating layer between two adjacent gate electrodes to form a second through hole in the insulating layer that exposes the electrode region of the second conductive layer, and making the orthographic projection of the second through hole on the substrate be within the range of the orthographic projection of the exposed electrode region on the substrate;

[0204] The second conductive layer is filled in the second through hole to obtain an extension portion located in the second through hole, and the extension portions of each transistor to be formed are spaced apart.

[0205] The technical solution of the embodiment of the present application is further explained below through the manufacturing process of the semiconductor device of the exemplary embodiment. The "patterned etching" mentioned in this embodiment includes deposition of film layers, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which is a mature preparation process in the relevant technology. The "photolithography" process mentioned in this embodiment includes coating of film layers, mask exposure and development, which is a mature preparation process in the relevant technology. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, etc., coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here.

[0206] 4A to 14D Schematic diagram of longitudinal sections of a device structure obtained in each step of a method for manufacturing a semiconductor device of an exemplary embodiment of the present application in directions a-a', b-b', c-c', and d-d'.

[0207] like 4A to 14D As shown, in an exemplary embodiment of the present application, the method for manufacturing the semiconductor device may include the following processes.

[0208] S10: providing a substrate 10, depositing an insulating layer 11 and a first conductive layer 12 on the substrate 10, and planarizing the first conductive layer 12 by a chemical mechanical polishing (CMP) process and controlling the thickness of the first conductive layer 12, such as 4A to 4D shown.

[0209] In an exemplary embodiment of the present application, the material of the insulating layer may be a low-K dielectric material, that is, a dielectric material with a dielectric constant K<3.9, including but not limited to silicon oxides, such as silicon dioxide (SiO 2 ) or other silicon-containing films, etc.

[0210] In an exemplary embodiment of the application, the material of the first conductive layer may be any one or more of a conductive metal, a nitride of a conductive metal, and polysilicon (Poly); the conductive metal includes but is not limited to tungsten (W), cobalt (Co), titanium (Ti), etc. The first conductive layer may be a single layer or a multilayer structure, for example, it may be a multilayer structure formed by Ti, TiN, and W. For example, Ti, TiN, and W may be deposited in sequence on the side of the insulating layer 11 away from the substrate 10 to form a first conductive layer 12 of a multilayer structure. Providing TiN between the side of W close to the substrate 10 and the insulating layer 11 can prevent W from being oxidized by the oxygen-containing insulating layer 11, so the film layer formed by TiN can be called an anti-oxidation layer. Of course, the insulating layer may be an oxygen-free film layer, and then the first conductive layer does not need to be added with an anti-oxidation layer.

[0211] In an exemplary embodiment of the present application, Ti may be deposited by a chemical vapor deposition (CVD) process; TiN may be deposited by an atomic layer deposition (ALD) process; and W may be deposited by a CVD or ALD process.

[0212] S20 : ​​performing patterning and etching on the first conductive layer 12 to form a bit line 50 .

[0213] Exemplarily, step S20 may include: using photolithography to define a photolithography pattern, using dry etching to pattern the first conductive layer 12, wherein the patterned first conductive layer 12 includes a plurality of spaced-apart bit lines 50, and the bit lines 50 are also used as first electrodes of transistors to be formed, such as FIG. 5A to FIG. 5D shown.

[0214] S30 : depositing an insulating layer 11 and a second conductive layer 13 in sequence on a side of the patterned first conductive layer 12 away from the substrate 10 .

[0215] Exemplarily, step S30 may include: after depositing the insulating layer 11 on the side of the patterned first conductive layer 12 away from the substrate 10, using a CMP process to planarize the surface of the insulating layer 11 and control the thickness of the insulating layer 11; and after depositing the second conductive layer 13, using a CMP process to planarize the surface of the second conductive layer 13 and control the thickness of the second conductive layer 13, such as FIG. 6A to FIG. 6D shown.

[0216] Exemplarily, the material of the second conductive layer may be any one or more of a conductive metal, a nitride of a conductive metal, and polysilicon (Poly); the conductive metal includes but is not limited to tungsten (W), cobalt (Co), titanium (Ti), etc.; the material of the second conductive layer and the first conductive layer may be the same or different, for example, both may be W. The second conductive layer may be a single layer or a multilayer structure, for example, a multilayer structure formed of Ti, TiN, and W. For example, Ti, TiN, and W may be sequentially deposited on the side of the insulating layer 11 away from the substrate 10 to form a second conductive layer 13 of a multilayer structure.

[0217] S40: The second conductive layer 13 is patterned and etched, wherein the patterned second conductive layer 13 includes a plurality of conductive regions distributed at intervals, and the orthographic projection of each bit line 50 on the substrate 10 falls within the range of the orthographic projection of each conductive region of the patterned second conductive layer 13 on the substrate 10, such as 7A to 7D shown.

[0218] Exemplarily, step S40 may include: using photolithography to define a photolithography pattern, and using dry etching to pattern the second conductive layer 13 so that the second conductive layer 13 is Figure 2A The c-c' direction and d-d' direction shown are disconnected; the patterned second conductive layer 13 includes a plurality of conductive regions distributed at intervals, and the orthographic projections of each bit line 50 on the substrate 10 fall within the range of the orthographic projections of each conductive region of the patterned second conductive layer 13 on the substrate 10, and the orthographic projections of different bit lines 50 on the substrate 10 fall within the range of the orthographic projections of different conductive regions on the substrate 10. For example, the width W1 of the conductive region in the second direction parallel to the substrate 10 can be made greater than the width W2 of the bit line 50 corresponding to the conductive region in the second direction, that is, W1≥W2.

[0219] Each conductive region may extend along the extension direction of the corresponding bit line 50. For example, each conductive region and the bit line 50 may extend along a first direction parallel to the substrate 10. The first direction and the second direction may intersect. For example, the first direction and the second direction may be perpendicular to each other. For another example, the first direction may be as follows: Figure 2B The a-a' direction or the b-b' direction shown in FIG. 1 , the second direction may be as follows Figure 2B The c-c' direction or the d-d' direction shown.

[0220] S50: depositing an insulating layer 11 covering each conductive region on the substrate 10, and planarizing the surface of the insulating layer 11 by a CMP process and controlling the thickness of the insulating layer 11, such as FIG. 8A to FIG. 8D shown.

[0221] S60: performing patterned etching on the conductive regions of the second conductive layer 13 so that each conductive region is disconnected in the first direction to form a plurality of electrode regions 23 spaced apart and distributed along the first direction.

[0222] Exemplarily, step S60 may include: using photolithography to define a photolithography pattern, using dry etching to pattern each conductive region of the second conductive layer 13, etching to form a groove extending along the second direction on the conductive region, the groove runs through each conductive region so that each conductive region is disconnected in the first direction, and a plurality of electrode regions 23 are formed that are spaced apart and distributed along the first direction, such as 9A to 9D shown.

[0223] Each electrode region 23 may be located at Figure 2A The intersection of the a-a' direction and the c-c' direction shown.

[0224] S70: depositing an insulating layer 11 covering each electrode region 23 on the substrate 10, and planarizing the surface of the insulating layer 11 by a CMP process and controlling the thickness of the insulating layer 11, such as FIG. 10A to FIG. 10D shown.

[0225] S80: etching each electrode region 23 of the second conductive layer 13 along the direction toward the substrate 10 to form a first through hole K1 penetrating each electrode region 23, wherein the first through hole K1 exposes the bit line 50, as shown in FIG. FIG. 11A to FIG. 11D shown.

[0226] Exemplarily, the orthographic projection of the first through hole K1 on the substrate 10 falls within the range of the orthographic projection of the bit line 50 on the substrate 10. For example, the aperture D of the first through hole K1 can be made smaller than the width W1 of the electrode region 23 where it is located in the second direction parallel to the substrate 10 (the width of the electrode region 23 in the second direction parallel to the substrate 10 is equal to the width W1 of the conductive region in the second direction parallel to the substrate 10 before the electrode region 23 is formed). D<W1, so that the first through hole K1 can be completely surrounded by the electrode region 23 after etching, and the etched electrode region 23 is subsequently used to form the second electrode 22 of the transistor.

[0227] Exemplarily, the diameter D of the first through hole K1 does not exceed the width W2 of the corresponding bit line 50 in the second direction, that is, D≤W2.

[0228] Since W1≥W2, D<W1, D≤W2, therefore D≤W2<W1.

[0229] The first through hole K1 is used to accommodate the semiconductor layer of the transistor to be formed subsequently. When D=W2, the contact area between the semiconductor layer of the transistor and the first electrode (bit line) is large, and the carrier transfer efficiency in the channel region is high. Therefore, in order to obtain a higher carrier transfer efficiency, D=W2<W1 can be selected.

[0230] Exemplarily, the first through hole K1 extends to a surface of the bit line 50 away from the substrate 10 or extends to the inside of the bit line 50. The first through hole K1 may extend in a direction perpendicular to the substrate 10.

[0231] For example, Fig.11A As shown, the distances between the sidewalls of the first through hole K1 and the edges of the electrode region 23 located therein on the two opposite sides in the first direction are different, that is, the widths of the rings of the annular electrode region 23 formed by the first through hole K1 are different. For example, Fig.11A As shown, the width of the annular electrode region 23 is smaller on the left side and larger on the right side, which is conducive to forming an extension portion of the second electrode on the side with a larger ring width.

[0232] S90 : depositing a semiconductor layer 30 and a gate insulating layer 42 in sequence on the inner wall of the first through hole K1 , and filling a gate electrode 41 in the first through hole K1 .

[0233] Exemplarily, step S09 may include:

[0234] S91: depositing a semiconductor layer 30 and a gate insulating layer 42 on the inner wall of the first through hole K1 in sequence, filling the first through hole K1 with a gate electrode material, and planarizing the gate electrode material on the surface of the substrate 10 by a CMP process so as to expose the gate insulating layer 42. The gate electrode material in the first through hole K1 forms a gate electrode 41 of the transistor;

[0235] S92: etching and removing the semiconductor layer 30 and the gate insulating layer 42 on the surface of the substrate 10, for example, wet etching can be used; then the insulating layer 11 is deposited on the surface of the substrate 10, and the surface of the insulating layer 11 is planarized by a CMP process and the thickness of the insulating layer 11 is controlled, such as FIG. 12A to FIG. 12D shown.

[0236] S100 : forming a word line 40 connected to the gate electrode 41 .

[0237] Exemplarily, step S100 may include:

[0238] S101: etching the insulating layer 11 covering the gate electrode 41 to expose the gate electrode 41;

[0239] S102: depositing a gate electrode material covering the exposed gate electrode 41 on the substrate 10, and planarizing the gate electrode material on the surface of the substrate 10 by a CMP process and controlling the thickness of the gate electrode material on the surface of the substrate 10;

[0240] S103: patterning and etching the insulating layer 11 and the gate electrode material on the surface of the substrate 10 by photolithography and dry etching to form a word line 40 connected to the end of the gate electrode 41 away from the substrate 10, the word line 40 extending along the second direction, and a column of gate electrodes 41 spaced apart along the second direction are connected to the same word line 40, such as FIG. 13A to FIG. 13D shown.

[0241] S110 : forming a second electrode 22 extending in a direction perpendicular to the substrate 10 on one side of the electrode region 23 .

[0242] Exemplarily, step S110 may include:

[0243] S111: depositing an insulating layer 11 covering the word line 40 on the surface of the substrate 10, and planarizing the surface of the insulating layer 11 by a CMP process and controlling the thickness of the insulating layer 11;

[0244] S112: Etching the insulating layer 11 between two adjacent gate electrodes 41 to form a second through hole K2 in the insulating layer 11 to expose the electrode region 23 of the second conductive layer 13. FIG. 14A to FIG. 14D As shown;

[0245] S113: Fill the second conductive layer in the second through hole K2 to form an extension portion 222 of the second electrode 22 to be formed, and the patterned electrode region 23 penetrated by the first through hole K1 serves as the surrounding portion 221 of the second electrode 22. The surrounding portion 221 and the extension portion 222 constitute the second electrode 22. FIG. 2A to FIG. 2D The semiconductor device shown.

[0246] Exemplarily, step S112 may include: using photolithography and etching methods to etch the insulating layer 11 located between two adjacent gate electrodes 41 along the first direction, forming a second through hole K2 in the insulating layer 11 that exposes the electrode region 23 of the second conductive layer 13, and making the orthographic projection of the second through hole K2 on the substrate 10 located within the range of the orthographic projection of the exposed electrode region 23 on the substrate 10. For example, each second through hole K2 can expose the side of the annular electrode region 23 with a larger width.

[0247] Exemplarily, step S113 may include: filling the second conductive layer in the second through hole K2, and flattening the second conductive layer by CMP process to expose the insulating layer 11; then depositing the insulating layer 11 covering the exposed insulating layer 11 and the second through hole K2 on the substrate 10; etching the insulating layer 11 covering the second through hole K2 by photolithography and dry etching to expose the extension 222 located in the second through hole K2. This step can separate the extensions 222 of each transistor to achieve insulation. The exposed extension 222 can be used to connect to the capacitor in the semiconductor device.

[0248] Exemplarily, the insulating layers deposited in each step may be the same or different, and their function is to perform insulation, as long as this function is achieved. For example, the insulating layers deposited in steps S10 to S112 may be formed of silicon oxide, and the insulating layer deposited in step S113 may be formed of silicon nitride.

[0249] Exemplarily, the manufacturing method may further include, after step S110 , forming a capacitor connected to the extension portion 222 of the second electrode 22 .

[0250] An embodiment of the present application further provides an electronic device, which includes the transistor or the semiconductor device provided in the above embodiment of the present application.

[0251] In an exemplary embodiment of the present application, the electronic device may be: a storage device, a smart phone, a computer, a tablet, an artificial intelligence device, a wearable device, or a mobile power supply, etc. The storage device may include a memory in a computer, etc., which is not limited here.

[0252] Although the embodiments disclosed in this application are as above, the contents described are only embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any technician in the field to which this application belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be based on the scope defined in the attached claims.

Claims

1. A semiconductor structure, characterized in that: include: A first electrode, used to be connected to a bit line; A second electrode including a surrounding portion and an extending portion; The extension portion extends in a direction perpendicular to the substrate; A semiconductor layer extending in a direction perpendicular to the substrate; At least a portion of the sidewall of the semiconductor layer is surrounded by the surrounding portion; A gate electrode, at least a portion of the sidewall of the gate electrode is surrounded by the semiconductor layer, and a gate insulating layer for insulation is arranged between the gate electrode and the semiconductor layer.

2. The semiconductor structure according to claim 1, characterized in that: The first electrode and the second electrode are spaced apart from each other in a direction perpendicular to the substrate.

3. The semiconductor structure according to claim 1, characterized in that: The surrounding portion of the second electrode has an opening, and the semiconductor layer penetrates the opening in a direction perpendicular to the substrate.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The gate electrode extends in a direction perpendicular to the substrate, an end surface of the gate electrode facing away from the substrate is used for connecting to a word line, and an end surface of the gate electrode close to the substrate is surrounded by the semiconductor layer.

5. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The semiconductor layer surrounding the gate electrode forms a hollow cylindrical structure; the cylindrical structure has side surfaces, a bottom surface and an opening, the side surfaces are surrounded and contacted by the surrounding portion of the second electrode, the bottom surface is in contact with the first electrode, the area on the side surface of the cylindrical structure located between the first electrode and the second electrode is a channel region, the channel region extends in a direction perpendicular to the substrate, and the gate electrode is filled in the cylindrical structure.

6. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The material of the semiconductor layer is a metal oxide semiconductor material.

7. A semiconductor device, characterized in that: It comprises a plurality of memory cells arranged in an array, wherein the memory cells comprise a semiconductor structure according to any one of claims 1 to 6, a plurality of bit lines, and a plurality of word lines, wherein the bit lines are connected to the first electrode of the semiconductor structure, and the word lines are connected to the gate electrode of the semiconductor structure.

8. The semiconductor device according to claim 7, characterized in that The bit line extends along a first direction parallel to the substrate; and / or, The first electrodes of the transistors of a column of the memory cells spaced apart along the first direction are connected to the same bit line; and / or, The word line extends along a second direction parallel to the substrate, the second direction intersecting the first direction; and / or, The gate electrodes of the transistors of a row of the memory cells spaced apart from each other along the second direction are connected to the same word line.

9. A method for manufacturing a semiconductor device, characterized in that: include: Depositing a first conductive layer on a substrate, and pattern-etching the first conductive layer to form a plurality of bit lines extending along a first direction and spaced apart in a second direction, wherein the first direction intersects the second direction; Depositing an insulating layer and a second conductive layer in sequence on a side of the bit line away from the substrate; Performing patterned etching on the second conductive layer to form a plurality of electrode regions distributed in an array along the first direction and the second direction; Performing patterning on the electrode region to form a semiconductor layer extending in a direction perpendicular to the substrate, a gate electrode, and a gate insulating layer located between the semiconductor layer and the gate electrode; An extension portion extending in a direction perpendicular to the substrate is formed on one side of each patterned electrode region, and the patterned electrode region and the extension portion are connected together to form a second electrode; The bit line is used as a first electrode and the second electrode, the semiconductor layer, and the gate electrode to form a transistor.

10. The manufacturing method according to claim 9, characterized in that: The second conductive layer is patterned and etched to form a plurality of electrode regions distributed in an array along the first direction and the second direction, comprising: Performing patterned etching on the second conductive layer, wherein the patterned second conductive layer includes a plurality of conductive regions distributed at intervals, and an orthographic projection of each bit line on the substrate and an orthographic projection of each conductive region of the patterned second conductive layer on the substrate have an overlapping area; Depositing the insulating layer covering each of the conductive regions on the substrate; The conductive region is pattern-etched to form a plurality of electrode regions that are spaced apart and distributed in an array along the first direction and the second direction.

11. The manufacturing method according to claim 10, characterized in that: The electrode region is patterned to form a semiconductor layer extending in a direction perpendicular to the substrate, a gate electrode, and a gate insulating layer located between the semiconductor layer and the gate electrode, comprising: Performing patterned etching on the electrode region to form a first through hole penetrating the electrode region and extending in a direction perpendicular to the substrate, wherein the first through hole exposes the bit line, and an orthographic projection of the first through hole on the substrate falls within a range of an orthographic projection of the bit line on the substrate; A semiconductor layer and a gate insulating layer are sequentially deposited on the inner wall of the first through hole, and a gate electrode is deposited in the first through hole.

12. The manufacturing method according to claim 11, characterized in that: The width of the electrode region parallel to the second direction is W1, the width of the bit line corresponding to the electrode region in the second direction is W2, and the aperture of the first through hole is D; D≤W2<W1.

13. The manufacturing method according to any one of claims 9 to 12, characterized in that: The method further comprises performing the following process after forming the gate electrode: Depositing an insulating layer covering the gate electrode and the semiconductor layer on the substrate; Etching the insulating layer covering the gate electrode to expose the gate electrode; Depositing a gate electrode material on the substrate to cover the exposed gate electrode; The insulating layer and gate electrode material on the surface of the substrate are pattern-etched to form a word line connected to an end of the gate electrode away from the substrate.

14. The manufacturing method according to claim 13, characterized in that: Forming an extension portion extending in a direction perpendicular to the substrate on one side of each patterned electrode region comprises: Depositing an insulating layer covering the word line on the surface of the substrate; Etching the insulating layer between two adjacent gate electrodes to form a second through hole in the insulating layer that exposes the electrode region of the second conductive layer, and making the orthographic projection of the second through hole on the substrate be within the range of the orthographic projection of the exposed electrode region on the substrate; The second conductive layer is filled in the second through hole to obtain an extension portion located in the second through hole.

15. An electronic device, characterized in that: The method comprises the semiconductor structure according to any one of claims 1 to 6, or comprises the semiconductor device according to claim 7 or 8.

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