Semiconductor memory device

Abstract

A semiconductor memory device is provided. The semiconductor memory device includes a first bit line extending in a first direction on a substrate, a word line extending on the first bit line and in a second direction crossing the first direction, a first channel pattern extending between the first bit line and the word line and along a first sidewall of the word line, and a first contact pattern on the first channel pattern, wherein, in a cross-sectional view taken along the first channel pattern in the second direction, the first contact pattern includes a connecting portion on the first channel pattern and a protruding portion connected to the connecting portion and extending along a sidewall of the first channel pattern.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a vertical channel transistor (VCT). Background Art

[0002] It may be desirable to increase the integration level of semiconductor memory devices to provide superior performance and low prices sought by consumers. In the case of semiconductor memory devices, increasing the integration level may be particularly desirable because the integration level is an important factor in determining the price of the product.

[0003] In the case of a two-dimensional or planar semiconductor memory device, the integration level is mainly determined by the area occupied by the unit memory cell and is therefore greatly affected by the level of fine pattern formation technology. However, since ultra-expensive equipment may be required to miniaturize the pattern, the integration level of two-dimensional semiconductor memory devices is increasing, but is still limited. Therefore, a semiconductor memory device including a vertical channel transistor whose channel extends in the vertical direction has been proposed as a method of increasing the integration level. Summary of the invention

[0004] Aspects of the present disclosure provide a semiconductor memory device having improved integration and electrical characteristics.

[0005] According to one aspect of the present disclosure, a semiconductor memory device is provided, comprising: a first bit line extending in a first direction on a substrate; a word line extending in a second direction intersecting the first direction on the first bit line; a first channel pattern extending between the first bit line and the word line and along a first side wall of the word line; and a first contact pattern on the first channel pattern, wherein in a cross-sectional view taken along the first channel pattern in the second direction, the first contact pattern includes a connecting portion on the first channel pattern and a protruding portion connected to the connecting portion and extending along the side wall of the first channel pattern.

[0006] According to one aspect of the present disclosure, a semiconductor device is provided, comprising: a first bit line extending in a first direction on a substrate; a word line extending in a second direction intersecting the first direction on the first bit line; a first channel pattern between the first bit line and the word line and extending in a third direction intersecting the first direction and the second direction along a first side wall of the word line; a first contact pattern on the first channel pattern; a second bit line spaced apart from the first bit line in the second direction and extending in the first direction; a second channel pattern between the second bit line and the word line, spaced apart from the first channel pattern in the second direction, and extending in the third direction along the first side wall of the word line; a second contact pattern on the second channel pattern; and an insulating pattern between the first channel pattern and the second channel pattern, wherein the insulating pattern comprises a first portion and a second portion, the first portion being between the first contact pattern and the second contact pattern, the second portion being below the first portion and between the first channel pattern and the second channel pattern relative to a substrate providing a base reference plane, and wherein a width of the first portion is smaller than a width of the second portion.

[0007] According to one aspect of the present disclosure, a semiconductor device is provided, comprising: a first bit line extending in a first direction on a substrate; a word line extending on the first bit line and in a second direction intersecting the first direction; a first channel pattern extending between the first bit line and the word line and along a first side wall of the word line in a third direction intersecting the first direction and the second direction; a gate insulating film extending in the third direction along the side wall of the first channel pattern and the first side wall of the word line between the first channel pattern and the word line; a first contact pattern on the first channel pattern; an insulating pattern extending along a side of the first contact pattern and a side of the first channel pattern; a landing pad on the first contact pattern; and a capacitor on the landing pad and connected to the first channel pattern, wherein in a cross-sectional view taken along the first channel pattern in the second direction, the first contact pattern comprises a connecting portion and a protruding portion, the connecting portion being on the first channel pattern, the protruding portion being connected to the connecting portion and extending along the side wall of the first channel pattern, wherein a lower surface of the protruding portion is located above a lower surface of the first channel pattern relative to a substrate providing a base reference plane.

[0008] However, the aspects of the present disclosure are not limited to what is described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects and features of the present disclosure will become more apparent by describing in detail illustrative embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0010] Figure 1is a layout diagram illustrating a semiconductor memory device according to some embodiments.

[0011] Figure 2 is along Figure 1 Cross-sectional views taken along lines AA, BB and CC.

[0012] Figure 3 is along Figure 1 A cross-sectional view taken along lines DD, EE and FF.

[0013] Figure 4 It is shown Figure 2 Magnified view of part P. Figure 5 yes Figure 2 Enlarged view of part Q.

[0014] Figure 6 yes Figure 3 Enlarged view of the R part.

[0015] Figure 7 is a layout diagram showing a semiconductor memory device according to some other embodiments.

[0016] Figure 8 is along Figure 7 Cross-sectional views taken along lines AA, BB and CC.

[0017] Fig. 9 is along Figure 7 A cross-sectional view taken along lines DD, EE and FF.

[0018] Fig.10 It is shown Fig. 9 Enlarged view of the R part.

[0019] Figures 11 to 14 is a schematic diagram illustrating a semiconductor memory device according to some other embodiments.

[0020] Figures 15 to 17 is a schematic diagram illustrating a semiconductor memory device according to some other embodiments.

[0021] Fig.18 and Fig.19 is a schematic diagram illustrating a semiconductor memory device according to some other embodiments.

[0022] Figure 20 to Figure 24 is a schematic diagram illustrating a semiconductor memory device according to some other embodiments.

[0023] Figure 25 to Figure 28 are schematic diagrams showing semiconductor memory devices according to some other embodiments.

[0024] Figure 29 to Figure 51is a schematic diagram illustrating an intermediate structure of a method for manufacturing a semiconductor memory device according to some embodiments. DETAILED DESCRIPTION

[0025] Embodiments of the inventive concepts according to the present disclosure will be described below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent the same elements, and therefore their description will be omitted. As used herein, the term "and / or" includes any and all combinations of one or more related listed items. Note that aspects described with respect to one embodiment can be incorporated into different embodiments, although not specifically described with respect thereto. That is, all embodiments and / or features of any embodiment can be combined in any manner and / or combination.

[0026] Figure 1 is a layout diagram illustrating a semiconductor memory device according to some embodiments. Figure 2 It is along Figure 1 Cross-sectional views taken along lines AA, BB and CC. Figure 3 It is along Figure 1 A cross-sectional view taken along lines DD, EE and FF. Figure 4 It is shown Figure 2 Magnified view of part P. Figure 5 It is shown Figure 2 Enlarged view of part Q. Figure 6 It is shown Figure 3 Enlarged view of the R part.

[0027] A semiconductor memory device according to an embodiment of the present disclosure may include a memory cell including a vertical channel transistor (VCT).

[0028] Reference Figures 1 to 6 , a semiconductor memory device according to some embodiments may include a peripheral gate structure PG, a bit line BL, word lines WL1 and WL2, a channel structure AP_ST, a protruding insulating pattern 175, a contact pattern BC, an insulating liner film 173, an insulating filling film 174, and a data storage pattern DSP.

[0029] The substrate 100 may be a silicon substrate, or may include other materials such as, but not limited to, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, and / or gallium antimonide.

[0030] The peripheral gate structure PG may be disposed on the substrate 100. The substrate 100 may include a cell array region and a peripheral circuit region. The peripheral gate structure PG may be disposed on the cell array region and the peripheral circuit region. In other words, a portion of the peripheral gate structure PG may be disposed in the cell array region of the substrate 100, and the remaining peripheral gate structure PG may be disposed in the peripheral circuit region of the substrate 100.

[0031] The peripheral gate structure PG may be included in a sensing transistor, a transfer transistor, a driving transistor, etc. The types of transistors provided in the cell array region and the peripheral circuit region may vary according to the design and layout of the semiconductor memory device.

[0032] The peripheral gate structure PG may include a peripheral gate insulating film 215 , a peripheral lower conductive pattern 223 , and a peripheral upper conductive pattern 225 .

[0033] The peripheral gate insulating film 215 may include a silicon oxide film, a silicon oxynitride film, a high dielectric constant insulating film having a higher dielectric constant than the silicon oxide film, or a combination thereof. The high dielectric constant insulating film may include, for example but not limited to, one or more of metal oxide, metal oxynitride, metal silicon oxide, and / or metal silicon oxynitride.

[0034] The peripheral lower conductive pattern 223 and the peripheral upper conductive pattern 225 may each include a conductive material. For example, the peripheral lower conductive pattern 223 and the peripheral upper conductive pattern 225 may each include one or more of a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbon nitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional (2D) material, a metal and / or a metal alloy. Although the illustrated peripheral gate structure PG includes a plurality of conductive patterns, embodiments of the present disclosure are not limited thereto.

[0035] In the semiconductor device according to some embodiments, the two-dimensional material may be a metal material and / or a semiconductor material. The 2D material may include a 2D allotrope or a 2D compound, and may include but is not limited to graphene, molybdenum disulfide (MoS 2 ), Molybdenum diselenide (MoSe 2 ), tungsten diselenide (WSe 2 ) and / or tungsten disulfide (WS 2 That is, since the above-mentioned 2D materials are listed only as examples, the 2D materials that may be included in the semiconductor memory device of the present disclosure are not limited to the above-mentioned materials.

[0036] The first lower peripheral insulating film 227 and the second lower peripheral insulating film 228 are disposed on the substrate 100. The first lower peripheral insulating film 227 and the second lower peripheral insulating film 228 may each be made of an insulating material.

[0037] The first peripheral wiring line 241a and the peripheral contact plug 241b may be disposed inside the first peripheral lower insulating film 227 and the second peripheral lower insulating film 228. Although the first peripheral wiring line 241a and the peripheral contact plug 241b are shown as films different from each other, the embodiments of the present disclosure are not limited thereto. The boundary between the first peripheral wiring line 241a and the peripheral contact plug 241b may not be distinguished. The first peripheral wiring line 241a and the peripheral contact plug 241b each include a conductive material.

[0038] The first and second peripheral upper insulating films 261 and 262 may be disposed on the first peripheral wiring line 241a and the peripheral contact plug 241b. The first and second peripheral upper insulating films 261 and 262 may each be made of an insulating material.

[0039] The second peripheral wiring line 243 and the peripheral via plug 242 are disposed on the first peripheral wiring line 241a. The peripheral via plug 242 may be disposed inside the first peripheral upper insulating film 261. The second peripheral wiring line 243 may be disposed inside the second peripheral upper insulating film 262.

[0040] The second peripheral wiring line 243 and the peripheral via plug 242 can be connected to the first peripheral wiring line 241a. The peripheral via plug 242 can connect the first peripheral wiring line 241a and the second peripheral wiring line 243. The second peripheral wiring line 243 and the peripheral via plug 242 each include a conductive material. Although the second peripheral wiring line 243 and the peripheral via plug 242 are shown as different films from each other, the embodiments of the present disclosure are not limited thereto. The boundary between the second peripheral wiring line 243 and the peripheral via plug 242 may not be distinguished.

[0041] The third, fourth, and fifth peripheral upper insulating films 263, 264, and 265 may be sequentially disposed on the second peripheral wiring line 243. The third, fourth, and fifth peripheral upper insulating films 263, 264, and 265 may each be made of an insulating material.

[0042] The fourth peripheral upper insulating film 264 may be made of an insulating material different from the third peripheral upper insulating film 263 and the fifth peripheral upper insulating film 265. For example, although the fourth peripheral upper insulating film 264 may be made of an oxide-based insulating material, and the third peripheral upper insulating film 263 and the fifth peripheral upper insulating film 265 may be made of a nitride-based insulating material, embodiments of the present disclosure are not limited thereto.

[0043] The cell connection plug 244 may be disposed inside the third peripheral upper insulating film 263, the fourth peripheral upper insulating film 264, and the fifth peripheral upper insulating film 265. The cell connection plug 244 may be connected to the second peripheral wiring line 243. The cell connection plug 244 includes a conductive material. Unlike the illustrated example, the peripheral upper insulating film may be composed of a single film that may be disposed in the cell connection plug 244.

[0044] The bit line BL is disposed on the peripheral gate structure PG. Specifically, the bit line BL may be disposed on the fifth peripheral upper insulating film 265. For example, the bit line BL may contact the fifth peripheral upper insulating film 265.

[0045] The bit lines BL may extend longitudinally in the second direction D2. Adjacent bit lines BL may be spaced apart in the first direction D1. The bit lines BL include long sidewalls extending in the second direction D2 and short sidewalls extending in the first direction D1.

[0046] Although not shown, each bit line BL may extend from the cell array region to the peripheral circuit region. An end portion of each bit line BL may be disposed on the peripheral circuit region of the substrate 100 .

[0047] Each bit line BL may be disposed on the cell connection plug 244. Each bit line BL may be connected to the cell connection plug 244. Each bit line BL may include, for example, one or more of a semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbon nitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material, a metal, and / or a metal alloy. Although each bit line BL is shown as a single film, embodiments of the present disclosure are not limited thereto.

[0048] The cell lower insulating film 171 may be disposed on the fifth peripheral upper insulating film 265. The cell lower insulating film 171 is disposed between the bit lines BL spaced apart in the first direction D1. The cell lower insulating film 171 may be made of an insulating material.

[0049] The protruding insulating pattern 175 may be disposed on the bit line BL and the lower cell insulating film 171. The protruding insulating pattern 175 may be made of an insulating material. Although the lower surface of the protruding insulating pattern 175 is shown as being in direct contact with the bit line BL and the lower cell insulating film 171, the embodiments of the present disclosure are not limited thereto. For example, an etching stop film may be disposed between the protruding insulating pattern 175 and the lower cell insulating film 171. In addition, the etching stop film may be disposed between the protruding insulating pattern 175 and the bit line BL. The etching stop film may include a material having an etching selectivity relative to the protruding insulating pattern 175.

[0050] A channel structure AP_ST may be provided on each bit line BL. A plurality of channel structures AP_ST may be connected to one bit line BL. A plurality of channel structures AP_ST provided on one bit line BL may be spaced apart in the second direction D2. For example, the channel structure AP_ST may be two-dimensionally provided along the first direction D1 and the second direction D2 intersecting each other.

[0051] In a cross section taken along the second direction D2, the channel structure AP_ST may have a “U” shape. Specifically, the channel structure AP_ST may include a horizontal portion and a vertical portion.

[0052] The horizontal portion of the channel structure AP_ST may extend along the upper surface of the bit line BL and the upper surface of the lower cell insulating film 171. The horizontal portion of the channel structure AP_ST may be disposed below the word lines WL1 and WL2. The horizontal portion of the channel structure AP_ST may overlap the lower surface WL_BS of the word lines WL1 and WL2 in the third direction D3. Figure 4 As shown, a horizontal portion of the channel structure AP_ST may be disposed under the gate insulating film GOX.

[0053] The vertical portion of the channel structure AP_ST may protrude from the horizontal portion. The vertical portion of the channel structure AP_ST may extend from the horizontal portion in the third direction D3. The vertical portion of the channel structure AP_ST may extend along the side of the protruding insulating pattern 175. Specifically, in a cross section taken along the second direction D2, the vertical portion of the channel structure AP_ST may extend along the side wall of the protruding insulating pattern 175. The vertical portion of the channel structure AP_ST may extend along the side of the insulating liner film 173. Specifically, in a cross section taken along the first direction D1, the vertical portion of the channel structure AP_ST may extend along the side of the insulating liner film 173.

[0054] The vertical portion of the channel structure AP_ST may include a first vertical portion and a second vertical portion. The first vertical portion and the second vertical portion of the channel structure AP_ST may be spaced apart parallel to the second direction D2.

[0055] The channel structure AP_ST may include an oxide semiconductor material. The channel structure AP_ST may include, for example, a metal oxide. As an example, the channel structure AP_ST may be an amorphous metal oxide film. As another example, the channel structure AP_ST may be a polycrystalline metal oxide film. As yet another example, the channel structure AP_ST may be a combination state of an amorphous metal oxide film and a polycrystalline metal oxide film. As yet another example, the channel structure AP_ST may be a CAAC (c-axis aligned crystal) metal oxide film.

[0056] The channel structure AP_ST may include, for example but not limited to, indium oxide, tin oxide, zinc oxide, In-Zn-based oxide (IZO), Sn-Zn-based oxide, Al-Zn-based oxide, Zn-Mg-based oxide, Sn-Mg-based oxide, In-Mg-based oxide, In-Ga-based oxide (IGO), In-Ga-Zn-based oxide (IGZO), In-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide , one or more of In-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, In-Sn-Ga-Zn-based oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide and / or In-Hf-Al-Zn-based oxide.

[0057] Here, In-Ga-Zn-based oxide refers to an oxide with In, Ga and Zn as main components, but does not indicate the ratio of In, Ga and Zn. That is, taking IGZO (indium gallium zinc oxide) as an example, the channel structure AP_ST may include IGZO (indium gallium zinc oxide, In x Ga y Zn z O). IGZO (In∶Ga∶Zn=1∶1∶1) containing indium, gallium and zinc in the same ratio may be an In-Ga-Zn based oxide. Ga-rich IGZO may have a higher gallium ratio than IGZO (In∶Ga∶Zn=1∶1∶1) and a lower indium ratio than IGZO (In∶Ga∶Zn=1∶1∶1). Ga-rich IGZO may also be an In-Ga-Zn based oxide. In-rich IGZO may also have a higher indium ratio than IGZO (In∶Ga∶Zn=1∶1∶1) and a lower gallium ratio than IGZO (In∶Ga∶Zn=1∶1∶1). In-rich IGZO may also be an In-Ga-Zn based oxide.

[0058] Although the above description is made using IGZO material, the embodiments of the present disclosure are not limited thereto. The above description may be applied when the channel structures AP_ST each include ternary or more metal oxides. In addition, when the channel structure AP_ST includes an In-Ga-Zn-based oxide, the channel structure AP_ST may further include doped metal elements other than In, Ga, and Zn.

[0059] The channel structure AP_ST may include a first channel pattern AP1, a second channel pattern AP2, and a connection channel pattern AP_CP. The connection channel pattern AP_CP may connect the first channel pattern AP1 and the second channel pattern AP2. The first channel pattern AP1 and the second channel pattern AP2 may be spaced apart in the second direction D2.

[0060] The first channel pattern AP1, the second channel pattern AP2, and the connection channel pattern AP_CP may be disposed on the bit line BL. The first channel pattern AP1 and the second channel pattern AP2 may be connected to the bit line BL.

[0061] The first channel pattern AP1 may include a portion of a horizontal portion of the channel structure AP_ST and a first vertical portion of the channel structure AP_ST. A portion of the horizontal portion of the channel structure AP_ST may be a horizontal portion of the first channel pattern AP1. The first vertical portion of the channel structure AP_ST may be a vertical portion of the first channel pattern AP1.

[0062] The second channel pattern AP2 may include another portion of the horizontal portion of the channel structure AP_ST and a second vertical portion of the channel structure AP_ST. Another portion of the horizontal portion of the channel structure AP_ST may be the horizontal portion of the second channel pattern AP2. The second vertical portion of the channel structure AP_ST may be the vertical portion of the second channel pattern AP2.

[0063] The connection channel pattern AP_CP includes a remaining portion of a horizontal portion of the channel structure AP_ST. The connection channel pattern AP_CP may be spaced apart in the first direction D1. The connection channel pattern AP_CP may be spaced apart between the first word line WL1 and the second word line WL2.

[0064] The first channel pattern AP1 , the second channel pattern AP2 , and the connection channel pattern AP_CP may be distinguished based on the first word line WL1 and the second word line WL2 , which will be described below.

[0065] The first word line WL1 may include an inner wall facing the sidewall of the protruding insulating pattern 175 and an outer wall opposite to the inner wall in the second direction D2. The outer wall of the first word line WL1 may face the gate separation pattern GSS. The boundary or interface between the first channel pattern AP1 and the connection channel pattern AP_CP may be an extension line of the outer wall of the first word line WL1 extending in the third direction D3.

[0066] The first word line WL1 may include a first sidewall and a second sidewall. The first sidewall of the first word line WL1 may face the sidewall of the protruding insulating pattern 175. The first sidewall of the first word line WL1 may face the second word line WL2, with the protruding insulating pattern 175 interposed therebetween. The first sidewall of the first word line WL1 may be an inner wall. The first sidewall of the first word line WL1 may extend along the gate insulating film GOX. The second sidewall of the first word line WL1 may face the gate separation pattern GSS. The second sidewall of the first word line WL1 may extend along the gate separation pattern GSS. The second sidewall of the first word line WL1 may be an outer wall.

[0067] The first channel pattern AP1 may be disposed on a first sidewall of the first word line WL1. The first channel pattern AP1 may extend along the first sidewall of the first word line WL1. The first channel pattern AP1 may be disposed on an inner wall of the first word line WL1.

[0068] The second word line WL2 may include a third sidewall and a fourth sidewall. The third sidewall of the second word line WL2 may face the sidewall of the protruding insulating pattern 175. The third sidewall of the second word line WL2 may face the first word line WL1, with the protruding insulating pattern 175 interposed therebetween. The third sidewall of the second word line WL2 may be an inner wall. The third sidewall of the second word line WL2 may extend along the gate insulating film GOX. The fourth sidewall of the second word line WL2 may face the gate separation pattern GSS. The fourth sidewall of the second word line WL2 may extend along the gate separation pattern GSS. The fourth sidewall of the second word line WL2 may be an outer wall.

[0069] The second channel pattern AP2 may be disposed on a third sidewall of the second word line WL2. The second channel pattern AP2 may extend along the third sidewall of the second word line WL2. The second channel pattern AP2 may be disposed on an inner wall of the second word line WL2.

[0070] The first word line WL1 and the second word line WL2 may be disposed on the channel structure AP_ST.

[0071] Each of the first word line WL1 and the second word line WL2 may extend in the first direction D1. The first word line WL1 and the second word line WL2 may be alternately arranged in the second direction D2. The first word line WL1 may be spaced apart from the second word line WL2 in the second direction D2.

[0072] The first word line WL1 and the second word line WL2 may be spaced apart from the bit line BL in the third direction D3. The first word line WL1 and the second word line WL2 may cross the bit line BL.

[0073] The first word line WL1 and the second word line WL2 may be disposed on a horizontal portion of the channel structure AP_ST. The first word line WL1 and the second word line WL2 are disposed between a first vertical portion of the channel structure AP_ST and a second vertical portion of the channel structure AP_ST.

[0074] The first word line WL1 is disposed on the first channel pattern AP1. The second word line WL2 is disposed on the second channel pattern AP2. The first word line WL1 and the second word line WL2 are disposed between the first channel pattern AP1 and the second channel pattern AP2. The first channel pattern AP1 is closer to the first word line WL1 than to the second word line WL2. The second channel pattern AP2 is closer to the second word line WL2 than to the first word line WL1.

[0075] The upper surface WL_US of the first word line and the upper surface WL_US of the second word line may be disposed below the upper surface AP_US of the channel structure, such as Figure 4 However, the embodiments are not limited thereto. For example, in other embodiments, the upper surface WL_US of the first word line and the upper surface WL_US of the second word line may be disposed above the upper surface AP_US of the channel structure AP_ST.

[0076] The lower surface WL_BS of the first word line and the lower surface WL_BS of the second word line may completely overlap with the channel structure AP_ST in the third direction. For example, the lower surface WL_BS of the first word line may completely overlap with the first channel pattern AP1 in the third direction D3. Figure 3 In the FF cross-section of FIG. 1 , the first channel pattern AP1 may extend in the first direction D1 under the first word line WL1. The lower surface WL_BS of the second word line WL2 may completely overlap the second channel pattern AP2 in the third direction D3.

[0077] The lower surfaces WL_BS of the first and second word lines WL1 and WL2 may overlap the gate insulating film GOX and the channel structure AP_ST. The lower surfaces WL_BS of the first and second word lines WL1 and WL2 may be disposed on the gate insulating film GOX and the channel structure AP_ST.

[0078] The first word line WL1 and the second word line WL2 include a conductive material and may include, for example, one or more of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, metal and / or metal alloy.

[0079] The first word line WL1 and the second word line WL2 may include an upper surface WL_US and a lower surface WL_BS opposite to each other in the third direction D3 . Lower surfaces of the first word line WL1 and the second word line WL2 face the bit line BL.

[0080] The gate insulating film GOX may be disposed between the first word line WL1 and the channel structure AP_ST and between the second word line WL2 and the channel structure AP_ST. The gate insulating film GOX may be disposed between the first word line WL1 and the first active pattern AP1 and between the second word line WL2 and the second active pattern AP2. The gate insulating film GOX may extend in the first direction D1 along the first word line WL1 and the second word line WL2.

[0081] The gate insulating film GOX may extend along the outline of the channel structure AP_ST. The gate insulating film GOX may extend along the horizontal portion of the channel structure AP_ST extending along the upper surface of the bit line BL. The gate insulating film GOX may extend in the third direction D3 along the vertical portion of the channel structure AP_ST extending along the side of the protruding insulating pattern 175. The gate insulating film GOX may extend along the first vertical portion of the channel structure AP_ST. The gate insulating film GOX may extend along the second vertical portion of the channel structure AP_ST.

[0082] On the connection channel pattern AP_CP of the channel structure AP_ST, the gate insulating film GOX may extend along the upper surface of the connection channel pattern AP_CP. Figure 2 and Figure 4 , the gate insulating film GOX may be disposed on an upper surface of the connection channel pattern AP_CP.

[0083] In a region where the connection channel pattern AP_CP is not provided, the gate insulating film GOX may overlap the first channel pattern AP1 and the second channel pattern AP2 in the third direction D3. Figure 2 and Figure 5 , the gate insulating film GOX may be disposed on the first channel pattern AP1 and the second channel pattern AP2. The gate insulating film GOX may completely overlap the first channel pattern AP1 and the second channel pattern AP2 in the third direction D3. The gate insulating film GOX extends only along the lower surface and inner wall of the first word line WL1 and the second word line WL2. The gate insulating film GOX may be separated by the gate separation pattern GSS. One side of the gate insulating film GOX may be coplanar with the outer wall of the first word line WL1 and the side of the first channel pattern AP1. One side of the gate insulating film GOX may be coplanar with the outer wall of the second word line WL2 and the side of the second channel pattern AP2.

[0084] The gate insulating film GOX may extend along the side of the contact pattern BC. The gate insulating film GOX may extend along the side of the connection portion 231 of the contact pattern BC. The gate insulating film GOX may extend along the side of the protrusion portion 232 of the contact pattern BC.

[0085] The gate insulating film GOX may extend along the contact pattern BC facing the gate separation pattern GSS. Figure 4 , the gate insulating film GOX extending between the first active pattern AP1 and the first word line WL1 may extend along the side of the connection portion 231 of the contact pattern BC disposed on the first active pattern AP1. The gate insulating film GOX extending between the second active pattern AP2 and the second word line WL2 may extend along the side of the connection portion 231 disposed on the second active pattern AP2.

[0086] In addition, refer to Figure 5 , the gate insulating film GOX may extend along the side of the protruding portion 232. The gate insulating film GOX extending between the first word line WL1 and the insulating liner film 173 may extend along the side of the protruding portion 232 adjacent to the first word line WL1. The gate insulating film GOX extending between the second word line WL2 and the insulating liner film 173 may extend along the side of the protruding portion 232 adjacent to the second word line WL2.

[0087] The gate insulating film GOX may include a silicon oxide film, a silicon oxynitride film, a high dielectric constant insulating film having a higher dielectric constant than the silicon oxide film, or a combination thereof.

[0088] A portion of the gate insulating film GOX may protrude beyond the upper surface WL_US of the first word line WL1 and the second word line WL2 in the third direction D3. A portion of the gate insulating film GOX may protrude beyond the uppermost portion of the vertical portion of the channel structure AP_ST in the third direction D3. The upper surface of the gate insulating film GOX may be coplanar with the upper surface of the gate separation pattern GSS. The upper surface of the gate insulating film GOX may be coplanar with the upper surface of the protruding insulating pattern 175. The upper surface of the gate insulating film GOX may be coplanar with the upper surface of the insulating liner film 173 and the upper surface of the insulating filling film 174.

[0089] The gate separation pattern GSS may be disposed on the bit line BL. The gate separation pattern GSS may be disposed on the channel structure AP_ST, the gate insulating film GOX, the first word line WL1, and the second word line WL2.

[0090] In the semiconductor memory device according to some embodiments, the gate separation pattern GSS may contact the channel structure AP_ST. The gate separation pattern GSS may be disposed on the connection channel pattern AP_CP. The gate separation pattern GSS may be spaced apart from the bit line BL in the third direction D3.

[0091] The gate separation pattern GSS may be disposed between the first and second word lines WL1 and WL2 adjacent to each other in the second direction D2. The first and second word lines WL1 and WL2 may be separated by the gate separation pattern GSS. The gate separation pattern GSS may extend in the first direction D1 between the first and second word lines WL1 and WL2.

[0092] The gate separation pattern GSS may be disposed between the connection channel patterns AP_CP adjacent in the first direction D1. A lower surface of the gate separation pattern GSS between the connection channel patterns AP_CP adjacent in the first direction D1 may contact the lower cell insulating film 171. A lower surface of the gate separation pattern GSS between the connection channel patterns AP_CP adjacent in the first direction D1 may be coplanar with a lower surface of the channel structure AP_ST.

[0093] In an area where the connection channel pattern AP_CP is not provided, the gate separation pattern GSS may be on and at least partially cover the side of the gate insulation film GOX, which is coplanar with the side of the first word line WL1 and the side of the first channel pattern AP1. In an area where the connection channel pattern AP_CP is not provided, the gate separation pattern GSS may be on and at least partially cover the side of the gate insulation film GOX and the side of the second channel pattern AP2, which is coplanar with the side of the second word line WL2.

[0094] The first word line WL1 may be disposed between the gate separation pattern GSS and the channel structure AP_ST. The second word line WL2 may be disposed between the gate separation pattern GSS and the channel structure AP_ST. The first word line WL1 may be disposed between the gate separation pattern GSS and the first channel pattern AP1. The second word line WL2 may be disposed between the gate separation pattern GSS and the second channel pattern AP2.

[0095] The gate separation pattern GSS may be a single-layer film. The gate separation pattern GSS may include a horizontal portion and a vertical portion. The vertical portion of the gate separation pattern GSS may protrude from the horizontal portion of the gate separation pattern GSS toward the bit line BL in the third direction D3. The vertical portion of the gate separation pattern GSS may be closer to the bit line BL than the horizontal portion of the gate separation pattern GSS. The horizontal portion of the gate separation pattern GSS may be disposed on the upper surface WL_US of the first word line WL1 and the second word line WL2. From the perspective of the cross-sectional view, the gate separation pattern GSS may have a "T" shape.

[0096] The upper surface of the gate separation pattern GSS may be disposed at the same height as the upper surface of the protruding insulating pattern 175 based on the upper surface of the bit line BL, ie, with the upper surface of the bit line BL providing a base reference plane, but the embodiment is not limited thereto.

[0097] The height from the upper surface of the bit line BL to the upper surface of the gate separation pattern GSS may be greater than the height from the upper surface of the bit line BL to the uppermost portion of the channel structure AP_ST. The uppermost portion of the channel structure AP_ST may refer to the upper surface AP_US of the first channel pattern AP1 or the second channel pattern AP2. The height from the upper surface of the bit line BL to the upper surface of the gate separation pattern GSS may be greater than the height from the upper surface of the bit line BL to the upper surfaces WL_US of the word lines WL1 and WL2.

[0098] The height from the upper surface of the bit line BL to the upper surface of the gate separation pattern GSS is shown to be the same as the height from the upper surface of the bit line BL to the uppermost portion of the gate insulation film GOX, but the embodiment is not limited thereto.

[0099] The landing pad LP may be disposed on the channel structure AP_ST. The landing pad LP may be connected to the first vertical portion AP_STV1 of the channel structure and the second vertical portion AP_STV2 of the channel structure.

[0100] The landing pad LP may be disposed on the first and second channel patterns AP1 and AP2. The landing pad LP is connected to the first and second channel patterns AP1 and AP2.

[0101] from Figure 1 From the perspective of the plan view shown, the landing pad LP may have various shapes such as a circle, an oval, a rectangle, a square, a diamond, and a hexagon.

[0102] The landing pad LP may be disposed on the protruding insulating pattern 175 and the gate separation pattern GSS. The landing pad LP may contact the upper surface of the protruding insulating pattern 175 and the upper surface of the gate separation pattern GSS. The landing pad LP may be disposed between the pad separation insulating patterns 235.

[0103] The pad separation insulating pattern 235 may be disposed between the landing pads LP. Figure 1 From the illustrated plan view, the landing pads LP may be arranged in a matrix along the first direction D1 and the second direction D2. An upper surface of the landing pads LP may be coplanar with an upper surface of the pad separation insulating pattern 245, but the embodiment is not limited thereto.

[0104] The landing pad LP may be disposed on the contact pattern BC. The landing pad LP may overlap the contact pattern BC in the third direction D3. The landing pad LP may be connected to the first channel pattern AP1 and the second channel pattern AP2 through the contact pattern BC. The landing pad LP may be disposed on the connection portion 231 of the contact pattern BC. The landing pad LP may contact the upper surface of the connection portion 231 of the contact pattern BC.

[0105] The landing pad LP includes a conductive material. The landing pad LP may include, for example, one or more of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, metal and / or metal alloy.

[0106] The data storage patterns DSP may be each disposed on the landing pads LP. The data storage pattern DSP may be connected to the first vertical portion of the channel structure AP_ST and the second vertical portion of the channel structure AP_ST. The data storage pattern DSP may be connected to each of the first channel pattern AP1 and the second channel pattern AP2.

[0107] The data storage patterns DSP may be arranged in a matrix form along the first direction D1 and the second direction D2, such as Figure 1 The data storage pattern DSP may completely or partially overlap the landing pad LP in the third direction D3. The data storage pattern DSP may contact the entire or a portion of the upper surface of the landing pad LP.

[0108] For example, the data storage pattern DSP may be a capacitor. The first channel pattern AP1 may be connected to the first capacitor. The second channel pattern AP2 may be connected to the second capacitor.

[0109] The data storage pattern DSP may include a capacitor dielectric film 253 interposed between the storage electrode 251 and the plate electrode 255. In this case, the storage electrode 251 may be in contact with the landing pad LP. From a plan view perspective, the storage electrode 251 may have various shapes such as a circle, an ellipse, a rectangle, a square, a diamond, and a hexagon. The data storage pattern DSP may completely or partially overlap the landing pad LP. The data storage pattern DSP may be in contact with all or part of the upper surface of the landing pad LP. The storage electrode 251 may penetrate or extend into the upper cell etch stop film 247. The upper cell etch stop film 247 may be made of an insulating material.

[0110] In contrast, the data storage pattern DSP may be a variable resistance pattern that can be switched between two resistance states by an electric pulse applied to the storage element. For example, the data storage pattern DSP may include a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material, in which the crystalline state changes according to the amount of current.

[0111] The contact pattern BC may be disposed on the channel structure AP_ST. The contact pattern BC may overlap the channel structure AP_ST in the third direction D3. The contact pattern BC may be on the upper surface AP_US of the channel structure AP_ST and at least partially cover the upper surface AP_US.

[0112] Specifically, the contact pattern BC may be disposed on the first channel pattern AP1 and the second channel pattern AP2. The contact pattern BC may be disposed on the upper surface AP_US of the first channel pattern and the upper surface AP_US of the second channel pattern. The contact pattern BC may not be disposed on the connection channel pattern AP_CP. The contact pattern BC may not overlap with the connection channel pattern AP_CP in the third direction D3.

[0113] The contact pattern BC may be on a portion of the side surface of the channel structure AP_ST and at least partially cover the portion of the side surface. The contact pattern BC may extend along the side surfaces of the first channel pattern AP1 and the second channel pattern AP2. Figure 6 , the contact pattern BC may extend along the side AP_SW of the second channel pattern AP2. The contact pattern BC may be on a portion of the side AP_SW of the second channel pattern AP2 and at least partially cover the portion of the side AP_SW.

[0114] The contact pattern BC may partially overlap the insulating liner film 173 in the third direction D3. The contact pattern BC may overlap the first channel pattern AP1 and the second channel pattern AP2 in the third direction D3.

[0115] The contact pattern BC may have a width greater than the first and second channel patterns AP1 and AP2 in the first direction D1. Therefore, the first and second channel patterns AP1 and AP2 do not overlap the insulating liner film 173 in the third direction D3, but the contact pattern BC may partially overlap the insulating liner film 173 in the third direction D3.

[0116] The contact pattern BC may include a connection portion 231 and a protrusion portion 232. The contact pattern BC may have a "U" shape rotated 180 degrees. The connection portion 231 and the protrusion portion 232 of the contact pattern BC may have a "U" shape rotated 180 degrees.

[0117] The connection portion 231 may be in contact with the landing pad LP. The connection portion 231 may be connected to the landing pad LP. Figure 4 As shown, the connection portion 231 may be disposed under the landing pad LP. Figure 4 As shown, the connection portion 231 may be disposed on the channel structure AP_ST. Figure 4 As shown, the connection portion 231 may be disposed on the upper surface AP_US of the channel structure AP_ST. Figure 4 As shown, the connection portion 231 may be disposed on the upper surface AP_US of the first channel pattern and the upper surface AP_US of the second channel pattern. In the first direction D1, the connection portion 231 may not overlap the first channel pattern AP1 and the second channel pattern AP2.

[0118] The connection portion 231 may be disposed between the insulating liner films 173 in the first direction D1. The connection portion 231 may be disposed between the gate insulating film GOX and the protruding insulating pattern 175 in the second direction D2.

[0119] The protruding portion 232 may protrude from the connecting portion 231 in the third direction D3. The protruding portion 232 may protrude from the connecting portion 231 toward the bit line BL and the lower cell insulating film 171 in the third direction D3. The protruding portion 232 may cover a portion of the side AP_SW of the channel structure. The protruding portion 232 may overlap a portion of the side AP_SW of the first channel pattern and the side AP_SW of the second channel pattern.

[0120] Specifically, the protruding portion 232 may be on a portion of the side AP_SW of the first channel pattern that is opposite to each other in the first direction D1, and at least partially covers the portion of the side AP_SW. The protruding portion 232 may be on a portion of the side AP_SW of the second channel pattern that is opposite to each other in the first direction D1, and at least partially covers the portion of the side AP_SW. The protruding portion 232 may extend in the third direction D3 along the side AP_SW of the channel structure. The protruding portion 232 may overlap the first channel pattern AP1 and the second channel pattern AP2 in the first direction D1.

[0121] The protrusion portion 232 may be disposed on the insulating liner film 173. The protrusion portion 232 may be disposed between the first channel pattern AP1 and the insulating liner film 173 and between the second channel pattern AP2 and the insulating liner film 173 in the first direction D1. The protrusion portion 232 may be disposed between the gate insulating film GOX and the insulating liner film 173 in the second direction D2.

[0122] Although the thickness TH231 of the connection portion is shown to be smaller than the thickness TH232 of the protruding portion, the embodiment is not limited thereto. For example, the thickness TH231 of the connection portion may be the same as the thickness TH232 of the protruding portion.

[0123] The connection portion 231 may not overlap the first word line WL1 and the second word line WL2 in the second direction D2. Based on the upper surface of the bit line BL, that is, when the upper surface of the bit line BL provides a base reference plane, the connection portion 231 may be disposed above the first word line WL1 and the second word line WL2. Based on the upper surface of the bit line BL, that is, when the upper surface of the bit line BL provides a base reference plane, the lower surface 231BS of the connection portion may be disposed above the upper surface WL_US of the first word line and the second word line.

[0124] The protruding portion 232 may overlap the first word line WL1 and the second word line WL2 in the second direction D2. Based on the upper surface of the bit line BL, that is, in the case where the upper surface of the bit line BL provides a base reference plane, the lower surface 232BS of the protruding portion may be disposed below the upper surface WL_US of the first word line and the second word line. However, the embodiment is not limited thereto. For example, the protruding portion 232 may not overlap the first word line WL1 and the second word line WL2 in the second direction D2. Based on the upper surface of the bit line BL, that is, in the case where the upper surface of the bit line BL provides a base reference plane, the lower surface 232BS of the protruding portion may be disposed above the upper surface WL_US of the first word line and the second word line.

[0125] The lower surface of the contact pattern BC may refer to a lower surface 232BS of the protruding portion. In the third direction D3, the lower surface 232BS of the protruding portion may be disposed between the lower surface of the channel structure AP_ST and the upper surface AP_US of the channel structure. Based on the upper surface of the bit line BL, that is, in the case where the upper surface of the bit line BL provides a base reference plane, the lower surface 232BS of the protruding portion may be disposed above the lower surface of the channel structure AP_ST, and may be disposed below the upper surface AP_US of the channel structure. The lower surface 232BS of the protruding portion may not be in contact with the upper surface of the lower insulating film 171 of the cell. The lower surface 232BS of the protruding portion may be spaced apart from the upper surface of the lower insulating film 171 of the cell in the third direction D3.

[0126] In the first direction D1, the width of the contact pattern BC may be greater than the width of the upper surface AP_US of the channel structure AP_ST. Figure 6 , in a cross-sectional view taken along the first direction D1, the protruding portion 232 of the contact pattern BC may be on the side surface AP_SW of the channel structure and at least partially cover the side surface AP_SW of the channel structure. In the first direction D1, the outer wall of the contact pattern BC may protrude beyond the side surface AP_SW of the channel structure. Therefore, in the first direction D1, the width W_BC of the contact pattern may be greater than the width W_AP of the upper surface AP_US of the channel structure.

[0127] In the second direction D2, the width of the contact pattern BC may be no greater than the width of the upper surface AP_US of the channel structure AP_ST. Figure 2 and Figure 4 , in the cross-sectional view taken along the second direction D2, the contact pattern BC may not cover the side of the channel structure AP_ST. Specifically, in the cross-sectional view taken along the second direction D2, the connection portion 231 of the contact pattern BC may completely overlap with the channel structure AP_ST in the third direction D3. In the cross-sectional view taken along the second direction D2, the side of the connection portion 231 of the contact pattern BC may completely overlap with the side of the channel structure AP_ST in the third direction D3. Therefore, in the second direction D2, the width W231 of the contact pattern BC may be the same as the width of the upper surface AP_US of the channel structure AP_ST.

[0128] The contact pattern BC may overlap with the insulating liner film 173 in the third direction D3. In the third direction D3, a portion of the contact pattern BC may be disposed on the insulating liner film 173. A portion of the contact pattern BC that does not overlap with the first channel pattern AP1 and the second channel pattern AP2 in the third direction D3 may be disposed on the insulating liner film 173. Specifically, a protruding portion 232 of the contact pattern BC may be disposed on the insulating liner film 173. A connecting portion 231 that overlaps with the protruding portion 232 of the contact pattern BC in the third direction D3 may be disposed on the insulating liner film 173.

[0129] In the first direction D1, the contact pattern BC may be disposed between the insulating liner films 173. In the second direction D2, the contact pattern BC may be disposed between the protruding insulating pattern 175 and the gate insulating film GOX. The contact pattern BC may extend along the sidewall of the protruding insulating pattern 175 in the third direction D3. The contact pattern BC may extend in the third direction D3 along the sidewall of the gate insulating film GOX. In the third direction D3, the contact pattern BC may be disposed between the landing pad LP and the first channel pattern AP1 or the second channel pattern AP2.

[0130] The contact pattern BC includes a conductive material. The contact pattern BC may include, for example, one or more of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, metal and / or metal alloy.

[0131] Since the contact pattern BC extends along the sides of the first and second channel patterns AP1 and AP2, the contact area between the contact pattern BC, the first and second channel patterns AP1 and AP2 may be increased. Therefore, the resistance between the contact pattern BC, the first and second channel patterns AP1 and AP2 may be reduced.

[0132] The insulating liner film 173 may be disposed between the contact patterns BC. In the first direction D1, the insulating liner film 173 may be disposed between the contact patterns BC. In the first direction D1, the insulating liner film 173 may be disposed between the first channel patterns AP1. In the first direction D1, the insulating liner film 173 may be disposed between the second channel patterns AP2.

[0133] From a plan view perspective, the insulating liner film 173 may be disposed between the protruding insulating patterns 175 in the first direction D1. The insulating liner film 173 may be disposed between side surfaces of the protruding insulating patterns 175 that are opposite to each other in the first direction D1.

[0134] The insulating liner film 173 may be disposed between the side surfaces AP_SW of the first channel pattern AP1 that are opposite to each other in the first direction D1. The insulating liner film 173 may be disposed between the side surfaces AP_SW of the second channel pattern AP2 that are opposite to each other in the first direction D1. The insulating liner film 173 may not overlap the first channel pattern AP1 and the second channel pattern AP2 in the third direction D3.

[0135] From a plan view perspective, the insulating liner film 173 may be disposed between the first word line WL1 and the second word line WL2 in the second direction D2. The insulating liner film 173 may extend along the gate insulating film GOX and the lower cell insulating film 171 between the first word line WL1 and the second word line WL2 in the second direction D2. The insulating liner film 173 may extend along the upper surface of the lower cell insulating film 171. The insulating liner film 173 may extend along the lower surface and side surfaces of the insulating filling film 174. The insulating liner film 173 may be on the lower surface and side surfaces of the insulating filling film 174 and at least partially cover the lower surface and side surfaces of the insulating filling film 174.

[0136] The insulating liner film 173 may abut and at least partially surround the protruding portion 232 of the contact pattern BC. The insulating liner film 173 may be on and at least partially cover the side and lower surface 232BS of the protruding portion 232 of the contact pattern BC. That is, the protruding portion 232 of the contact pattern BC may be disposed inside the insulating liner film 173.

[0137] In the first direction D1, the insulating liner film 173 may be disposed between the contact patterns BC. Figure 6 , the insulating liner film 173 may at least partially fill in the space between the contact patterns BC.

[0138] In addition, in the first direction D1, the insulating liner film 173 may be disposed between the channel structures AP_ST. Figure 6 , the insulating liner film 173 may at least partially fill the space between the second channel patterns AP2.

[0139] The insulating liner film 173 may include a first portion 173a and a second portion 173b. The first portion 173a may be disposed on the second portion 173b. The first portion 173a may extend from the second portion 173b to a portion between the contact patterns BC. The first portion 173a of the insulating liner film 173 may be disposed between the contact patterns BC. The first portion 173a of the insulating liner film 173 may at least partially fill the space between the contact patterns BC.

[0140] The first portion 173a may be disposed between the contact patterns BC spaced apart in the first direction D1. The first portion 173a may be disposed between the connection portions 231 spaced apart in the first direction D1. The first portion 173a may be disposed between the protrusion portions 232 spaced apart in the first direction D1. The first portion 173a may extend in the third direction D3 along the side of the contact pattern BC.

[0141] The second portion 173b may be disposed under the first portion 173a. The second portion 173b may be connected to the first portion 173a. The second portion 173b of the insulating liner film 173 may be disposed under the contact pattern BC. The second portion 173b of the insulating liner film 173 may be disposed between the channel structures AP_ST spaced apart in the first direction D1. For example, the second portion 173b may be disposed between the second active patterns AP2 spaced apart in the first direction D1.

[0142] The width of the first portion 173a may be smaller than the width of the second portion 173b. That is, in the first direction D1, a distance between the contact patterns BC adjacent to each other may be smaller than a distance between the channel structures AP_ST adjacent to each other.

[0143] The insulating filling film 174 may be disposed on the insulating liner film 173. The insulating filling film 174 may at least partially fill a lower portion of the pad separation insulating pattern 235 on the insulating liner film 173. The insulating filling film 174 may be adjacent to or at least partially surrounded by the insulating liner film 173. The insulating filling film 174 may extend along an inner surface and a lower surface of the insulating liner film 173.

[0144] In the first direction D1, the insulating filling film 174 may overlap with the protruding insulating pattern 175. In the first direction D1, the insulating filling film 174 may not overlap with the first channel pattern AP1 and the second channel pattern AP2. In addition, in the first direction D1, the insulating filling film 174 may not overlap with the contact pattern BC. In the first direction D1, the insulating liner film 173 overlaps with the contact pattern BC, but the insulating filling film 174 may not overlap with the contact pattern BC. Therefore, referring to Figure 6 , only the insulating liner film 173 is disposed between the contact patterns BC, and the insulating filling film 174 may not be disposed.

[0145] In the second direction D2, the insulating filling film 174 may not overlap with the contact pattern BC. The insulating filling film 174 may not overlap with the contact pattern BC in the third direction D3. The insulating filling film 174 of the contact pattern BC may not be provided. The insulating liner film 173 below overlaps with the contact pattern BC in the third direction D3, but the insulating filling film 174 may not overlap with the contact pattern BC.

[0146] The insulating liner film 173 and the insulating filling film 174 may each include an insulating material. The insulating liner film 173 and the insulating filling film 174 may each include silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and a combination thereof. For example, the insulating liner film 173 may include silicon nitride, and the insulating filling film 174 may include silicon oxide.

[0147] Figure 7 is a layout diagram showing a semiconductor memory device according to some other embodiments. Figure 8 It is along Figure 7 Cross-sectional views taken along lines AA, BB and CC. Fig. 9 It is along Figure 7 A cross-sectional view taken along lines DD, EE and FF. Fig.10 It is shown Fig. 9 For ease of explanation, the explanation will focus on the reference Figures 1 to 6 The characteristics described are different from those of the others.

[0148] Reference Figures 7 to 10 , the insulating filling film 174 may overlap the first channel pattern AP1 and the second channel pattern AP2 in the first direction D1. In addition, the insulating filling film 174 may overlap the contact pattern BC in the first direction D1.

[0149] For example, refer to Figure 8 In the CC cross section, the thickness of the side portion of the insulating liner film 173 extending along the gate insulating film GOX may be smaller than the thickness of the lower portion of the insulating liner film 173 extending along the upper surface of the cell lower insulating film 171 .

[0150] and Figure 1 Compared with reference Figure 7 From a plan view perspective, the insulating filling film 174 at least partially surrounded by the insulating liner film 173 increases in width in the second direction D2. Therefore, the insulating filling film 174 may overlap the first channel pattern AP1, the second channel pattern AP2, and the contact pattern BC in the first direction D1.

[0151] Specifically, refer to Fig.10 , the insulating filling film 174 may extend in the third direction D3 between the contact patterns BC adjacent in the first direction D1. The insulating filling film 174 may at least partially fill the space between the contact patterns BC adjacent in the first direction D1. The insulating filling film 174 may contact the connection portion 231 and the protrusion portion 232 of the contact pattern BC.

[0152] The insulating liner film 173 may extend along the side of the second channel pattern AP2 under the connection portion 231. The insulating liner film 173 may have a “U” shape under the connection portion 231. The insulating liner film 173 may have a “U” shape between the second channel patterns AP2 in the first direction D1.

[0153] Although not shown, the insulating liner film 173 may similarly extend along the side of the first channel pattern AP1 under the connection portion 231. The insulating liner film 173 may have a “U” shape between the first channel patterns AP1 in the first direction D1.

[0154] For example, the insulating liner film 173 may include a third portion 173d and a fourth portion 173c. The third portion 173d may be disposed on the upper surface of the lower cell insulating film 171. The third portion 173d may extend along the upper surface of the lower cell insulating film 171. The third portion 173d may be disposed under the insulating filling film 174.

[0155] The fourth portion 173 c may protrude from the third portion 173 d in the third direction D3 . The fourth portion 173 c may extend along a side of the second channel pattern AP2 . The fourth portion 173 c may be disposed in a side portion of the insulating filling film 174 .

[0156] The insulating filling film 174 may be disposed on the insulating liner film 173. The insulating filling film 174 may be adjoined by or at least partially surrounded by the insulating liner film 173 under the connection portion 231.

[0157] Figures 11 to 14 is a schematic diagram showing a semiconductor memory device according to some other embodiments. For ease of explanation, the explanation will focus on Figures 1 to 6 The features described are different on the features.

[0158] Reference Figures 11 to 14 , the connection portion 231 may overlap the first word line WL1 and the second word line WL2 in the second direction D2. Based on the upper surface of the bit line BL, that is, when the upper surface of the bit line BL provides a base reference plane, the lower surface 231BS of the connection portion may be disposed below the upper surfaces WL_US of the first and second word lines.

[0159] The upper surface WL_US of the first word line and the upper surface WL_US of the second word line may be disposed on the upper surface AP_US of the channel structure AP_ST, such as Fig.13As shown. The thickness TH231 of the connection portion may be greater than the thickness TH232 of the protruding portion. However, the embodiment is not limited thereto. For example, even if the connection portion 231 overlaps the first word line WL1 and the second word line WL2 in the second direction D2, the thickness TH231 of the connection portion may be less than the thickness TH232 of the protruding portion.

[0160] Figures 15 to 17 is a schematic diagram showing a semiconductor memory device according to some other embodiments. For ease of explanation, the explanation will focus on Figures 1 to 6 The features described are different on the features.

[0161] Reference Figures 15 to 17 , the insulating liner film 173 may not extend along the lower surface of the insulating filling film 174. The insulating liner film 173 and the insulating filling film 174 may not overlap in the third direction D3. The insulating liner film 173 may not cover the lower surface of the insulating filling film 174. The insulating liner film 173 may extend only along the side of the insulating filling film 174. The insulating liner film 173 may not extend along the upper surface of the lower cell insulating film 171.

[0162] The lower surface of the insulating filling film 174 may be in contact with the upper surface of the lower cell insulating film 171. The lower surface of the insulating filling film 174 may be coplanar with the lower surface of the second channel pattern AP2. The insulating filling film 174 may extend from the upper surface of the lower cell insulating film 171 to the lower surface of the pad separation insulating pattern 235 in the third direction D3 between the first channel pattern AP1 or the second channel pattern AP2 in the first direction D1. The lower surface of the insulating filling film 174 may be coplanar with the lower surface of the protruding insulating pattern 175.

[0163] Fig.18 and Fig.19 is a schematic diagram showing a semiconductor memory device according to some other embodiments. For ease of explanation, the explanation will focus on Figures 1 to 6 The features described are different on the features.

[0164] Reference Fig.18 and Fig.19, the gate separation pattern GSS may include a plurality of films. The gate separation pattern GSS may include a gate separation pad 151, a gate separation filling film 153, and a gate separation covering film 155. The gate separation pad 151 may extend along the upper surface of the first word line WL1 and the second word line WL2 and along the outer wall of the first word line WL1 and the second word line WL2. The gate separation pad 151 may extend along the horizontal portion of the channel structure AP_ST. The gate separation pad 151 may be in contact with the connection channel pattern AP_CP. The gate separation pad 151 may extend along the gate insulation film GOX protruding beyond the upper surface of the first word line WL1 and the second word line WL2. Unlike the illustrated example, the gate separation pad 151 may not extend along the gate insulation film GOX protruding beyond the upper surface WL_US of the first word line WL1 and the second word line WL2.

[0165] The gate separation filling film 153 may be disposed on the gate separation liner 151. The gate separation filling film 153 is disposed between the first word line WL1 and the second word line WL2. The gate separation filling film 153 may overlap the first word line WL1 and the second word line WL2 in the second direction D2.

[0166] The gate separation capping film 155 may be disposed on the gate separation filling film 153. The gate separation capping film 155 may be disposed on the first word line WL1 and the second word line WL2. The gate separation capping film 155 may not overlap the first word line WL1 and the second word line WL2 in the second direction D2. The gate separation pad 151, the gate separation filling film 153, and the gate separation capping film 155 may each be made of an insulating material.

[0167] Figure 20 to Figure 24 is a schematic diagram showing a semiconductor memory device according to some other embodiments. For ease of explanation, the explanation will focus on Figures 1 to 6 The features described are different on the features.

[0168] For reference, Fig. 20 is a layout diagram illustrating a semiconductor memory device according to some embodiments. Fig.21 It is along Fig. 20 Cross-sectional views taken along lines AA, BB and CC. Fig. 22 It is along Fig. 20 A cross-sectional view taken along lines DD, EE and FF. Fig.23 yes Fig.21 Magnified view of part P. Fig.24 It is shown Fig.21 Enlarged view of part Q.

[0169] Reference Figure 20 to Figure 24, in the semiconductor memory device according to some embodiments, the first channel pattern AP1 and the second channel pattern AP2 spaced apart in the second direction D2 are not connected.

[0170] The channel structure AP_ST may not be disposed between the first and second word lines WL1 and WL2 that face each other with the gate separation pattern GSS interposed therebetween.

[0171] The first channel pattern AP1 may include a horizontal portion extending along the upper surface of the bit line BL and a vertical portion extending along the sidewall of the protruding insulating pattern 175. The vertical portion of the first channel pattern AP1 may protrude from the horizontal portion of the first channel pattern AP1 in the third direction D3.

[0172] The second channel pattern AP2 may include a horizontal portion extending along the upper surface of the bit line BL and a vertical portion extending along the sidewall of the protruding insulating pattern 175. The vertical portion of the second channel pattern AP2 may protrude from the horizontal portion of the second channel pattern AP2 in the third direction D3.

[0173] The gate separation pattern GSS may contact the upper surface of the bit line BL. The horizontal portion of the first channel pattern AP1 and the horizontal portion of the second channel pattern AP2 may be spatially separated by the gate separation pattern GSS. The gate separation pattern GSS may contact the upper surface of the under-cell insulating film 171.

[0174] A lower surface of the gate separation pattern GSS may be coplanar with a lower surface of the insulating liner film 173. A lower surface of the gate separation pattern GSS may be coplanar with a lower surface of the protruding insulating pattern 175.

[0175] Figure 25 to Figure 28 are schematic diagrams showing semiconductor memory devices according to some other embodiments. For ease of explanation, the explanation will focus on Figures 1 to 6 The features described are different on the features.

[0176] Reference Fig.25 In the semiconductor memory device according to some embodiments, the first channel pattern AP1 and the second channel pattern AP2 may be alternately arranged in a diagonal direction with respect to the first direction D1 and the second direction D2. Here, the diagonal direction may be parallel to the upper surface of the substrate 100.

[0177] The channel structure AP_ST may be twisted in a diagonal direction. From a plan view perspective, the first channel pattern AP1, the second channel pattern AP2, and the connection channel pattern AP_CP may each have a parallelogram or a rhombus shape.

[0178] Reference Fig.26In the semiconductor memory device according to some embodiments, the landing pads LP and the data storage patterns DSP may be arranged in a zigzag shape or a honeycomb shape from a plan view perspective.

[0179] Reference Fig. 27 In the semiconductor memory device according to some embodiments, the data storage pattern DSP may be disposed to at least partially come out of the landing pad LP from a plan view perspective.

[0180] Each of the data storage patterns DSP may make contact with a portion of the landing pad LP.

[0181] Reference Fig.28 In the semiconductor memory device according to some embodiments, each of the landing pads LP disposed on the first and second channel patterns AP1 and AP2 may have a semicircular or semi-elliptical shape from a plan view perspective.

[0182] The landing pads LP may be disposed symmetrically to each other from a plan view perspective.

[0183] Figures 29 to 51 is an intermediate structural diagram illustrating a method for manufacturing a semiconductor memory device according to some embodiments.

[0184] Reference Figure 29 to Figure 31 , a peripheral gate structure PG may be formed on the substrate 100 .

[0185] A first peripheral wiring line 241 a and a peripheral contact plug 241 b may be formed on the substrate 100 .

[0186] Peripheral insulating films 261, 262, 263, 264 and 265 may be sequentially formed on the first peripheral wiring line 241a and the peripheral contact plug 241b. The second peripheral wiring line 243, the peripheral via plug 242 and the cell connection plug 244 may be formed inside the peripheral insulating films 261, 262, 263, 264 and 265.

[0187] Subsequently, a bit line BL may be formed on the fifth peripheral upper insulating film 265. The bit line BL may extend longitudinally in the second direction D2 on the substrate 100. A cell lower insulating film 171 may be formed on the fifth peripheral upper insulating film 265. The cell lower insulating film 171 may expose an upper surface of the bit line BL.

[0188] Reference Fig.32 and Fig.33 , the protruding insulating pattern 175 may be formed on the substrate 100 . Specifically, the protruding insulating pattern 175 may be formed on the bit line BL and the under-cell insulating film 171 .

[0189] The protruding insulating patterns 175 may extend in the first direction D1. The protruding insulating patterns 175 may be spaced apart from each other in the second direction D2.

[0190] From a plan view perspective, the protrusion insulating pattern 175 may cross the bit line BL. From a cross-sectional view perspective, the protrusion insulating pattern 175 may protrude from the bit line BL in the third direction D3.

[0191] Reference Figure 34 to Figure 36 , a pre-channel pattern AP_P, a pre-gate insulating film GOX_P, a first word line WL1, and a second word line WL2 may be formed.

[0192] The pre-channel pattern AP_P may be formed on the bit line BL and the protruding insulating pattern 175. The pre-channel pattern AP_P may extend along the upper surface of the bit line BL and the contour of the protruding insulating pattern 175. The pre-channel pattern AP_P may be on the upper surface of the protruding insulating pattern 175 and at least partially cover the upper surface of the protruding insulating pattern 175.

[0193] The pre-gate insulating film GOX_P may be formed on the pre-channel pattern AP_P. The pre-gate insulating film GOX_P may extend along the contour of the pre-channel pattern AP_P. The pre-gate insulating film GOX_P may be on the upper surface of the protruding insulating pattern 175 and at least partially cover the upper surface of the protruding insulating pattern 175.

[0194] The first word line WL1 and the second word line WL2 may be formed on the pre-gate insulating film GOX_P. The first word line WL1 and the second word line WL2 may be formed on the pre-gate insulating film GOX_P to be spaced apart from each other in the second direction D2. Based on the upper surface of the bit line BL, that is, in the case where the upper surface of the bit line BL provides a base reference plane, the first word line WL1 and the second word line WL2 may be formed below the upper surface of the protruding insulating pattern 175. Based on the upper surface of the bit line BL, that is, in the case where the upper surface of the bit line BL provides a base reference plane, the first word line WL1 and the second word line WL2 may be formed below the upper surface of the pre-channel pattern AP_P.

[0195] Reference Figure 37 to Figure 39 , the protruding insulation pattern 175 and the pre-channel pattern AP_P may be cut in the first direction D1.

[0196] The protruding insulating patterns 175 may be separated between the bit lines BL to be spaced apart in the first direction D1 . An upper surface of the cell under-insulating film 171 may be exposed between the protruding insulating patterns 175 in the first direction D1 .

[0197] The first pre-channel patterns AP1_P may be spaced apart from each other in the first direction D1. The second pre-channel patterns AP2_P may be spaced apart from each other in the first direction D1. The pre-channel patterns AP_P may be separated to form connection channel patterns AP_CP. The connection channel patterns AP_CP may be spaced apart from each other in the first direction D1. From a plan view perspective, the connection channel pattern AP_CP may be disposed between the first word line WL1 and the second word line WL2. In the first direction D1, the upper surface of the lower cell insulating film 171 may be exposed between the connection channel patterns AP_CP.

[0198] The pre-channel pattern AP_P disposed under the first word line WL1 and the second word line WL2 may not be cut in the first direction D1. Fig.39 In the FF cross-section of FIG. 1 , the pre-channel pattern AP_P may extend in the first direction D1 under the first word line WL1 .

[0199] The pre-channel pattern AP_P and the pre-gate insulating film (AP_P) at least partially covering the upper surface of the protruding insulating pattern 175 may be removed. Fig.35 As a result, the upper surface of the protruding insulating pattern 175 is exposed, and a gate insulating film GOX may be formed. The upper surface of the gate insulating film GOX may be coplanar with the upper surface of the protruding insulating pattern 175. The gate insulating film GOX may not be cut in the first direction D1. The gate insulating film GOX may extend in the first direction D1.

[0200] Reference Figure 40 to Figure 42 , a pre-insulating liner film 173P and an insulating filling film 174 may be formed.

[0201] In the first direction D1, the pre-insulating liner film 173P may be disposed between the protruding insulating patterns 175. In the first direction D1, the pre-insulating liner film 173P may at least partially fill the space between the first pre-channel patterns AP1_P. The pre-insulating liner film 173P may extend in the third direction D3 along the side of the first pre-channel pattern AP1_P.

[0202] The pre-insulating liner film 173P may at least partially fill a space between the second pre-channel patterns AP2_P in the first direction D1. The pre-insulating liner film 173P may extend in the third direction D3 along sides of the second pre-channel patterns AP2_P.

[0203] The pre-insulating liner film 173P may extend along the sidewalls of the gate insulating film GOX facing each other in the second direction D2 and the upper surface of the cell lower insulating film 171. The upper surface of the pre-insulating liner film 173P may be coplanar with the upper surface of the protruding insulating pattern 175. The upper surface of the pre-insulating liner film 173P may be coplanar with the upper surface of the gate insulating film GOX.

[0204] The insulating filling film 174 may be formed on the pre-insulating liner film 173P. An upper surface of the insulating filling film 174 may be coplanar with an upper surface of the pre-insulating liner film 173P. The pre-insulating liner film 173P may abut or at least partially surround the insulating filling film 174.

[0205] Reference Fig.43 and Fig.44 , a gate separation pattern GSS may be formed.

[0206] The gate separation pattern GSS may be formed on the cell lower insulating film 171, the channel structure AP_ST, the gate insulating film GOX, the first word line WL1, and the second word line WL2. The upper surface of the gate separation pattern GSS may be coplanar with the upper surface of the gate insulating film GOX and the upper surface of the pre-insulating liner film 173P. The gate separation pattern GSS may be formed on the cell lower insulating film 171 between the connection channel patterns AP_CP spaced apart in the first direction D1. The gate separation pattern GSS may be on and at least partially cover the connection channel pattern AP_CP and the gate insulating film GOX.

[0207] Reference Fig.45 and Fig.46 , a protruding groove 232R may be formed.

[0208] A protrusion groove 232R may be formed on an upper surface of the pre-insulation liner film 173P. A portion of the pre-insulation liner film 173P may be removed.

[0209] In the first direction D1, the protruding groove 232R may be formed on the sides of the first pre-channel pattern AP1_P and the second pre-channel pattern AP2_P. A portion of the pre-insulating liner film 173P that at least partially covers the sides of the first pre-channel pattern AP1_P and the second pre-channel pattern AP2_P may be removed. When the protruding groove 232R is formed, a portion of the sides of the first pre-channel pattern AP1_P and the second pre-channel pattern AP2_P may be exposed.

[0210] Reference Fig.47 and Fig.48 , a connection groove 231R may be formed.

[0211] The first pre-channel pattern ( Fig.45 and Fig.46 AP1_P) and a portion of the second pre-channel pattern ( Fig.45 and Fig.46 The first pre-channel pattern ( Fig.45 and 46The upper portion of AP1_P) and the second pre-channel pattern ( Fig.45 and 46 The upper portion of the protruding insulating pattern 175 has the same upper surface height as the protruding insulating pattern 175. Therefore, the first channel pattern AP1 and the second channel pattern AP2 may be formed. When the connection groove 231R is formed, the upper surface of the first channel pattern AP1 and the upper surface of the second channel pattern AP2 may be disposed below the upper surface of the protruding insulating pattern 175, such as Fig.47 shown.

[0212] In the third direction D3, the insulating liner film 173 may protrude beyond the first channel pattern AP1 and the second channel pattern AP2. Fig.45 and Fig.46 The upper portion of AP1_P) and the second pre-channel pattern ( Fig.45 and Fig.46 When the upper portion of the insulating liner film 173 is formed by the insulating liner film 173, the upper surface of the insulating liner film 173 may be set to be higher than the upper surface of the first channel pattern AP1 and the upper surface of the second channel pattern AP2. Fig.48 shown.

[0213] Reference Figures 49 to 51 , a contact pattern BC may be formed.

[0214] The contact pattern BC may be formed in the connection groove ( Fig.47 231R) and protruding grooves ( Fig.47 and Fig.48 The contact pattern BC may be on a portion of the side of the first channel pattern AP1 and the second channel pattern AP2 and at least partially cover the portion of the side. The contact pattern BC may at least partially fill the connection groove ( Fig.47 231R) and protruding grooves ( Fig.47 and Fig.48 232R).

[0215] In summarizing the detailed description, those skilled in the art will appreciate that various changes and modifications may be made to the preferred embodiments without substantially departing from the principles of the inventive concept. Therefore, the preferred embodiments disclosed in the present invention are only for general and descriptive purposes, and not for limiting purposes.

Claims

1. A semiconductor storage device, comprising: a first bit line extending in a first direction on the substrate; a word line on the first bit line and extending in a second direction crossing the first direction; a first channel pattern between the first bit line and the word line and extending along a first sidewall of the word line; as well as a first contact pattern on the first channel pattern, Wherein, in a cross-sectional view taken along the first channel pattern in the second direction, the first contact pattern includes: a connecting portion on the first channel pattern, and A protruding portion connected to the connecting portion and extending along a sidewall of the first channel pattern.

2. The semiconductor memory device according to claim 1, The width of the upper surface of the first contact pattern in the second direction is greater than the width of the upper surface of the first channel pattern in the second direction.

3. The semiconductor memory device according to claim 1, The width of the upper surface of the first contact pattern in the first direction is the same as the width of the upper surface of the first channel pattern in the first direction.

4. The semiconductor memory device according to claim 1, further comprising: a gate insulating film between the first side wall of the word line and the first channel pattern, The gate insulating film extends along a side wall of the first contact pattern.

5. The semiconductor memory device according to claim 1, further comprising: a second bit line spaced apart from the first bit line in the second direction; a second channel pattern between the second bit line and the word line, spaced apart from the first channel pattern in the second direction, and extending along a first sidewall of the word line; a second contact pattern on the second channel pattern and on a portion of a sidewall of the second channel pattern; as well as An insulating pattern is disposed between the first contact pattern and the second contact pattern.

6. The semiconductor memory device according to claim 5, The insulating pattern comprises: a first portion between the first contact pattern and the second contact pattern, and a second portion disposed below the first portion and between the first channel pattern and the second channel pattern with respect to the substrate providing a base reference plane, and A width of the first portion in the second direction is smaller than a width of the second portion in the second direction.

7. The semiconductor memory device according to claim 5, The insulating pattern comprises: a liner film under the first contact pattern and the second contact pattern relative to the substrate providing a base reference plane and extending along sidewalls of the first channel pattern and the second channel pattern, and A filling film is on the liner film and does not overlap the first contact pattern and the second contact pattern in a third direction perpendicular to the first direction and the second direction.

8. The semiconductor memory device according to claim 7, wherein the liner film comprises silicon nitride, and The filling film includes silicon oxide.

9. The semiconductor memory device according to claim 1, Wherein, relative to an upper surface of the first bit line providing a base reference plane, a lower surface of the protruding portion of the first contact pattern is below an upper surface of the word line.

10. The semiconductor memory device according to claim 1, Wherein, relative to an upper surface of the first bit line providing a base reference plane, a lower surface of the protruding portion of the first contact pattern is above a lower surface of the first channel pattern.

11. The semiconductor memory device according to claim 1, Wherein, relative to an upper surface of the first bit line providing a base reference plane, a lower surface of the connection portion of the first contact pattern is above an upper surface of the word line.

12. The semiconductor memory device according to claim 1, Wherein, relative to an upper surface of the first bit line providing a base reference plane, a lower surface of the connection portion of the first contact pattern is below an upper surface of the word line.

13. The semiconductor memory device according to claim 1, The lower surface of the word line completely overlaps with the first channel pattern in a third direction intersecting the first direction and the second direction.

14. The semiconductor memory device according to claim 1, further comprising: A capacitor is on the first contact pattern and connected to the first channel pattern.

15. A semiconductor storage device comprising: a first bit line extending in a first direction on the substrate; a word line on the first bit line and extending in a second direction crossing the first direction; a first channel pattern between the first bit line and the word line and extending along a first side wall of the word line in a third direction intersecting the first direction and the second direction; a first contact pattern on the first channel pattern; a second bit line spaced apart from the first bit line in the second direction and extending in the first direction; a second channel pattern between the second bit line and the word line, spaced apart from the first channel pattern in the second direction, and extending in the third direction along the first sidewall of the word line; a second contact pattern on the second channel pattern; as well as an insulating pattern between the first channel pattern and the second channel pattern, The insulating pattern comprises: a first portion between the first contact pattern and the second contact pattern, and a second portion below the first portion relative to the substrate providing a base reference plane and between the first channel pattern and the second channel pattern, and The width of the first portion is smaller than the width of the second portion.

16. The semiconductor memory device according to claim 15, The side surface of the first contact pattern overlaps the side surface of the first channel pattern in the second direction.

17. The semiconductor memory device according to claim 15, The lower surface of the first contact pattern is between the lower surface of the first channel pattern and the upper surface of the first channel pattern.

18. The semiconductor memory device according to claim 15, The first contact pattern comprises: a connecting portion on an upper surface of the first channel pattern, and A protruding portion is on a lower surface of the connecting portion and extends along a sidewall of the first channel pattern.

19. The semiconductor memory device according to claim 15, The entire lower surface of the word line extending in the second direction overlaps the first channel pattern in the third direction.

20. A semiconductor storage device, comprising: a first bit line extending in a first direction on the substrate; a word line on the first bit line and extending in a second direction crossing the first direction; a first channel pattern between the first bit line and the word line and extending along a first side wall of the word line in a third direction crossing the first direction and the second direction; a gate insulating film between the first channel pattern and the word line and extending in the third direction along a sidewall of the first channel pattern and the first sidewall of the word line; a first contact pattern on the first channel pattern; an insulating pattern extending along a side surface of the first contact pattern and a side surface of the first channel pattern; a landing pad on the first contact pattern; as well as a capacitor on the landing pad and connected to the first channel pattern, Wherein, in a cross-sectional view taken along the first channel pattern in the second direction, the first contact pattern includes: a connecting portion on the first channel pattern, and a protruding portion connected to the connecting portion and extending along the sidewall of the first channel pattern, and Wherein, relative to the substrate providing a base reference plane, a lower surface of the protruding portion is located above a lower surface of the first channel pattern.

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