Magnetic skyrmion memory

Abstract

The invention provides a magnetic skyrmion memory. The magnetic skyrmion memory comprises a magnetic structure track, a magnetic tunnel junction and a ferroelectric back gate. The magnetic structure track comprises a topological material layer and a ferromagnetic layer and is constructed to comprise a middle area and extension parts extending from the two sides of the middle area, and the ferromagnetic layers of the extension parts on the two sides are pinned in the opposite magnetic moment directions through antiferromagnetic coupling; the magnetic tunnel junction is located on the middle area of the magnetic structure track and is configured to be used for electrically reading the resistance state change of the memory; the ferroelectric back gate comprises a ferroelectric layer and a bottom electrode, and the ferroelectric back gate is located below the middle area of the magnetic structure track; when current is injected into the topological material layer, a spin-orbit moment is generated to regulate and control a magnetic structure in the ferromagnetic layer to move in the ferromagnetic layer, and the electric polarization direction of the ferroelectric layer is adjusted by applying grid voltage, so that the size of an antisymmetric exchange effect of an interface between the topological material layer and the ferromagnetic layer is regulated and controlled. Finally, the memory works in a Skyrmion mode or a binary mode.

Description

Technical Field

[0001] The present disclosure relates to the field of magnetic storage technology, and in particular to a magnetic skyrmion storage device. Background Art

[0002] As a topologically protected chiral magnetic structure, magnetic skyrmions have the advantages of small size, low drive circuit, and topological protection, and are expected to be used in the next generation of high-density, high-energy-efficiency spintronic devices. However, traditional ferromagnetic skyrmions have a significant skyrmion Hall effect and are easily annihilated at the edge of the device. In addition, ferromagnetic skyrmions move slowly, which limits the operating speed of the device. Although ferrimagnetic and antiferromagnetic skyrmions solve the above problems, it is difficult to achieve efficient electrical reading. Skyrmions can be stimulated to nucleate and drive through spin transfer torque or spin-orbit torque, but this requires higher current density and energy consumption. Summary of the invention

[0003] In view of this, in order to at least partially solve at least one of the above-mentioned technical problems, the present disclosure provides a magnetic skyrmion memory.

[0004] In order to achieve the above purpose, the technical solution of the present invention is as follows:

[0005] According to an embodiment of one aspect of the present disclosure, a magnetic skyrmion memory is provided, comprising: a magnetic structure racetrack, a magnetic tunnel junction, and a ferroelectric back gate.

[0006] The magnetic structure track includes a topological material layer and a ferrimagnetic layer, and is constructed to include a middle region and extensions extending from both sides of the middle region, respectively, and the ferrimagnetic layers of the extensions on both sides are pinned in opposite magnetic moment directions by antiferromagnetic coupling; the magnetic tunnel junction is located in the middle region of the magnetic structure track, and is constructed to be used for electrically reading the resistance state change of the memory; the ferroelectric back gate includes a ferroelectric layer and a bottom electrode, and the ferroelectric back gate is located below the middle region of the magnetic structure track;

[0007] When current is injected into the topological material layer, spin-orbit torque is generated to regulate the movement of the magnetic structure in the ferrimagnetic layer. By applying gate voltage to adjust the electric polarization direction of the ferroelectric layer, the magnitude of the antisymmetric exchange interaction at the interface between the topological material layer and the ferrimagnetic layer is regulated, ultimately making the memory operate in skyrmion mode or binary mode.

[0008] According to an embodiment of the present disclosure, the middle area of ​​the magnetic structure racetrack is circular, and the extension portion is in the shape of an elongated strip; the magnetic tunnel junction is located above the middle area of ​​the magnetic structure racetrack, and the magnetic tunnel junction is constructed in a circular shape and its diameter is not greater than the circular diameter of the middle area of ​​the magnetic structure racetrack.

[0009] According to an embodiment of the present disclosure, the memory also includes an interface layer, which is prepared between the topological material layer and the ferrimagnetic layer, and the interface layer is configured to improve the interface properties between the topological material layer and the ferrimagnetic layer, and improve the driving efficiency of the spin-orbit torque of the topological material layer.

[0010] According to an embodiment of the present disclosure, the magnetic structure includes magnetic domain walls and / or skyrmions.

[0011] According to the embodiment of the present disclosure, the ferroelectric layer may be HfZrO x , one or a combination of HfO2, BiFeO3, BaTiO3, In2Se3;

[0012] The material of the topological material layer is selected from one or a combination of topological insulators (BiSe)2Te3, Bi2Sb3, Bi2Se3, Sb2Te3, Bi2Te3, and topological semimetals PtSe2, WSe2, PtTe2, and WTe2; the material of the ferrimagnetic layer is selected from one or a combination of GdFeCo, GdFeO, GdCo, and TbCo; the material of the pinning material layer used for pinning is selected from (Co / Tb) periodic multilayer films, GdFeCo, GdFeO, TbCo, and GdCo alloy materials, and by adjusting the chemical component ratio, the pinning materials on both sides have different coercive forces; the pinning material layers on both sides are configured to have opposite magnetic moment directions by an external magnetic field.

[0013] According to an embodiment of the present disclosure, a magnetic tunnel junction includes a ferromagnetic free layer and a ferromagnetic reference layer, wherein the ferromagnetic free layer and the ferromagnetic reference layer are separated by a non-magnetic insulating barrier layer; the ferromagnetic free layer and the ferrimagnetic layer are antiferromagnetically coupled through a space layer located between the two; the ferromagnetic reference layer is pinned by a synthetic antiferromagnetic structure formed thereon; the materials of the ferromagnetic free layer and the ferromagnetic reference layer are selected from one or a combination of CoFeB, CoFe, and Co; the insulating barrier layer material is selected from MgO, AlO x One or a combination of the above; the space layer material is selected from one or a combination of Ru, Cu, and W.

[0014] According to the embodiments of the present disclosure, different voltages are applied to the back gate to change the electric polarization direction of the ferroelectric layer. The electric polarization direction can regulate the magnitude of the antisymmetric exchange interaction at the interface between the topological material layer and the ferrimagnetic layer, thereby changing the device operating mode. When the interface antisymmetric exchange interaction is greater than a set threshold, skyrmions can exist stably, and the memory operates in the skyrmion mode. When the interface antisymmetric exchange interaction is less than a set threshold, skyrmions cannot exist stably, and the device operates in the binary mode.

[0015] According to the embodiments of the present disclosure, the two ends of the ferrimagnetic layer are pinned in opposite magnetic moment directions, and a stable magnetic domain wall exists at the edge of the pinned region at one end; by applying a driving current to the topological material layer, the magnetic domain wall can be driven to the edge of the middle region of the magnetic structure track; the two ends of the magnetic domain wall at the edge of the middle region are pinned, and the non-uniform tension on the magnetic domain wall will break to form skyrmions; due to the strong antiferromagnetic coupling between the ferrimagnetic layer and the ferromagnetic free layer, corresponding skyrmions will also be generated in the ferromagnetic layer, thereby changing the resistance state of the magnetic tunnel junction.

[0016] According to the embodiments of the present disclosure, more resistance states are achieved by making more skyrmions stably exist in the middle region of the magnetic structure racetrack; and the operating speed of the device is increased by increasing the movement speed of skyrmions.

[0017] According to the embodiment of the present disclosure, the memory also includes three transistors: a gate control tube, a write control tube, and a read control tube. The gate control tube is configured as a select gate. When switching the working mode, the select gate voltage is pulled up to the power supply voltage V DD , turn on the gate control tube, pull the write word line WBL voltage up to the mode selection voltage Vselect, and the other metal lines are grounded. Apply gate voltage to regulate the polarization direction of the ferroelectric layer. When working in binary mode and performing a write 0 operation, the write bit line WWL voltage is pulled up to the power supply voltage V DD , the write word line WBL is pulled high to the first write voltage V write1 , the remaining metal lines are grounded, and the write current flows from the write word line into the source line SL to drive the magnetic domain wall movement and flip the magnetic moment of the ferrimagnetic layer; when performing the write 1 operation, the source line voltage is pulled up to the first write voltage V write1 , the write word line is grounded to implement the write 1 operation; when working in the skyrmion mode, the write bit line WWL voltage is pulled up to the power supply voltage V DD , the write word line WBL voltage is pulled up to the second write voltage V write2 , V write2 ≠V write1 , the rest of the metal wires are grounded. At this time, under the action of the non-uniform tension generated by the current, the magnetic domain wall breaks to form skyrmions. The accumulated number of skyrmions is linearly related to the resistance of the magnetic tunnel junction. When the reset operation is performed, the write bit line WWL voltage is pulled up to the power supply voltage V DD , the source line voltage is pulled up to the first write voltage V write1 , driving the magnetic domain wall back to its initial position. Due to the antiferromagnetic pinning at both ends of the magnetic structure track, the magnetic domain wall will not be annihilated.

[0018] The magnetic skyrmion memory proposed in the present disclosure uses a ferroelectric back gate to regulate the memory operation mode and enrich the device functions; the topological material used has a spin Hall angle much larger than that of conventional heavy metal materials, which improves the device energy efficiency; ferrimagnetic skyrmions effectively suppress the skyrmion Hall effect, reduce the size of skyrmions, and increase the movement speed of skyrmions, so that more skyrmions can exist stably and realize more resistance states. At the same time, the device operation speed and energy efficiency are improved; the conventional CoFeB-based magnetic tunnel junction can be used to achieve efficient electrical reading through the antiferromagnetic coupling between the ferrimagnetic layer and the ferromagnetic free layer; the two ends of the ferrimagnetic layer are pinned in opposite magnetization directions through the antiferromagnetic coupling with the pinning material, so that there are stable magnetic domain walls in the memory, and the spin-orbit moment is used to drive the magnetic domain walls to break into skyrmions in the circular area below the magnetic tunnel junction, which can greatly reduce the energy consumption of skyrmion nucleation and improve the device energy efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0020] Figure 1A A schematic diagram of a main film stack structure of a magnetic skyrmion memory provided by an embodiment of the present disclosure;

[0021] Figure 1B A schematic diagram of another main film stack structure of a magnetic skyrmion memory provided by an embodiment of the present disclosure;

[0022] Figure 2 A schematic diagram of the three-dimensional structure of a magnetic skyrmion memory provided by an embodiment of the present disclosure;

[0023] Figure 3 A schematic diagram of the mechanism of the ferroelectric polarization regulation working mode of the ferroelectric layer according to an embodiment of the present disclosure;

[0024] Figure 4 A schematic diagram of antiferromagnetic coupling between a ferrimagnetic layer and a ferromagnetic layer according to an embodiment of the present disclosure;

[0025] Figure 5 A schematic diagram of the mechanism of converting a magnetic domain wall into skyrmions according to an embodiment of the present disclosure;

[0026] Figure 6 Schematic diagram of resistance state reversal curves of the magnetic skyrmion memory in different working modes according to the embodiment of the present disclosure;

[0027] Figure 7 A schematic diagram of a magnetic skyrmion memory connected to an external circuit and related operating parameters according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] The present disclosure provides a magnetic skyrmion memory having the advantages of small size, low driving voltage, and topological protection, and is expected to be applied to the next generation of high-density, high-energy-efficiency spin electronic devices.

[0029] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0030] In an embodiment of the present disclosure, a magnetic skyrmion memory is provided, Figure 1A , Figure 1B , Figure 2 As shown, the memory includes: a magnetic structure track, a magnetic tunnel junction, and a ferroelectric back gate. The magnetic structure track includes a topological material layer and a ferrimagnetic layer, and is constructed to include a middle area and extensions extending from both sides of the middle area, respectively, and the ferrimagnetic layers of the extensions on both sides are pinned in opposite magnetic moment directions by antiferromagnetic coupling; the magnetic tunnel junction is located in the middle area of ​​the magnetic structure track, and is constructed to be used for electrically reading the resistance state change of the memory; the ferroelectric back gate includes a ferroelectric layer and a bottom electrode, and the ferroelectric back gate is located under the middle area of ​​the magnetic structure track; when the topological material layer injects current, a spin-orbit moment is generated to regulate the movement of the magnetic structure in the ferrimagnetic layer in the ferrimagnetic layer, and the polarization direction of the ferroelectric layer is adjusted by applying a gate voltage, thereby regulating the magnitude of the antisymmetric exchange interaction at the interface between the topological material layer and the ferrimagnetic layer, and finally making the memory work in a skyrmion mode or a binary mode.

[0031] According to the embodiment of the present disclosure, Figure 2 As shown, the middle area of ​​the magnetic structure track is circular, and the extended part is a long strip; the magnetic tunnel junction is located above the middle area of ​​the magnetic structure track, and the magnetic tunnel junction is constructed in a circular shape and its diameter is not larger than the circular diameter of the middle area of ​​the magnetic structure track.

[0032] According to the embodiment of the present disclosure, Figure 1B As shown, the memory may also include an interface layer, which is prepared between the topological material layer and the ferrimagnetic layer, and the interface layer is configured to improve the interface properties between the topological material layer and the ferrimagnetic layer, improve the driving efficiency of the spin-orbit moment of the topological material layer, and improve the energy efficiency of the memory device.

[0033] According to an embodiment of the present disclosure, the magnetic structure includes magnetic domain walls and / or skyrmions.

[0034] According to the embodiment of the present disclosure, the ferroelectric layer may be HfZrO x , one or a combination of HfO2, BiFeO3, BaTiO3, In2Se3;

[0035] The material of the topological material layer is selected from one or a combination of topological insulators (BiSe)2Te3, Bi2Sb3, Bi2Se3, Sb2Te3, Bi2Te3, and topological semimetals PtSe2, WSe2, PtTe2, and WTe2; the material of the ferrimagnetic layer is selected from one or a combination of GdFeCo, GdFeO, GdCo, and TbCo; the material of the pinning material layer used for pinning is selected from (Co / Tb) periodic multilayer films, GdFeCo, GdFeO, TbCo, and GdCo alloy materials, and by adjusting the chemical component ratio, the pinning materials on both sides have different coercive forces; the pinning material layers on both sides are configured to have opposite magnetic moment directions by an external magnetic field.

[0036] According to an embodiment of the present disclosure, a magnetic tunnel junction includes a ferromagnetic free layer and a ferromagnetic reference layer, wherein the ferromagnetic free layer and the ferromagnetic reference layer are separated by a non-magnetic insulating barrier layer; Figure 2 As shown, the ferromagnetic free layer and the ferrimagnetic layer are antiferromagnetically coupled through a space layer located between the two; the ferromagnetic reference layer is pinned by a synthetic antiferromagnetic structure formed thereon; the materials of the ferromagnetic free layer and the ferromagnetic reference layer are selected from one or a combination of CoFeB, CoFe, and Co; the insulating barrier layer material is selected from MgO, AlO x One or a combination of the above, x represents a component; the space layer material is selected from one or a combination of Ru, Cu, and W.

[0037] According to the embodiments of the present disclosure, different voltages are applied to the back gate to change the electric polarization direction of the ferroelectric layer. The electric polarization direction can regulate the magnitude of the antisymmetric exchange interaction at the interface between the topological material layer and the ferrimagnetic layer, thereby changing the device operating mode. When the interface antisymmetric exchange interaction is greater than a set threshold, skyrmions can exist stably, and the memory operates in the skyrmion mode. When the interface antisymmetric exchange interaction is less than a set threshold, skyrmions cannot exist stably, and the device operates in the binary mode.

[0038] According to the embodiments of the present disclosure, the two ends of the ferrimagnetic layer are pinned in opposite magnetic moment directions, and a stable magnetic domain wall exists at the edge of the pinned region at one end; by applying a driving current to the topological material layer, the magnetic domain wall can be driven to the edge of the middle region of the magnetic structure track; the two ends of the magnetic domain wall at the edge of the middle region are pinned, and the non-uniform tension on the magnetic domain wall will break to form skyrmions; due to the strong antiferromagnetic coupling between the ferrimagnetic layer and the ferromagnetic free layer, corresponding skyrmions will also be generated in the ferromagnetic layer, thereby changing the resistance state of the magnetic tunnel junction.

[0039] According to the embodiments of the present disclosure, more resistance states are achieved by making more skyrmions stably exist in the middle region of the magnetic structure racetrack; and the operating speed of the device is increased by increasing the movement speed of skyrmions.

[0040] According to the embodiment of the present disclosure, the memory also includes three transistors: a gate control tube, a write control tube, and a read control tube. The gate control tube is configured as a selection gate. When switching the working mode, the selection gate voltage is pulled up to the power supply voltage V DD , turn on the gate control tube, pull the write word line WBL voltage up to the mode selection voltage Vselect, and the other metal lines are grounded. Apply gate voltage to regulate the polarization direction of the ferroelectric layer. When working in binary mode and performing a write 0 operation, the write bit line WWL voltage is pulled up to the power supply voltage V DD , the write word line WBL is pulled high to the first write voltage V write1 , the remaining metal lines are grounded, and the write current flows from the write word line into the source line SL to drive the magnetic domain wall movement and flip the magnetic moment of the ferrimagnetic layer; when performing the write 1 operation, the source line voltage is pulled up to the first write voltage V write1 , the write word line is grounded to implement the write 1 operation; when working in the skyrmion mode, the write bit line WWL voltage is pulled up to the power supply voltage V DD , the write word line WBL voltage is pulled up to the second write voltage V write2 , V write2 ≠V write1 , the rest of the metal wires are grounded. At this time, under the action of the non-uniform tension generated by the current, the magnetic domain wall breaks to form skyrmions. The accumulated number of skyrmions is linearly related to the resistance of the magnetic tunnel junction. When the reset operation is performed, the write bit line WWL voltage is pulled up to the power supply voltage V DD , the source line voltage is pulled up to the first write voltage V write1 , driving the magnetic domain wall back to its initial position. Due to the antiferromagnetic pinning at both ends of the magnetic structure track, the magnetic domain wall will not be annihilated.

[0041] In the embodiments of the present disclosure, Figure 3 As shown in the figure, due to the strong spin-orbit coupling effect, there is a strong antisymmetric exchange interaction (Dzyaloshinskii–Moriya interaction, DMI) at the interface between the topological material layer and the ferrimagnetic layer. The character D in the figure represents the DMI constant, and the character P represents the ferroelectric polarization. The strong interface DMI ensures that room temperature stable skyrmions can exist in the system. The ferroelectric polarization of the ferroelectric layer can regulate the amplitude of the interface DMI. When the DMI is reduced to the threshold, room temperature stable skyrmions cannot be formed in the memory system. For example, when the ferroelectric polarization is upward, denoted as P>0, the interface DMI is enhanced to exceed the threshold, and the skyrmions can exist stably. At this time, the device will work in the skyrmion mode; when the ferroelectric polarization is downward, denoted as P<0, the DMI is reduced to below the threshold, and the skyrmions cannot exist stably. At this time, the device works in the binary mode.

[0042] In the embodiments of the present disclosure, Figure 4As shown, ferrimagnetic skyrmions can effectively suppress the skyrmion Hall effect, increase the skyrmion movement speed, reduce the skyrmion size, etc. However, the efficient electrical reading of ferrimagnetism needs to be solved urgently. Due to the skyrmion Hall effect, skyrmions in ferromagnetic materials are easily annihilated at the device boundary, and the skyrmion movement speed is slow, which limits the device operating speed. However, in ferromagnetic materials represented by CoFeB, magnetic tunnel junctions with higher tunneling magnetoresistance ratio (TMR) can be achieved, achieving efficient electrical reading. Therefore, in the skyrmion memory disclosed in the present invention, the ferrimagnetic layer is antiferromagnetically coupled with the ferromagnetic free layer. Skyrmions nucleate and move in the ferrimagnetic racetrack. Due to the antiferromagnetic coupling, corresponding skyrmions will also be formed in the ferromagnetic layer, and the skyrmion resistance state will be read through the TMR effect.

[0043] In the embodiments of the present disclosure, Figure 5 As shown in the figure, both ends of the ferrimagnetic track in the magnetic structure track are pinned by antiferromagnetic coupling, so a stable magnetic domain wall is formed at the edge of the pinned area. When current is applied, the spin-orbit coupling torque generated by the spin Hall effect (SHE) or the Rashba-Edelstein effect drives the movement of the magnetic domain wall. When the magnetic domain wall moves to the boundary of the circular area, both ends of the magnetic domain wall are pinned by the boundary. Due to the tension shown by the arrow at the boundary of the circular area, the magnetic domain wall will break, forming a stable skyrmion as in the middle area.

[0044] In the embodiments of the present disclosure, Figure 6 As shown in the figure, when the magnetic memory device works in the binary mode, skyrmions cannot be formed. The dark color in the circular area indicates that the magnetic moment is upward, and the light color area indicates that the magnetic moment is downward. The transition area between the dark and light colors indicates the magnetic domain wall. At this time, the current drives the magnetic domain wall to expand, causing the magnetic tunnel junction area to flip. When the magnetic memory device works in the skyrmion mode, skyrmions are stably generated at the boundary of the magnetic tunnel junction area under the stimulation of current. As the accumulated number of skyrmions in the magnetic tunnel junction area is different, the resistance of the memory device is different, which is reflected in the multi-step flip curve shown in the figure.

[0045] In the embodiments of the present disclosure, Figure 7 As shown, the memory also includes three transistors: a gate control tube, a write control tube, and a read control tube. The gate control tube is configured as a select gate. When the memory device switches modes, the voltage of the select gate is pulled up to the power supply voltage V DD , turn on the gate control tube, pull the write word line WBL voltage up to the mode selection voltage Vselect, and the other metal lines are grounded. Applying gate voltage controls the polarization direction of the ferroelectric layer. When performing a write 0 operation, the write bit line WWL voltage is pulled up to the power supply voltage V DD , the write word line WBL is pulled high to the first write voltage V write1, the remaining metal lines are grounded, and the write current flows from the write word line into the source line SL to drive the magnetic domain wall movement and flip the magnetic moment of the ferrimagnetic layer; when performing the write 1 operation, the source line voltage is pulled up to the first write voltage V write1 , the write word line is grounded to implement the write 1 operation; when working in the skyrmion mode, the write bit line WWL voltage is pulled up to the power supply voltage V DD , the write word line WBL voltage is pulled up to the second write voltage V write2 , (V write2 ≠V write1 ), the rest of the metal wires are grounded. At this time, under the action of the non-uniform tension generated by the current, the magnetic domain wall breaks to form skyrmions; the accumulated number of skyrmions is linearly related to the resistance of the magnetic tunnel junction. When performing a reset operation, the write bit line WWL voltage is pulled up to the power supply voltage V DD , the source line voltage is pulled up to the first write voltage V write1 , driving the magnetic domain wall back to its initial position. Due to the antiferromagnetic pinning at both ends of the magnetic structure track, the magnetic domain wall will not be annihilated.

[0046] So far, the embodiments of the present disclosure have been described in detail in conjunction with the accompanying drawings. It should be noted that the implementation methods not shown or described in the drawings or the body of the specification are all forms known to ordinary technicians in the relevant technical field and are not described in detail. In addition, the above definitions of each element and method are not limited to the various specific structures, shapes or methods mentioned in the embodiments, and ordinary technicians in the field can simply change or replace them.

[0047] According to the above description, those skilled in the art should have a clear understanding of the magnetic skyrmion memory disclosed in the present invention.

[0048] In summary, the present disclosure provides a magnetic skyrmion memory, in which the two ends of the ferrimagnetic layer are pinned in opposite magnetization directions through antiferromagnetic coupling with the pinning material, so that a stable magnetic domain wall exists in the memory, and the spin-orbit torque is used to drive the magnetic domain wall to break into skyrmions in the circular area below the magnetic tunnel junction, which can greatly reduce the energy consumption of skyrmion nucleation and improve the energy efficiency of the memory device.

[0049] It should be noted that, in this document, unless otherwise specified, “a” element is not limited to a single element, but may include one or more elements.

[0050] In addition, in this document, unless otherwise specified, ordinal numbers such as "first" and "second" are only used to distinguish multiple components with the same name, and do not indicate that there is a hierarchy, level, execution order, or process order between them. A "first" component and a "second" component may appear together in the same component, or appear in different components. The presence of a component with a larger ordinal number does not necessarily indicate the presence of another component with a smaller ordinal number.

[0051] In this document, unless otherwise specified, the so-called feature A "or" or "and / or" (and / or) feature B means that A exists alone, B exists alone, or A and B exist at the same time; the so-called feature A "and" (and) or "and" (and) or "and" (and) feature B means that A and B exist at the same time; the so-called "include", "comprise", "have" and "contain" mean including but not limited to these.

[0052] In addition, in this document, the terms "upper", "lower", "left", "right", "front", "back", or "between" are only used to describe the relative positions between multiple elements, and can be extended to include translation, rotation, or mirroring. In addition, in this document, unless otherwise specified, "an element is on another element" or similar descriptions do not necessarily mean that the element contacts the other element.

[0053] In addition, unless the steps are specifically described or must occur in sequence, the order of the above steps is not limited to the above list, and can be changed or rearranged according to the required design. And the above embodiments can be mixed and matched with each other or with other embodiments based on design and reliability considerations, that is, the technical features in different embodiments can be freely combined to form more embodiments.

[0054] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above description is only a specific embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A magnetic skyrmion memory, comprising: A magnetic structure racetrack, comprising a topological material layer and a ferrimagnetic layer, and being constructed to include a middle region and extensions extending from both sides of the middle region, wherein the ferrimagnetic layers of the extensions on both sides are pinned in opposite magnetic moment directions by antiferromagnetic coupling; A magnetic tunnel junction, located in the middle region of the magnetic structure racetrack and configured to electrically read a change in the resistance state of the memory; A ferroelectric back gate, comprising a ferroelectric layer and a bottom electrode, wherein the ferroelectric back gate is located under the middle region of the magnetic structure racetrack; When current is injected into the topological material layer, a spin-orbit torque is generated to regulate the movement of the magnetic structure in the ferrimagnetic layer in the ferrimagnetic layer. By applying a gate voltage to adjust the polarization direction of the ferroelectric layer, the magnitude of the antisymmetric exchange interaction at the interface between the topological material layer and the ferrimagnetic layer is regulated, thereby ultimately making the memory operate in a skyrmion mode or a binary mode.

2. The memory according to claim 1, wherein: The middle area of ​​the magnetic structure track is circular, and the extended part is long and narrow; The magnetic tunnel junction is located above the middle area of ​​the magnetic structure racetrack, and the magnetic tunnel junction is constructed in a circular shape with a diameter no greater than the circular diameter of the middle area of ​​the magnetic structure racetrack.

3. The memory according to claim 1 further includes an interface layer, which is prepared between the topological material layer and the ferrimagnetic layer, and the interface layer is configured to improve the interface properties between the topological material layer and the ferrimagnetic layer and improve the driving efficiency of the spin-orbit moment of the topological material layer. 4 . The memory according to claim 1 , wherein the magnetic structure comprises a magnetic domain wall and / or a skyrmion.

5. The memory according to claim 1, wherein: The ferroelectric layer may be HfZrO x , one or a combination of HfO2, BiFeO3, BaTiO3, In2Se3; The material of the topological material layer is selected from one or a combination of topological insulators (BiSe)2Te3, Bi2Sb3, Bi2Se3, Sb2Te3, Bi2Te3, and topological semimetals PtSe2, WSe2, PtTe2, and WTe2; The material of the ferrimagnetic layer is selected from one or a combination of GdFeCo, GdFeO, GdCo and TbCo; The pinning material layer used for pinning is selected from (Co / Tb) periodic multilayer film, GdFeCo, GdFeO, TbCo, and GdCo alloy materials. By adjusting the chemical composition ratio, the pinning materials on both sides have different coercive forces; the pinning material layers on both sides are configured with opposite magnetic moment directions through an external magnetic field.

6. The memory according to claim 1, wherein the magnetic tunnel junction comprises a ferromagnetic free layer and a ferromagnetic reference layer, wherein the ferromagnetic free layer and the ferromagnetic reference layer are separated by a non-magnetic insulating barrier layer; the ferromagnetic free layer and the ferrimagnetic layer are antiferromagnetically coupled via a space layer located therebetween; and the ferromagnetic reference layer is pinned by a synthetic antiferromagnetic structure formed thereon; The materials of the ferromagnetic free layer and the ferromagnetic reference layer are selected from one or a combination of CoFeB, CoFe, and Co; the material of the insulating barrier layer is selected from MgO, AlO x One or a combination of the above; the space layer material is selected from one or a combination of Ru, Cu, and W.

7. The memory according to claim 1, wherein different voltages are applied to the back gate to change the polarization direction of the ferroelectric layer, and the polarization direction can regulate the magnitude of the antisymmetric exchange interaction at the interface between the topological material layer and the ferrimagnetic layer, thereby changing the device operation mode; When the interface antisymmetric exchange interaction is greater than the set threshold, skyrmions can exist stably, and the memory works in the skyrmion mode. When the interface antisymmetric exchange interaction is smaller than the set threshold, skyrmions cannot exist stably and the device operates in binary mode.

8. According to the memory described in claim 1, the two ends of the ferrimagnetic layer are pinned in opposite magnetic moment directions, and there is a stable magnetic domain wall at the edge of the pinning area at one end; by applying a driving current to the topological material layer, the generated spin-orbit torque can drive the magnetic domain wall to the edge of the middle area of ​​the magnetic structure track; at the edge of the middle area, the two ends of the magnetic domain wall are pinned, and the non-uniform tension on the magnetic domain wall will break to form skyrmions; due to the strong antiferromagnetic coupling between the ferrimagnetic layer and the ferromagnetic free layer, corresponding skyrmions will also be generated in the ferromagnetic layer, thereby changing the resistance state of the magnetic tunnel junction.

9. The memory according to claim 1 realizes more resistance states by making more skyrmions stably exist in the middle area of ​​the magnetic structure racetrack; and increases the operating speed of the device by increasing the movement speed of skyrmions.

10. The memory according to claim 1, further comprising three transistors, namely, a gate control transistor, a write control transistor, and a read control transistor, wherein the gate control transistor is configured as a selection gate; When switching the working mode, the selection gate voltage is pulled up to the power supply voltage V DD , turn on the gate control tube, and pull the write word line WBL voltage up to the mode selection voltage V select , the rest of the metal wires are grounded, and gate voltage is applied to regulate the polarization direction of the ferroelectric layer; When working in binary mode and performing a write 0 operation, the write bit line WWL voltage is pulled up to the power supply voltage V DD , the write word line WBL is pulled high to the first write voltage V write1 , the remaining metal lines are grounded, and the write current flows from the write word line into the source line SL to drive the magnetic domain wall movement and flip the magnetic moment of the ferrimagnetic layer; when performing the write 1 operation, the source line voltage is pulled up to the first write voltage V write1 , the write word line is grounded to implement the write 1 operation; When operating in the skyrmion mode, the write bit line WWL voltage is pulled up to the power supply voltage V DD , the write word line WBL voltage is pulled up to the second write voltage V write2 , V write2 ≠V write1 , the rest of the metal wires are grounded. At this time, under the action of the non-uniform tension generated by the current, the magnetic domain wall breaks to form skyrmions. The accumulated number of skyrmions is linearly related to the resistance of the magnetic tunnel junction. When performing a reset operation, the write bit line WWL voltage is pulled up to the power supply voltage V DD , the source line voltage is pulled up to the first write voltage V write1 , driving the magnetic domain wall back to its initial position. Due to the antiferromagnetic pinning at both ends of the magnetic structure track, the magnetic domain wall will not be annihilated.

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