Semiconductor package

Abstract

The invention relates to a semiconductor package. A semiconductor package includes: a substrate; the first chip and the second chip are stacked on the substrate; each of the plurality of semiconductor devices includes a first pad, a cell region, a first-stage serializer-deserializer connected to the first pad, a second-stage serializer-deserializer connected between the first-stage serializer-deserializer and the cell region, and a second pad connected to a node between the first-stage serializer-deserializer and the second-stage serializer-deserializer; and a first connection member connecting the second pad of the first chip to the second pad of the second chip.

Description

Technical Field

[0001] Various embodiments generally relate to a semiconductor package having a chip stack structure. Background Art

[0002] According to the demand for high integration, the integration has been increased by a shrinking method of reducing line width, but as the shrinking technology has reached its limit, a chip stacking structure has received attention.

[0003] The chip stacking structure includes a plurality of chips stacked on each other. The plurality of chips in the chip stacking structure can transmit and receive signals to and from other devices through bonding wires. Summary of the invention

[0004] In an embodiment, a semiconductor package may include: a substrate; a first chip and a second chip stacked on the substrate, the first chip and the second chip each including a first pad, a unit area, a first-level serializer-deserializer connected to the first pad, a second-level serializer-deserializer connected between the first-level serializer-deserializer and the unit area, and a second pad connected to a node between the first-level serializer-deserializer and the second-level serializer-deserializer; and a first connecting member connecting the second pad of the first chip to the second pad of the second chip.

[0005] In an embodiment, a semiconductor package may include: a first chip, which is disposed on a substrate, the first chip includes an external data pad, a first slice data pad, and a first-level serializer-deserializer connected between the external data pad and the first slice data pad; a second chip, which is stacked on the first chip, the second chip includes a second slice data pad and a second-level serializer-deserializer connected to the second slice data pad; and a first connecting member, which connects the first slice data pad and the second slice data pad.

[0006] In an embodiment, a semiconductor package may include: a substrate; a first chip and a second chip stacked on the substrate, the first chip and the second chip each including an external signal pad and a chip signal pad, the external signal pad being included in a first pad column located in a first edge portion, and the chip signal pad being included in a second pad column located in the first edge portion; a first connecting member connecting the chip signal pad of the first chip to the chip signal pad of the second chip; and a second connecting member connecting the substrate to the external signal pad of the first chip, wherein, in each of the first chip and the second chip, the first pad column is arranged between a chip side surface included in the first edge portion and the second pad column.

[0007] In an embodiment, a semiconductor package may include: a substrate; a first chip stacked on the substrate, the first chip including external signal pads and first signal pads, the external signal pads being included in a first pad column located in a first edge portion, and the first signal pads being included in a second pad column located in the first edge portion; a second chip stacked on the first chip, the second chip including second signal pads; a first connecting member connecting the first signal pads to the second signal pads; and a second connecting member connecting the substrate to the external signal pads, wherein the first pad column is disposed between a side surface of the first chip included in the first edge portion and the second pad column. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of a memory system including a semiconductor package according to an embodiment of the disclosed technology.

[0009] Figure 2 is a perspective view of a semiconductor package according to an embodiment of the disclosed technology.

[0010] Figure 3 It is along Figure 2 A cross-sectional view taken along line II′.

[0011] Figure 4 It is along Figure 2 A cross-sectional view taken along line II-II′.

[0012] Figures 5 to 8 is a diagram illustrating a data input / output path of a semiconductor package according to an embodiment of the disclosed technology.

[0013] Fig. 9 , Fig.10 , Fig.12 and Fig.14 is a perspective view of a semiconductor package according to an embodiment of the disclosed technology.

[0014] Fig.11 It is along Fig.10 A cross-sectional view taken along line III-III′.

[0015] Fig.13 is an example Fig.12 A three-dimensional view of a substrate, a first chip, and a connecting member connecting the substrate and the first chip. DETAILED DESCRIPTION

[0016] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, although the same elements are shown in different drawings, the same elements will be referred to by the same reference numerals. In addition, in the following description of the present disclosure, when the detailed description of the known functions and structures incorporated herein may make the subject matter of the present disclosure unclear, the detailed description will be omitted. It should be noted that, unless otherwise clearly stated, the terms "including", "having", "comprising" etc. used in the specification and claims should not be interpreted as being limited to the elements listed thereafter. When using indefinite or definite articles (such as "one", "an" and "the") when referring to a singular noun, unless otherwise clearly stated, this may include the plural form of the noun.

[0017] In addition, when describing the components of the present disclosure, terms such as first, second, A, B, (a), and (b) may be used. These terms are only for the purpose of distinguishing one component from another component, and do not limit the substance, order, sequence, or quantity of the components.

[0018] In the description of the positional relationship of components, when it is described that at least two components are “connected,” “coupled,” or “linked,” it is to be understood that the at least two components may be directly “connected,” “coupled,” or “linked,” and may be indirectly “connected,” “coupled,” or “linked” using another component interposed between the two components. Here, the other component may be included in at least one of the at least two components that are “connected,” “coupled,” or “linked” to each other.

[0019] In the description of the time flow relationship of an operating method, a manufacturing method, or a component, when the temporal sequence or the process sequence is described, for example, by "after," "subsequently," "next," or "before," non-continuous situations may be included unless "immediately" or "directly" is used.

[0020] When referring to a numerical value of a component or its corresponding information (e.g., level, etc.), even without a separate explicit description, the numerical value or its corresponding information can be interpreted as including an error range that may be caused by various factors (e.g., process variables, internal or external shocks, noise, etc.).

[0021] Hereinafter, various embodiments of the disclosed technology will be described in detail with reference to the accompanying drawings.

[0022] Various embodiments are directed to providing a semiconductor package having a chip stack structure.

[0023] According to an embodiment, a semiconductor package having a chip stack structure having a plurality of chips capable of transmitting and receiving signals to and from other devices through bonding wires may be manufactured.

[0024] Figure 1 is a block diagram of a memory system including a semiconductor package according to an embodiment of the disclosed technology.

[0025] Reference Figure 1 , the semiconductor package 10 may be connected to the external device 20 through the channel CH.

[0026] The external device 20 may control the overall operation (eg, a read operation and a write operation) of the semiconductor package 10 in response to a request of a host (not shown). The external device 20 may include a memory controller or a processor.

[0027] The semiconductor package 10 may include a first chip 11 and a second chip 12. Hereinafter, a case where the semiconductor package 10 includes two semiconductor chips will be described, but the disclosed technology is not limited thereto. The semiconductor package 10 may include at least three semiconductor chips. The semiconductor chips included in the semiconductor package 10 may be referred to as slices.

[0028] The first chip 11 and the second chip 12 may include various types of memories. For example, each of the first chip 11 and the second chip 12 may include a dynamic random access memory (DRAM). However, the disclosed technology is not limited thereto, and each of the first chip 11 and the second chip 12 may include a volatile memory such as an SRAM (static RAM), or a non-volatile memory such as a NAND flash memory, a resistive RAM (RRAM), a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), and a ferroelectric RAM (FRAM).

[0029] The first chip 11 may operate as a master chip, and the second chip 12 may operate as a slave chip. The first chip 11 and the second chip 12 may operate as follows: they receive the same chip selection signal, and specific layers of the first chip 11 and the second chip 12 may be accessed through an address signal. In another embodiment, the first chip 11 and the second chip 12 may be used as different logic blocks.

[0030] The first chip 11 may be connected to the channel CH to interface with the external device 20 through the channel CH, may exchange data with the external device 20 , and may receive a command, an address, and a clock from the external device 20 .

[0031] The first chip 11 may be connected to the second chip 12 to interface with the second chip 12 , may exchange data with the second chip 12 , and may provide commands and addresses to the second chip 12 .

[0032] The first chip 11 may parallelize write data input from the external device 20. The first chip 11 may serialize data read from the first chip 11 or the second chip 12, and may output the data to the external device 20. The first chip 11 may generate an internal command by decoding a command input from the external device 20. The first chip 11 may generate an internal address by decoding an address input from the external device 20. The internal command may include an internal read command and an internal write command. The internal address may include a bank address, a row address, and a column address.

[0033] The first chip 11 may output parallelized write data to the second chip 12, and may receive read data from the second chip 12. The first chip 11 may provide the second chip 12 with an internal command and an internal address.

[0034] The second chip 12 may be connected to the first chip 11 to interface with the first chip 11. Only the first chip 11 may be connected to the channel CH, and the second chip 12 may not be connected to the channel CH. Only the first chip 11 may face the load of the channel CH and have the channel load, and the second chip 12 may be decoupled from the channel CH load. Therefore, since the load factor of the semiconductor package 10 remains low, the timing and bus speeds may be increased, and the data input / output speed may be increased. In addition, the signal integrity may be improved, and the power consumption may be reduced.

[0035] The disclosed technology proposes a semiconductor package in which signals are transmitted between chips using bonding wires.

[0036] Figure 2 is a perspective view of a semiconductor package according to an embodiment of the disclosed technology, Figure 3 It is along Figure 2 A cross-sectional view taken along line II′ of Figure 4 It is along Figure 2 A cross-sectional view taken along line II-II′.

[0037] Reference Figures 2 to 4 The semiconductor package 10 may include a substrate 13 , a first chip 11 , and a second chip 12 . The first chip 11 and the second chip 12 are stacked on the substrate 13 .

[0038] The substrate 13 may include a circuit and / or a wiring structure for electrically connecting the first chip 11 to an external device. For example, the substrate 13 may include a printed circuit board (PCB), an interposer, or a redistribution layer.

[0039] A plurality of top substrate pads 13A and 13B may be disposed on the top surface of the substrate 13. When the substrate 13 is connected to the first chip 11 by bonding wiring, the top substrate pads 13A and 13B may include bonding fingers. A bottom substrate pad 13C for connection with the external connection terminal 14 may be disposed on the bottom surface of the substrate 13. When the external connection terminal 14 is a solder ball, the bottom substrate pad 13C may include a ball land. Each of the top substrate pads 13A and 13B may be electrically connected to the corresponding bottom substrate pad 13C by a circuit and / or wiring structure in the substrate 13.

[0040] The first chip 11 may be disposed on the substrate 13, and the second chip 12 may be disposed on the first chip 11. The first adhesive layer 31 may be disposed between the substrate 13 and the first chip 11 to attach the first chip 11 to the substrate 13. The second adhesive layer 32 may be disposed between the first chip 11 and the second chip 12 to attach the first chip 11 to the second chip 12.

[0041] The first chip 11 and the second chip 12 may have physically the same structure as each other. The first chip 11 and the second chip 12 may be the same type of chips. The first chip 11 and the second chip 12 may have the same size.

[0042] Each of the first chip 11 and the second chip 12 may have a top surface TS on which pads P1, P2, and P3 are provided, a bottom surface US located on an opposite side of the top surface TS, and side surfaces S11, S12, S21, and S22 connecting the top surface TS to the bottom surface US. The side surfaces S11, S12, S21, and S22 may include two side surfaces S11 and S12 located on opposite sides of each other in a first direction FD parallel to the top surface of the substrate 13, and two side surfaces S21 and S22 located on opposite sides of each other in a second direction SD parallel to the top surface of the substrate 13 and perpendicular to the first direction FD. Hereinafter, the two side surfaces S11 and S12 located on opposite sides of each other in the first direction FD will be referred to as the first side surface S11 and the second side surface S12.

[0043] The pads P1 , P2 , and P3 may include a plurality of external signal pads P1 , a plurality of chip signal pads P2 , and a plurality of power supply pads P3 .

[0044] External signal pads P1 may include external data pads, external command / address (CA) pads, external clock pads, etc. Chip signal pads P2 may include chip data pads, chip command pads, chip address pads, etc. Optionally, chip signal pads P2 may also include chip power pads.

[0045] Each of the first chip 11 and the second chip 12 may include a first pad column C1 and a second pad column C2 located in a first edge portion EP1 including the first side surface S11. In each of the first chip 11 and the second chip 12, the first pad column C1 may be located between the first side surface S11 and the second pad column C2. For example, each chip may include a plurality of pad columns, and among the pad columns included in each chip, the first pad column C1 may be an outermost pad column closest to the first side surface S11, and the second pad column C2 may be a pad column adjacent to the first pad column C1 but farther away from the first side surface S11 than the first pad column C1.

[0046] In each of the first chip 11 and the second chip 12 , the external signal pads P1 may be included in the first pad column C1 , and the chip signal pads P2 may be included in the second pad column C2 .

[0047] The second chip 12 may be offset with respect to the first chip 11 to expose the first pad column C1 and the second pad column C2 of the first chip 11 .

[0048] In a plan view, the first pad column C1 of the first chip 11 may be disposed between the top substrate pads 13A and 13B of the substrate 13 and the second pad column C2 of the first chip 11, and the second pad column C2 of the first chip 11 may be disposed between the first pad column C1 of the first chip 11 and the second chip 12. The first pad column C1 of the first chip 11 may be adjacent to the top substrate pads 13A and 13B of the substrate 13, and the second pad column C2 of the first chip 11 may be adjacent to the second chip 12.

[0049] The chip signal pads P2 of the first chip 11 and the chip signal pads P2 of the second chip 12 may be connected to each other through the first connection members 21. Each chip signal pad P2 of the first chip 11 may be connected to the corresponding chip signal pad P2 of the second chip 12 through the first connection members 21. The first connection members 21 may include bonding wires.

[0050] The first top substrate pad 13A of the substrate 13 and the external signal pad P1 of the first chip 11 may be connected to each other through the second connection member 22. Each external signal pad P1 of the first chip 11 may be connected to the corresponding first top substrate pad 13A through the second connection member 22. The second connection member 22 may include a bonding wire.

[0051] Each external signal pad P1 of the first chip 11 may contact a bonding wire connected to the substrate 13. Each external signal pad P1 of the second chip 12 may not contact the bonding wire. The external signal pads P1 of the second chip 12 may be in a disabled state.

[0052] In each of the first chip 11 and the second chip 12, the power supply pad P3 may be included in the first pad column C1. The power supply pad P3 may be disposed in the same pad column as the external signal pad P1. In the first pad column C1, the arrangement of the external signal pad P1 and the power supply pad P3 may be changed in various ways.

[0053] The second top substrate pad 13B of the substrate 13 and the power pad P3 of the first chip 11 may be connected to each other through the third connection member 23. Each power pad P3 of the first chip 11 may be connected to the corresponding second top substrate pad 13B through the third connection member 23. The third connection member 23 may include a bonding wire. The first chip 11 may be provided with power from the substrate 13 through the third connection member 23. The power may include VDD, VSS, VDDQ, and VSSQ.

[0054] The power supply pad P3 of the first chip 11 may contact the bonding wiring connected to the substrate 13. The power supply pad P3 of the second chip 12 may not be connected to the bonding wiring. The power supply pad P3 of the second chip 12 may not contact the bonding wiring connected to the substrate 13. The power supply pad P3 of the second chip 12 may be in a disabled state.

[0055] Since the external signal pads P1 and the power pads P3 of the first chip 11 are disposed in the first pad column C1 adjacent to the top substrate pads 13A and 13B of the substrate 13, and the chip signal pads P2 of the first chip 11 are disposed in the second pad column C2 adjacent to the second chip 12, the first connection member 21 and the second and third connection members 22 and 23 may be disposed respectively on opposite sides of the first edge portion EP1 of the first chip 11. That is, the first connection member 21 may be disposed on one side of the first edge portion EP1 of the first chip 11, and the second and third connection members 22 and 23 may be disposed on the other side of the first edge portion EP1 of the first chip 11.

[0056] Since the second connection member 22 and the third connection member 23 are disposed only on one side of the first edge portion EP1 of the first chip 11, the second connection member 22 and the third connection member 23 may not be disposed on the other side of the first edge portion EP1 of the first chip 11. Therefore, a large number of first connection members 21 may be disposed on the other side of the first edge portion EP1 of the first chip 11 without being spatially limited by the second connection member 22 and the third connection member 23. Therefore, even when the number of chip signals is large, the chip signals may be transmitted by using the first connection member 21 (e.g., bonding wires).

[0057] Figures 5 to 8is a diagram illustrating a data input / output path of a semiconductor package based on an embodiment of the disclosed technology. Hereinafter, for simplicity of explanation, repeated description of the same configuration between different embodiments will be omitted, and only differences will be mainly described.

[0058] Reference Figure 5 , the first chip 11 may include a cell region CELL and a peripheral region PERI. The second chip 12 may include a cell region CELL′ and a peripheral region PERI′.

[0059] The memory cell array 110 may be disposed in the cell region CELL of the first chip 11. The memory cell array 110′ may be disposed in the cell region CELL′ of the second chip 12. Each of the memory cell arrays 110 and 110′ may include a plurality of memory banks BANK. The number of memory banks included in each of the memory cell arrays 110 and 110′ may be, for example, 2, 4, 8, 16, 32, or any number that is a multiple of 2. Each memory bank BANK may include a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC. The memory cells MC may be disposed at the intersection of the word lines WL and the bit lines BL. For simplicity of illustration, Figure 5 Only one word line WL, only one bit line BL, and only one memory cell MC are illustrated.

[0060] Although not shown, each of the first chip 11 and the second chip 12 may include a row decoder for selecting a word line and a column decoder for selecting a bit line. A row decoder and a column decoder may be provided for each memory bank BANK. The row decoder and the column decoder of the first chip 11 may be disposed in the cell region CELL, and the row decoder and the column decoder of the second chip 12 may be disposed in the cell region CELL′, but the disclosed technology is not limited thereto.

[0061] exist Figure 5, reference numeral P1a refers to an external data pad of the first chip 11, and reference numeral P2a refers to a slice data pad of the first chip 11. Reference numeral P1a′ refers to an external data pad of the second chip 12, and reference numeral P2a′ refers to a slice data pad of the second chip 12. Hereinafter, for ease of explanation, the external data pads P1a and P1a′ are referred to as first pads, and the slice data pads P2a and P2a′ are referred to as second pads. A plurality of external data pads P1a may be included in a first pad column C1 of the first chip 11, and a plurality of slice data pads P2a may be included in a second pad column C2 of the first chip 11. A plurality of external data pads P1a′ may be included in a first pad column C1 of the second chip 12, and a plurality of slice data pads P2a′ may be included in a second pad column C2 of the second chip 12. Each of the first chip 11 and the second chip 12 may further include external command / address (CA) pads and external clock pads in the first pad column C1, and may further include chip command pads and chip address pads in the second pad column C2. However, illustration of these pads has been omitted for ease of explanation.

[0062] The peripheral region PERI may be located in a chip edge region of the first chip 11, and may include an edge portion where the first pad column C1 and the second pad column C2 are located. The peripheral region PERI′ may be located in a chip edge region of the second chip 12, and may include an edge portion where the first pad column C1 and the second pad column C2 are located. Each of the first chip 11 and the second chip 12 may have an edge peripheral structure.

[0063] The peripheral circuit of the first chip 11 may be arranged in the peripheral region PERI. The peripheral circuit of the first chip 11 may include a serializer-deserializer (SERDES) 120, an input / output driver (IODRV) 130, and a plurality of input / output buffers 140. The peripheral circuit of the second chip 12 may be arranged in the peripheral region PERI′. The peripheral circuit of the second chip 12 may include a serializer-deserializer (SERDES′) 120′, an input / output driver (IODRV′) 130′, and a plurality of input / output buffers 140′.

[0064] In the first chip 11, the serializer-deserializer 120 may be connected between the first pad P1a and the first node N1. The serializer-deserializer 120 may be connected to the first pad P1a through the input / output buffer 140. In the second chip 12, the serializer-deserializer 120′ may be connected between the first pad P1a′ and the first node N1′. The serializer-deserializer 120′ may be connected to the first pad P1a′ through the input / output buffer 140′.

[0065] The serializer-deserializer 120 of the first chip 11 may receive write data from an external device through the first pad P1a of the first chip 11. The serializer-deserializer 120 may parallelize the received write data, and may output the parallelized write data to the first node N1 of the first chip 11. For example, the serializer-deserializer 120 of the first chip 11 may receive four 16-bit data input through four first pads P1a, may parallelize the four 16-bit data into 64-bit data, and may output the 64-bit data to the first node N1 of the first chip 11. The write data input to the first pad P1a of the first chip 11 from the external device may pass through the input / output buffer 140 of the first chip 11, may be parallelized in the serializer-deserializer 120 of the first chip 11, and may be output to the first node N1 of the first chip 11.

[0066] The serializer-deserializer 120 of the first chip 11 may receive data read from the cell region CELL of the first chip 11 or the cell region CELL′ of the second chip 12, and may serialize the data. For example, the serializer-deserializer 120 of the first chip 11 may receive 64-bit data through 64 first nodes N1, and may serialize the 64-bit data into four 16-bit data. The read data read from the cell region CELL of the first chip 11 or the cell region CELL′ of the second chip 12 may be transmitted to the first node N1 of the first chip 11. Then, the read data may be serialized in the serializer-deserializer 120 of the first chip 11, and output to the first pad P1a of the first chip 11 through the input / output buffer 140 of the first chip 11.

[0067] In the first chip 11, the input / output driver 130 may be connected between the first node N1 and the cell region CELL. The input / output driver 130 may be connected to the serializer-deserializer 120 through the first node N1. The input / output driver 130 may receive write data from the serializer-deserializer 120 through the first node N1. The input / output driver 130 may output the received write data to the cell region CELL, and thus, the data may be stored in the cell region CELL. The input / output driver 130 may receive read data from the cell region CELL, and may output the received read data to the first node N1. In the second chip 12, the input / output driver 130′ may be connected between the first node N1′ and the cell region CELL′. The input / output driver 130′ may be connected to the serializer-deserializer 120′ through the first node N1′. The input / output driver 130′ may receive write data from the first chip 11 through the first connection member 21, the second pad P2a′, the internal wiring L1′, and the first node N1′. The input / output driver 130' may output the received write data to the cell region CELL', and thus the data may be stored in the cell region CELL'. The input / output driver 130' may receive read data from the cell region CELL' and may output the received read data to the first node N1'.

[0068] In the first chip 11, the first node N1 may be connected to the second pad P2a through the internal wiring L1. Each first node N1 may be connected to the corresponding second pad P2a through the internal wiring L1. The first node N1 may correspond one-to-one with the second pad P2a. In the second chip 12, the first node N1′ may be connected to the second pad P2a′ through the internal wiring L1′. Each first node N1′ may be connected to the corresponding second pad P2a′ through the internal wiring L1′. The first node N1′ may correspond one-to-one with the second pad P2a′.

[0069] The second pads P2a of the first chip 11 and the second pads P2a′ of the second chip 12 may be connected by the first connection member 21. Each second pad P2a of the first chip 11 may be connected to the corresponding second pad P2a′ of the second chip 12 by the first connection member 21. Figure 5 , illustration of the first connection members 21 adjacent to the SerDes 120 among the first connection members 21 has been omitted.

[0070] The input / output driver 130 of the first chip 11 may be interfaced with the serializer-deserializer 120 of the first chip 11 through the first node N1 of the first chip 11 , thereby being able to exchange data with the serializer-deserializer 120 of the first chip 11 .

[0071] The input / output driver 130′ of the second chip 12 can be connected to the serializer-deserializer 120 interface of the first chip 11 through the first node N1′ of the second chip 12, the internal wiring L1′ of the second chip 12, the second pad P2a′ of the second chip 12, the first connecting member 21, the second pad P2a of the first chip 11, the internal wiring L1 of the first chip 11 and the first node N1 of the first chip 11, thereby exchanging data with the serializer-deserializer 120 of the first chip 11.

[0072] The input / output driver 130 of the first chip 11 and the input / output driver 130 ′ of the second chip 12 may be commonly interfaced with the serializer-deserializer 120 of the first chip 11 , and may share the serializer-deserializer 120 of the first chip 11 .

[0073] The serializer-deserializer 120′ of the second chip 12 may not be used. In addition, the input / output buffer 140′ and the first pad P1a′ of the second chip 12 may not be used. The serializer-deserializer 120′, the input / output buffer 140′, and the first pad P1a′ of the second chip 12 may be dummy structures that are electrically inactive. In other words, the first pad P1a′ of the second chip 12 may be a dummy pad, the input / output buffer 140′ of the second chip 12 may be a dummy input / output buffer, and the serializer-deserializer 120′ of the second chip 12 may be a dummy serializer-deserializer.

[0074] When the device including the semiconductor package 10 is started, the first chip 11 may perform an initial setup operation in response to a command input from an external device. In the initial setup operation, the first chip 11 may generate a disable signal for disabling the serializer-deserializer 120′ and the input / output buffer 140′ of the second chip 12, and may provide the disable signal to the second chip 12. The serializer-deserializer 120′ and the input / output buffer 140′ of the second chip 12 may be disabled in response to the disable signal received from the first chip 11. After the initial setup operation, the serializer-deserializer 120′ and the input / output buffer 140′ of the second chip 12 may remain in a disabled state regardless of the operation of the semiconductor package 10 and the device including the semiconductor package 10.

[0075] Since the serializer-deserializer 120' and the input / output buffer 140' of the second chip 12 remain in a disabled state, the power consumption of the second chip 12 can be less than that of the first chip 11. Therefore, the power consumption can be reduced compared to the case where the first chip 11 and the second chip 12 are driven in the same manner.

[0076] The first pad P1a of the first chip 11 may be connected to the first top substrate pad 13A of the substrate 13 through the second connection member 22. The second connection member 22 may include a bonding wire. Each first pad P1a′ of the second chip 12 may be in a floating state. Each first pad P1a′ of the second chip 12 may not contact the bonding wire connected to the substrate 13.

[0077] Reference Figure 6 , the serializer-deserializer of the first chip 11 may be divided into two stages. In addition, the serializer-deserializer of the second chip 12 may be divided into two stages. The serializer-deserializer of the first chip 11 may include a first-stage serializer-deserializer (SERDES1) 121 and a second-stage serializer-deserializer (SERDES2) 122. The serializer-deserializer of the second chip 12 may include a first-stage serializer-deserializer (SERDES1′) 121′ and a second-stage serializer-deserializer (SERDES2′) 122′.

[0078] In the first chip 11, the first-stage serializer-deserializer 121 may be connected between the first pad P1a and the second node N2. The first-stage serializer-deserializer 121 may be connected to the first pad P1a through the input / output buffer 140. In the second chip 12, the first-stage serializer-deserializer 121′ may be connected between the first pad P1a′ and the second node N2′. The first-stage serializer-deserializer 121′ may be connected to the first pad P1a′ through the input / output buffer 140′.

[0079] The first stage SerDes 121 may receive write data from an external device through the first pad P1a of the first chip 11. The first stage SerDes 121 may parallelize the received write data and may output the parallelized write data to the second node N2 of the first chip 11.

[0080] The first-stage SerDes 121 may parallelize write data input through the first pad P1 a , thereby expanding a window of write data to 2F (F is a natural number) times.

[0081] The first-stage serializer-deserializer 121 may receive read data from the cell region CELL of the first chip 11 or the cell region CELL′ of the second chip 12, and may serialize the received read data. The read data may be transmitted to the second node N2. The read data may be serialized in the first-stage serializer-deserializer 121 and output to the first pad P1a through the input / output buffer 140 of the first chip 11.

[0082] In the first chip 11, the second-level serializer-deserializer 122 may be connected between the second node N2 and the first node N1. The second-level serializer-deserializer 122 may receive write data input from the first-level serializer-deserializer 121 through the second node N2. The second-level serializer-deserializer 122 may parallelize the received write data, and may output the parallelized write data to the first node N1. The second-level serializer-deserializer 122 may expand the window of the received write data to 2K (K is a natural number) times. For example, K may be 1. In the second chip 12, the second-level serializer-deserializer 122′ may be connected between the second node N2′ and the first node N1′. The second-level serializer-deserializer 122′ may receive write data from the first chip 11 through the first connection member 21, the internal wiring L2′, and the second node N2′. The second-level serializer-deserializer 122′ may parallelize the received write data, and may output the parallelized write data to the first node N1′. The second-stage serializer-deserializer 122 ′ may expand the window of received write data to 2K (K is a natural number) times. For example, K may be 1.

[0083] In the first chip 11, the second-level serializer-deserializer 122 can receive read data from the cell area CELL through the first node N1. The second-level serializer-deserializer 122 can serialize the received read data and output the serialized read data to the second node N2. The number of second nodes N2 can be 1 / 2K (K is a natural number) times the number of first nodes N1. For example, K can be 1. When the number of first nodes N1 is 64, the number of second nodes N2 can be 32, which is half the number of first nodes N1. In the second chip 12, the second-level serializer-deserializer 122′ can receive read data from the cell area CELL′ through the first node N1′. The second-level serializer-deserializer 122′ can serialize the received read data and output the serialized read data to the second node N2′. The number of second nodes N2′ can be 1 / 2K (K is a natural number) times the number of first nodes N1′. For example, K can be 1. When the number of the first nodes N1 ′ is 64, the number of the second nodes N2 ′ may be 32, which is half the number of the first nodes N1 ′.

[0084] In the first chip 11, the second node N2 may be connected to the second pad P2a through the internal wiring L2. The second node N2 and the second pad P2a may be connected to each other through the internal wiring L2. The number of second pads P2a may be the same as the number of second nodes N2. The second pads P2a may correspond one-to-one to the second node N2. In the second chip 12, the second node N2′ may be connected to the second pad P2a′ through the internal wiring L2′. The second node N2′ and the second pad P2a′ may be connected to each other through the internal wiring L2′. The number of second pads P2a′ may be the same as the number of second nodes N2′. The second pads P2a′ may correspond one-to-one to the second node N2′.

[0085] The second pads P2 a of the first chip 11 and the second pads P2 a ′ of the second chip 12 may be connected to each other by the first connection members 21 .

[0086] The second-stage SerDes 122 of the first chip 11 may be interfaced with the first-stage SerDes 121 of the first chip 11 through the second node N2 of the first chip 11 to exchange data with the first-stage SerDes 121 of the first chip 11 .

[0087] The second-level serializer-deserializer 122′ of the second chip 12 can be connected to the first-level serializer-deserializer 121 interface of the first chip 11 through the second node N2′ of the second chip 12, the internal wiring L2′ of the second chip 12, the second pad P2a′ of the second chip 12, the first connecting member 21, the second pad P2a of the first chip 11, the internal wiring L2 of the first chip 11 and the second node N2 of the first chip 11 to exchange data with the first-level serializer-deserializer 121 of the first chip 11.

[0088] The second level SerDes 122 of the first chip 11 and the second level SerDes 122 ′ of the second chip 12 may be commonly interfaced with the first level SerDes 121 of the first chip 11 and may share the first level SerDes 121 of the first chip 11 .

[0089] The first-level serializer-deserializer 121′ of the second chip 12 may not be used. In addition, the input / output buffer 140′ of the second chip 12 and the first pad P1a′ of the second chip 12 may not be used. The first-level serializer-deserializer 121′, the input / output buffer 140′, and the first pad P1a′ of the second chip 12 may be non-operating dummy structures. That is, the first pad P1a′ of the second chip 12 may be a dummy pad, the input / output buffer 140′ of the second chip 12 may be a dummy input / output buffer, and the first-level serializer-deserializer 121′ of the second chip 12 may be a dummy first-level serializer-deserializer.

[0090] When the device including the semiconductor package 10 is started, the first chip 11 may perform an initial setup operation in response to an external command input from an external device. In the initial setup operation, the first chip 11 may generate a disable signal for disabling the first-level serializer-deserializer 121′ and the input / output buffer 140′ of the second chip 12, and may provide the disable signal to the second chip 12. The first-level serializer-deserializer 121′ and the input / output buffer 140′ of the second chip 12 may be disabled in response to the disable signal from the first chip 11. After the initial setup operation, regardless of the operation of the semiconductor package 10 and the device including the semiconductor package 10, the first-level serializer-deserializer 121′ and the input / output buffer 140′ of the second chip 12 may remain in a disabled state.

[0091] Since the first-stage serializer-deserializer 121′ and the input / output buffer 140′ of the second chip 12 remain in a disabled state, the power consumption of the second chip 12 can be less than that of the first chip 11. Therefore, compared with the case where the first chip 11 and the second chip 12 are driven in the same manner, the power consumption can be reduced.

[0092] According to the present embodiment, since the SerDes of the first chip 11 is divided into the first-stage SerDes 121 and the second-stage SerDes 122, and the second pad P2a is connected to the second node N2 between the first-stage SerDes 121 and the second-stage SerDes 122, the number of the second pads P2a can be reduced compared to the case where the second pad P2a is connected to the first node N1. Since the SerDes of the second chip 12 is divided into the first-stage SerDes 121′ and the second-stage SerDes 122′, and the second pad P2a′ is connected to the second node N2′ between the first-stage SerDes 121′ and the second-stage SerDes 122′, the number of the second pads P2a′ can be reduced compared to the case where the second pad P2a′ is connected to the first node N1′. Therefore, the number of first connection members 21 connecting the second pads P2a of the first chip 11 and the second pads P2a' of the second chip 12 can be reduced, and a space required to dispose the first connection members 21 can be reduced.

[0093] Although the case where the first chip 11 and the second chip 12 are the same type of chips has been described above, the first chip 11 and the second chip 12 may be different types of chips. In this case, as will be described below with reference to Figure 7 and Figure 8 As described, the configuration disabled in the second chip 12 in the previous embodiment may be omitted.

[0094] Reference Figure 7 ,and Figure 5 Compared with the second chip 12, the second chip 12 may not include Figure 5 The serializer-deserializer 120', Figure 5 The input / output buffer 140′ and Figure 5 The second chip 12 may not include other external signal pads.

[0095] although Figure 7 The case where the second chip 12 does not include all of the serializer-deserializer 120', the input / output buffer 140', and the first pad P1a' is illustrated, but the second chip 12 may not include at least one of the serializer-deserializer 120', the input / output buffer 140', and the first pad P1a'. Although not shown, the second chip 12 may also not include other external signal pads, for example, an external command / address (CA) pad and an external clock pad.

[0096] Since at least one of the SerDes 120 ′, the I / O buffer 140 ′, the external signal pads, and the power pads P3 ′ has been omitted, space for the omitted components can be saved. Therefore, the second chip 12 can be smaller in size than the first chip 11 .

[0097] Reference Figure 8 ,and Figure 6 Compared with the second chip 12, the second chip 12 may not include Figure 6 The first stage serializer-deserializer 121′, Figure 6 The input / output buffer 140′ and Figure 6 The first pad P1a′.

[0098] although Figure 8 The case where the second chip 12 does not include all of the first-stage serializer-deserializer 121′, the input / output buffer 140′, and the first pad P1a′ is illustrated, but the second chip 12 may not include at least one of the first-stage serializer-deserializer 121′, the input / output buffer 140′, and the first pad P1a′. Although not shown, the second chip 12 may not include other external signal pads.

[0099] Since at least one of the first-stage SerDes 121 ′, the input / output buffer 140 ′, the external signal pads, and the power pads P3 ′ has been omitted, space for the omitted components can be saved. Therefore, the second chip 12 can be smaller in size than the first chip 11 .

[0100] Fig. 9is a perspective view of a semiconductor package according to an embodiment of the disclosed technology, and illustrates a case where the first chip 11 and the second chip 12 are chips of different types.

[0101] Reference Fig. 9 , compared with the first chip 11 , the second chip 12 may not include the external signal pad P1 .

[0102] Since the second chip 12 does not include the external signal pads P1, the second chip 12 may not have pad columns for providing the external signal pads P1. The second chip 12 may have fewer pad columns than the first chip 11.

[0103] Since the second chip 12 includes fewer pad columns than the first chip 11, the second chip 12 may have a smaller width than the first chip 11. For example, when the width of the first chip 11 is W1, the width of the second chip 12 may be W2 which is smaller than W1.

[0104] Since second chip 12 has no pad column for providing external signal pads P1 , pad column C2 ′ provided with chip signal pads P2 ′ in second chip 12 may be provided close to first side surface S11 of second chip 12 adjacent to first edge portion EP1 of first chip 11 .

[0105] The chip signal pads P2 of the first chip 11 and the chip signal pads P2′ of the second chip 12 connected to each other by the first connection members 21 may be adjacent to each other with the first side surface S11 of the second chip 12 interposed therebetween. The first connection members 21 may have a short length connecting the chip signal pads P2 of the first chip 11 to the chip signal pads P2′ of the second chip 12, and the chip signal pads P2 of the first chip 11 and the chip signal pads P2′ of the second chip 12 are adjacent to each other.

[0106] although Figures 2 to 9 The embodiment of the present invention illustrates a case where the power supply pad P3 is disposed in the first edge portion EP1 or EP1′ together with the external signal pad P1 and the chip signal pad P2 or P2′, but the power supply pad P3 may be disposed in another edge portion of the chip other than the first edge portion EP1 or EP1′, as will be described below with reference to Figures 10 to 13 as described.

[0107] Fig.10 is a perspective view of a semiconductor package according to an embodiment of the disclosed technology, and Fig.11 It is along Fig.10 A cross-sectional view taken along line III-III′.

[0108] Reference Fig.10 and Fig.11, each of the first chip 11 and the second chip 12 may include a third pad column C3, and the third pad column C3 is located in the second edge portion EP2 on the opposite side of the corresponding chip compared to the first edge portion EP1. For example, the third pad column C3 may be the outermost pad column closest to the second side surface S12 included in the second edge portion EP2 among the plurality of pad columns included in each chip. In each of the first chip 11 and the second chip 12, the power pad P3 may be included in the third pad column C3. A pad P4 for another purpose not described may be additionally provided in at least one of the first pad column C1 and the third pad column C3. For simplicity of illustration, Fig.10 It is illustrated that the connection member is not connected to the pad P4 , but if necessary, the connection member may be connected to the pad P4 .

[0109] The power pad P3 of the first chip 11 and the power pad P3 of the second chip 12 may be connected to the second top substrate pad 13B of the substrate 13 through the third connection member 23. When viewed from the top, the second top substrate pad 13B connected to the power pad P3 of the first chip 11 through the third connection member 23 may be adjacent to the second edge portion EP2 of the first chip 11. When viewed from the top, the second top substrate pad 13B connected to the power pad P3 of the second chip 12 through the third connection member 23 may be adjacent to the second edge portion EP2 of the second chip 12. The third connection member 23 may be provided on one side of the second edge portion EP2 of the first chip 11 and the second chip 12.

[0110] By setting the power supply pad P3 in the second edge portion EP2, the area allocated in the first edge portion EP1 to set the chip signal pad P2 can be increased. For example, the number of chip signal pads P2 set in the first edge portion EP1 can be increased. In addition, by increasing the size of the chip signal pad P2, the power supply capacity can be improved.

[0111] Fig.10 and Fig.11 The case where the first chip 11 and the second chip 12 are the same type of chips and the second chip 12 includes an unused external signal pad P1 is illustrated, but the disclosed technology is not limited thereto. Although not shown, the first chip 11 and the second chip 12 may be different types of chips, and compared with the first chip 11, the second chip 12 may not include the external signal pad P1.

[0112] Fig.12 is a perspective view of a semiconductor package according to an embodiment of the disclosed technology, and Fig.13 is an example Fig.12 A three-dimensional view of a substrate, a first chip, and a connecting member connecting the substrate to the first chip.

[0113] Reference Fig.12 and Fig.13 , in each of the first chip 11 and the second chip 12, the first pad column C1 may be located in the first edge portion EP1, and the second pad column C2 may be located in the second edge portion EP2. Among the plurality of pad columns included in each chip, the first pad column C1 may be the outermost pad column closest to the first side surface S11 of each chip, and the second pad column C2 may be the outermost pad column closest to the second side surface S12 of each chip.

[0114] In each of the first chip 11 and the second chip 12 , the external signal pads P1 and the power supply pads P3 may be included in the first pad column C1 , and the chip signal pads P2 may be included in the second pad column C2 .

[0115] Second chip 12 may be offset relative to first chip 11 to expose second pad column C2 including chip signal pad P2 of first chip 11. Since second pad column C2 of first chip 11 is the outermost pad column, second chip 12 may be offset relative to first chip 11 by only a width corresponding to one pad column.

[0116] Each of the first chip 11 and the second chip 12 may have a peripheral region PERI including a second edge portion EP2. Although not shown, a peripheral circuit (not shown) connected to the chip signal pad P2 may be provided in the peripheral region PERI. For example, the peripheral circuit may include Figure 5 The serializer-deserializer 120, the input / output driver 130 and the input / output buffer 140. For another example, the peripheral circuit may include Figure 6 The first-stage serializer-deserializer 121 and the second-stage serializer-deserializer 122, the input / output driver 130, and the input / output buffer 140. The chip signal pad P2 and the peripheral circuit may be disposed close to each other in the peripheral region PERI.

[0117] By disposing the external signal pads P1 and the power supply pads P3 in the first edge portion EP1, the second edge portion EP2 can be completely allocated for disposing the chip signal pads P2. Therefore, since the number of chip signal pads P2 disposed in the second edge portion EP2 can be increased, the chip signals can be transmitted using the first connection member 21 even when the number of chip signals is large.

[0118] Fig.14 is a perspective view of a semiconductor package according to an embodiment of the disclosed technology.

[0119] Reference Fig.14, each of the first chip 11 and the second chip 12 may include a first pad column C1 located in the first edge portion EP1 and a second pad column C2 located in the second edge portion EP2 .

[0120] In each of the first chip 11 and the second chip 12 , the external signal pads P1 and the chip signal pads P2 may be included in a first pad column C1 .

[0121] Each of the first chip 11 and the second chip 12 may have a peripheral region PERI including a first edge portion EP1. A peripheral circuit (not shown) connected to the external signal pad P1 and the chip signal pad P2 may be disposed in the peripheral region PERI. For example, the peripheral circuit may include Figure 5 The serializer-deserializer 120, the input / output driver 130 and the input / output buffer 140. For another example, the peripheral circuit may include Figure 6 The first-stage SerDes 121 and the second-stage SerDes 122 , the input / output driver 130 , and the input / output buffer 140 .

[0122] The chip signal pads P2 of the first chip 11 and the chip signal pads P2 of the second chip 12 may be connected to each other by the first connection member 21. The first connection member 21 may be disposed on one side of the first edge portion EP1 of the first chip 11 and the second chip 12.

[0123] The external signal pad P1 of the first chip 11 and the first top substrate pad 13A of the substrate 13 may be connected by the second connection member 22. The second connection member 22 may be disposed on one side of the first edge portion EP1 of the first chip 11.

[0124] The power pads P3 of the first and second chips 11 and 12 may be connected to the second top substrate pads 13B of the substrate 13 through the third connection members 23. The third connection members 23 may be disposed on one side of the second edge portion EP2 of the first and second chips 11 and 12.

[0125] Fig.12 and Fig.14 The case where the first chip 11 and the second chip 12 are the same type of chips and the second chip 12 includes an unused external signal pad P1 is illustrated, but the disclosed technology is not limited thereto. Although not shown, the first chip 11 and the second chip 12 may be different types of chips, and compared with the first chip 11, the second chip 12 may not include the external signal pad P1.

[0126] In the detailed description, components of the first chip and components of the second chip with similar functions are indicated by the same reference numerals, but this is only for simplicity. Components denoted by the same reference numerals should not be interpreted as being completely identical.

[0127] Although the exemplary embodiments of the present disclosure have been described for illustrative purposes, those skilled in the art will recognize that various modifications, additions and substitutions are possible without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered only as illustrative and not intended to limit the scope of the technology. The technical scope of the present disclosure is not limited by the embodiments and the accompanying drawings.

Claims

1. A semiconductor package, comprising: substrate; A first chip and a second chip, the first chip and the second chip are stacked on the substrate, the first chip and the second chip each including a first pad, a cell region, a first-level serializer-deserializer connected to the first pad, a second-level serializer-deserializer connected between the first-level serializer-deserializer and the cell region, and a second pad connected to a node between the first-level serializer-deserializer and the second-level serializer-deserializer; and A first connection member connects the second pad of the first chip to the second pad of the second chip.

2. The semiconductor package according to claim 1, wherein: The first connection member includes a bonding wire.

3. The semiconductor package according to claim 1, wherein: The second-level serializer-deserializer of the first chip and the second-level serializer-deserializer of the second chip are commonly connected to the first-level serializer-deserializer interface of the first chip.

4. The semiconductor package according to claim 1, wherein: Each of the first chip and the second chip further includes an input / output buffer connected between the first pad and the first-stage serializer-deserializer.

5. The semiconductor package according to claim 1, in, The first pad of the first chip contacts the bonding wiring connected to the substrate, and The first pad of the second chip does not contact the bonding wiring connected to the substrate.

6. The semiconductor package according to claim 1, in, The node includes a plurality of nodes, Wherein, the second pad includes a plurality of second pads, In each of the first chip and the second chip, the number of the nodes corresponds to the number of the second pads one by one.

7. The semiconductor package according to claim 1, in, Each of the first chip and the second chip includes a first pad column and a second pad column located in a first edge portion, wherein the first pad array is located between the chip side surface included in the first edge portion and the second pad array, and In each of the first chip and the second chip, the first pad is included in the first pad column, and the second pad is included in the second pad column.

8. The semiconductor package according to claim 7, in, Each of the first chip and the second chip includes a plurality of pad columns, and wherein the first pad column is a pad column closest to the chip side surface included in the first edge portion among the plurality of pad columns, and The second pad column is a pad column adjacent to the first pad column and close to the chip side surface included in the first edge portion.

9. The semiconductor package according to claim 7, in, The second chip is stacked on the first chip, and The second chip is offset relative to the first chip to expose a first pad column and a second pad column of the first chip.

10. The semiconductor package according to claim 7, wherein: In each of the first chip and the second chip, the first-stage SerDes and the second-stage SerDes are disposed in a peripheral region including the first edge portion.

11. The semiconductor package according to claim 7, in, Each of the first chip and the second chip further includes a power supply pad, the power supply pad being included in the first pad column, wherein the power supply pad of the first chip contacts the bonding wiring connected to the substrate, and The power supply pad of the second chip does not contact the bonding wiring connected to the substrate.

12. The semiconductor package according to claim 7, in, Each of the first chip and the second chip further includes a power supply pad located in the second edge portion, wherein the first edge portion and the second edge portion are on opposite sides of a corresponding chip, and The power pad of the first chip and the power pad of the second chip are respectively connected to the substrate through bonding wiring.

13. The semiconductor package according to claim 1, in, Each of the first chip and the second chip includes a first pad column located in a first edge portion and a second pad column located in a second edge portion, wherein the first edge portion and the second edge portion are on opposite sides of the corresponding chip, and In each of the first chip and the second chip, the first pad is included in the first pad column, and the second pad is included in the second pad column.

14. The semiconductor package according to claim 13, in, The second chip is stacked on the first chip, and The second chip is offset relative to the first chip to expose a second pad column of the first chip.

15. The semiconductor package according to claim 13, wherein: In each of the first chip and the second chip, the first-stage SerDes and the second-stage SerDes are disposed in a peripheral region including the second edge portion.

16. The semiconductor package according to claim 13, in, Each of the first chip and the second chip further includes a power supply pad connected to the substrate through a bonding wire, and In each of the first chip and the second chip, the power supply pad is included in the first pad column.

17. The semiconductor package according to claim 1, in, Each of the first chip and the second chip includes a first pad column located in a first edge portion, and In each of the first chip and the second chip, the first pad and the second pad are included in the first pad column.

18. The semiconductor package according to claim 17, in, The second chip is stacked on the first chip, and The second chip is offset relative to the first chip to expose a first pad column of the first chip.

19. The semiconductor package according to claim 17, wherein: In each of the first chip and the second chip, the first-stage SerDes and the second-stage SerDes are disposed in a peripheral region including the first edge portion.

20. The semiconductor package according to claim 17, wherein Each of the first chip and the second chip further includes a power supply pad located in the second edge portion and connected to the substrate through a bonding wire, and Wherein, the first edge portion and the second edge portion are on opposite sides of the corresponding chip.

21. A semiconductor package, comprising: A first chip, the first chip is arranged on a substrate, the first chip comprises an external data pad, a first data pad, and a first-stage serializer-deserializer connected between the external data pad and the first data pad; a second chip, the second chip being stacked on the first chip, the second chip comprising a second-chip data pad and a second-stage serializer-deserializer connected to the second-chip data pad; and A first connection member connects the first data pad and the second data pad.

22. The semiconductor package according to claim 21, wherein The first connection member includes a bonding wire.

23. The semiconductor package according to claim 21, in, The first chip includes a first pad column and a second pad column located in a first edge portion, wherein the first pad column is located between the side surface of the first chip included in the first edge portion and the second pad column, and The external data pad is included in the first pad column, and the first data pad is included in the second pad column.

24. The semiconductor package according to claim 23, in, The second chip includes a plurality of pad columns, and The second piece of data pads is included in an outermost pad column that is closest to a side surface of the second chip adjacent to the first edge portion of the first chip among the plurality of pad columns.

25. The semiconductor package according to claim 23, wherein: The second chip is offset relative to the first chip to expose the first pad column and the second pad column of the first chip.

26. The semiconductor package according to claim 23, in, The first chip further includes a power supply pad connected to the substrate through a bonding wire, and The power pad is included in the first pad column of the first chip.

27. The semiconductor package according to claim 21, wherein The number of pad columns of the second chip is smaller than the number of pad columns of the first chip.

28. The semiconductor package according to claim 21, wherein The second chip has a smaller width than the first chip.

29. The semiconductor package according to claim 21, in, Each of the first chip and the second chip includes a first pad column located in a first edge portion and a second pad column located in a second edge portion, wherein the first edge portion and the second edge portion are on opposite sides of the corresponding chip, wherein the external data pad is included in a first pad column of the first chip, The first data pad is included in the second pad column of the first chip, and The second data pads are included in a second pad column of the second chip.

30. The semiconductor package according to claim 29, wherein The second chip is offset relative to the first chip to expose a second pad column of the first chip.

31. The semiconductor package according to claim 29, in, The first chip also includes a power pad, and The power pad is included in the first pad column.

32. The semiconductor package according to claim 21, in, Each of the first chip and the second chip includes a first pad column located in a first edge portion, wherein the external data pad and the first chip data pad are included in a first pad column of the first chip, and The second data pads are included in the first pad column of the second chip.

33. The semiconductor package according to claim 32, wherein: The second chip is offset relative to the first chip to expose a first pad column of the first chip.

34. The semiconductor package according to claim 32, in, Each of the first chip and the second chip further includes a power pad, wherein, in each of the first chip and the second chip, the power supply pad is included in a second pad column located in a second edge portion, and Wherein, the first edge portion and the second edge portion are on opposite sides of the corresponding chip.

35. A semiconductor package, comprising: substrate; A first chip and a second chip, the first chip and the second chip are stacked on the substrate, the first chip and the second chip each comprising: an external signal pad included in a first pad column located in a first edge portion; and a chip signal pad included in a second pad column located in the first edge portion; a first connection member connecting a chip signal pad of the first chip to a chip signal pad of the second chip; and a second connecting member connecting the substrate to an external signal pad of the first chip, Among them, in each of the first chip and the second chip, the first pad column is provided between a chip side surface included in the first edge portion and the second pad column.

36. The semiconductor package according to claim 35, wherein: The first connection member and the second connection member include bonding wires.

37. The semiconductor package according to claim 35, in, Each of the first chip and the second chip includes a plurality of pad columns, and The first pad column is a pad column among the multiple pad columns that is closest to the chip side surface included in the first edge portion, and the second pad column is a pad column adjacent to the first pad column and close to the chip side surface included in the first edge portion.

38. The semiconductor package according to claim 35, in, The second chip is stacked on the first chip, and The second chip is offset relative to the first chip to expose the first pad column and the second pad column of the first chip.

39. The semiconductor package according to claim 35, wherein: The first connection member and the second connection member are respectively disposed on opposite sides of the first edge portion of the first chip.

40. The semiconductor package according to claim 35, in, The external signal pads of the first chip contact bonding wiring connected to the substrate, and The external signal pads of the second chip do not contact the bonding wiring connected to the substrate.

41. The semiconductor package according to claim 35, in, Each of the first chip and the second chip includes a cell region and a peripheral region, and Herein, in each of the first chip and the second chip, the first edge portion is included in the peripheral region, and the external signal pad and the chip signal pad are connected to a peripheral circuit provided in the peripheral region.

42. The semiconductor package according to claim 35, in, Each of the first chip and the second chip further includes a power supply pad, the power supply pad being included in the first pad column, wherein the power supply pad of the first chip contacts the bonding wiring connected to the substrate, and The power supply pad of the second chip does not contact the bonding wiring connected to the substrate.

43. The semiconductor package according to claim 35, in, Each of the first chip and the second chip further includes a power supply pad located in the second edge portion, wherein the first edge portion and the second edge portion are on opposite sides of the corresponding chip, and The power pad of the first chip and the power pad of the second chip are respectively connected to the substrate through bonding wiring.

44. A semiconductor package, comprising: substrate; A first chip, the first chip is stacked on the substrate, the first chip includes: an external signal pad, the external signal pad is included in a first pad column located in a first edge portion; and a first signal pad, the first signal pad is included in a second pad column located in the first edge portion; A second chip, the second chip is stacked on the first chip, and the second chip includes a second signal pad; a first connection member connecting the first chip signal pad to the second chip signal pad; and a second connection member connecting the substrate to the external signal pad, The first pad column is disposed between a side surface of the first chip included in the first edge portion and the second pad column.

45. The semiconductor package according to claim 44, wherein: The first connection member and the second connection member include bonding wires.

46. ​​The semiconductor package according to claim 44, in, The second chip includes a plurality of pad columns, and The second-piece signal pads are included in an outermost pad column that is closest to a side surface of the second chip adjacent to the first edge portion of the first chip among the plurality of pad columns.

47. The semiconductor package according to claim 44, wherein: The second chip is offset relative to the first chip to expose the first pad column and the second pad column.

48. The semiconductor package according to claim 44, wherein The first connection member and the second connection member are respectively disposed on opposite sides of the first edge portion of the first chip.

49. The semiconductor package according to claim 44, wherein: The first chip further includes a power supply pad connected to the substrate through a bonding wire.

50. The semiconductor package according to claim 49, wherein The power supply pad is included in the first pad column.

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