Power device and manufacturing method thereof

Abstract

The invention provides a power device and a manufacturing method thereof, and the power device comprises the components of a semiconductor layer which comprises a first doped region, a second doped region, a well region and a third doped region which are successively adjacent in a vertical direction; the isolation part extends into the second doped region from the first surface of the semiconductor layer and is adjacent to the well region and the third doped region; the semiconductor device further comprises a first resistor structure, a second resistor structure and a first diode structure, the first resistor structure is used for forming a first resistor, the second resistor structure is used for forming a second resistor, the diode structure is used for forming a first diode, a first end of the first resistor is electrically connected with the third doped region, and a second end of the second resistor is electrically connected with the second doped region. The second end of the first resistor is electrically connected with the cathode of the first diode and the first end of the second resistor, the anode of the first diode is electrically connected with the third doped region, the second end of the second resistor is electrically connected with the well region, and the resistance value of the first resistor is smaller than that of the second resistor.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor devices, and more specifically, to a power device and a method for manufacturing the same. Background Art

[0002] Insulated Gate Bipolar Transistor (IGBT) is the core device of power electronic systems in the medium and high power fields. As a composite device of field effect transistor and bipolar transistor, IGBT has the characteristics of high input impedance, simple driving, high current capability and low on-state voltage drop.

[0003] Compared with ordinary metal oxide semiconductor field effect transistors (MOSFET), IGBTs have lower on-state voltage drop, which is due to the conductivity modulation effect in the drift region when the IGBT is turned on. At present, further reducing the on-state voltage drop of the IGBT and thus reducing the on-state power consumption of the IGBT is still an important research topic in the IGBT field. Summary of the invention

[0004] In view of the above problems, the purpose of the present disclosure is to provide a power device and a manufacturing method thereof, by setting additional resistors and diodes in the power device, so as to adjust the potential of different regions in the power device and thereby reduce the on-state voltage drop of the power device.

[0005] According to one aspect of an embodiment of the present disclosure, a power device is provided, comprising: a semiconductor layer having a first surface and a second surface opposite to each other, the semiconductor layer comprising a first doping region, a second doping region, a well region, and a third doping region sequentially adjacent to each other along a direction from the second surface toward the first surface;

[0006] an isolation portion extending from the first surface of the semiconductor layer into the second doping region and adjacent to the well region and the third doping region; and

[0007] a gate conductor located in the isolation portion,

[0008] The first doping region and the well region are of a first doping type, the second doping region and the third doping region are of a second doping type, and the first doping type is opposite to the second doping type.

[0009] The semiconductor device further includes: a first resistor structure, a second resistor structure and a first diode structure, wherein the first resistor structure is used to form a first resistor, the second resistor structure is used to form a second resistor, and the diode structure is used to form a first diode.

[0010] The first end of the first resistor is electrically connected to the third doped region, the second end of the first resistor is electrically connected to the cathode of the first diode and the first end of the second resistor respectively, the anode of the first diode is electrically connected to the third doped region, and the second end of the second resistor is electrically connected to the well region.

[0011] Wherein, the resistance value of the first resistor is smaller than the resistance value of the second resistor.

[0012] Optionally, the first doped region, the second doped region and the well region are used to form a first transistor,

[0013] The second doping region, the well region and the third doping region are used to form a second transistor and a third transistor,

[0014] The first transistor is a PNP transistor, the second transistor is an NPN transistor, and the third transistor is an NMOS transistor.

[0015] The emitter of the first transistor is connected to a first potential, the base of the first transistor is respectively connected to the collector of the second transistor and the first current terminal of the third transistor, the collector of the first transistor is respectively connected to the base of the second transistor and the substrate of the third transistor, and the emitter of the second transistor is connected to the second current terminal of the third transistor.

[0016] The anode of the first diode is connected to the emitter of the second transistor, and the cathode of the first diode is connected to the second potential.

[0017] The first resistor is connected in series between the emitter of the second transistor and the second potential.

[0018] The second resistor is connected in series between the base of the second transistor and the second potential.

[0019] Optionally, the semiconductor device further includes a fourth doped region adjacent to the well region, and the second end of the second resistor is electrically connected to the fourth doped region.

[0020] Wherein, the fourth doping region is of the first doping type.

[0021] Optionally, the gate conductor, the first resistance structure, the second resistance structure, and the diode structure are located in the same isolation portion;

[0022] Alternatively, at least one of the gate conductor, the first resistance structure, the second resistance structure, and the diode structure is located in different isolation portions.

[0023] Optionally, the diode structure includes a first filling portion extending from a surface of the isolation portion into the isolation portion.

[0024] Optionally, the diode structure further includes a fifth doped region extending from a surface of the first filling portion into the first filling portion,

[0025] The fifth doping region is of the first doping type, and the first filling portion is of the second doping type.

[0026] Optionally, the diode structure further includes a metal layer located on a surface of the first filling portion.

[0027] Wherein, the first filling portion contacts the metal layer to form a Schottky diode.

[0028] Optionally, the first filling portion is made of the same material as that of the gate conductor.

[0029] Optionally, the material of the first filling part includes polysilicon or silicon carbide.

[0030] Optionally, the first resistor structure extends from the surface of the isolation portion into the isolation portion, or the first resistor structure is located on the surface of the isolation portion;

[0031] The second resistor structure extends from the surface of the isolation portion into the isolation portion, or the second resistor structure is located on the surface of the isolation portion.

[0032] Optionally, a material of the first resistance structure and / or the second resistance structure is the same as a material of the gate conductor.

[0033] Optionally, a material of the first resistance structure and / or the second resistance structure includes polysilicon or silicon carbide.

[0034] According to another aspect of an embodiment of the present disclosure, a method for manufacturing a power device is provided, comprising: forming a first doping region, a second doping region, a well region, and a third doping region that are adjacent to each other in sequence in the semiconductor layer along a direction from a second surface of the semiconductor layer toward a first surface;

[0035] forming an isolation portion in the semiconductor layer, the isolation portion extending from the first surface into the second doping region and adjacent to the well region and the third doping region; and

[0036] forming a gate conductor in the isolation portion,

[0037] The first doping region and the well region are of a first doping type, the second doping region and the third doping region are of a second doping type, and the first doping type is opposite to the second doping type.

[0038] The manufacturing method further includes: forming a first resistance structure, a second resistance structure and a diode structure,

[0039] The first resistor structure is used to form a first resistor, the second resistor structure is used to form a second resistor, and the diode structure is used to form a first diode.

[0040] The first end of the first resistor is electrically connected to the third doped region, the second end of the first resistor is electrically connected to the cathode of the first diode and the first end of the second resistor respectively, the anode of the first diode is electrically connected to the third doped region, and the second end of the second resistor is electrically connected to the well region.

[0041] Optionally, the step of forming the diode structure includes: forming a first filling portion in the isolation portion,

[0042] The first filling portion and the gate conductor are formed in the same step.

[0043] Optionally, the first resistance structure and / or the second resistance structure and the gate conductor are formed in the same step.

[0044] Optionally, the method further includes forming a fourth doping region in the semiconductor layer, wherein the fourth doping region extends from the first surface toward the second surface and is adjacent to the well region.

[0045] The step of forming the diode structure further includes: forming a fifth doping region in the first filling portion,

[0046] The fourth doping region and the fifth doping region are of the first doping type, and the first filling portion is of the second doping type.

[0047] The fourth doping region and the fifth doping region are formed in the same step.

[0048] One of the above technical solutions has the following beneficial effects:

[0049] By setting additional dual resistors and diodes in the power device, the potential of different regions in the power device can be adjusted, thereby reducing the on-state voltage drop of the power device and having a stronger anti-latch capability.

[0050] In some embodiments, since a dual resistor structure and / or a diode structure is formed outside the doped region of the semiconductor layer and no additional carrier storage layer is introduced to increase the doping concentration, the breakdown voltage (BV) of the power device will not be degraded.

[0051] In some embodiments, the resistor structure and / or the diode structure are formed in the isolation portion and integrated with the IGBT main circuit in the same device, thereby reducing adverse effects such as noise and RC delay caused by external wiring.

[0052] Furthermore, the resistor structure and / or the diode structure and the gate conductor share the same isolation portion, which can save space occupied by the isolation portion and increase the unit area utilization of the device.

[0053] In some embodiments, the first filling portion of the diode structure and / or the resistor structure are made of the same material as the gate conductor and are formed in the same step as the gate conductor, so that when manufacturing the power device, there is no need to additionally design a mask template for the first filling portion and / or the resistor structure, thereby saving manufacturing costs.

[0054] In some embodiments, the fifth doped region of the diode structure and the contact region (fourth doped region) of the well region are formed in the same step, so that when manufacturing the power device, there is no need to additionally design a mask template for the fifth doped region, saving manufacturing costs.

[0055] In addition, in some embodiments, since the device does not have a floating P region adjacent to the gate, the gate capacitance is equivalently reduced and the risk of displacement current charging the gate is greatly reduced. Therefore, the power device of the embodiment of the present disclosure also has high dv / dt resistance capability.

[0056] It should be noted that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0058] Figure 1 A schematic diagram of the three-dimensional structure of a power device according to the first embodiment of the present disclosure is shown.

[0059] Figure 2 Shown along Figure 1 Schematic diagram of the cross section taken along line AA.

[0060] Figure 3 Shows Figure 2 Schematic diagram of some adjacent cells and the structure between them.

[0061] Figure 4 Shows Figure 3 Schematic diagram of the circuit structure in .

[0062] Figures 5 to 10The schematic cross-sectional view shows a part of the stages in the method for manufacturing a power device according to the first embodiment of the present disclosure.

[0063] Fig.11 A schematic structural diagram of a power device according to a second embodiment of the present disclosure is shown.

[0064] Fig.12 A schematic structural diagram of a power device according to a third embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0065] The present disclosure will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0066] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Furthermore, if the device is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0067] If the purpose is to describe the situation of being directly on another layer or another area, this article will use expressions such as "directly on..." or "on... and adjacent to...".

[0068] Many specific details of the present disclosure are described below, such as device structure, materials, dimensions, processing technology and techniques, so as to more clearly understand the present disclosure. However, as those skilled in the art will appreciate, the present disclosure may not be implemented in accordance with these specific details.

[0069] In the related art, there are two technologies to reduce the on-state voltage drop of IGBT: first, increasing the channel density, such as using a planar gate and a grooved gate together, to increase the electron current concentration in the drift region, thereby enhancing the conductivity modulation effect; second, introducing an N-type carrier storage layer with a hole blocking effect at the cathode end of the IGBT to increase the carrier concentration in the drift region close to the cathode end, which can also enhance the conductivity modulation effect.

[0070] However, the means of increasing the channel density will be limited by the key process size, and the effect of improving the current capability of the device is not significant; introducing an N-type carrier storage layer on the cathode side of the IGBT will cause the device BV to decrease when the doping concentration of the N-type carrier storage layer is high, and when the doping concentration of the N-type carrier storage layer is low, the effect of improving the current capability of the device will be greatly reduced; and an additional injection is required, which increases the cost.

[0071] In view of the above problems, the purpose of the present disclosure is to provide a power device and a manufacturing method thereof, by setting additional dual resistors and diodes in the power device, so as to adjust the potential of different regions in the power device and thereby reduce the on-state voltage drop of the power device.

[0072] Figure 1 The figure shows a three-dimensional structure diagram of a power device according to the first embodiment of the present disclosure. Figure 2 Shown along Figure 1 Schematic diagram of the cross section taken along line AA. Figure 3 Shows Figure 2 Schematic diagram of some adjacent cells and the structures between them. Figure 4 Shows Figure 3 The schematic diagram of the circuit structure in FIG. Figures 1 to 3 The interlayer dielectric layer and the wiring layer above the semiconductor layer are omitted in order to more clearly express the positional relationship between various structures and regions. Figure 3 Only the connection relationship between each region in the second cell Cell-2 and the first resistance structure 181, the second resistance structure 182, and the diode structure 190 is shown to more clearly express the circuit connection structure. The circuit connection of other cell structures can refer to the second cell Cell-2.

[0073] like Figures 1 to 4 As shown, the power device of the first embodiment of the present disclosure includes: a semiconductor layer 101, an isolation portion 160, a gate conductor 170, a first resistor structure 181, a second resistor structure 182 and a diode structure 190. The semiconductor layer 101 is, for example, a Si or SiC substrate or a stacked structure consisting of a substrate and an epitaxial layer. However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art can make other settings for the material and number of layers of the semiconductor layer 101 as needed.

[0074] The semiconductor layer 101 has a first surface 101a and a second surface 101b opposite to each other. The semiconductor layer 101 includes: a first doping region 110, a second doping region 102, a well region 140, a third doping region 151 and a fourth doping region 152. Along the direction from the second surface 101b to the first surface 101a, the first doping region 110, the second doping region 102 and the well region 140 are adjacent to each other in sequence, and the third doping region 151 and the fourth doping region 152 extend from the first surface 101a to the second surface 101b and are adjacent to the well region 140. The third doping region 151 and the fourth doping region 152 may be adjacent to each other or separated by the well region 140. Among them, the first doping region 110, the well region 140 and the fourth doping region 152 are of the first doping type, the second doping region 102 and the third doping region 151 are of the second doping type, and the first doping type is opposite to the second doping type. The first doping type is one of the P type and the N type, and the second doping type is the other of the P type and the N type. In the following description, an example is given in which the first doping type is P type and the second doping type is N type.

[0075] In this embodiment, the second doping region 102 includes a buffer region 120 and a drift region 130. Optionally, the buffer region 120 may not be provided. The doping concentration of the third doping region 151 is greater than that of the well region 140, so as to serve as a contact region of the well region 140. Optionally, the third doping region 151 may not be provided.

[0076] The isolation portion 160 extends from the first surface 101a of the semiconductor layer 101 into the drift region 130, and the sidewalls of the isolation portion 160 are adjacent to the well region 140 and the third doped region 151. The material of the isolation portion 160 includes, for example, an oxide layer, a nitride layer or other high-K dielectric layer. The gate conductor 170 is located in the isolation portion 160, wherein the isolation portion 160 located between the gate conductor 170 and the well region 140 serves as a gate dielectric layer.

[0077] The power device of the first embodiment of the present disclosure has a plurality of cell structures. Figure 2 Only three cell structures are listed, including the first cell Cell-1, the second cell Cell-2 and the third cell Cell-3, wherein the first cell Cell-1 is mirror-symmetric with the second cell Cell-2, and the second cell Cell-2 is mirror-symmetric with the third cell Cell-3. Each cell structure includes a first doping region 110, a second doping region 102, a well region 140, a third doping region 151, a fourth doping region 152 and a trench gate structure (including a gate conductor 170 and a gate dielectric layer).

[0078] However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art may make other arrangements for the internal structure, quantity, and symmetric relationship of the cellular structure as needed.

[0079] In this embodiment, the first resistor structure 181, the second resistor structure 182 and the diode structure 190 are all located in the isolation part 160 between the second cell Cell-2 and the third cell Cell-3, and are located between the gate conductor 170 of the second cell Cell-2 and the gate conductor 170 of the third cell Cell-3. Among them, the first resistor structure 181, the second resistor structure 182, the diode structure 190 and the gate conductor 170 are separated from each other by the isolation part 160. Optionally, the first resistor structure 181 and the second resistor structure 182 are respectively located on both sides of the diode structure 190, thereby increasing the symmetry of the power device. Optionally, at least one of the gate conductor 170, the first resistor structure 181, the second resistor structure 182 and the diode structure 190 is located in different isolation parts 160.

[0080] The diode structure 190 includes a first filling portion 191 and a fifth doping region 192, wherein the first filling portion 191 is of the second doping type, and the fifth doping region 192 is of the first doping type, thereby forming a first diode D1. The first resistor structure 181 is used to form a first resistor R1, and the second resistor structure 182 is used to form a second resistor R2, and the resistance of the first resistor R1 is less than the resistance of the second resistor R2, and the resistance of the first resistor R1 and the second resistor R2 can be adjusted by adjusting the doping concentration of the first resistor structure 181 and the second resistor structure 182 or by adjusting the size of the first resistor structure 181 and the second resistor structure 182.

[0081] In some preferred embodiments, the first filling portion 191 , the first resistance structure 181 , the second resistance structure 182 , and the gate conductor 170 are made of the same material, such as polysilicon.

[0082] In some other implementations, the material of the first filling portion 191 , the first resistance structure 181 , and the second resistance structure 182 may also be SiC.

[0083] However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art may make other arrangements for the materials of the first filling portion 191 , the first resistor structure 181 , and the second resistor structure 182 as needed.

[0084] The first doping region 110, the second doping region 102 and the well region 140 are used to form a first transistor T1, and the second doping region 102, the well region 140 and the third doping region 151 are used to form a second transistor T2 and a third transistor T3, wherein the first transistor T1 is a PNP transistor, the second transistor T2 is an NPN transistor, and the third transistor T3 is an NMOS transistor. The first transistor T1, the second transistor T2 and the third transistor T3 form a main IGBT circuit 10, and a parasitic diode formed by the well region 140 and the third doping region 151 exists between the base and the emitter of the second transistor T2.

[0085] The third doped region 151 on the cathode side of the main IGBT circuit 10 (the side connected to the second potential V2 in the power device) is connected to the second potential V2 of the entire device through the first resistor R1, and the third doped region 151 is also connected to the anode of the first diode D1, and the cathode of the first diode D1 is connected to the second potential V2 of the entire device; the fourth doped region 152 on the cathode side of the main IGBT circuit 10 is connected to the second potential V2 of the entire device through the second resistor R2.

[0086] Specifically, the emitter of the first transistor T1 is connected to the first potential V1, the base of the first transistor T1 is respectively connected to the collector of the second transistor T2 and the first current end of the third transistor T3, the collector of the first transistor T1 is respectively connected to the base of the second transistor T2 and the substrate of the third transistor T3, the emitter of the second transistor T2 is connected to the second current end of the third transistor T3, the anode of the first diode D1 is connected to the emitter of the second transistor T2, the cathode of the first diode D1 is connected to the second potential V2, the first resistor R1 is connected in series between the emitter of the second transistor T2 and the second potential V2, the second resistor R2 is connected in series between the base of the second transistor T2 and the second potential V2, wherein the first current end and the second current end of the third transistor T3 can be interchanged (that is, the drain and source of the third transistor T3 can be interchanged). The working principle of the power device of the first embodiment of the present disclosure will be described below.

[0087] When the power device is in the blocking state, the potentials of the fourth doping region 152 and the third doping region 151 on the cathode side of the main IGBT circuit 10 are the same as the second potential V2 , and the insulation breakdown voltage BV of the power device is the same as that of the main IGBT circuit 10 .

[0088] When a high level is applied to the gate G of the power device, as the voltage of the first potential V1 increases, the power device is turned on. Since the resistance value of the first resistor R1 is smaller than the resistance value of the second resistor R2, the potential of the fourth doping region 152 on the cathode side of the main IGBT circuit 10 rises faster than the potential of the third doping region 151, resulting in a voltage difference between the potential of the fourth doping region 152 and the potential of the third doping region 151, so that the parasitic diode formed by the well region 140 and the third doping region 151 is turned on. At this time, carriers are injected into the drift region 130 through the turned-on parasitic diode and the channel formed on the side surface of the well region 140 close to the gate G, thereby enhancing the conductivity modulation effect in the drift region 130 and reducing the turn-on voltage Von of the power device. As the voltage of the first potential V1 further increases, the potential of the third doping region 151 rises to the turn-on voltage of the first diode D1, thereby turning on the first diode D1. At this time, the potential of the third doping region 151 and the potential of the fourth doping region 152 are clamped, and the current of the entire power device reaches a saturated state. This saturated current is higher than the saturation current of the IGBT device without the first resistor R1, the second resistor R2 and the first diode D1. Therefore, the driving energy of the power device in the embodiment of the present disclosure is stronger.

[0089] When a short circuit occurs in the external circuit of the power device of the embodiment of the present disclosure, causing the power of the embodiment of the present disclosure to be subjected to a high current and high voltage condition, the first diode D1 and the parasitic diode formed by the well region 140 and the third doping region 151 are both turned on, but the power device does not trigger latching and cause failure. This is because the high power in the power device causes the device temperature to continue to rise, and at the same time the carrier mobility of the device decreases, causing the current in the third doping region 151 and the fourth doping region 152 of the main IGBT circuit 10 to decrease, the potential of the third doping region 151 slowly decreases with the potential of the first diode D1, and the potential of the fourth doping region 152 decreases rapidly with the first resistor R1, causing the parasitic diode formed by the well region 140 and the third doping region 151 to be quickly turned off, and the barrier height of the PN junction of the parasitic diode will continue to increase with the temperature, making it more difficult to turn on.

[0090] In some specific embodiments, the power device (referred to as: power device A) of the embodiment of the present disclosure is connected in series with the external device B. Since the normal working mode of the IGBT device is generally the mutual conversion between the two states of "gate G turned off, anode (first potential V1) high voltage off state" and "gate G turned on (i.e. large current passes through the IGBT device), anode low voltage on state". However, when the external device B is short-circuited, the power device A may suffer from the situation that the gate G is turned on and the anode is high voltage at the same time. For example: the power device A is turned on and the anode is low voltage, and the external device B connected in series with it is turning off the pressure resistance, but the external device B suddenly short-circuits, then the voltage drop of the external device B before will be added to the power device A, so that the power device A suffers from a "short-circuit state". In this state, the power device A is easily burned by the heat accumulation caused by the high power. Therefore, in this state, the power device A needs to withstand (buffer) for at least a period of time so that other external circuits can make corresponding feedback, thereby solving the short-circuit problem of the external device B. Since the power device of the embodiment of the present disclosure is provided with the first resistor R1, the second resistor R2 and the first diode D1, a longer buffer time can be obtained.

[0091] For an IGBT device without the first resistor R1, the second resistor R2 and the first diode D1, as the temperature of the parasitic diode increases, the barrier height will gradually decrease due to the increase in the concentration of intrinsic excited carriers, causing the device parasitic diode to turn on, thereby triggering latching and causing device failure. Therefore, the power device of the embodiment of the present disclosure has a strong anti-latch capability under high current.

[0092] When a low level is applied to the gate G of the power device, the current flowing through the third doping region 151 decreases, the potential of the third doping region 151 decreases, and the fourth doping region 152 also decreases accordingly, the conductivity modulation effect is weakened, and finally the power device is turned off.

[0093] Figures 5 to 10 The schematic cross-sectional view shows a part of the stages in the method for manufacturing a power device according to the first embodiment of the present disclosure.

[0094] like Figure 5 As shown, along the direction from the second surface 101 b of the semiconductor layer 101 toward the first surface 101 a , a first doped region 110 , a buffer region 120 , a drift region 130 and a well region 140 are sequentially formed in the semiconductor layer 101 .

[0095] Furthermore, a groove 103 is formed in the semiconductor layer 101, such as Figure 6 shown.

[0096] In this step, for example, the semiconductor layer 101 is etched by an etching process to form a groove 103 penetrating the well region 140 . The etching stops near the drift region 130 , so that the bottom surface of the groove 103 is located in the drift region 130 .

[0097] Furthermore, an isolation portion 160 is formed in the groove 103, such as Figure 7 shown.

[0098] Furthermore, a gate conductor 170, a first resistor structure 181, a second resistor structure 182 and a first filling portion 191 are formed in the isolation portion 160, as shown in FIG. Figure 8 shown.

[0099] In this step, for example, a plurality of trenches are formed in the isolation portion 160 by using an etching process, and then the gate conductor 170 , the first resistance structure 181 , the second resistance structure 182 and the first filling portion 191 are respectively formed in different trenches.

[0100] Optionally, the first resistance structure 181 and the second resistance structure 182 are symmetrically arranged on both sides of the first filling portion 191 , and the two gate conductors 170 are symmetrically arranged on both sides of the first filling portion 191 , thereby increasing the overall symmetry of the device.

[0101] Optionally, the gate conductor 170, the first resistance structure 181, the second resistance structure 182 and the first filling portion 191 are made of the same material and can be formed in the same step. Therefore, when manufacturing the power device, there is no need to additionally design a mask template for the first resistance structure 181, the second resistance structure 182 and the first filling portion 191, which is compatible with the original process and saves manufacturing costs.

[0102] Furthermore, a fourth doping region 152 is formed in the well region 130, and a fifth doping region 192 is formed in the first filling portion 191, as shown in FIG. Fig. 9 shown.

[0103] In this step, the fourth doping region 152 and the fifth doping region 192 are formed simultaneously, so that when manufacturing the power device, there is no need to additionally design a mask template for the fifth doping region 192, which is compatible with the original process and saves manufacturing costs.

[0104] Furthermore, a third doping region 151 is formed in the well region 140, such as Fig.10 The step of forming the third doping region 151 can be exchanged with the step of forming the fourth doping region 152 and the fifth doping region 192 .

[0105] The power device of the first embodiment of the present disclosure is provided with additional dual resistors and diodes to adjust the potentials of different regions in the power device, thereby reducing the on-state voltage drop of the power device and having a stronger anti-latch capability.

[0106] Furthermore, since the dual resistor structure and / or the diode structure is formed outside the doping region of the semiconductor layer, no additional carrier storage layer is introduced to increase the doping concentration, thus not causing degradation of the breakdown voltage BV of the power device.

[0107] Furthermore, the first resistance structure, the second resistance structure and the diode structure are all formed in the isolation portion and integrated with the IGBT main circuit in the same device (integrated in the same semiconductor layer), thereby reducing adverse effects such as noise and RC delay caused by external connections.

[0108] Furthermore, the first resistance structure, the second resistance structure, the diode structure and the gate conductor share the same isolation portion, which can save space occupied by the isolation portion and increase the unit area utilization of the device.

[0109] In addition, in this embodiment, no floating P-type doping region is provided. Since the floating P-type doping region will have a carrier storage effect when the device is switched, resulting in a local potential change, which will charge and discharge the gate through the displacement current, and the displacement current injected into the gate will not only reduce the switching frequency of the device (equivalently increase the gate capacitance area), but also cause the device to suffer greater dV / dt stress, making the reliability of the device worse. In this embodiment, no floating P-type doping region is provided, and the area between the cell trench gate structure is directly filled with an isolation part, and then a resistor structure and a diode structure are made in the isolation part, which is equivalent to reducing the gate capacitance and greatly reducing the risk of displacement current charging the gate. Therefore, this solution also has a high ability to resist dV / dt stress.

[0110] Fig.11 A schematic structural diagram of a power device according to a second embodiment of the present disclosure is shown.

[0111] like Fig.11 As shown, the similarities between the power device of the second embodiment of the present disclosure and the first embodiment are not repeated here, and reference may be made to Figures 1 to 10 The difference is that the diode structure of this embodiment is a Schottky diode formed by the contact between the first filling portion 191 and the metal layer 193 , wherein the metal layer 193 is located on the surface of the first filling portion 191 .

[0112] Fig.12 A schematic structural diagram of a power device according to a third embodiment of the present disclosure is shown.

[0113] like Fig.12 As shown, the similarities between the power device of the third embodiment of the present disclosure and the first embodiment are not repeated here, and reference may be made to Figures 1 to 10The difference is that, between the third doping regions 151 of the two cell structures, the two gate conductors 170 and the diode structure 190 are respectively located in different isolation portions 160. A thin layer of isolation portion 160 is also formed on the first surface of the semiconductor layer 101 between the diode structure 190 and the two gate conductors 170, and the first resistor structure 181 and the second resistor structure 182 are respectively located on the thin layer of isolation portion 160.

[0114] Optionally, the semiconductor layer 101 further includes a sixth doping region 104 located between two adjacent isolation portions 160 , wherein the doping type of the sixth doping region 104 may be the same as or opposite to the doping type of the well region 140 .

[0115] In some specific embodiments, when the well region 140 is of P type, the sixth doped region 104 is of N type. Since the N-type sixth doped region 104 accumulates fewer net holes during the conduction process of the power device, resulting in less potential rise in the floating region, the gate G displacement current will also be charged less, thereby enabling the power device to have a high ability to resist dV / dt stress.

[0116] In some other embodiments, the first diode D2 may be disposed outside the semiconductor layer 101 .

[0117] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A power device, comprising: A semiconductor layer having a first surface and a second surface opposite to each other, wherein the semiconductor layer comprises a first doping region, a second doping region, a well region and a third doping region which are adjacent to each other in sequence along a direction from the second surface to the first surface; an isolation portion extending from the first surface of the semiconductor layer into the second doping region and adjacent to the well region and the third doping region; as well as a gate conductor located in the isolation portion, The first doping region and the well region are of a first doping type, the second doping region and the third doping region are of a second doping type, and the first doping type is opposite to the second doping type. The semiconductor device further includes: a first resistor structure, a second resistor structure and a first diode structure, wherein the first resistor structure is used to form a first resistor, the second resistor structure is used to form a second resistor, and the diode structure is used to form a first diode. The first end of the first resistor is electrically connected to the third doped region, the second end of the first resistor is electrically connected to the cathode of the first diode and the first end of the second resistor respectively, the anode of the first diode is electrically connected to the third doped region, and the second end of the second resistor is electrically connected to the well region. Wherein, the resistance value of the first resistor is smaller than the resistance value of the second resistor.

2. The power device according to claim 1, wherein: The first doped region, the second doped region and the well region are used to form a first transistor, The second doping region, the well region and the third doping region are used to form a second transistor and a third transistor, The first transistor is a PNP transistor, the second transistor is an NPN transistor, and the third transistor is an NMOS transistor. The emitter of the first transistor is connected to a first potential, the base of the first transistor is respectively connected to the collector of the second transistor and the first current terminal of the third transistor, the collector of the first transistor is respectively connected to the base of the second transistor and the substrate of the third transistor, and the emitter of the second transistor is connected to the second current terminal of the third transistor. The anode of the first diode is connected to the emitter of the second transistor, and the cathode of the first diode is connected to the second potential. The first resistor is connected in series between the emitter of the second transistor and the second potential. The second resistor is connected in series between the base of the second transistor and the second potential.

3. The power device according to claim 1, wherein: The semiconductor device further includes a fourth doped region adjacent to the well region, and the second end of the second resistor is electrically connected to the fourth doped region. Wherein, the fourth doping region is of the first doping type.

4. The power device according to claim 1, wherein: The gate conductor, the first resistance structure, the second resistance structure, and the diode structure are located in the same isolation portion; Alternatively, at least one of the gate conductor, the first resistance structure, the second resistance structure, and the diode structure is located in different isolation portions.

5. The power device according to claim 1, wherein: The diode structure includes a first filling portion extending from a surface of the isolation portion into the isolation portion.

6. The power device according to claim 5, wherein: The diode structure further includes a fifth doped region extending from a surface of the first filling portion into the first filling portion, The fifth doping region is of the first doping type, and the first filling portion is of the second doping type.

7. The power device according to claim 5, wherein: The diode structure further includes a metal layer located on a surface of the first filling portion. Wherein, the first filling portion contacts the metal layer to form a Schottky diode.

8. The power device according to any one of claims 5 to 7, wherein: The first resistor structure extends from the surface of the isolation portion into the isolation portion, or the first resistor structure is located on the surface of the isolation portion; The second resistor structure extends from the surface of the isolation portion into the isolation portion, or the second resistor structure is located on the surface of the isolation portion.

9. The power device according to claim 8, wherein: The material of the first filling part and / or the first resistance structure and / or the second resistance structure is the same as the material of the gate conductor.

10. A method for manufacturing a power device, comprising: Forming a first doping region, a second doping region, a well region and a third doping region which are adjacent to each other in sequence in the semiconductor layer along a direction from the second surface of the semiconductor layer toward the first surface; forming an isolation portion in the semiconductor layer, the isolation portion extending from the first surface to the second doping region and adjacent to the well region and the third doping region; as well as forming a gate conductor in the isolation portion, The first doping region and the well region are of a first doping type, the second doping region and the third doping region are of a second doping type, and the first doping type is opposite to the second doping type. The manufacturing method further includes: forming a first resistance structure, a second resistance structure and a diode structure, The first resistor structure is used to form a first resistor, the second resistor structure is used to form a second resistor, and the diode structure is used to form a first diode. The first end of the first resistor is electrically connected to the third doped region, the second end of the first resistor is electrically connected to the cathode of the first diode and the first end of the second resistor respectively, the anode of the first diode is electrically connected to the third doped region, and the second end of the second resistor is electrically connected to the well region.

11. The manufacturing method according to claim 10, wherein: The steps of forming the diode structure include: forming a first filling portion in the isolation portion, The first filling portion and the gate conductor are formed in the same step.

12. The manufacturing method according to claim 10 or 11, wherein: The first resistance structure and / or the second resistance structure are formed in the same step as the gate conductor.

13. The manufacturing method according to claim 11, further comprising forming a fourth doping region in the semiconductor layer, wherein the fourth doping region extends from the first surface toward the second surface and is adjacent to the well region, The step of forming the diode structure further includes: forming a fifth doping region in the first filling portion, The fourth doping region and the fifth doping region are of the first doping type, and the first filling portion is of the second doping type. The fourth doping region and the fifth doping region are formed in the same step.

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