NAND die compensating for altered bond wire bandwidth in memory device by wire bond inductance

Abstract

A memory device includes a substrate of a memory package, the substrate including: a first pin pad; a controller mounted on the substrate and electrically connected to the first pin pad, the controller configured to manage data communication over the data channel; and a first memory die. The first memory die includes a front pin pad electrically connected to the first pin pad of the substrate through a first bond wire, a rear pin pad, a conductor segment electrically connecting the front pin pad and the rear pin pad of the first memory die, and a plurality of memory cells configured to provide non-volatile storage accessible through the data channel.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Non-Provisional Application No. 18 / 355,111, filed in the U.S. Patent and Trademark Office on July 19, 2023, entitled “NAND DIE WITH WIRE-BONDINDUCTIVE COMPENSATION FOR ALTERED BOND WIRE BANDWIDTH IN MEMORY DEVICES,” and is hereby incorporated by reference in its entirety for all purposes, which application claims priority to U.S. Provisional Application No. 63 / 419,414, filed on October 26, 2022. Background Art

[0003] Semiconductor memory and storage devices are widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices and non-mobile computing devices. Semiconductor memory may include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery). Examples of non-volatile memory include flash memory (e.g., NAND-type flash memory and NOR-type flash memory) and electrically erasable programmable read-only memory (EEPROM).

[0004] A typical NAND-type memory package provides one or more input / output (I / O) data channels from a substrate such as a ball grid array (BGA) package through one or more stacked NAND memory dies (e.g., to make the storage capacity larger). Each of these I / O channels is typically connected in series from the substrate to each memory die using bonding wires, wherein the bonding wires connect a pin cap on the substrate to a pin cap (e.g., an input pin or memory pad) on the memory die, or from a pin cap on one memory die to a pin cap on another memory die. Each of these bonding wire segments represents resistance and inductance in the I / O channel (e.g., wherein the I / O channel acts as a transmission line connecting portions of all memory dies to the BGA package). However, a typical I / O channel with such a conventional architecture with bonding wires exhibits a significant impedance mismatch, resulting in limited bandwidth on the channel. What is needed is an architecture that can increase the bandwidth on such I / O channels with bonding wires. Summary of the invention

[0005] The present application describes a storage device, which includes a substrate of a memory package. The substrate of the memory package includes a first pin pad. The storage device also includes a controller mounted on the substrate and electrically connected to the first pin pad, the controller being configured to manage data communications on a data channel. The storage device also includes a first memory die. The memory die includes a front pin pad electrically connected to the first pin pad of the substrate by a first bonding wire, a rear pin pad, a conductor segment electrically connecting the front pin pad and the rear pin pad of the first memory die, and a plurality of memory cells configured to provide non-volatile storage that can be accessed through the data channel.

[0006] The present application also describes a memory die. The memory die includes a first pin pad. The memory die also includes a second pin pad. The memory die also includes a conductor segment that electrically connects the first pin pad and the second pin pad through a single circuit segment of a predetermined length, the conductor segment being a conductor bond wire formed in a surface of the memory die.

[0007] The present application also describes a memory device. The memory device includes a substrate of a memory package, the substrate including means for electrically connecting a first pin pad of the memory package to a controller, thereby defining a data channel for data communication between at least the memory package and the controller. The memory device also includes a first memory die. The first memory die includes means for electrically connecting a front pin pad of the first memory die to a first pin pad of the substrate. The first memory die also includes means for electrically connecting a front pin pad and a rear pin pad of the first memory die through a conductor segment.

[0008] This Summary is provided to introduce some concepts in a simplified form that are further described in the Detailed Description below. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Non-limiting and non-exhaustive examples are described with reference to the following figures.

[0010] Figure 1A A conventional memory package is shown that includes a BGA package substrate on which four memory dies (eg, NAND memory dies) are mounted.

[0011] Figure 1B yes Figure 1A A model of an I / O channel is shown along with an electrical diagram of various exemplary electrical parameters associated with the channel.

[0012] Figure 1C It is shown Figure 1A and Figure 1B An exemplary graph of the bandwidth limitation of a bond wireframe is shown.

[0013] Figure 2A is an exemplary architecture of a memory package that implements an intermediate conductor segment (or just "intermediate conductor") between pairs of pin caps within a memory die to increase the maximum bandwidth on an I / O channel.

[0014] Figure 2B yes Figure 2A A diagram of a first example of an intermediate conductor segment is shown.

[0015] Figure 2C It is available with Figure 2A Schematic diagram of a second exemplary conductor segment for use with a memory package shown.

[0016] Figure 3 is achieved with Figure 2A Another exemplary architecture of a memory package having similar intermediate bonded lead segments is shown.

[0017] Figure 4 is shown in Figure 2 and Figure 3 A model of an I / O channel in a memory package along with an electrical diagram of various exemplary electrical parameters associated with the channel.

[0018] Figure 5 Figure 2 to Figure 4 An exemplary graph of the bandwidth limitation of a bond wireframe is shown.

[0019] Figure 6 is a perspective view of a memory system including a three-dimensional (3D) stacked nonvolatile memory.

[0020] Figure 7 An exemplary storage device such as Figure 6 Functional block diagram of a 3D stacked non-volatile memory device).

[0021] Figure 8 is an exemplary block diagram of an exemplary storage system depicting further details of the controller. DETAILED DESCRIPTION

[0022] In the following detailed description, reference is made to the drawings that form part of the detailed description, and in the drawings, specific embodiments or examples are shown by way of illustration. These aspects may be combined, other aspects may be utilized, and the structure may be changed without departing from the present disclosure. Examples may be practiced as methods, systems, or devices. Therefore, examples may take the form of hardware implementations, all-software implementations, or implementations combining software and hardware aspects. Therefore, the following detailed description should not be considered to have a limiting meaning, and the scope of the present disclosure is defined by the appended claims and their equivalents.

[0023] In some NAND memory devices, bonding wires are used to form I / O channels between the substrate of a memory package (e.g., a BGA package) and multiple NAND memory dies included in the package. Due to the need to increase storage capacity, multiple NAND flash memory dies can be stacked in a highly integrated, complex package system. For example, some BGA packages may include 2, 4, 8, or 16 memory dies in a single package. These memory dies can be integrated together into one or more I / O channels using a "single cap" bonding wire architecture, in which the pin caps of the package substrate are wired to the pin caps on the first memory die via bonding wires, and then wired from the pin caps on the first memory die to the pin caps on the second memory die via another bonding wire, and so on. The inductance of conventional pin cap to pin cap bonding wiring typically limits the bandwidth on the I / O channel (e.g., due to the impedance mismatch between the high impedance source and endpoints of a given channel and the low impedance transmission segment within the channel). As used herein, the term "pin cap" refers to a bonding pad, for example, a bonding pad formed on a substrate or a bonding pad formed on a semiconductor chip, wherein an electrical connection can be made between the chip and the substrate or between the chip and another chip using bonding wires or solder balls, such as in the case of a flip chip connection.

[0024] In order to increase the bandwidth on these I / O channels, the present application describes an architecture that introduces additional impedance into each segment of the I / O channel so that the bandwidth of these segments can be greatly increased. In one example, each memory die includes one or more pairs of pin caps (e.g., a pair of pin caps for each I / O channel supported by the memory die). Each pair of pin caps is separated by an electrical connector such as a bonding lead segment (a "middle bonding lead" or "middle segment" of a specific length) or a conductor wire bond, which introduces additional impedance into the I / O channel before connecting into the internal NAND circuit system of the memory die itself and wire bonding out to the next memory die. For example, for a given I / O channel, the substrate of the memory package is wire bonded from the pin caps on the substrate to the "front pin cap" of the first memory die, and the "back pin cap" of the first memory die is wire bonded to the front pin cap of the second memory die, and so on, until the last memory die. A conductor wire bond may be formed between the front pin cap and the rear pin cap, or a length of an intermediate bond wire may extend between the front pin cap and the rear pin cap and may wrap around the front pin cap or the rear pin cap before terminating at the rear pin cap.

[0025] In this example, each intermediate bond wire on the I / O channel increases the impedance of the channel segment by a predetermined amount (e.g., based on the size of the intermediate segment), so that the I / O channel can support a larger bandwidth. Modeling of the architecture shows that the impedance in each bond wire + intermediate bond wire segment increases from, for example, 200 picohenries (pH) to 600 picohenries of inductance, increasing the bandwidth of the total segment from 2 gigahertz (GHz) to 13 GHz. Therefore, adding the intermediate segment to each memory die increases the total bandwidth of the channel. Similarly, memory packages are described that utilize intermediate bond wires or conductor wires on multiple I / O channels to implement such intermediate connections, and have different numbers of dies per channel.

[0026] The following will refer to Figures 1 to Figure 8 These various benefits and examples are described in more detail.

[0027] Figures 1A to 1C 1 shows a conventional single cap bond wireframe of the memory package 100. Figure 1AAs shown, the memory package 100 includes a BGA package substrate 110 on which four memory dies 120 (e.g., NAND memory dies) are mounted. The exemplary memory package 100 shows one I / O channel (or just "channel") 112, wherein the BGA package 110 communicates with each of the memory dies 120 (e.g., passing data input / output operations and responses back and forth) through the channel. Each of the memory dies 120 can be, for example, a NAND flash memory die that includes internal circuitry (not shown) for providing volatile storage or non-volatile storage. It should be understood that Figure 1A The separation between the memory die 120 and the BGA package 110 is presented for illustration purposes, and it should be understood that many other circuitry details regarding the memory die 120 and the memory package 100 that are not particularly relevant to the present disclosure are not included for ease of discussion.

[0028] In this example, the BGA package 110 and each of the memory dies 120 include individual pin caps 104A-104E. For example, the BGA package 110 includes pin caps 104A, and each of the memory dies 120 includes pin caps 104B-104E, respectively. These pin caps or "I / O pads" 104 are used to connect the internal circuitry of the memory die 120 to the I / O channels 112. Each of the memory dies 120 presents underlying circuitry (e.g., NAND memory circuitry) that is Figure 1A 1 , represented as capacitance 106 , originates from pin caps 104B to 104E on each of the memory dies 120 .

[0029] More specifically, each of the pin caps 104 is connected to an adjacent memory die 120 or to the BGA package 110 itself via one or two bond wires 102. The bond wires 102 represent electrical connections (e.g., wires) that may be soldered or otherwise electrically connected to the pin caps 104. Figure 1A In the example shown, a bonding wire 102A connects a pin cap 104A on the surface of the substrate of the BGA package 110 with a pin cap 104B of the first memory die 120. Similarly, another bonding wire 102B connects the pin cap 104B of the first memory die 120 to the pin cap 104C of the second memory die 120, and so on, the bonding wire 102C connects the pin cap 104C to the pin cap 104D, and the bonding wire 102D connects the pin cap 104D to the pin cap 104E. Thus, a series of bonding wires 102 form a data transmission path, which is a channel 112 shared by all memory dies 120 and the BGA package 110.

[0030] Figure 1B yes Figure 1A 1 is a model of an I / O channel 112 along with an electrical diagram 140 of various exemplary electrical parameters associated with the channel 112. In this example, the four bond wires 102A and 102B to 102D are represented by inductances of L=1200pH and L=200pH, respectively. Each of the pin caps 104B to 104E on the memory die 120 is represented by a capacitance 106 of C=0.9 picofarads (pF). The channel 112 also includes a pin cap 104A (e.g., Z=50 ohms), which represents a transmission segment within the circuit system of the BGA package 110. Since the bond wire 102B to 102D segments in the channel 112 represent low impedance segments (e.g., Z o ≈14.9 ohms), so there is an obvious impedance mismatch between the low impedance section and the high impedance section.

[0031] In this example, channel 112 exhibits an impedance mismatch, which causes reflections and associated signal loss at certain points, and the signal reflections limit the bandwidth on the channel. For example, the reflection coefficient r between the 50 ohm segment and the 14.9 ohm segment can be calculated as follows:

[0032]

[0033] This reflection coefficient between segments where there is an impedance mismatch causes a certain percentage of the signal to be lost, thus limiting the overall bandwidth of the channel.

[0034] Figure 1C It is shown Figure 1A and Figure 1B An exemplary graph 150 of the bandwidth limitation of a bond wireframe is shown. In this example, the graph 150 includes a graph of frequency (in GHz, X-axis) versus insertion loss (S(2,1), in decibels (dB), Y-axis) (e.g., signal loss due in part to reflections occurring when impedance mismatches occur). In this example, Where V1 is the signal voltage at the beginning of channel 112, and V2 is the signal voltage at the end of channel 112. Therefore, when there is no voltage loss between the beginning and the end of the channel (e.g., when V2 = V1), then Y = 0. At Y = -3, 70% of the signal will pass, while 30% of the signal will be blocked.

[0035] Figure 2A 2 is an exemplary architecture of a memory package 200 that implements an intermediate conductor segment (or just “intermediate conductor”) 208 between each pair of pin caps 204A, 204B within a memory die 220 to increase the maximum bandwidth on an I / O channel 212. Figure 2AIn the example shown, each memory die 220 includes a pair of pin caps 204A, 204B for data transmission over the channel 212. Running between each pair of pin caps 204A, 204B is an intermediate conductor segment 208 formed on or in the surface of the memory die 220 (e.g., etched into the memory die 220). In some examples, the conductor segment 208 is a bonding wire, while in other examples, the conductor segment is a conductor wire bond. For example, a spiral inductor can be constructed using a p-type substrate having a stacked passivation oxide layer, a dielectric layer, and a metal layer. A physical spiral metal wiring is constructed using metal layers between the dielectric layers to form an inductor in the signal path. The spiral structure is connected between two pads 204A and 204B, such as Figure 2B As shown. The middle conductor segment 208 connects the "front" pin cap 204A of the memory die 220 (e.g., the pin cap 204A that is closest to the pin cap 204 of the BGA package 210) with the "back" pin cap 204B of the memory die 220. The middle conductor segment 208 forms a single wired path of a predetermined length, which in one example is wrapped around the back pin cap 204B (e.g., the predetermined length is achieved by using coiled wiring around the back pin cap, spanning at least the separation distance between the two pin caps 204A, 204B, and possibly longer). In addition, the internal circuit system (e.g., NAND circuit system) of the memory die 220 is connected to the back pin cap 204B within the memory die 220, as shown herein by the "lumped" capacitor 206.

[0036] Figure 2B yes Figure 2A 2 is a diagram of a first example of an intermediate conductor segment 208 shown. In this example, a conductor wire bond 230 is used to connect the front pin cap 204A to the rear pin cap 204B. The front pin cap 204A and the rear pin cap 204B are separated by a separation distance 240 on the memory die 220. The dimensions of the intermediate conductor segment 208 and its associated conductor wire bond 230 are configured such as to add a predefined additional impedance to a segment of the channel 212 (e.g., before the next lumped capacitor 206 on the channel 212).

[0037] like Figure 2BAs shown, the middle conductor segment 208 includes a first segment (or "straight segment") 224 of the conductor wire 230 and a second segment (or "coiled segment") 222 of the conductor wire 230. The straight segment 224 extends a first length 242 from the front lead pad 204A toward the rear lead pad 204, which in this example covers a majority of the separation distance 240 between the two lead pads 204A, 204B. Prior to being connected to the rear lead pad 204B, the conductor wire 230 is wrapped around the rear lead pad 204B (e.g., in a geometric shape such as a circle, rectangle, octagon, etc.) one or more times, or portions thereof. The second segment 222 defines a second length (in Figure 2B 2 (not separately shown in the figure), the second length, when added to the first length 242, defines the overall length of the intermediate conductor segment 208.

[0038] In this example, the width of the straight segment 224 of the conductor bond wire 230 is between 5 microns and 25 microns (μm) and the total length is between 10 microns and 30 microns. The width of the coiled segment 222 of the conductor bond wire 230 is five microns and is separated by a separation distance 232 of two microns. The outermost diameter 244 of the coiled segment 222 is 50 microns (e.g., between 40 microns and 60 microns) in this example, reducing to an innermost diameter of 28 microns (e.g., between 18 microns and 38 microns). The size of the pin pads 204A, 204B is 60×65 microns, and the separation distance 240 between the two pin pads 204A and 204B is between 21 microns and 41 microns. Thus, the total path length of the bond wire 230 between the first lead pad 204A and the second lead pad 204B is between 226 microns and 246 microns, between 200 microns and 300 microns, or a length and width that adds, for example, 50 ohms of additive impedance ("target" additive impedance).

[0039] In another example (not shown), the middle conductor segment 208 may begin at the front pin pad 204A with a coiled segment 222 (e.g., wrapping around the front pin pad 204A and coiling outwardly, thereby increasing the diameter), and may end at a straight segment 224 (e.g., extending from the outer edge of the coiled segment 222 to the rear pin pad 204B). In yet another example (not shown), the middle conductor segment 208 may have a coiled segment 222 around the front pin pad 204A and another coiled segment 222 around the rear pin pad 204B.

[0040] Figure 2C It is available with Figure 2A FIG. 2 is a diagram of a second exemplary conductor segment 208 for use with the memory package 200 shown in FIG. Figure 2BThe example shown is similar, with the conductor segment 208 including a straight segment 224 and a coiled segment 222. However, inside the coiled segment 222, the conductor bond wire 230 is instead connected to a hole 250A. The hole 250A descends into the lower layer (e.g., below the surface) of the memory die 220 and extends toward the rear pin pad 204B with a metal bond wire 252 (shown in dashed lines to indicate traversal of the lower layer / plane). Once the metal bond wire 252 is outside the coiled segment 222, another hole 250B takes the path up to the surface of the memory die 220 and travels along the surface of the memory die 220 to terminate at the rear pin pad 204B.

[0041] In this example, the width of the straight segment 224 of the conductor wire bond (e.g., bonding wire) 230 is between 5 microns and 25 microns (μm) and the total length is between 10 microns and 30 microns. The width of the coiled segment 222 of the conductor wire bond 230 is five microns and is separated by a separation distance 232 of two microns. The outermost diameter 244 of the coiled segment 222 is 50 microns (e.g., between 40 microns and 60 microns) in this example, reducing to an innermost diameter of 28 microns (e.g., between 18 microns and 38 microns). The dimensions of the pin pads 204A, 204B are 60×65 microns. The separation distance 258 between the two holes 250A and 250B is between 42 microns and 65 microns, and the separation distance between the first hole 250A and the rear pin pad 204B is between 44 microns and 65 microns. The total separation distance 254 between the pin pads 204A, 204B can be between 60 microns and 100 microns. Thus, the total path length of the conductor wire bond 230 between the first lead pad 204A and the second lead pad 204B is between 271 microns and 311 microns, between 250 microns and 350 microns, or a length and width that adds, for example, 50 ohms of additive impedance ("target" additive impedance).

[0042] Figure 3 is achieved with Figure 2A200. In this example, the BGA package 310 includes a plurality of I / O channels 212 (e.g., 2, 4, 8, or 16 channels), each of which is wire bonded out from a separate pin pad 204 on the BGA package 310 to a memory die 320. Each of the memory dies 320 includes a plurality of pairs of pin pads 204A, 204B, each of which is similarly connected by a middle conductor segment 208. It should be understood that more or fewer channels 212 may be supported by the BGA package 310 and by the memory die 320, more or fewer memory die 320 may be supported by the BGA package 310 on each of the channels 212, and additional groups of channels 212 and memory die 320 may be included on the BGA package 310. In this example, channels 212 (eg, on BGA package 210 and on memory die 220) are separated from each other by 150 microns (eg, between 100 microns and 200 microns).

[0043] exist Figure 3 In the example shown, Figure 2B The middle conductor segment 208 (eg, the coiled segment 222 surrounds the rear pin pad 204B). In another example (not shown), the coiled segment 222 surrounding the front pin pad 204B may be used to achieve Figure 2B In another example (not shown), it is possible to implement Figure 2C The middle conductor segment 208 of the memory die 220 (eg, each pair of holes 250 extends the channel 212 through another layer of the memory die 220 to appear outside the coiled segment 222 before connecting to the rear lead pad 204B).

[0044] Reference now Figure 2A and Figure 3 , the pin cap 204 of the BGA package 210, 310 connects the I / O channel 212 to a controller, such as Figures 7 and 8 The controller 622 is shown. Figure 2A and Figure 3 In the configuration shown, the memory packages 200, 300 may be configured to operate the I / O channels 212 at any frequency up to the 13 GHz threshold (eg, 3.6 GHz, 4.8 GHz, etc.).

[0045] Figure 4 It is shown in Figure 2A and Figure 31. A model of an I / O channel 212 in a memory package 200, 300 of FIG. 1 along with an electrical diagram 400 of various exemplary electrical parameters associated with the channel 212. In this example, the four bond wires 202A and 202B to 102D are represented by an inductance of L=200pH. Each rear pin cap 204B on the memory die 220 is represented by a capacitance 206 of C=0.9 picofarads (pF). The channel 212 also includes a pin cap 204 (e.g., Z=50 ohms), which represents a transmission segment within the circuit system of the BGA package 110.

[0046] In addition, each intermediate conductor segment 208 is represented in diagram 400 as an additional inductance of L=400pH (e.g., between 300pH and 500pH) on the associated segment of channel 212 (e.g., connected in series before the corresponding capacitor 206 in the preceding to succeeding item). Therefore, in this example, each segment with a bond wire 202 combined with the intermediate conductor segment 208 forms a total inductance of 700pH (e.g., between 600pH and 800pH). For higher pad capacitance, the number of turns of the coil can be increased to achieve higher inductance values ​​(e.g., above 1nH).

[0047] In one example, the middle conductor segment 208 is modeled as a microstrip, which is a transmission line in which the conductor is surrounded by two different dielectric materials above and below the wiring. For an inductance of about 400 pH, a middle conductor segment 208 with a conductor length of 1200 μm (micrometer) and a width of 10 μm is formed. In other examples, the length and width can vary, but still reach or approach an inductance of 400 pH. In some examples, the dielectric material surrounding the conductor can be silicon oxide (e.g., at 1 GHz, dielectric constant = 4) and air (dielectric constant = 1 at all frequencies). In some examples, the length of the middle conductor segment 208 can be between 1000 μm and 1400 μm. In some examples, the width of the middle conductor segment 208 can be between 8 μm and 12 μm. In some examples, the target inductance can be between 300 pH and 500 pH. In some examples, the additional inductance provided by the middle conductor segment 208 can be provided based on the resistance of the highest segment on the channel 112. In some examples, the inductance added by the middle conductor segment 208 is greater than or equal to 100 pH or greater than or equal to 300 pH (eg, a combination of conductor length and width so as to produce at least such target inductance).

[0048] Figure 5 Figure 2 to Figure 45. An exemplary graph 500 of the bandwidth limitation of the architecture shown in FIG. 5 includes, in this example, a graph of frequency (in GHz, X-axis) versus insertion loss (S(2,1), in decibels (dB), Y-axis) (e.g., signal loss due in part to reflections occurring when impedance mismatches occur). At -3.0 dB, by using Figures 2A to 4 The middle conductor segment 208 can achieve a bandwidth of about 13 GHz. Figures 1A to 1C Compared with the architecture of Figure 1C As shown, Figures 2A to 4 The improved middle bond wire segment architecture allows the bandwidth of the I / O channel 212 to be increased from 2 GHz to 13 GHz.

[0049] Figures 6 to 8 Describes what can be Figures 2A to 3 An example of a memory system that can include memory packages 200, 300 and memory dies 220, 320. In some examples, the memory packages 200, 300 are similar to the memory device 600, and the memory dies 220, 320 are similar to the memory device 600. Figures 6 to 8 Memory die 608 is shown to be similar. Figure 6 6 is a perspective view of a memory device 600 including a three-dimensional (3D) stacked non-volatile memory. The memory device 600 includes a substrate 601. On and above the substrate are exemplary blocks of memory cells formed by memory cells (non-volatile memory elements), including BLK0 and BLK1. Also on the substrate 601 is a peripheral area 604, which has supporting circuits for the blocks. The substrate 601 may also carry circuits below the blocks, together with one or more lower metal layers, which are patterned in conductive paths to carry signals of the circuits. The blocks may be formed in a middle area 602 of the memory device 600. In an upper area 603 of the memory device 600, one or more upper metal layers are patterned in conductive paths to carry signals of the circuits. Each memory cell block includes a stacking area of ​​memory cells, wherein the alternating layers of the stack represent word lines. Although only two blocks are depicted as examples, additional blocks extending in the x-direction and / or the y-direction may be used.

[0050] In one exemplary implementation, the length of the plane in the x-direction represents the direction in which the signal path of the word line extends (e.g., the word line direction or the drain terminal select gate (SGD) line direction), and the width of the plane in the y-direction represents the direction in which the signal path of the bit line extends (e.g., the bit line direction). The z-direction represents the height of the memory device 600.

[0051] Figure 7 is an exemplary storage device 600 (such as Figure 6 Functional block diagram of a 3D stacked non-volatile memory device). Figure 7 The components depicted in are circuits. The storage device 600 includes one or more memory dies 608. Each memory die 608 includes a three-dimensional memory structure 626 of memory cells (e.g., a 3D array of memory cells), a control circuit system 610, and a read / write circuit 628. In other examples, a two-dimensional array memory cell can be used. The memory structure 626 can be addressed by word lines using a decoder 624 (e.g., a row decoder), and can be addressed by bit lines using a column decoder 632. The read / write circuit 628 includes a plurality of sense blocks 650, including SB1, SB2...SBp (e.g., a sense circuit system) and allows a page of memory cells to be read or programmed in parallel. In some systems, the controller 622 is included in the same storage device 600 (e.g., a removable memory card) as one or more memory dies 608. In some examples, the controller is formed on a die bonded to the memory die, in which case each memory die has its own controller. In other examples, the controller die controls all memory dies. Commands and data are transferred between the host 640 and the controller 622 using the data bus 620, and between the controller 622 and one or more memory dies 608 via lines 618. In one example, the memory die 608 includes a set of input and / or output (I / O) pins connected to the lines 618.

[0052] The memory structure 626 may include one or more memory cell arrays, including 3D arrays. The memory structure may include a monolithic 3D memory structure in which multiple memory levels are formed above (e.g., rather than in) a single substrate (such as a wafer) without an intermediate substrate. The memory structure may include any type of non-volatile memory formed monolithically in one or more physical levels of an array of memory cells having active regions disposed above a silicon substrate. The memory structure may be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is above or within the substrate.

[0053] The control circuit system 610 cooperates with the read / write circuit 628 to perform memory operations (e.g., erase, program, read, etc.) on the memory structure 626, and includes a state machine 612, an on-chip address decoder 614, and a power control module 616. The state machine 612 provides chip-level control of memory operations. The temperature detection circuit 613 is configured to detect temperature and can be any suitable temperature detection circuit known in the art. In one example, the state machine 612 is programmed by software. In other examples, software is not used and the state machine 612 is implemented entirely in hardware (e.g., circuits). In one example, the control circuit system 610 includes registers, ROM fuses, and other devices for storing default values ​​(such as reference voltages and other parameters).

[0054] The on-chip address decoder 614 provides an address interface between the address used by the host 640 or the controller 622 to the hardware address used by the decoder 624 and the decoder 632. The power control module 616 controls the power and voltage provided to the word lines and bit lines during memory operations. It may include drivers for the word line layer in a 3D configuration, select transistors (e.g., SGS and SGD transistors), and source lines. The power control module 616 may include a charge pump for forming voltages. The sense block includes a bit line driver. The SGS transistor is a select gate transistor at the source end of the NAND string, and the SGD transistor is a select gate transistor at the drain end of the NAND string.

[0055] Any one or any combination of the control circuit system 610, state machine 612, decoder 614 / 624 / 632, temperature detection circuit 613, power control module 616, sensing block 650, read / write circuit 628, and controller 622 may be considered as one or more control circuits or management circuits that perform some or all of the functions described herein.

[0056] In one example, the controller 622, which may be a circuit on or off the chip, may include one or more processors 622c, ROM 622a, RAM 622b, memory interface 622d, and host interface 622e, all of which are interconnected. One or more processors 622c are an example of a control circuit. Other examples may use a state machine or other custom circuits designed to perform one or more functions. Devices such as ROM 622a and RAM 622b may include codes such as instruction sets, and the processor 622c may be operable to execute the instruction set to provide some or all of the functions described herein. Alternatively or in addition, the processor 622c may access code from a memory device in a memory structure, such as a reserved area of ​​a memory cell connected to one or more word lines. The memory interface 622d communicating with ROM 622a, RAM 622b, and processor 622c is a circuit that provides an electrical interface between the controller 622 and the memory die 608. For example, the memory interface 622d may change the format or timing of a signal, provide a buffer, isolate surges, latch I / O, etc. The processor 622c may use the memory interface 622d to issue commands to the control circuit system 610 or any other component of the memory die 608. The host interface 622e, which communicates with the ROM 622a, the RAM 622b, and the processor 622c, is a circuit that provides an electrical interface between the controller 622 and the host 640. For example, the host interface 622e may change the format or timing of a signal, provide a buffer, isolate surges, latch I / O, etc. Commands and data from the host 640 are received by the controller 622 through the host interface 622e. Data sent to the host 640 is transmitted using the host interface 622e.

[0057] The multiple memory elements in the memory structure 626 can be configured so that they are connected in series or so that each element is individually accessible. As a non-limiting example, a flash memory storage device in a NAND configuration (e.g., NAND flash memory) typically contains memory elements connected in series. A NAND string is an example of a group of memory cells and select gate transistors connected in series.

[0058] A NAND flash memory array can be configured such that the array includes multiple NAND strings, where a NAND string includes multiple memory cells that share a single bit line and are accessed as a group. Alternatively, the memory elements can be configured such that each element can be accessed individually (e.g., a NOR memory array). NAND and NOR memory configurations are exemplary, and memory cells can be configured in other ways.

[0059] Memory cells may be arranged in an ordered array in a single memory device level, such as in multiple rows and / or columns. However, memory elements may be arranged in irregular or non-orthogonal configurations, or in structures that are not considered arrays.

[0060] Some three-dimensional memory arrays are arranged so that memory cells occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., x, y and z directions, where the z direction is substantially vertical and the x and y directions are substantially parallel to the major surface of the substrate).

[0061] As a non-limiting example, a 3D memory structure may be arranged vertically as a stack of multiple 2D memory device levels. As another non-limiting example, a 3D memory array may be arranged as a plurality of vertical columns (e.g., columns substantially perpendicular to the major surface of the substrate such as extending in the y-direction), wherein each column has a plurality of memory cells. The vertical columns may be arranged into a two-dimensional arrangement of memory cells, wherein the memory cells are located on a plurality of vertically stacked memory planes. Other configurations of three-dimensional memory elements may also constitute a 3D memory array.

[0062] As a non-limiting example, in a 3D NAND memory array, memory elements may be coupled together to form vertical NAND strings that traverse multiple horizontal memory device levels. Other 3D configurations are contemplated in which some NAND strings contain memory elements in a single memory level while other strings contain memory elements that span multiple memory levels. The 3D memory array may also be designed in a NOR configuration and in a ReRAM configuration.

[0063] One of ordinary skill in the art will recognize that the technology described herein is not limited to a single specific memory structure, but encompasses many related memory structures within the spirit and scope of the technology described herein and as understood by one of ordinary skill in the art.

[0064] Figure 8 6 is a block diagram of an exemplary storage device 600, which depicts more details of the controller 622. In one example, Figure 8The system is a solid state drive (SSD). As used herein, a flash memory controller is a device that manages data stored on a flash memory and communicates with a host such as a computer or other electronic device. In addition to the specific functions described herein, a flash memory controller may also have various functions. For example, a flash memory controller may format a flash memory to ensure that the memory operates properly, map out bad flash memory cells, and allocate spare memory cells to replace future failed memory cells. Some of the spare memory cells may be used to accommodate firmware to operate the flash memory controller and implement other features. In operation, when a host reads data from or writes data to the flash memory, the host communicates with the flash memory controller. If the host provides a logical address to read / write data, the flash memory controller may convert the logical address received from the host into a physical address in the flash memory. Alternatively, in some examples, the host may provide a physical address. The flash memory controller may also perform various memory management functions, such as, but not limited to, wear leveling (e.g., allocating writes to avoid wear of a particular memory block that would otherwise be repeatedly written) and garbage collection (e.g., after a block is full, only valid data pages are moved to a new block, so that the complete block can be erased and reused). Nonvolatile memory other than flash memory may have a nonvolatile memory controller similar to the flash memory controller.

[0065] The communication interface between the controller 622 and the non-volatile memory die 608 can be any suitable flash memory interface, such as a switch mode. In one example, the storage device 600 can be a card-based system, such as a secure digital card (SD) or a micro secure digital (micro SD) card. In another example, the storage system 600 can be part of an embedded storage system. For example, the flash memory can be embedded in a host, such as in the form of a solid state disk drive housed in a personal computer.

[0066] In some examples, the storage system 600 includes a single channel between the controller 622 and the non-volatile memory die 608. However, the subject matter described herein is not limited to having a single memory channel. For example, in some storage system architectures, there are two, four, eight, or more channels 608 between the controller and the memory die (e.g., depending on the capabilities of the controller). In any of the examples described herein, even if a single channel is shown in the figures, there may be more than a single channel between the controller and the memory die 608.

[0067] like Figure 8 As depicted, the controller 622 includes a front end module 808 that interacts with a host, a back end module 810 that interacts with one or more non-volatile memory dies 608, and various other modules that perform the functions described herein.

[0068] Figure 8 The components of the controller 622 depicted in the figure may take the form of a packaged functional hardware unit (e.g., circuit) designed for use with other components, a portion of a program code (e.g., software or firmware) that can be executed by a processing circuit system that performs related functions or specific functions, or a separate set of hardware or software components that interact with a larger system. The controller 622 may include an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a circuit, a digital logic circuit, an analog circuit, a combination of discrete circuits, gates, or any other type of hardware, or a combination thereof. Figure 8 The architecture depicted may or may not be used Figure 7 An exemplary implementation of components of controller 622 (e.g., RAM, ROM, processor, interfaces) is depicted in FIG.

[0069] Referring again to the modules of controller 622, buffer management / bus controller 814 manages the buffers in random access memory (RAM) 816 and controls the internal bus arbitration of controller 622. Read only memory (ROM) 818 stores the system boot code. Figure 6 Shown as being located separate from the controller 622, but in other examples, one or both of the RAM 816 and ROM 818 may be located within the controller 622 and external to the controller 622. Furthermore, in some implementations, the controller 622, RAM 816, and ROM 818 may be located on separate semiconductor dies.

[0070] The front-end module 808 includes a host interface 820 and a physical layer interface 822 (PHY) that provide an electrical interface with a host or a next-level storage controller. The type of host interface 820 can be selected according to the type of memory used. Examples of host interface 820 include, for example, SATA, SATA Express, SAS, Fibre Channel, USB, PCIe, and NVMe. The host interface 820 can be a communication interface that facilitates the transmission of data, control signals, and timing signals.

[0071] The backend module 810 includes an error correction controller (ECC) engine 824 that encodes data bytes received from the host and decodes and corrects data bytes read from the non-volatile memory. A command sequencer 826 generates command sequences, such as a program command sequence and an erase command sequence, for transmission to the non-volatile memory die 608. A RAID (Redundant Array of Independent Dies) module 828 manages the generation of RAID parity and the recovery of failed data. RAID parity can be used as an additional level of integrity protection for data written to the storage device 600. In some cases, the RAID module 828 can be part of the ECC engine 824. It should be noted that RAID parity can be added as one or more additional dies, or can be added within an existing die (e.g., as (one or more) additional planes, (one or more) additional blocks, or (one or more) additional WLs within (one or more) blocks). The ECC engine 824 and the RAID module 828 can calculate redundant data that can be used to recover when errors occur and can be considered as examples of redundant encoders. The ECC engine 824 and the RAID module 828 can be considered to form a combined redundant encoder 834 together. The memory interface 830 provides command sequences to the non-volatile memory die 608 and receives status information from the non-volatile memory die 608. In some examples, the memory interface 830 can be a double data rate (DDR) interface. The flash control layer 832 controls the overall operation of the back-end module 810.

[0072] Figure 8 Additional components of the memory device 600 shown include a media management layer 838 that performs wear leveling of the memory cells of the non-volatile memory die 608. The memory device 600 also includes other discrete components 840, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that can interact with the controller 622. In other examples, one or more of the physical layer interface 822, the media management layer 838, and the buffer management / bus controller 814 are optional components that are not necessary in the controller 622.

[0073] A flash translation layer (FTL) or media management layer (MML) 838 may be integrated as part of the flash management that may handle flash errors and interface with the host. Specifically, the MML may be a module in the flash management and may be responsible for the internals of the NAND management. Specifically, the MML 838 may include an algorithm in the storage device firmware that converts writes from the host into writes to the flash memory structure 626 of the memory die 608. The MML 838 may be used because, for example, the endurance of the flash memory may be limited, the flash memory structure 626 may only be written in the form of multiple pages, or the flash memory structure 626 may not be written unless it is erased as a block (e.g., a block may be considered the smallest erase unit and such non-volatile memory may be considered a block-erasable non-volatile memory).

[0074] MML 838 is configured to work within these potential limitations of flash memory structure 626, which may not be visible to the host. Therefore, MML 838 attempts to convert writes from the host into writes into flash memory structure 626.

[0075] The controller 622 can interface with one or more memory dies 608. In one example, the controller 622 and the plurality of memory dies 608 (e.g., together comprising the storage device 600) implement an SSD that can emulate, replace, or be used in place of a hard drive within a host device, such as a NAS device, etc. Additionally, the SSD need not function as a hard drive.

[0076] In one example, the present application describes a memory device, the memory device comprising: a substrate of a memory package, the substrate comprising a first pin pad; a controller mounted on the substrate and electrically connected to the first pin pad, the controller being configured to manage data communication on a data channel; and a first memory die, the first memory die comprising: a front pin pad, the front pin pad being electrically connected to the first pin pad of the substrate through a first bonding wire; a rear pin pad; a first conductor segment, the first conductor segment electrically connecting the front pin pad and the rear pin pad of the first memory die; and a plurality of memory cells, the plurality of memory cells being configured to provide non-volatile storage that can be accessed through a data channel. In one example, the first conductor segment is wound around one or more of the front pin pad and the rear pin pad at least once. In one example, the first conductor segment forms a straight segment extending from a portion of the distance between the front pin pad toward the rear pin pad, wherein the first conductor segment also forms a winding segment that at least partially wraps around the rear pin pad. In one example, the rear pin pad is electrically connected to the pin pad of the second memory die through the second bonding wire, thereby extending the data channel to at least the second memory die. In one example, the first conductor segment introduces at least 100 picohenries (pH) of additional impedance on the channel segment between the front pin pad and the rear pin pad of the first memory die. In one example, the additional impedance on the segment is between 300 picohenries and 500 picohenries (pH). In one example, the first conductor segment defines a conductor having a length between 200 microns and 350 microns and a conductor width between 3 microns and 15 microns. In one example, a plurality of memory cells are electrically connected to the data channel through the rear pin pad of the first memory die. In one example, the first memory die also includes one or more pairs of pin pads, each pair of pin pads is separated by other conductor segments, and the other conductor segments are electrically connected to each pin pad in the associated pin pad pair through a single circuit segment. In one example, the front pin pad and the rear pin pad and the first conductor segment are formed on the top surface of the first memory die, wherein the first conductor segment is a conductor wire.

[0077] The present application also describes a memory die, the memory die comprising: a first pin pad; a second pin pad; and a conductor segment, the conductor segment electrically connecting the first pin pad and the second pin pad through a single circuit segment of a predetermined length, the conductor segment being a conductor wire bond formed on a surface of the memory die. In one example, the conductor wire bond wraps around one or more of the first pin pad and the second pin pad at least once. In one example, the conductor wire bond forms a straight segment extending from the first pin pad toward a portion of the distance between the second pin pad, wherein the conductor wire bond also forms a winding segment at least partially wrapped around the second pin pad. In one example, the second pin pad is electrically connected to the pin pad of the second memory die through a second bonding wire, thereby extending the data channel to at least the second memory die. In one example, the conductor wire bond introduces at least 100 picohenry (pH) of additional impedance on the segment between the first pin pad and the second pin pad of the first memory die. In one example, the additional impedance on the segment is between 300 picohenry and 500 picohenry (pH). In one example, the conductor wirebond defines a conductor having a length between 200 microns and 350 microns and a conductor width between 3 microns and 15 microns. In one example, the plurality of memory cells are electrically connected to a second pin pad of the memory die. In one example, the first memory die further comprises one or more pairs of pin pads, each pair of pin pads being separated by other conductor segments, the other conductor segments being electrically connected to each pin pad of the associated pair of pin pads via the conductor wirebond.

[0078] The present application also describes a storage device, which includes: a substrate of a memory package, the substrate including a device for electrically connecting a first pin pad of the memory package to a controller, thereby defining a data channel for data communication between at least the memory package and the controller; and a first memory die, the first memory die including: a device for electrically connecting a front pin pad of the first memory die to a first pin pad of the substrate; and a device for electrically connecting the front pin pad and the rear pin pad of the first memory die through a conductor segment.

[0079] The term computer-readable medium used herein may include computer storage media. Computer storage media may include volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures or program modules. Computer storage media may include RAM, ROM, electrically erasable read-only memory (EEPROM), flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical storage devices, cassettes, magnetic tapes, magnetic disk storage devices or other magnetic storage devices, or any other products that can be used to store information and can be accessed by a computing device. Any such computer storage medium may be part of a computing device. Computer storage media does not include carrier waves or other propagated or modulated data signals.

[0080] Additionally, the examples described herein may be discussed in the general context of computer-executable instructions residing on some form of computer-readable storage media, such as program modules executed by one or more computers or other devices. By way of example and not limitation, computer-readable storage media may include non-transitory computer storage media and communication media. In general, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The functionality of program modules may be combined or distributed in various examples as desired.

[0081] Communication media may be embodied by computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and includes any information delivery media. The term "modulated data signal" may describe a signal that has one or more characteristics set or changed in a manner that encodes information in the signal. By way of example and not limitation, communication media may include wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, radio frequency (RF), infrared, and other wireless media.

[0082] The description and illustration of one or more aspects provided in this disclosure are not intended to limit or restrict the scope of this disclosure in any way. The various aspects, examples, and details provided in this disclosure are considered to be sufficient to convey ownership and enable others to make and use the best way of the disclosed content protected by the claims.

[0083] The disclosure protected by the claims should not be understood as being limited to any aspect, example or detail provided in the disclosure. Whether shown and described in combination or individually, various features (both structural and method features) are intended to be selectively rearranged, included or omitted to produce examples with a particular set of features. Having provided the description and illustration of the present application, those skilled in the art may envision variations, modifications and substitutions that fall within the spirit of the broader aspects of the general inventive concept embodied in the present application and that do not depart from the broader scope of the disclosure protected by the claims.

[0084] Various aspects of the present disclosure have been described below with reference to schematic flow charts and / or schematic block diagrams of methods, devices, systems, and computer program products according to examples of the present disclosure. It should be understood that each box of the schematic flow chart and / or schematic block diagram, and the combination of boxes in the schematic flow chart and / or schematic block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor or other programmable data processing device of a computer to produce a machine, so that the instructions executed by the processor or other programmable data processing device create a device for implementing the functions and / or actions specified in one or more boxes of the schematic flow chart and / or schematic block diagram.

[0085] The use of names such as "first," "second," and the like to refer to elements herein does not generally limit the number or order of those elements. Rather, these names can be used as a method of distinguishing two or more elements or instances of elements. Thus, reference to a first element and a second element does not mean that only two elements may be used, nor does it mean that the first element must precede the second element. Additionally, unless otherwise specified, a group of elements may include one or more elements.

[0086] A term of the form "at least one of A, B, or C" or "A, B, C, or any combination thereof" used in the specification or claims means "A or B or C or any combination of these elements." For example, this term may include A, or B, or C, or A and B, or A and C, or A and B and C, or 2A, or 2B, or 2C, or 2A and B, etc. As an additional example, "at least one of A, B, or C" is intended to cover A, B, C, AB, AC, BC, and ABC, and multiples of the same member. Similarly, "at least one of A, B, and C" is intended to cover A, B, C, AB, AC, BC, and ABC, and multiples of the same member.

[0087] Similarly, as used herein, a phrase referring to a list of items linked with "and / or" refers to any combination of items. As an example, "A and / or B" is intended to cover A alone, B alone, or A and B together. As another example, "A, B, and / or C" is intended to cover A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together.

Claims

1. A storage device, comprising: a substrate of a memory package, the substrate comprising a first pin pad; a controller mounted on the substrate and electrically connected to the first pin pads, the controller being configured to manage data communications on a data channel; as well as A first memory die, the first memory die comprising: a front pin pad electrically connected to the first pin pad of the substrate through a first bonding wire; Rear pin pad; a first conductor segment electrically connecting the front lead pad and the back lead pad of the first memory die; and A plurality of memory cells are configured to provide non-volatile storage accessible through the data channel.

2. The storage device according to claim 1, wherein: The first conductor segment is wrapped at least once around one or more of the front pin pad and the rear pin pad.

3. The storage device according to claim 1, wherein: The first conductor segment forms a straight segment extending a portion of the distance between the front lead pads toward the rear lead pads, wherein the first conductor segment also forms a coiled segment at least partially wrapped around the rear lead pads.

4. The storage device according to claim 1, wherein: The rear pin pads are electrically connected to pin pads of a second memory die through second bonding wires, thereby extending the data channel to at least the second memory die.

5. The storage device according to claim 1, wherein: The first conductor segment introduces at least 100 picohenries (pH) of additional impedance on a channel segment between the front lead pad and the back lead pad of the first memory die.

6. The storage device according to claim 5, wherein: The additional impedance on the segment is between 300 and 500 picohenries (pH).

7. The storage device according to claim 1, wherein: The first conductor segment defines a conductor having a length between 200 microns and 350 microns and a conductor width between 3 microns and 15 microns.

8. The storage device according to claim 1, wherein: The plurality of memory cells are electrically connected to the data channel through the back pin pads of the first memory die.

9. The storage device according to claim 1, wherein: The first memory die also includes one or more pairs of pin pads, each pair of pin pads being separated by other conductor segments that electrically connect each pin pad in an associated pair of pin pads through a single circuit segment.

10. The storage device according to claim 1, wherein: The front and rear pin pads and the first conductor segment are formed on a top surface of the first memory die, wherein the first conductor segment is a conductor wire bond.

11. A memory die, the memory die comprising: First pin pad; Second pin pad; as well as A conductor segment electrically connects the first pin pad and the second pin pad through a single circuit segment of a predetermined length, the conductor segment being a conductor bonding wire formed on a surface of the memory die.

12. The memory die of claim 11, wherein: The conductor bond wire is wrapped around one or more of the first lead pad and the second lead pad at least once.

13. The memory die of claim 11, wherein: The conductor bond wire forms a straight segment extending a portion of the distance between the first lead pad toward the second lead pad, wherein the conductor bond wire also forms a coiled segment at least partially wrapped around the second lead pad.

14. The memory die of claim 11 , wherein: The second pin pad is electrically connected to a pin pad of a second memory die through a second bonding wire, thereby extending a data channel to at least the second memory die.

15. The memory die of claim 11, wherein: The conductor bond wire introduces at least 100 picohenries (pH) of additional impedance over a segment between the first pin pad and the second pin pad of the first memory die.

16. The memory die of claim 15, wherein: The additional impedance on the segment is between 300 and 500 picohenries (pH).

17. The memory die of claim 11, wherein: The conductor wirebond defines a conductor having a length between 200 microns and 350 microns and a conductor width between 3 microns and 15 microns.

18. The memory die of claim 11, wherein: A plurality of memory cells are electrically connected to the second pin pads of the memory die.

19. The memory die of claim 11, wherein: The first memory die also includes one or more pairs of pin pads, each pair of pin pads being separated by other conductor segments that electrically connect each pin pad in an associated pair of pin pads via conductor wire bonds.

20. A storage device, comprising: a substrate of a memory package, the substrate comprising means for electrically connecting a first pin pad of the memory package to a controller, thereby defining a data channel for data communication between at least the memory package and the controller; as well as A first memory die, the first memory die comprising: means for electrically connecting the front pin pads of the first memory die to the first pin pads of the substrate; as well as Means for electrically connecting the front and rear lead pads of the first memory die via conductor segments.

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