Silicon-based high-throughput single-molecule detection nanopore chip and preparation method

Abstract

The application belongs to the technical field of high-throughput sequencing sensors, and relates to a silicon-based high-throughput single-molecule detection nanopore chip and a preparation method thereof. The silicon-based high-throughput single-molecule detection nanopore chip comprises a silicon substrate, a nanopore array and a sample pool array. The nanopore array and the sample pool array are arranged on the upper surface and the lower surface of the silicon substrate respectively. The nanopore array comprises M*N nanopores. The sample pool array comprises a plurality of non-intercommunicating sample pools. The number of the sample pools corresponds to the number of the nanopores. Through holes corresponding to the number of the nanopores are arranged on the upper surface of the silicon substrate. The nanopores are in communication with the sample pools through the through holes. The application can realize low cost, portable use, multiple application scenarios, high sensitivity and high accuracy of the nanopore. A sequencer is developed by using the technology, and the development of the fourth-generation sequencing technology is promoted.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of high-throughput sequencing sensors, and relates to a nanopore chip and a preparation method, in particular to a silicon-based high-throughput single-molecule detection nanopore chip and a preparation method. BACKGROUND

[0002] The third-generation sequencing technology, i.e., single-molecule sequencing, has the characteristics of not needing PCR amplification of samples and being capable of realizing high-throughput sequencing, and is the main direction of future development of sequencing technology. The third-generation sequencing mainly has two core technologies: single-molecule fluorescent technology and single-molecule nanopore technology. The current mature nanopore technology adopts a biological pore, and utilizes a motor protein to drag a DNA single strand to pass through a nanopore protein and detect the current passing through the pore. The structure of the biological pore can be artificially designed and prepared by an artificial synthesis method. The advantage of the biological pore is that the pore diameter is small, the signal passing through the pore is more sensitive, and the bases of the single-stranded DNA can be directly recorded by the current passing through the pore. However, the biological pore also has many shortcomings, such as high production cost, uncontrollable pore diameter, the need for low-temperature storage of the biological pore chip, and extremely limited reuse times. Another developing nanopore technology is a solid-state pore, which utilizes an electric field to drive a charged DNA molecule to pass through a nanopore and detect the current passing through the pore. The solid-state pore is a semiconductor element, and a nanopore is opened on the semiconductor element by physical and chemical processing. Due to the controllability of the pore diameter, the chip can be designed for different biological molecules, and not only DNA and RNA, but also proteins and other biological macromolecules can be detected.

[0003] However, the limitations of the current solid-state pore are also very obvious. First, the design and use of the single-channel solid-state pore tend to be mature, but as the sequencing scale expands, the speed of a single channel is limited and cannot meet the demand. The design of multiple channels can effectively solve this demand, but due to the design scheme, use process and processing conditions, a series of problems are generated in the application, including but not limited to: 1) in the manufacturing process, the size and shape of the nanopore of each channel are different; 2) there is signal interference between the channels; 3) as the number of channels increases, the heat dissipation problem becomes more prominent, affecting the accuracy and shortening the service life. Secondly, due to the limitations of integration, heat dissipation treatment and process level, most solid-state pores adopt a single-electrode structure, which has limitations in the detection of the electrical property change of the signal detection and the molecule passing through the nanopore. Since there is only one electrode, it cannot provide enough electric field to drive the molecule to pass through the nanopore, and the sensitivity is low when detecting small molecules. In addition, the traditional solid-state pore array does not have a dedicated external pad for the electrode, causing signal crosstalk between different channels, being unable to complete the independent control of a specific number of pore diameters, and being unable to accurately exclude faults when the molecule passes through the pore blockage. SUMMARY

[0004] Invention purposes: In view of the limitations and deficiencies of the prior art, the present application provides a silicon-based high-throughput single-molecule detection nanopore chip to solve the technical defects of the existing solid-state pore. At the same time, a preparation method of the silicon-based high-throughput single-molecule detection nanopore chip is provided to realize low-cost, portable use, multiple application scenarios, high sensitivity, and high accuracy of the nanopore. The technology is used to develop a sequencer and promote the development of the fourth-generation sequencing technology.

[0005] Technical scheme: In order to achieve the above-mentioned purpose, the present application adopts the following technical scheme: a silicon-based high-throughput single-molecule detection nanopore chip, comprising a silicon substrate, a nanopore array and a sample pool array; the nanopore array and the sample pool array are respectively arranged on the upper surface and the lower surface of the silicon substrate; the nanopore array comprises MxN nanopores; the sample pool array comprises a plurality of non-interconnected sample pools; the number of sample pools corresponds to the number of nanopores; the silicon substrate is provided with through holes corresponding to the number of nanopores; the nanopores are in communication with the sample pools through the through holes.

[0006] Wherein, M represents a number consistent with the number of rows of the matrix; N represents a number consistent with the number of columns of the matrix; MxN, that is, represents MxN nanopores.

[0007] Preferably, the silicon-based high-throughput single-molecule detection nanopore chip adopted by the present application comprises a nanopore forming unit group, the nanopore forming unit group comprises a plurality of nanopore forming units, and the plurality of nanopore forming units are arranged on the upper surface of the silicon substrate in a matrix manner; each nanopore forming unit is provided with nanopores of the same structure, and the nanopores on the plurality of nanopore forming units form a nanopore array together.

[0008] Preferably, the nanopore forming units adopted by the present application are of the same structure.

[0009] Preferably, the nanopore forming unit adopted by the present application comprises a Si3N4 passivation layer, an upper Pt electrode layer, a Si3N4 insulation layer and a lower Pt electrode layer arranged on the silicon substrate in sequence from top to bottom; the nanopore penetrates the Si3N4 passivation layer, the upper Pt electrode layer, the Si3N4 insulation layer and the lower Pt electrode layer in sequence.

[0010] Preferably, the lower Pt electrode layer adopted by the present application comprises a lower Pt electrode, a lower Pt wire and a lower Pt electrode interface; the lower Pt electrode interface is connected with the lower Pt electrode through the lower Pt wire; the lower Pt electrode is in the form of a whole disc; and the nanopore is arranged along the center of the lower Pt electrode.

[0011] Preferably, the lower Pt electrode interfaces of each nanometer through hole forming unit in the nanometer through hole forming unit group used in the present application are arranged on the same side of the lower Pt electrode or oppositely arranged on both sides of the lower Pt electrode.

[0012] Preferably, the structure of the upper Pt electrode layer used in the present application is completely same as that of the lower Pt electrode layer.

[0013] Preferably, the nanometer through hole array used in the present application includes 2*2 nanometer through holes.

[0014] Preferably, the aperture of the nanometer through hole used in the present application is not greater than 50 nm.

[0015] A preparation method for preparing the silicon-based high-throughput single molecule detection nanometer hole chip as described above, the preparation method comprising the following steps:

[0016] 1) sputtering depositing 100-300 nm thick Pt on the silicon substrate, coating photoresist, exposing, developing, and etching Pt to form a lower Pt electrode layer;

[0017] 2) on the substrate obtained in step 1), growing a 50-100 nm thick Si3N4 layer by chemical vapor deposition process, and photoetching Si3N4 to form a Si3N4 insulation layer;

[0018] 3) on the substrate obtained in step 2), sputtering depositing 100-300 nm thick Pt, coating photoresist, exposing, developing, and etching Pt to form an upper Pt electrode layer;

[0019] 4) on the substrate obtained in step 3), growing a 50-100 nm thick Si3N4 layer by chemical vapor deposition process, and photoetching Si3N4 to form a Si3N4 passivation layer;

[0020] 5) on the substrate obtained in step 4), using electron beam lithography process to etch a nanometer through hole at the center of the upper Pt electrode layer, which penetrates the Si3N4 passivation layer, the upper Pt electrode layer, the Si3N4 insulation layer and the lower Pt electrode layer from top to bottom, and the aperture of the nanometer through hole is not greater than 50 nm;

[0021] 6) coating photoresist on the back of the substrate obtained in step 5), exposing, developing, and etching the silicon substrate by deep reactive ion etching process, leaving a silicon substrate about 50±5 μm thick;

[0022] 7) isotropic etching in HNA solution to etch away the silicon substrate about 50±5 μm thick left in step 6), forming a silicon-based high-throughput single molecule detection nanometer hole chip.

[0023] The present application has the following advantages:

[0024] The nanopore chip of the present application is prepared based on a silicon-based semiconductor process, and has low production cost; compared with traditional biological pore chips, it can be stored at room temperature; and it can be repeatedly used multiple times. The nanopore chip of the present application has controllable pore diameter and pore number, and through strict control of the design scheme and processing technology, the demand for high-throughput sequencing can be met. The nanopore chip of the present application adopts a double-electrode structure, and through accurate control of the electrode potential, selective response to specific ions is realized, and the electrochemical environment of the electrode interface is effectively controlled and adjusted; at the same time, a stable and uniform electric field is provided, noise is reduced, and the voltage value can also be freely adjusted according to needs, and the speed of the macromolecule through-hole is selected. The double-electrode system can balance the charge transfer between the electrodes, reduce the potential fluctuation caused by the change of the electrode surface state, and ensure the stability and reproducibility of the sensor, which is particularly important for repeated use and high-precision application. The nanopore chip of the present application designs efficient metal wiring and exclusive external pads for each metal electrode, and through the exclusive pads, voltage can be applied to each pore and signals can be read, so that more fine control and operation are realized. At the same time, it is helpful to isolate the signal paths of each channel and reduce the electromagnetic interference between different channels. By optimizing the pad layout and the distance between the pores, crosstalk can be further reduced, and the signal-to-noise ratio of the system can be improved. In combination with the design of specific voltage waveforms and current detection strategies, better control can be provided when the molecule passes through the nanopore, and the possibility of molecule blockage can be reduced. When blockage occurs, the voltage on the exclusive pad can be adjusted to try to remove the blocked molecule and restore the function of the nanopore. The design of the exclusive pad enables each channel to be independently connected to the external circuit, which is helpful for the integration and expansion of the system. When more channels need to be added or the system needs to be upgraded in the future, this design provides greater flexibility. When a nanopore in the system fails, the problem channel can be quickly located and repaired or replaced individually, without affecting the operation of the entire system. The present application has the characteristics of high sequencing stability, high sequencing throughput, miniaturization and low cost. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 is a longitudinal sectional view of the silicon-based high-throughput single-molecule detection nanopore chip provided by the present application;

[0026] Figure 2 is a structure diagram of a lower Pt electrode layer of a single-sided layout method adopted by the present application;

[0027] Figure 3 is a structure diagram of an upper Pt electrode layer of a single-sided layout method adopted by the present application;

[0028] Figure 4 is a top view of the overall structure of the single-sided layout method adopted by the present application;

[0029] Figure 5 is the structure diagram of the upper Pt electrode layer and the lower Pt electrode layer of the double-sided layout adopted by the present application;

[0030] Figure 6 is the overall structure top view of the double-sided layout adopted by the present application;

[0031] Figure 7 is the schematic diagram of the nanopore structure adopted by the present application;

[0032] wherein:

[0033] 1-silicon substrate; 2-lower Pt electrode layer; 3-Si3N4 insulating layer; 4-upper Pt electrode layer, 5-sample pool array; 6-nanopore array; 7-Si3N4 passivation layer. DETAILED DESCRIPTION

[0034] The present application provides a silicon-based high-throughput single molecule detection nanopore chip, which comprises a silicon substrate 1, a nanopore array 6 and a sample pool array 5; the nanopore array 6 and the sample pool array 5 are respectively arranged on the upper surface and the lower surface of the silicon substrate 1; the nanopore array 6 comprises MxN nanopores; the sample pool array 5 comprises a plurality of non-intercommunicating sample pools; the number of sample pools corresponds to the number of nanopores; a plurality of through holes corresponding to the number of nanopores are arranged on the upper surface of the silicon substrate 1; the nanopores are in communication with the sample pools through the through holes. M rows*N columns

[0035] The silicon-based high-throughput single molecule detection nanopore chip comprises a nanopore forming unit group, the nanopore forming unit group comprises a plurality of nanopore forming units, and the plurality of nanopore forming units are arranged on the upper surface of the silicon substrate 1 in a matrix manner; each nanopore forming unit is provided with nanopores of the same structure, and the nanopores on the plurality of nanopore forming units form the nanopore array 6 together. The nanopore forming units adopted by the present application have the same structure, and exemplarily, the nanopore forming unit comprises a Si3N4 passivation layer 7, an upper Pt electrode layer 4, a Si3N4 insulating layer 3 and a lower Pt electrode layer 2 arranged on the silicon substrate 1 in turn from top to bottom; the nanopore penetrates the Si3N4 passivation layer 7, the upper Pt electrode layer 4, the Si3N4 insulating layer 3 and the lower Pt electrode layer 2 in turn. The lower Pt electrode layer 2 comprises a lower Pt electrode, a lower Pt wire and a lower Pt electrode interface; the lower Pt electrode interface is connected to the lower Pt electrode through the lower Pt wire; the lower Pt electrode has a whole disc shape; the nanopore is arranged along the center of the lower Pt electrode. The lower Pt electrode interfaces of each nanopore forming unit in the nanopore forming unit group are arranged on the same side of the lower Pt electrode, or are oppositely arranged on both sides of the lower Pt electrode. The structure of the upper Pt electrode layer 4 is the same as that of the lower Pt electrode layer 2.

[0036] The working principle of the high-throughput single-molecule detection nanopore chip is introduced by taking a single-sided layout as an example. When the biological macromolecule passes through the nanopore from the horizontal direction, the chip adopts a single-sided layout, and the chip is vertically placed in the sample liquid. The lower Pt electrode interface and the upper Pt electrode interface are designed on one side of the chip, and in use, the side above the liquid surface. The passing-through current in the nanopore can be detected through the upper Pt electrode and the lower Pt electrode on both sides of the nanopore, so as to analyze the passing-through electric signal generated by the molecule to be detected when passing through the nanopore. The single-sided layout places the lower Pt electrode interface and the upper Pt electrode interface on the upper side of the sample liquid, avoiding the problems of short circuit and rapid structural consumption caused by liquid corrosion and penetration. At the same time, the upper Pt electrode interface and the lower Pt electrode interface are placed in the same area, which is convenient for integrated design and maintenance of functional partition. The double-sided layout is applied to the vertical passing-through of biological molecules, and the principle is similar to that of the single-sided layout. By increasing the number of nanopores, the integration of the chip is improved, and the chip can be applied to larger-scale sequencing.

[0037] In the following, the technical solutions provided by the present application will be described in detail by taking a 2*2 nanopore array 6 as an example and in combination with the corresponding drawings:

[0038] As shown in Figure 1 , the present application provides a silicon-based high-throughput single-molecule detection nanopore chip, which comprises a silicon substrate 1, a lower Pt electrode layer 2, a Si3N4 insulating layer 3, an upper Pt electrode layer 4, and a Si3N4 passivation layer 7 from bottom to top. The nanopore array 6 includes four identical nanopores, which are located at the center of the upper Pt electrode layer 4, have a pore diameter of less than 50 nm, and penetrate through the Si3N4 passivation layer 7, the upper Pt electrode layer 4, the Si3N4 insulating layer 3, and the lower Pt electrode layer 2. The sample cell array 5 includes four identical and non-interconnected sample cells, which are located on the back of the silicon substrate 1 and penetrate to the lower surface of the lower Pt electrode layer 2, and are located directly below the nanopore array 6.

[0039] Referring to Figure 2 , the lower Pt electrode layer 2 includes four lower Pt electrodes, a lower Pt wire, and four lower Pt electrode interfaces. Each lower Pt electrode is connected to the corresponding lower Pt electrode interface through the lower Pt wire. The four lower Pt electrodes have equal areas and thicknesses and are not connected to each other, and the whole presents a 2*2 square array distribution, and the distances between the vertically and horizontally adjacent lower Pt electrodes are equal. The lower Pt electrode is in the form of a regular disc, so as to facilitate effective reading of the passing-through signal and reduce signal errors caused by irregularities of the electrode itself. The lower Pt wire is arranged in parallel, the corner of the wire is 90 degrees, and any two wires do not cross. The four lower Pt electrode interfaces have the same size and are isolated from each other. According to the vertical or horizontal placement direction of the chip in the sample liquid, the layout mode of the lower Pt wire and the lower Pt electrode interface has two modes of single-sided layout and double-sided layout.

[0040] Referring to Figure 5 When the chip is vertically placed, a single-sided layout scheme is adopted. The lower Pt electrode interfaces are located on the vertical upper side of the lower Pt electrodes and are on the same horizontal line. The four lower Pt electrode interfaces are connected to the lower left electrode, the upper left electrode, the upper right electrode, and the lower right electrode of the lower Pt electrodes from left to right, respectively. Referring to Figure 6 When the chip is horizontally placed, a double-sided layout scheme is adopted, and the lower Pt electrode interfaces are located on the upper and lower sides of the lower Pt electrodes.

[0041] Referring to Figure 1 The Si3N4 insulating layer 3 uniformly covers the upper and side of the lower Pt electrode layer 2 and the surface of the silicon substrate 1 where the lower Pt electrode layer 2 is not formed, completely isolating the lower Pt electrode layer 2 from the air.

[0042] As shown in Figure 3 The upper Pt electrode layer 4 includes four upper Pt electrodes, upper Pt wires, and four upper Pt electrode interfaces. Each upper Pt electrode is connected to the corresponding upper Pt electrode interface through the upper Pt wire. The size and thickness of the upper Pt electrode are exactly the same as those of the lower Pt electrode, and the circuit duality is ensured through the manufacturing process to improve the accuracy of sequencing. The upper Pt wires are arranged in parallel, with a 90-degree corner and no intersection between any two wires. The four upper Pt electrode interfaces are the same size and isolated from each other. According to the vertical or horizontal placement direction of the chip in the sample liquid, the layout of the upper Pt wire and the upper Pt electrode interface also has a single-sided layout and a double-sided layout, which matches the layout of the lower Pt electrode interface and the lower Pt wire.

[0043] As shown in Figure 4 , Figure 5 and Figure 6 When the chip is vertically placed, a single-sided layout scheme is adopted. The upper Pt electrode interfaces are all located on the vertical upper side of the upper Pt electrodes and are connected to the lower left electrode, the upper left electrode, the upper right electrode, and the lower right electrode of the upper Pt electrodes from left to right, respectively. The upper Pt electrode interfaces and the lower Pt electrode interfaces are located on the same straight line and symmetrically distributed on the left and right sides. When the chip is horizontally placed, a double-sided layout scheme is adopted. The upper Pt electrode interfaces are located on the upper and lower sides of the upper Pt electrodes. The upper Pt electrode interfaces and the lower Pt electrode interfaces are symmetrically distributed as a whole.

[0044] The preparation method of the above-mentioned silicon-based high-throughput single-molecule detection nanopore chip includes:

[0045] Step 1: Deposit a layer of 100-300 nm thick Pt on the silicon substrate 1 by sputtering or other methods, coat photoresist, expose, develop, and etch Pt to form the lower Pt electrode layer 2.

[0046] Step 2: A 50-100 nm thick Si3N4 layer is grown on the substrate obtained in Step 1 by a process such as chemical vapor deposition, and the Si3N4 is photoetched to form a Si3N4 insulating layer 3.

[0047] Step 3: A 100-300 nm thick Pt layer is deposited on the substrate obtained in Step 2 by sputtering or the like, photoresist is applied, exposed, developed, and the Pt is etched to form an upper Pt electrode layer 4.

[0048] Step 4: A 50-100 nm thick Si3N4 layer is grown on the substrate obtained in Step 3 by a process such as chemical vapor deposition, and the Si3N4 is photoetched to form a Si3N4 passivation layer 7.

[0049] Step 5: A via is etched in the center of the four upper Pt electrodes on the substrate obtained in Step 4 by an electron beam lithography process, and the via penetrates the Si3N4 passivation layer 7, the upper Pt electrode layer 4, the Si3N4 insulating layer 3, and the lower Pt electrode layer 2 in that order from top to bottom, with a via aperture of less than 50 nm.

[0050] Step 6: Photoresist is applied to the back of the substrate obtained in Step 5, exposed, developed, and the silicon substrate 1 is etched by a deep reactive ion etching process to etch away about 350 μm of the silicon substrate 1, leaving about 50 μm of the silicon substrate 1;

[0051] Step 7: Isotropic etching is performed in an HNA solution to etch away the about 50 μm of the silicon substrate 1 left in Step 6, forming a silicon-based high-throughput single-molecule detection nanopore chip.

Claims

1. A silicon-based high-throughput single-molecule detection nanopore chip, characterized in that: The silicon-based high-throughput single-molecule detection nanoporous chip includes a silicon substrate (1), a nanoporous array (6), and a sample cell array (5); the nanoporous array (6) and the sample cell array (5) are respectively disposed on the upper and lower surfaces of the silicon substrate (1); the nanoporous array (6) includes M×N nanoporous holes; the sample cell array (5) includes multiple non-interconnected sample cells; the number of sample cells corresponds to the number of nanoporous holes; the silicon substrate (1) is provided with through holes corresponding to the number of nanoporous holes; the nanoporous holes are connected to the sample cells through the through holes; the nanoporous forming unit includes a Si3N4 passivation layer (7) and an upper Pt electrode disposed sequentially on the silicon substrate (1) from top to bottom. The structure consists of a layer (4), an upper Pt electrode layer (3), and a lower Pt electrode layer (2). The nano-vias sequentially penetrate the Si3N4 passivation layer (7), the upper Pt electrode layer (4), the Si3N4 insulating layer (3), and the lower Pt electrode layer (2). The lower Pt electrode layer (2) includes a lower Pt electrode, a lower Pt wire, and a lower Pt electrode interface. The lower Pt electrode interface is connected to the lower Pt electrode through the lower Pt wire. The lower Pt electrode is generally disk-shaped. The nano-vias are arranged along the center of the lower Pt electrode. The lower Pt electrode interface of each nano-via forming unit in the nano-via forming unit group is placed on the same side of the lower Pt electrode or opposite to each other on both sides of the lower Pt electrode.

2. The silicon-based high-throughput single-molecule detection nanopore chip according to claim 1, characterized in that: The silicon-based high-throughput single-molecule detection nanopore chip includes a nanopore forming unit group, which includes multiple nanopore forming units arranged in a matrix on the upper surface of a silicon substrate (1). Each nanopore forming unit has nanopores with identical structures, and the nanopores on multiple nanopore forming units together form a nanopore array (6).

3. The silicon-based high-throughput single-molecule detection nanopore chip according to claim 2, characterized in that: The structures of the nanopore forming units are completely identical.

4. The silicon-based high-throughput single-molecule detection nanopore chip according to claim 1, characterized in that: The structure of the upper Pt electrode layer (4) is exactly the same as that of the lower Pt electrode layer (2).

5. The silicon-based high-throughput single-molecule detection nanopore chip according to any one of claims 1-4, characterized in that: The nanopore array (6) includes 2×2 nanopores.

6. The silicon-based high-throughput single-molecule detection nanopore chip according to claim 5, characterized in that: The pore size of the nanopore is no greater than 50 nm.

7. A method for preparing a silicon-based high-throughput single-molecule detection nanoporous chip as described in claim 6, characterized in that: The preparation method includes the following steps: 1) A 100-300 nm thick Pt layer is sputtered and deposited on a silicon substrate (1), coated with photoresist, exposed, developed, and etched to form a lower Pt electrode layer (2). 2) On the substrate obtained in step 1), a 50-100 nm thick Si3N4 layer is grown by chemical vapor deposition, and Si3N4 is photolithographically formed to form a Si3N4 insulating layer (3). 3) On the substrate obtained in step 2), a 100-300 nm thick Pt layer is deposited by sputtering, coated with photoresist, exposed, developed, and etched to form an upper Pt electrode layer (4). 4) On the substrate obtained in step 3), a 50-100 nm thick Si3N4 layer is grown by chemical vapor deposition, and Si3N4 is photolithographically formed to form a Si3N4 passivation layer (7). 5) On the substrate obtained in step 4), a nano-through hole is etched at the center of the upper Pt electrode layer (4) using electron beam lithography. The nano-through hole passes through the Si3N4 passivation layer (7), the upper Pt electrode layer (4), the Si3N4 insulating layer (3), and the lower Pt electrode layer (2) from top to bottom. The diameter of the nano-through hole is no greater than 50 nm. 6) Coat the back of the substrate obtained in step 5) with photoresist, expose, develop, and etch the silicon substrate (1) by deep reactive ion etching process, leaving a silicon substrate (1) with a thickness of 50±5μm. 7) Isotropic etching is performed in the HNA solution to etch away the 50±5μm thick silicon substrate (1) retained in step 6) to form a silicon-based high-throughput single-molecule detection nanopore chip.

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