A hybrid storage and computing architecture of lithium niobate photonic chip and its implementation method

Abstract

The present invention discloses a hybrid storage and computing architecture of a lithium niobate photonic chip and an implementation method thereof. The architecture includes a lithium niobate optical path, a photoelectric conversion module, and a lithium niobate memristor storage and computing module. The lithium niobate optical path includes an optical coupling incident module, a cascade modulation module, an optical coupling output module, a first parallel waveguide, and a second parallel waveguide; high-frequency signal communication between the photoelectric conversion module and the memristor storage and computing module is achieved through the lithium niobate optical path. The interconnection of the present invention is based on integrated optics, which overcomes the difficulties of insufficient bandwidth and high thermal management cost of traditional electronic storage and computing chips; secondly, the present invention can be directly controlled by an optical switch in a waveguide without external electrical bias, and the chip storage and computing will only be limited by the switching speed (GHz) of the memristor. The present invention is suitable for parallel computing with low power consumption and high bandwidth requirements, such as machine learning reasoning and neural computing.

Description

Technical Field

[0001] The present invention relates to the technical field of optoelectronic integrated chips, and in particular to a hybrid storage and computing architecture of a lithium niobate photonic chip and an implementation method thereof. Background Art

[0002] At present, the mainstream storage-computing integrated technology is based on memristors. Although the non-gate-controlled cross-array of memristors is conducive to large-scale density integration and can perform computing and storage functions simultaneously, thus overcoming the inherent data transmission limitations of the separation of calculators and memories in traditional chip architectures, the high leakage current and working crosstalk of memristors make it demanding for large-scale interconnection and heat dissipation (Prezioso M, Merrikh-Bayat F, Hoskins BD, et al. Training and operation of an integrated neuromorphic network based on metal-oxide memristors[J]. Nature, 2015, 521(7550): 61-64.). At present, advanced integrated optics has natural advantages in ultra-low loss interconnection, heat dissipation, and bandwidth. Some photonic devices have demonstrated bandwidths exceeding 100 GHz, and data transmission power consumption is less than 100 fj / bit (Song MK, Kang JH, Zhang X, et al. Recent advances and future prospects for memristive materials, devices, and systems [J]. ACS nano, 2023, 17 (13): 11994-12039.). Optical-electrical hybrid integration is expected to enhance the performance of memristors. In addition, the energy properties of photons make it difficult to perform long-term storage. Hybrid integration based on high-speed photoelectric conversion will help high-density storage and reading of optical signals, providing a hardware foundation for high-speed storage and computing integrated chips (Xu R, Taheriniya S, Ovvyan AP, et al. Hybrid photonic integrated circuits for neuromorphic computing [J]. Optical Materials Express, 2023, 13 (12): 3553-3606.).

[0003] The relevant technologies are mainly divided into two parts, as follows:

[0004] First, memristor is a metastable device based on phase change, and multi-level storage needs to be achieved through external current limiting to control the strength of conductive filaments. The general solution is generally 1T1R, that is, one transistor controls the storage and computing state of a memristor, but the signal exchange between 1T-1R still causes information redundancy, thereby reducing the working speed of the entire chip. For optical signal transmission, the photoelectric conversion process will simplify the chip interface and reduce power consumption. 1P1R proposed the use of photodetectors to control memristor storage and computing (Peng H, Gan L, Guo X, et al. Memristor based Spiking Neural Networks: Cooperative Development of Neural Network Architecture / Algorithmsand Memristors[J]. Chip, 2024: 100093.), but the performance of the detector is currently far from matching the performance of the memristor, especially in terms of response speed (Huang B, Lei Z, Cao X, et al. High-quality two-dimensional tellurium flakes grown by high-temperature vapor deposition[J]. Journal of Materials Chemistry C, 2021, 9(40): 14394-14400.).

[0005] Second: non-volatile storage of photon integration. The advanced technical solution uses optical phase change materials and optical waveguides through evanescent wave coupling, and the phase change unit is prepared by low-temperature deposition heterogeneous integration. This solution has inherent defects: First, the phase change is a sudden metastable process. It is difficult to execute multi-level storage states without adding external control, and commercial memory requires at least 32 states (5 bits). Second, the storage state executed by the phase change cannot be erased by in-situ optical means, and electrical reset is required, which greatly limits the operating speed of the chip and cannot match the high-speed operation of the photonic chip (Zhou W, Dong B, Farmakidis N, et al. In-memory photonic dot-product engine with electrically programmable weight banks [J]. Nature Communications, 2023, 14 (1): 2887.).

[0006] In summary, there is no optimal solution in the design of new high-load storage and computing architectures for how to efficiently complement the advantages of the above two technologies, that is, how to apply integrated optical interconnection and optical manipulation to unleash the storage and computing speed of memristor chips. Summary of the invention

[0007] The purpose of the present invention is to provide a hybrid storage and computing architecture of a lithium niobate photonic chip and an implementation method thereof, so as to solve the hybrid integration problem of electrical memristors and integrated optics proposed in the above background technology.

[0008] The purpose of the present invention is achieved by at least one of the following technical solutions.

[0009] A hybrid storage and computing architecture of a lithium niobate photonic chip, including a lithium niobate optical path, a photoelectric conversion module and a memristor storage and computing module;

[0010] The lithium niobate optical path includes an optical coupling incident module, a cascade modulation module, an optical coupling output module, a first parallel waveguide and a second parallel waveguide;

[0011] The optical coupling input module includes an input grating coupler and a 1:1 beam splitter; the cascade modulation module includes a cascade Mach-Zehnder modulator; the optical coupling output module includes a beam combiner and an output grating coupler;

[0012] The two output ends of the 1:1 beam splitter are respectively connected to the two input ends of the cascaded Mach-Zehnder modulator, the two output ends of the cascaded Mach-Zehnder modulator are respectively connected to one end of the first parallel waveguide and the second parallel waveguide, and the other ends of the first parallel waveguide and the second parallel waveguide are respectively connected to the beam combiner;

[0013] The photoelectric conversion module includes a heterogeneously integrated photodetector, wherein gold-semi-contact electrodes at both ends of the photodetector are symmetrically arranged, and the coverage area of ​​the gold-semi-contact electrodes is located above the first parallel waveguide and the second parallel waveguide;

[0014] The memristor storage and computing module includes a lithium niobate memristor;

[0015] The photodetector is connected to a lithium niobate memristor;

[0016] The optical coupling incident module receives the optical signal to be processed, and the optical signal to be processed is coupled to the lithium niobate optical path through the incident grating coupler. The optical signal to be processed is divided into two coherent optical signals by a 1:1 beam splitter and sent to the cascade modulation module;

[0017] The two coherent optical signals are intensity modulated or switched by the electrical carrier of the cascaded Mach-Zehnder modulator, and the processed two coherent optical signals are parallelly introduced into the photoelectric conversion module through the first parallel waveguide and the second parallel waveguide respectively;

[0018] The optical signals in the first parallel waveguide and the second parallel waveguide are coupled into the gold-half contact region of the photodetector directly above by the evanescent wave. The photodetector generates electron-hole pairs based on the photoelectric effect according to the switching state of the coherent optical signals in the first parallel waveguide and the second parallel waveguide, and drives the gold-half potential barrier to separate and generate opposite photocurrents to realize the detection of the optical signals, thereby realizing XOR gate logic calculation.

[0019] The opposite photocurrent generated by the photodetector is input into the lithium niobate memristor, driving the lithium niobate memristor to switch the storage state, and the calculation result is stored in the lithium niobate memristor, realizing the high-speed processing and non-volatile storage function of optical signals;

[0020] The beam combiner combines the residual light in the first parallel waveguide and the second parallel waveguide that is not absorbed by the photodetector, and then outputs the lithium niobate optical path through the output grating coupler, thereby avoiding the influence of optical path reflection on system operation.

[0021] Furthermore, the cascaded Mach-Zehnder modulator comprises a first Mach-Zehnder modulator and a second Mach-Zehnder modulator cascaded in parallel; the first Mach-Zehnder modulator and the second Mach-Zehnder modulator both use push-pull traveling wave electrodes to apply carrier waves.

[0022] Further, the photoelectric conversion module covers the parallel first parallel waveguide and the second parallel waveguide;

[0023] The photodetector comprises a two-dimensional semiconductor single crystal channel and two symmetrically arranged metal electrodes; the two symmetrically arranged metal electrodes are deposited at two ends of the upper surface of the two-dimensional semiconductor single crystal channel, and are symmetrically distributed along the parallel midlines of the first parallel waveguide and the second parallel waveguide, and the first gold-semi-contact region and the second gold-semi-contact region formed at the two ends are completely identical;

[0024] The first parallel waveguide and the second parallel waveguide are located directly below the first gold-semi-contact region and the second gold-semi-contact region, respectively. The evanescent wave coupling region is between the first parallel waveguide and the second parallel waveguide and the two-dimensional semiconductor single crystal channel. The optical signals in the first parallel waveguide and the second parallel waveguide enter the first gold-semi-contact region and the second gold-semi-contact region of the photodetector directly above them by evanescent wave coupling.

[0025] Further, the lithium niobate memristor is placed on one side of the lithium niobate optical path, next to the first parallel waveguide;

[0026] The lithium niobate memristor includes a lithium niobate memristor channel, a first memristor electrode and a second memristor electrode. Different from the conventional vertical memristor structure, the lithium niobate memristor is a horizontal structure. The lithium niobate memristor channel is etched into a ridge shape, exposing electrode contact areas on both sides. The first memristor electrode and the second memristor electrode are respectively deposited on both sides of the ridge-shaped lithium niobate memristor channel. The lithium niobate memristor channel, the first memristor electrode and the second memristor electrode are horizontally distributed on the lithium niobate sheet.

[0027] A first memristor electrode and a second memristor electrode of the lithium niobate memristor are interconnected with metal electrodes at two ends of the photodetector respectively;

[0028] The resistance state in the lithium niobate memristor is controlled by the magnitude and direction of the photocurrent generated in the photodetector, thereby storing the calculation results of the photodetector.

[0029] Furthermore, the photodetector generates electron-hole pairs based on the photoelectric effect according to the switching state of the coherent optical signals in the first parallel waveguide and the second parallel waveguide, and generates opposite photocurrents driven by the gold-half-potential barrier to detect the optical signal, thereby realizing XOR gate logic calculation, as follows:

[0030] Different optical states in the first parallel waveguide and the second parallel waveguide are used to perform XOR gate logic calculation, that is, the photodetector does not generate photocurrent when the coherent optical signals in the first parallel waveguide and the second parallel waveguide are fully on or fully off, that is, the off state, and the photodetector generates photocurrent only when the coherent optical signals in the first parallel waveguide and the second parallel waveguide are in different optical states, that is, the on state;

[0031] When the coherent light signal in the first parallel waveguide is turned on and the coherent light signal in the second parallel waveguide is turned off, based on the photoelectric effect of evanescent wave coupling, the photodetector generates photogenerated electron-hole pairs on one side of the first parallel waveguide, and the contact potential barrier at the gold-half junction drives the electron-hole pairs to separate and generate photocurrent that enters the lithium niobate memristor; because the gold-half contact of the photodetector is symmetrical, a back-to-back potential barrier is formed, and when the coherent light signal in the second parallel waveguide is turned on and the coherent light signal in the first parallel waveguide is turned off, the photocurrent generated by the photodetector is opposite to the direction of the photocurrent generated by the photodetector when the coherent light signal in the first parallel waveguide is turned on and the coherent light signal in the second parallel waveguide is turned off, forming an exclusive-OR logic gate for calculation;

[0032] The photodetector operates without external voltage bias.

[0033] A method for implementing a hybrid storage and computing architecture of a lithium niobate photonic chip comprises the following steps:

[0034] S1. Manufacturing a lithium niobate optical path including a light coupling incident module, a cascade modulation module, a light coupling output module, a first parallel waveguide and a second parallel waveguide on a lithium niobate wafer;

[0035] S2, preparing a photodetector with symmetrically arranged metal electrodes on the first parallel waveguide and the second parallel waveguide;

[0036] S3, forming a vertical lithium niobate memristor by etching lithium niobate on one side of the lithium niobate optical path;

[0037] S4. Connect the photodetector and the lithium niobate memristor to achieve interconnection communication.

[0038] Further, the spacing between the first parallel waveguide and the second parallel waveguide is 10-15 um;

[0039] A photodetector with symmetrically arranged metal electrodes is prepared on the first parallel waveguide and the second parallel waveguide by van der Waals transfer or reactive ion etching;

[0040] The photodetector is made of a two-dimensional semiconductor single crystal channel made of a two-dimensional single crystal tellurium nanosheet, and the thickness of the tellurium nanosheet is 20~50nm;

[0041] The photodetector is prepared from Ti / Pt metal (Ti-based Pt plating) with two symmetrically arranged metal electrodes, so that the first gold-semi-contact area and the second gold-semi-contact area fully cover or semi-cover the first parallel waveguide or the second parallel waveguide.

[0042] Further, in step S3, a lithium niobate memristor is obtained by vertically etching downward on the X-cut lithium niobate, the etching depth is 300-600 nm, the width of the lithium niobate memristor is 20-100 nm, and the orientation of the lithium niobate memristor is the Z-cut direction;

[0043] In the lithium niobate memristor, the first electrode of the memristor is an ITO oxide metal electrode, and the second electrode of the memristor is prepared by etching synchronously with the first parallel waveguide and the second parallel waveguide in step S1, so as to realize one-step patterning.

[0044] Furthermore, in step S4, the gold-semi-contact electrode of the photodetector and two ends of the lithium niobate memristor are short-circuited with a copper metal wire to establish a loop.

[0045] Compared with the prior art, the beneficial effects of the present invention are as follows: a hybrid storage and computing architecture of a lithium niobate photonic chip and its implementation method are disclosed. First, the main interconnection of this architecture is based on integrated optics, which overcomes the difficulties of insufficient bandwidth and high thermal management cost of traditional electronic storage and computing chips; secondly, this architecture overcomes the field barriers of integrated optical non-volatile storage, combines optical interconnection with electrical storage and computing, and can be directly controlled and driven by the optical switch in the waveguide without external electrical bias. According to the current mainstream modulator bandwidth (>50GHz), photodetector bandwidth (>10GHz) and memristor manipulation speed (~1GHz), the architecture provides a highly feasible high-speed hybrid integrated storage and computing system. And based on the monolithic integrated design of lithium niobate, it is compatible with CMOS and has a simple heterogeneous integration process. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 Schematic diagram of the structure of a hybrid storage and computing architecture of a lithium niobate photonic chip in an embodiment of the present invention.

[0047] Figure 2 Schematic diagram of the structure of a cascaded Mach-Zehnder modulator in an embodiment of the present invention.

[0048] Figure 3 Schematic diagram of the structural relationship between the photodetector and the first parallel waveguide and the second parallel waveguide in an embodiment of the present invention.

[0049] Figure 4 Schematic diagram of multi-wavelength response photocurrent of the photodetector in an embodiment of the present invention.

[0050] Figure 5 Schematic diagram of the photocurrent response of the photodetector to a 1550nm communication light source pulse signal in an embodiment of the present invention.

[0051] Figure 6 Schematic diagram of the structure of a lithium niobate memristor in an embodiment of the present invention.

[0052] Figure 7 Schematic diagram of voltage scanning hysteresis curve of lithium niobate memristor in an embodiment of the present invention.

[0053] Figure 8 Schematic diagram of the cyclic switching stability of a lithium niobate memristor in an embodiment of the present invention.

[0054] Fig. 9 This is a flow chart of the operating method of a hybrid storage and computing architecture of a lithium niobate photonic chip in an embodiment of the present invention. DETAILED DESCRIPTION

[0055] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0056] Example:

[0057] A hybrid storage and computing architecture of lithium niobate photonic chips, such as Figure 1 and Fig. 9 As shown, it includes a lithium niobate optical path, a photoelectric conversion module 3 and a memristor storage and calculation module 4;

[0058] The lithium niobate optical path includes a light coupling incident module 1, a cascade modulation module 2, a light coupling output module 5, a first parallel waveguide 61 and a second parallel waveguide 62;

[0059] The optical coupling incident module 1 includes an incident grating coupler 11 and a 1:1 beam splitter 12; the cascade modulation module 2 includes a cascade Mach-Zehnder modulator 21; the optical coupling output module 5 includes a beam combiner 51 and an output grating coupler 52;

[0060] The two output ends of the 1:1 beam splitter 12 are respectively connected to the two input ends of the cascaded Mach-Zehnder modulator 21, the two output ends of the cascaded Mach-Zehnder modulator 21 are respectively connected to one end of the first parallel waveguide 61 and the second parallel waveguide 62, and the other ends of the first parallel waveguide 61 and the second parallel waveguide 62 are respectively connected to the beam combiner 51;

[0061] The photoelectric conversion module 3 includes a heterogeneously integrated photodetector 31, the gold-semi-contact electrodes at both ends of the photodetector 31 are symmetrically arranged, and the coverage area of ​​the gold-semi-contact electrodes is located above the first parallel waveguide 61 and the second parallel waveguide 62;

[0062] The memristor storage and computing module 4 includes a lithium niobate memristor 41;

[0063] The photodetector 31 is connected to the lithium niobate memristor 41;

[0064] The optical coupling incident module 1 receives the optical signal to be processed, and the optical signal to be processed is coupled to the lithium niobate optical path through the incident grating coupler 11 to achieve optical coupling, and the optical signal to be processed is divided into two coherent optical signals by the 1:1 beam splitter 12 and sent to the cascade modulation module 2;

[0065] The two coherent optical signals are intensity modulated or switch-controlled by the electrical carrier of the cascaded Mach-Zehnder modulator 21, respectively. The intensity modulation realizes optical modulation, and the switch control realizes event loading. The processed two coherent optical signals are parallelly introduced into the photoelectric conversion module 3 through the first parallel waveguide 61 and the second parallel waveguide 62 respectively.

[0066] The optical signal in the first parallel waveguide 61 and the second parallel waveguide 62 is coupled into the gold-half contact area of ​​the photodetector 31 directly above by the evanescent wave. The photodetector 31 generates electron-hole pairs based on the photoelectric effect according to the switching state of the coherent optical signal in the first parallel waveguide 61 and the second parallel waveguide 62, and drives the gold-half potential barrier to separate and generate opposite photocurrents to realize the detection of the optical signal, realize photoelectric detection, and then realize XOR gate logic calculation;

[0067] The opposite photocurrent generated by the photodetector 31 is input into the lithium niobate memristor 41, driving the lithium niobate memristor 41 to switch the storage state, and storing the calculated photocurrent in the lithium niobate memristor 41, so as to realize the high-speed processing and non-volatile storage function of the optical signal, and realize the electrical event input, event storage / calculation, and the output of the processed event based on the electrical interconnection;

[0068] The beam combiner 51 combines the residual light in the first parallel waveguide 61 and the second parallel waveguide 62 that is not absorbed by the photodetector 31, and then guides the residual light out of the lithium niobate optical path through the output grating coupler 52, thereby preventing the optical path reflection from affecting the operation of the system.

[0069] like Figure 2 As shown, the cascaded Mach-Zehnder modulator 21 includes a first Mach-Zehnder modulator 211 and a second Mach-Zehnder modulator 212 cascaded in parallel; the first Mach-Zehnder modulator 211 and the second Mach-Zehnder modulator 212 both use a push-pull traveling wave electrode 213 to apply a carrier.

[0070] like Figure 2 As shown, in one embodiment, the first Mach-Zehnder modulator 211 and the second Mach-Zehnder modulator 212 include a silicon substrate 217 with a thickness of 525 um, a silicon dioxide buried layer 216 with a thickness of 2 um, a lithium niobate core layer 215 with a thickness of 600 nm, a first parallel waveguide arm 218 and a second parallel waveguide arm 219 with a thickness of 300 nm, and a silicon dioxide cladding 214 with a thickness of 500 nm and a traveling wave electrode 213 with a thickness of 1 um that wrap the waveguide arms, which are stacked in sequence from bottom to top; the height and thickness are both measurements in the vertical direction in the figure, and the width and distance are both measurements in the horizontal direction in the figure.

[0071] The first parallel waveguide arm 218 and the second parallel waveguide arm 219 of the first Mach-Zehnder modulator 211 and the second Mach-Zehnder modulator 212 are prepared by etching the lithium niobate core layer 215, and the spacing between the first parallel waveguide arm 218 and the second parallel waveguide arm 219 is 29.5um, forming the basic optical structure of the second Mach-Zehnder modulator 212. The width of the first parallel waveguide arm 218 and the second parallel waveguide arm 219 are both 1um and the height is 300nm; the traveling wave electrode 213 is made of gold above the silicon dioxide cladding 214 of the first parallel waveguide arm 218 and the second parallel waveguide arm 219, and the thickness of the traveling wave electrode 213 is 1um. It is patterned at a horizontal distance of 5um between the first parallel waveguide arm 218 and the second parallel waveguide arm 219 through CMOS processes such as photolithography, coating, and stripping. The first Mach-Zehnder modulator 211 has the same structural composition as the cascaded second Mach-Zehnder modulator 212. The spacing between the first Mach-Zehnder modulator 211 and the second Mach-Zehnder modulator 212 is 90um. When opposite RF voltage signals (push-pull) are applied to the two arms of the modulator, an optical phase difference is generated in the first parallel waveguide arm 218 and the second parallel waveguide arm 219, so that interference enhancement or reduction occurs at the output. When the modulation extinction ratio exceeds 20dB, it is considered that the light on / off states are realized in the waveguide. A smaller photocurrent is formed under a lower extinction ratio and an intermediate storage state is formed. The first Mach-Zehnder modulator 211 and the second Mach-Zehnder modulator 212 can be used to adjust the light on / off in one waveguide at high frequency. The cascaded first Mach-Zehnder modulator 211 and the second Mach-Zehnder modulator 212 control the two rear-end first parallel waveguides 61 and the second parallel waveguide 62. The spacing between the first parallel waveguide 61 and the second parallel waveguide 62 is 15um. The photoelectric conversion module 3 covers the parallel first parallel waveguide 61 and the second parallel waveguide 62.

[0072] like Figure 3 As shown, the photodetector 31 includes a two-dimensional semiconductor single crystal channel 314 and two symmetrically arranged metal electrodes 311; the two symmetrically arranged metal electrodes 311 are deposited on both ends of the upper surface of the two-dimensional semiconductor single crystal channel 314, and are symmetrically distributed along the parallel midlines of the first parallel waveguide 61 and the second parallel waveguide 62, and the first gold-semi-contact area 312 and the second gold-semi-contact area 313 formed at the two ends are exactly the same.

[0073] The first parallel waveguide 61 and the second parallel waveguide 62 are located directly below the first gold-semi-contact region 312 and the second gold-semi-contact region 313 respectively, and the evanescent wave coupling region 315 is between the first parallel waveguide 61 and the second parallel waveguide 62 and the two-dimensional semiconductor single crystal channel 314; the optical signals in the first parallel waveguide 61 and the second parallel waveguide 62 enter the first gold-semi-contact region 312 and the second gold-semi-contact region 313 of the photodetector 31 directly above them respectively by evanescent wave coupling.

[0074] like Figure 1 As shown, the lithium niobate memristor 41 is placed on one side of the lithium niobate optical path, next to the first parallel waveguide 61 .

[0075] The cross section of the lithium niobate memristor 41 is shown in FIG. Figure 6 As shown, the lithium niobate memristor 41 comprises a lithium niobate memristor channel 411, a first memristor electrode 412 and a second memristor electrode 413; different from the conventional vertical memristor structure, the lithium niobate memristor (41) is a horizontal structure, the lithium niobate memristor channel 411 is etched into a ridge shape, exposing both sides as electrode contact areas, the first memristor electrode 412 and the second memristor electrode 413 are respectively deposited on both sides of the ridge-shaped lithium niobate memristor channel 411, and the lithium niobate memristor channel 411, the first memristor electrode 412 and the second memristor electrode 413 are horizontally distributed on the lithium niobate sheet.

[0076] The memristor first electrode 412 and the memristor second electrode 413 of the lithium niobate memristor 41 are respectively interconnected with the metal electrodes at both ends of the photodetector 31;

[0077] The resistance state in the lithium niobate memristor 41 is controlled by the magnitude and direction of the photocurrent generated in the photodetector 31 , thereby storing the calculation result of the photodetector 31 .

[0078] Lithium niobate vertically etched memristors have the following advantages:

[0079] The lithium niobate memristor 41 requires the dielectric film to have soft breakdown characteristics at a relatively low voltage (<10V), and is often required to have a thickness of tens of nanometers. However, it is difficult to prepare large-scale, high-quality lithium niobate films with a thickness of tens of nanometers by conventional ion slicing and wafer bonding. The preparation of vertical memristor arrays by photolithography and etching depends on the photolithography process, and the commonly used CMOS process can easily achieve a precision of tens of nanometers. The ideal width of the lithium niobate memristor 41 in the present invention should be less than 100nm, but is limited by the photolithography process in the present invention. This example demonstrates the performance of a 100nm wide lithium niobate memristor 41. Figure 7 and Figure 8 shown. Figure 7 Since the film thickness is larger than the ideal lithium niobate memristor 41, the on-state voltage is too high. However, the device still has an obvious storage window below 4V. Based on the nearly exponential physical relationship between the film width and the driving voltage, it is easy to foresee that reducing the lithium niobate film process to 50nm can achieve storage below 1V, thereby matching the open circuit voltage of the photodetector 31. Figure 8 As shown, the lithium niobate memristor 41 prepared in this example has an erase stability of more than 1000 times and a switching ratio of more than cubic. These properties can be used to execute a parallel storage and computing module based on a cross-array distributed memristor 41.

[0080] When working in the active state, the photogenerated carriers excited by the evanescent wave coupling assisted by the electrical bias control the memristor 41 to realize multi-level storage and calculation; more importantly, when the open circuit voltage matches the memristor read and write voltage, the device can work in the passive state, based on the rapid switching of the light state in the first parallel waveguide 61 and the second parallel waveguide 62, directly and quickly control the photocurrent direction of the photodetector 3, and then control the resistance state of the memristor storage and calculation module 4, while the input light signal can perform XOR gate logic calculation inside the photodetector 31 to reduce the channel requirements of the back-end computing module. Since the resistance state switching of the lithium niobate memristor 41 is non-volatile, the adjustable multi-level resistance state can be used for matrix calculation, and the stable resistance state can be used for non-volatile storage.

[0081] Further, the photodetector 31 generates electron-hole pairs based on the photoelectric effect according to the switching state of the coherent optical signals in the first parallel waveguide 61 and the second parallel waveguide 62, and generates opposite photocurrents driven by the gold-half-potential barrier to detect the optical signals, thereby realizing XOR gate logic calculation, as follows:

[0082] Different optical states in the first parallel waveguide 61 and the second parallel waveguide 62 are used to perform XOR gate logic calculations, that is, when the coherent optical signals in the first parallel waveguide 61 and the second parallel waveguide 62 are fully on or fully off, the photodetector 31 does not generate a photocurrent, that is, it is an off state. Only when the coherent optical signals in the first parallel waveguide 61 and the second parallel waveguide 62 are in different optical states, the photodetector 31 generates a photocurrent, that is, it is an on state.

[0083] When the coherent light signal in the first parallel waveguide 61 is turned on and the coherent light signal in the second parallel waveguide 62 is turned off, based on the photoelectric effect of evanescent wave coupling, the photodetector 31 generates photogenerated electron-hole pairs on one side of the first parallel waveguide 61, and the contact potential barrier at the gold-half junction drives the electron-hole pairs to separate and generate photocurrents that enter the lithium niobate memristor 41; since the gold-half contact of the photodetector 31 is symmetrical, back-to-back potential barriers are formed, and when the coherent light signal in the second parallel waveguide 62 is turned on and the coherent light signal in the first parallel waveguide 61 is turned off, the photocurrent generated by the photodetector 31 is opposite in direction to the photocurrent generated by the photodetector 31 when the coherent light signal in the first parallel waveguide 61 is turned on and the coherent light signal in the second parallel waveguide 62 is turned off, forming an XOR logic gate for calculation;

[0084] The photodetector 31 operates without external voltage bias.

[0085] In one embodiment, when the cascaded Mach-Zehnder modulator 21 controls the incident light signal in the first parallel waveguide 61, the light signal in the first parallel waveguide 61 is turned off. The first gold-semi-contact region 312 absorbs the light signal in the first parallel waveguide 61 through the evanescent wave coupling region 315, and generates electron-hole pairs through transition. The electron-hole pairs are driven by the built-in electric field. The specific electric field driving direction depends on the carriers formed by the barrier energy band. The electric field formed by the movement of the carriers is applied to both ends of the lithium niobate memristor 41. The accumulated electric field will drive the ions in the lithium niobate memristor 41 to form a conductive channel, so that the lithium niobate memristor 41 is turned on and presents a low resistance state. On the contrary, when the light signal in the first parallel waveguide 61 is turned off and the light signal in the first parallel waveguide 61 is incident, based on the fact that the second gold-semi-contact region 313 is opposite to the first gold-semi-contact region 312, the carriers will accumulate at the opposite ends of the lithium niobate memristor 41, driving it to close and present a high resistance state. The response performance of the photodetector 31 to the communication light is Figure 4-Figure 5 In the representation, from Figure 4 It can be seen that the tellurium two-dimensional single crystal as a two-dimensional semiconductor single crystal channel 314 can exhibit a photocurrent of more than microamperes over a very wide near-infrared band, which will make the storage and computing architecture proposed in the present invention not only limited to a single wavelength of 1550nm, but all C-band communication segments; and after the input of stimulation light, an open-circuit voltage is formed in the loop, which will drive the resistance state change of the lithium niobate memristor 41. Figure 5 The frequency response of the photodetector 31 to pulse incident light signals of different powers is shown in FIG. The different response photocurrents to different powers indicate good light intensity sensitivity, and the steep response rising and falling edges indicate that the photodetector 31 has the potential for high-speed photoelectric conversion.

[0086] A method for implementing a hybrid storage and computing architecture of a lithium niobate photonic chip comprises the following steps:

[0087] S1, manufacturing a lithium niobate optical path including a light coupling incident module 1, a cascade modulation module 2, a light coupling output module 5, a first parallel waveguide 61 and a second parallel waveguide 62 on a lithium niobate wafer;

[0088] In one embodiment, the spacing between the first parallel waveguide 61 and the second parallel waveguide 62 is 15 um;

[0089] S2. In one embodiment, a photodetector 31 with symmetrically arranged metal electrodes is prepared on the first parallel waveguide 61 and the second parallel waveguide 62 by van der Waals transfer or reactive ion etching;

[0090] In one embodiment, the photodetector 31 is made of a two-dimensional semiconductor single crystal channel 314 made of a two-dimensional single crystal tellurium nanosheet, and the thickness of the tellurium nanosheet is 40 nm;

[0091] The photodetector 31 is made of Ti / Pt metal (Ti-based Pt plating) with two symmetrically arranged metal electrodes 311 , so that the first gold-semi-contact area 312 and the second gold-semi-contact area 313 fully cover or semi-cover the first parallel waveguide 61 or the second parallel waveguide 62 .

[0092] S3, forming a vertical lithium niobate memristor 41 on one side of the lithium niobate optical path by etching lithium niobate;

[0093] In one embodiment, the lithium niobate memristor 41 is obtained by vertically etching downward on the X-cut lithium niobate, the etching depth is 500 nm, the width of the lithium niobate memristor 41 is 50 nm, and the orientation of the lithium niobate memristor 41 is the Z-cut direction;

[0094] In one embodiment, in the lithium niobate memristor 41 , the memristor first electrode 412 is an ITO oxide metal electrode, and the memristor second electrode 413 is a Ti / Pt metal electrode (Ti-based Pt-plated metal electrode).

[0095] In one embodiment, the lithium niobate memristor 41 is exposed using an electron beam lithography machine, and the lithium niobate optical circuit is exposed using a deep ultraviolet lithography machine to facilitate high-throughput production.

[0096] The lithium niobate memristor 41 in step S3 is prepared by etching simultaneously with the first parallel waveguide 61 and the second parallel waveguide 62 in step S1 to achieve one-step patterning.

[0097] S4, connecting the photodetector 31 and the lithium niobate memristor 41 to achieve interconnection communication;

[0098] In one embodiment, the gold-semi-contact electrode of the photodetector 31 and two ends of the lithium niobate memristor 41 are short-circuited by a copper metal wire to establish a loop.

[0099] Based on the above, the advantage of the present invention is that when used, the present invention overcomes the problem of non-volatile storage of photon states in integrated optics to a certain extent, and also alleviates the interconnection power consumption and thermal management problems of the memristor storage chip architecture to a certain extent. In particular, the on-chip light source driven storage architecture significantly improves the operational speed and compactness of the chip, and is expected to enable the speed of neural network chips based on in-detector computing and memristor storage to be accelerated to gigahertz by optical paths.

[0100] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A hybrid storage and computing architecture of a lithium niobate photonic chip, characterized by: The invention comprises a lithium niobate optical path, a photoelectric conversion module (3) and a memristor storage and calculation module (4); the lithium niobate optical path comprises an optical coupling incident module (1), a cascade modulation module (2), an optical coupling output module (5), a first parallel waveguide (61) and a second parallel waveguide (62); the optical coupling incident module (1) comprises an incident grating coupler (11) and a 1:1 beam splitter (12); the cascade modulation module (2) comprises a cascaded Mach-Zehnder modulator (21); the optical coupling output module (5) comprises a beam combiner (51) and an output grating coupler (52); two output ends of the 1:1 beam splitter (12) are respectively connected to two input ends of the cascaded Mach-Zehnder modulator (21); two output ends of the cascaded Mach-Zehnder modulator (21) are respectively connected to one end of the first parallel waveguide (61) and one end of the second parallel waveguide (62); and the other ends of the first parallel waveguide (61) and the second parallel waveguide (62) are respectively connected to the beam combiner (51); The photoelectric conversion module (3) comprises a heterogeneously integrated photodetector (31), the gold-semi-contact electrodes at both ends of the photodetector (31) are symmetrically arranged, and the coverage area of ​​the gold-semi-contact electrodes is located above the first parallel waveguide (61) and the second parallel waveguide (62); the memristor storage and computing module (4) comprises a lithium niobate memristor (41); the photodetector (31) is connected to the lithium niobate memristor (41); The optical coupling incident module (1) receives the optical signal to be processed, and the optical signal to be processed is coupled into the lithium niobate optical path through the incident grating coupler (11), and the optical signal to be processed is split into two coherent optical signals by the 1:1 beam splitter (12) and sent to the cascade modulation module (2); The two coherent optical signals are intensity modulated or switched by the electrical carrier of the cascaded Mach-Zehnder modulator (21), and the processed two coherent optical signals are parallelly introduced into the photoelectric conversion module (3) through the first parallel waveguide (61) and the second parallel waveguide (62); The optical signals in the first parallel waveguide (61) and the second parallel waveguide (62) are coupled into the gold-half contact region of the photodetector (31) directly above by evanescent wave coupling; the photodetector (31) generates electron-hole pairs based on the photoelectric effect according to the switching state of the coherent optical signals in the first parallel waveguide (61) and the second parallel waveguide (62), and drives the gold-half potential barrier to separate and generate opposite photocurrents to achieve optical signal detection, thereby achieving XOR gate logic calculation; the opposite photocurrents generated by the photodetector (31) are input into the lithium niobate memristor (41), driving the lithium niobate memristor (41) to switch the storage state, and storing the calculation results in the lithium niobate memristor (41); The beam combiner (51) combines the residual light in the first parallel waveguide (61) and the second parallel waveguide (62) that is not absorbed by the photodetector (31), and then outputs the residual light to the lithium niobate optical path through the output grating coupler (52).

2. The hybrid storage and computing architecture of a lithium niobate photonic chip according to claim 1, characterized in that: The cascaded Mach-Zehnder modulator (21) comprises a first Mach-Zehnder modulator (211) and a second Mach-Zehnder modulator (212) cascaded in parallel; the first Mach-Zehnder modulator (211) and the second Mach-Zehnder modulator (212) both use a push-pull traveling wave electrode (213) to apply a carrier.

3. The hybrid storage and computing architecture of a lithium niobate photonic chip according to claim 1, characterized in that: The photoelectric conversion module (3) covers the first parallel waveguide (61) and the second parallel waveguide (62) which are parallel to each other; The photodetector (31) comprises a two-dimensional semiconductor single crystal channel (314) and two symmetrically arranged metal electrodes (311); the two symmetrically arranged metal electrodes (311) are deposited on both ends of the upper surface of the two-dimensional semiconductor single crystal channel (314), and are symmetrically distributed along the parallel midlines of the first parallel waveguide (61) and the second parallel waveguide (62); the first gold-semi-contact region (312) and the second gold-semi-contact region (313) formed at the two ends are completely identical; The first parallel waveguide (61) and the second parallel waveguide (62) are respectively located directly below the first gold-semi-contact region (312) and the second gold-semi-contact region (313); an evanescent wave coupling region (315) is provided between the first parallel waveguide (61) and the second parallel waveguide (62) and the two-dimensional semiconductor single crystal channel (314); optical signals in the first parallel waveguide (61) and the second parallel waveguide (62) enter the first gold-semi-contact region (312) and the second gold-semi-contact region (313) of the photoelectric detector (31) directly above them respectively by evanescent wave coupling.

4. The hybrid storage and computing architecture of a lithium niobate photonic chip according to claim 3, characterized in that: The lithium niobate memristor (41) is placed on one side of the lithium niobate optical path, next to the first parallel waveguide (61); The lithium niobate memristor (41) comprises a lithium niobate memristor channel (411), a first memristor electrode (412) and a second memristor electrode (413); the lithium niobate memristor channel (411) is etched into a ridge shape, exposing two sides as electrode contact areas, the first memristor electrode (412) and the second memristor electrode (413) are respectively deposited on two sides of the ridge-shaped lithium niobate memristor channel (411), and the lithium niobate memristor channel (411), the first memristor electrode (412) and the second memristor electrode (413) are horizontally distributed on the lithium niobate sheet; A first memristor electrode (412) and a second memristor electrode (413) of the lithium niobate memristor (41) are respectively interconnected with metal electrodes at two ends of the photodetector (31); The resistance state in the lithium niobate memristor (41) is controlled by the magnitude and direction of the photocurrent generated in the photodetector (31), thereby storing the calculation result of the photodetector (31).

5. The hybrid storage and computing architecture of a lithium niobate photonic chip according to claim 3, characterized in that: The photodetector (31) generates electron-hole pairs based on the photoelectric effect according to the switching state of the coherent light signal in the first parallel waveguide (61) and the second parallel waveguide (62), and generates opposite photocurrents driven by the gold-half-potential barrier to detect the light signal, thereby realizing XOR gate logic calculation, as follows: Different optical states in the first parallel waveguide (61) and the second parallel waveguide (62) are used to perform XOR gate logic calculations, that is, when the coherent optical signals in the first parallel waveguide (61) and the second parallel waveguide (62) are fully on or fully off, the photodetector (31) does not generate a photocurrent, i.e., it is an off state; only when the coherent optical signals in the first parallel waveguide (61) and the second parallel waveguide (62) are in different optical states does the photodetector (31) generate a photocurrent, i.e., it is an on state; When the coherent light signal in the first parallel waveguide (61) is turned on and the coherent light signal in the second parallel waveguide (62) is turned off, based on the photoelectric effect of evanescent wave coupling, the photodetector (31) generates photogenerated electron-hole pairs on one side of the first parallel waveguide (61), and the contact potential barrier at the gold-half junction drives the electron-hole pairs to separate and generate photocurrents that enter the lithium niobate memristor (41); because the gold-half contacts of the photodetector (31) are symmetrical, back-to-back potential barriers are formed, and when the coherent light signal in the second parallel waveguide (62) is turned on and the coherent light signal in the first parallel waveguide (61) is turned off, the photocurrent generated by the photodetector (31) is opposite in direction to the photocurrent generated by the photodetector (31) when the coherent light signal in the first parallel waveguide (61) is turned on and the coherent light signal in the second parallel waveguide (62) is turned off, forming an exclusive-OR logic gate for calculation; The photodetector (31) operates without external voltage bias.

6. A method for implementing a hybrid storage and computing architecture of a lithium niobate photonic chip according to any one of claims 1 to 5, characterized in that: The steps include: S1. Manufacturing a lithium niobate optical path including a light coupling input module (1), a cascade modulation module (2), a light coupling output module (5), a first parallel waveguide (61), and a second parallel waveguide (62) on a lithium niobate sheet; S2, preparing a photodetector (31) with symmetrically arranged metal electrodes on the first parallel waveguide (61) and the second parallel waveguide (62); S3, forming a vertical lithium niobate memristor (41) by etching lithium niobate on one side of the lithium niobate optical path; S4, connecting the photodetector (31) and the lithium niobate memristor (41) to achieve interconnection communication.

7. The method for implementing a hybrid storage and computing architecture of a lithium niobate photonic chip according to claim 6, characterized in that: The spacing between the first parallel waveguide (61) and the second parallel waveguide (62) is 10-15 um; A photodetector (31) having symmetrically arranged metal electrodes is prepared on the first parallel waveguide (61) and the second parallel waveguide (62) by van der Waals transfer or reactive ion etching; The photodetector (31) is made of a two-dimensional single crystal tellurium nanosheet to prepare a two-dimensional semiconductor single crystal channel (314), wherein the tellurium nanosheet has a thickness of 20 to 50 nm; The photodetector (31) is made of Ti / Pt metal to form two symmetrically arranged metal electrodes (311), so that the formed first gold-semi-contact area (312) and the second gold-semi-contact area (313) fully cover or semi-cover the first parallel waveguide (61) or the second parallel waveguide (62).

8. The method for implementing a hybrid storage and computing architecture of a lithium niobate photonic chip according to claim 6, characterized in that: In step S3, a lithium niobate memristor (41) is obtained by vertically etching downward on X-cut lithium niobate, the etching depth is 300-600 nm, the width of the lithium niobate memristor (41) is 20-100 nm, and the orientation of the lithium niobate memristor (41) is in the Z-cut direction; In the lithium niobate memristor (41), the first electrode (412) of the memristor is an ITO oxide metal electrode, and the second electrode (413) of the memristor is a Ti-based Pt-plated metal electrode.

9. The method for implementing a hybrid storage and computing architecture of a lithium niobate photonic chip according to claim 6, characterized in that: The lithium niobate memristor (41) in step S3 is prepared by etching simultaneously with the first parallel waveguide (61) and the second parallel waveguide (62) in step S1, thereby achieving one-step patterning.

10. The method for implementing a hybrid storage and computing architecture of a lithium niobate photonic chip according to claim 6, characterized in that: In step S4, the gold-semi-contact electrode of the photodetector (31) and the two ends of the lithium niobate memristor (41) are short-circuited using a copper metal wire to establish a loop.

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