Critical timing driven adaptive voltage frequency regulation

Abstract

The invention relates to adaptive voltage frequency regulation for critical timing driving. An example method of adjustable voltage frequency adjustment for critical timing driving may include performing a plurality of sensing operations on a system-on-chip (SoC) at a respective plurality of time windows, each associated with a particular data value; comparing at least two of the particular data values associated with at least two respective time windows of the plurality of time windows; in response to the at least two of the particular data values being the same data value, determining that a clock margin is higher than a threshold clock margin; and in response to the at least two of the particular data values being different data values, determining that a clock margin is below a threshold clock margin. In some cases, in response to determining that the clock margin is above a threshold clock margin, timing of the SoC may be adjusted, a voltage of at least one operation of the SoC, and / or a timing frequency of at least one operation of the SoC may be adjusted, among other possibilities.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to critical timing driven adaptive voltage frequency scaling (AVFS). Background Art

[0002] Various types of electronic devices, such as digital logic circuits and memory systems, can store and process data. A digital logic circuit is an electronic circuit that processes digital signals or binary information that can take two possible values ​​(usually represented as 0 and 1). A digital logic circuit can use logic gates to manipulate and transform digital signals or binary information. Digital logic circuits can be used, for example, in a wide range of electronic devices including computers, calculators, digital clocks, and many other electronic devices that employ digital processing. Digital logic circuits can be designed to perform specific logic operations on digital inputs to produce digital outputs, and in some cases, can be combined to form more complex circuits to perform more complex operations. In general, power supply, voltage control, and / or clock control can change voltage or frequency during the operation of digital logic. A memory device may include one or more memory devices that store data. A memory device may be, for example, a nonvolatile memory device and a volatile memory device. In general, a host system can utilize a memory system to store data at a memory device and retrieve data from a memory device. Summary of the invention

[0003] On the one hand, the present disclosure provides a method for adaptive voltage frequency regulation, comprising: performing multiple sensing operations on a system on a chip (SoC) at corresponding multiple time windows, wherein each time window of the multiple time windows is associated with a specific data value; comparing at least two of the specific data values ​​associated with at least two corresponding time windows of the multiple time windows; in response to the at least two of the specific data values ​​being the same data value, determining that the clock margin is higher than a threshold clock margin; and in response to the at least two of the specific data values ​​being different data values, determining that the clock margin is lower than a threshold clock margin.

[0004] On the other hand, the present disclosure provides a device for adaptive voltage and frequency regulation, comprising: a controller configured to: perform multiple sensing operations on a system on a chip (SoC) at corresponding multiple time windows, wherein each time window of the multiple time windows is associated with a specific data value; compare at least two of the specific data values ​​associated with at least two corresponding time windows of the multiple time windows; determine that a clock margin is higher than a threshold clock margin in response to the at least two of the specific data values ​​being the same data value; and determine that the clock margin is lower than a threshold clock margin in response to the at least two of the specific data values ​​being different data values.

[0005] On the other hand, the present disclosure provides an apparatus for adaptive voltage-frequency regulation, comprising: a controller; a voltage control component coupled to the controller; and a clock control component coupled to the controller; wherein the controller is configured to: perform multiple sensing operations on a system on a chip (SoC) at corresponding multiple time windows, wherein each time window in the multiple time windows is associated with a specific data value; compare at least two of the specific data values ​​associated with at least two corresponding time windows in the multiple time windows; in response to the at least two of the specific data values ​​being the same data value, determine that the clock margin is higher than a threshold clock margin and perform remedial measures; and in response to the at least two of the specific data values ​​being different data values, determine that the clock margin is lower than a threshold clock margin and perform remedial measures. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description provided below and the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example system for adjustable voltage-frequency regulation for critical timing driving according to some embodiments of the present disclosure is shown.

[0008] Figure 2A-2B Each shows an example system for adjustable voltage-frequency regulation for critical timing driving according to some embodiments of the present disclosure.

[0009] Figure 3A-3B An example system including sensors for adjustable voltage-frequency regulation of critical timing drives according to some embodiments of the present disclosure is shown.

[0010] Figure 4-7 Each shows an example timing diagram of adjustable voltage-frequency regulation for critical timing driving according to some embodiments of the present disclosure.

[0011] Figure 8 An example system including sensors for adjustable voltage-frequency regulation of critical timing drives according to some embodiments of the present disclosure is shown.

[0012] Fig. 9 An example method of adjustable voltage-frequency regulation for critical timing driving according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0013] Aspects of the present disclosure relate to adaptive voltage frequency scaling (AVFS) driven by critical timing. As will be described below, several sensors can be used to monitor critical timing. The monitored time associated with the critical timing path of the circuit can be used to adjust the voltage and / or frequency to ensure that the circuit functions as expected. For example, the sensor can be set to arrive earlier or later to determine the state of data at a specific location within a data storage element, such as a flip-flop, a latch, etc., of a system on a chip (SoC) before and / or after a functionally critical endpoint, where the data is actually sampled from the location at the functionally critical endpoint. In this way, the clock frequency can be adjusted to avoid excessive margin and still provide sufficient margin to avoid errors. Clock margin, such as a clock margin that is specifically higher than a threshold clock margin, can be used to ensure that accurate data is sampled from the location. For example, the clock frequency of at least one operation of the SoC can be adjusted in response to determining that the clock margin is higher than a threshold clock margin. In one example, the voltage and / or timing frequency of at least one operation of the SoC can be adjusted in response to determining that the clock margin is higher than a threshold clock margin.

[0014] Voltage and frequency scaling (VFS) can be used to match system power consumption with desired performance. The workload associated with a system (e.g., a computing system) can be monitored to determine settings for voltage and clock speed, and the hardware of the system can be appropriately configured. Dynamic voltage and frequency scaling (DVFS) is a technique that aims to reduce the power consumption of a system or improve system performance by dynamically adjusting the voltage and frequency of the system. This can take advantage of the fact that systems typically have discrete frequency and voltage settings. Dynamic voltage regulation to increase voltage can be referred to as overvolting, while dynamic voltage regulation to reduce voltage can be referred to as undervolting. Undervolting can be performed to save power, particularly in laptops and other mobile devices where energy comes from batteries and is therefore limited, or in rare cases to increase reliability. Overvolting can be performed to support higher frequencies for performance. The term "overvolting" can also be used to refer to increasing the static operating voltage of a component to allow operation at a higher speed (e.g., when overvolted).

[0015] The voltage and frequency applied to the various components of the systems described herein may be dynamically adjusted based on the desired power and performance associated with the voltage, frequency, and / or temperature data (in addition to other parameters, if monitored) collected during a monitoring operation (e.g., an AC (or full speed) sweep operation, or other data collection and / or monitoring operation), and / or through dedicated embedded monitors, built-in self-tests (BIST), or some tables compiled using modeling and / or characterization, and other means. The voltage, frequency, and / or temperature data of the monitoring operation (e.g., AC sweep or other monitoring operation) may collect a large portion of the measured data of the system and provide a more accurate way to adjust the voltage and frequency for regulation. For example, measured data may refer to data that is not from a simulation but from an actual sweep and is not extrapolated. Therefore, voltage frequency regulation may provide benefits in systems that rely on instantaneous (or near instantaneous) changes in the voltage, frequency, and temperature of the system (e.g., an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), an automated power management system, etc.), where each parameter may affect one of the other parameters.

[0016] In some previous approaches, a clock frequency or period using an excessive margin (e.g., an excessive clock margin) can be used to avoid sampling incorrect data from a location in the SoC, where the excessive clock margin refers to a slower clock or a clock with a longer period. For example, if the length of the clock period is sufficient to cover the propagation time of the data from the starting point (e.g., the rising edge of the clock) to the end point (e.g., the rising edge of the subsequent clock) and some clock margin, then the data will be accurate when sampled. However, excessive clock margin can affect system performance by introducing excessive time that is not required to provide accurate data. Compared to these previous approaches, the methods and systems described herein attempt to compensate for the shortcomings of the previous approaches by using several sensors to sense the time for data to propagate to the location, while still providing sufficient clock margin to ensure that inaccurate data will not be sampled from the location, and avoid such problems. In addition, the several sensors used may include enough sensors to determine whether a data violation has occurred and / or the location is not in action or may provide inaccurate data when sampling from the location.

[0017] Figure 1An example system 101 of adjustable frequency voltage regulation driven by critical timing according to some embodiments of the present disclosure is shown. System 101 may include an automatic test equipment (ATE) component 120 and a system on a chip (SoC) 110. Components such as ATE component 120 described herein may include various circuit systems to facilitate operations associated with the component, such as testing a portion of a SoC (e.g., SoC 110). For example, ATE component 120 may include specialized circuit systems in the form of ASICs, FPGAs, state machines, and / or other logic circuit systems or software and / or firmware that may allow ATE component 120 to test other components and / or parameters of SoC 110. For example, ATE component 120 may be a simple computer-controlled digital multimeter, or a complex system containing dozens or more complex test instruments (real or simulated electronic test equipment), including systems on chips and / or integrated circuits, which are capable of automatically testing and diagnosing faults in precision electronic package components or on wafer testing.

[0018] In addition, SoC 110 may be an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), etc. SoC 110 includes a design unit 122 and a power management controller 124. The power management controller 124 may apply or determine whether to perform a dynamic voltage frequency adjustment (DVFS) operation using a one-time programmable (OTP) memory 116, a temperature sensor 118, and any other available inputs, as will be described below. Design unit 122 includes a circuit system that may include one or more cores (e.g., "intellectual property (IP) cores"). As used herein, a "core" or "IP core" generally refers to one or more data blocks and / or logic blocks that form a constituent component of an application specific integrated circuit or a field programmable gate array. A "core" or "IP core" may be designed, constructed, and / or otherwise configured to perform specific tasks and / or functions within the system described herein. In some examples, the power management controller 124 may be a power management integrated circuit (or PMIC) for managing the power of the system 101. Although PMIC can refer to a wide range of chips (or modules in system-on-chip (SoC) devices), most include several DC / DC converters. A DC to DC converter is an electronic circuit or electromechanical device that converts a direct current (DC) source from one voltage level to another. It is a type of power converter. PMICs are often included in battery-operated devices such as cell phones and portable media players to reduce the amount of space required.

[0019] ATE assembly 120 communicates with design unit 122 by " memory built-in self test " (MBIST) controller 112 and / or monitor assembly 115. Although MBIST controller 112 is described herein, embodiments are not limited thereto. For example, MBIST is just an example self-test controller / circuit, and any number of self-test circuits can be used. Monitor assembly 115 can refer to circuitry and / or control logic for controlling and managing monitoring operations (such as AC scanning operations, and other monitoring operations), as will be further described below. MBIST can refer to the industry standard method for testing embedded memory. MBIST operates by performing read and write sequences according to a test algorithm. There are many industry standard test algorithms. The MBIST controller produces the correct read and write sequences to all locations. When doing so, some extra test coverages are realized in the address and data path that MBIST uses. Additionally, the design unit 122 may communicate with the power management controller 124 through a clock (“CLK”) control component 128 and a voltage control component 130, which communicates with the power supply component 126 and communicates with the design unit 122 through the power supply component 126. The voltage control component 130 may control the voltage of the power supply component 126 according to instructions received from the power management controller 124. In some examples, the power management controller 124 may be a power management integrated circuit system (PMIC).

[0020] The clock control component 128 may include various circuit systems and / or logic inserted on the SoC 110 for controlling the clock. The clock control component 128 may adjust the clock timing according to the instructions received from the power management controller 124. In addition, since the monitoring of the AC (full speed) test usually requires two or more clock pulses in the capture mode, whose frequency is equal to or substantially close to the functional clock frequency, without the clock control component 128, it may be necessary to provide full-speed pulses for the ATE component 120 through the input / output (I / O) pads of the SoC 110. However, these I / O pads may have limitations in terms of the maximum frequency they can support. On the other hand, the clock control component 128 may use an internal phase-locked loop (PLL) clock in some instances for generating clock pulses for testing, and / or use an internal delay-locked loop (DLL) clock in other instances for generating clock pulses for testing. Although the clock control component 128 is described as providing timing for the ATE component 120 according to the instructions received from the power management controller 124, and also providing the clock, the embodiment is not limited thereto. For example, clock control component 128 may be used to adjust frequency according to instructions from power management controller 124 to dynamically adjust the frequency for DVF regulation, and different clock control components (not shown) may be used separately for ATE component 120 and for clock timing of the ATE test itself.

[0021] In some instances, a PLL clock may refer to a circuit system and / or logic that generates an output signal whose phase is related to the phase of an input signal. Although there are several different types of PLL clock circuits, the simplest is an electronic circuit consisting of a variable frequency oscillator and a phase detector in a feedback loop. The oscillator generates a periodic signal, and the phase detector compares the phase of the signal with the phase of the input periodic signal, thereby adjusting the oscillator to maintain phase matching. Keeping the input and output phases in lock step also means keeping the input and output frequencies the same. Therefore, in addition to synchronizing the signal, the phase-locked loop can also track the input frequency, or it can generate a frequency that is an integer multiple of the input frequency. These characteristics are used for computer clock synchronization, demodulation, and frequency synthesis.

[0022] In other examples, a delay-locked loop (DLL) may be a digital circuit similar to a phase-locked loop (PLL), wherein the main difference is that there is no internal voltage-controlled oscillator, which is replaced by a delay line. A DLL can be used to change the phase of a clock signal (a signal with a periodic waveform), and is typically used to enhance the timing characteristics of an integrated circuit (such as a DRAM device) from the clock rise to the valid data output. A DLL can also be used for clock recovery (CDR). From an external point of view, a DLL can be viewed as a negative delay gate placed in the clock path of a digital circuit. The main component of a DLL may be a delay chain consisting of many delay gates connected to the output to the input. The input of the chain (and therefore the DLL) is connected to the clock to be negatively delayed. A multiplexer may be connected to each stage of the delay chain, and the selector of this multiplexer may be automatically updated by a control circuit to produce a negative delay effect. The output of the DLL may be the resulting negatively delayed clock signal.

[0023] Phase-locked loops are widely used in radio, telecommunications, computers, and other electronic applications. They can be used to demodulate signals, recover signals from noisy communication channels, generate stable frequencies at multiple input frequencies (frequency synthesis), or distribute precisely timed clock pulses in digital logic circuits such as microprocessors. Since a single integrated circuit can now provide a complete phase-locked loop building block, the technology is widely used in modern electronic devices, with output frequencies ranging from a fraction of a hertz to several gigahertz. In addition, although a phase-locked loop (PLL) and a delay-locked loop (DLL) are provided in these examples, the embodiments are not limited thereto. For example, any circuit capable of generating a clock or frequency change can be used.

[0024] In the case of DC (fixed) testing, the clock control component 128 can ensure that only one clock pulse is generated in the capture phase. Similarly, during AC (full speed) testing, the clock control component 128 ensures that two or more clock pulses are generated in the capture phase, the frequency of which is equal to the frequency of the functional clock. Therefore, the test clock used in the scan design can be routed through the clock control component 128, which controls the clock operation in the scan mode (in both fixed and full speed testing) and bypasses the functional clock in the functional mode.

[0025] In general, AC scanning is configured to detect full-speed faults, and DC scanning is configured to detect stuck-at faults. AC scanning detects manufacturing defects that appear as delays on the gate input-output ports. Therefore, in AC scanning, each port is tested for logic 0 to 1 transition delay (slow rise fault) or logic 1 to 0 transition delay (slow fall fault). Like stuck faults, full-speed faults can be at the input or output of the gate, so a simple 2-input AND gate has six possible full-speed faults. For example, assume that a slow fall fault occurs at the output of the AND gate. A slower 1 to 0 transition at the output of the AND gate can occur and can affect the captured value. It is important to note that full-speed faults can only be detected when the initial state in the flip-flop is '1' and the input is 010.

[0026] Referring back to the DC (fixed) scan, the DC scan models manufacturing defects that occur when a circuit node is shorted to a positive supply voltage or "VDD" (fixed 1 fault) or a ground voltage "GND" (fixed 0 fault). The fault can be at the input or output of the gate. Therefore, a simple 2-input AND gate has six possible fixed faults. For example, assume that a fixed 0 fault is at the output of the AND gate. It is important to note that for this example, there are three input ports in the circuit, so there can be eight different input or mode combinations {000, 001, 010, 011, 100, 101, 110, 111}; of the eight modes, only one mode {011} is able to detect this fault. Like the rest of the modes, in the presence of this fixed 0 fault, the expected output can be the same as the actual circuit output. Since this example is a small circuit, the mode that detects this fault can be easily found. However, more complex circuits will use more complex fixed 0 fault modes to test all possible fault locations using complex steps, and are expected to be within the scope of the present disclosure.

[0027] In addition, Figure 1In this example shown in FIG, the ATE component 120 may configure the power management controller 124 via a one-time programmable ("OTP") memory 116. However, embodiments are not limited thereto, and the power management controller 124 may be configured via other methods or components. For example, a programmable component that is not a one-time programmable component may be used, such as a memory that can be programmed multiple times or more than once. A one-time programmable memory (OTP) may refer to a specific type of non-volatile memory (NVM) that permits data to be written to the memory only once. Once the memory has been programmed, it retains its value after power is lost (i.e., is non-volatile). OTP memory may be used in applications that require reliable and repeatable data reading. Examples include boot code, encryption keys, and configuration parameters for analog, sensor, or display circuit systems. OTP NVM is characterized over other types of NVMs such as electronic fuses (eFuse) or electrically erasable programmable read-only memories (EEPROM) by providing a low-power, small footprint memory structure. Thus, OTP memory may be used in microprocessors, display drivers, and power management ICs (PMICs).

[0028] The OTP memory 116 may include a voltage-frequency-temperature table ("VFT") 132. The VFT table 132 may be a set of cells for storing data related to the performance of an AC scan operation and / or data related to the performance of a memory built-in self-test (MBIST) operation. For example, a monitoring operation (e.g., an AC scan or other monitoring operation) may be performed by the monitor component 115 (or, in the case of an AC scan, by an AC scan controller, e.g., Figure 2A-2BThe AC scanning controller 214 in the system 101 and the data generated from the monitor operation (e.g., AC scanning) and associated with parameters such as voltage (V), frequency (F), temperature (T), etc., and may be stored in the VFT table 132. The data stored in the VFT table 132 can be used to determine the specific frequency and / or voltage to be used in the SoC 110 based on the error rate and / or error amount occurring at the specific frequency, temperature and / or voltage. In some embodiments, although the monitor operation may occur at the time of manufacturing and before use by the user, the monitor operation may be performed at different time windows throughout the life cycle of the system 101 and / or SoC 110. For example, the monitoring operation may be performed at the startup of the SoC 110 at a specific time period after manufacturing or after use by the user. The data associated with the frequency and / or voltage and / or temperature and the corresponding error rate and / or error amount may have changed from the initial monitor operation or several initial monitor operations associated with the manufacturing time. This may be due to the effect of unit aging, which may cause the frequency, voltage and / or temperature to change the efficacy and / or accuracy of the data stored in the unit over time. Thus, adjusted data based on such post-manufacturing scans may be stored in registers and / or specific locations within SoC 110 and may be used to modify the manner in which VFT table 132 adjusts voltage and / or frequency and / or temperature values ​​of SoC 110 .

[0029] Additionally, the temperature sensor 118 may communicate with the power management controller 124 and may provide temperature data to the power management controller 124. The temperature sensor 118 may be embedded within the SoC 110 and may provide temperature values ​​at a number of different locations within the SoC 110. For example, the temperature sensor 118 may be embedded near a power transistor that is near a heat source for the SoC 110. Although one temperature sensor 118 is described, embodiments are not limited thereto. For example, any number of temperature sensors may be located throughout the SoC 110, such as near a particular heat dissipating transistor, near a power supply component 126, etc.

[0030] In some embodiments, the system 101 may be deployed on or otherwise included in a system (e.g., a storage device, a memory module, or a hybrid of a storage device and a memory module). Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0031] In other embodiments, the system 101 may be deployed on or otherwise included in a computing device, such as a desktop computer, a laptop computer, a server, a network server, a mobile computing device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such computing device including a memory and a processing device. As used herein, the term "mobile computing device" generally refers to a handheld computing device having a tablet or tablet phone form factor. Generally speaking, the tablet form factor may include a display screen between approximately 3 inches and 5.2 inches (measured diagonally), while the tablet phone form factor may include a display screen between approximately 5.2 inches and 7 inches (measured diagonally). However, examples of a "mobile computing device" are not limited thereto, and in some embodiments, a "mobile computing device" may refer to an IoT device, as well as other types of edge computing devices.

[0032] Such a computing device may include a host system coupled to a memory system (e.g., one or more storage devices, memory modules, or a mixture of storage devices and memory modules). The host system may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system uses the storage devices, memory modules, or a mixture of storage devices and memory modules, such as writing data to the storage devices, memory modules, or a mixture of storage devices and memory modules, and reading data from the storage devices, memory modules, or a mixture of storage devices and memory modules.

[0033] In these examples, the host system may include a processing unit, such as a central processing unit (CPU), configured to execute an operating system. In some embodiments, the processing unit may execute a complex instruction set computer architecture, such as x86 or other architecture suitable for use as a CPU for the host system.

[0034] The host system may be coupled to the memory system via a physical host interface. Examples of the physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, a fiber channel, a serial attached SCSI (SAS), a small computer system interface (SCSI), a double data rate (DDR) memory bus, a dual in-line memory module (DIMM) interface (e.g., a DIMM socket interface supporting double data rate (DDR)), an open NAND flash interface (ONFI), a double data rate (DDR), a low power double data rate (LPDDR), or any other interface. The physical host interface may be used to transfer data between the host system and the memory system. When the memory system is coupled to the host system via a PCIe interface, the host system may further utilize an NVM express (NVMe) interface to access the component. The physical host interface may provide an interface for transmitting control, address, data, and other signals between the memory system and the host system. In general, the host system may access multiple memory subsystems via the same communication connection, multiple independent communication connections, and / or a combination of communication connections.

[0035] The system may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0036] Some examples of non-volatile memory devices include NAND-type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on changes in body resistance in conjunction with a stackable cross-grid data access array. In addition, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0037] Although nonvolatile memory components such as three-dimensional cross-point arrays of nonvolatile memory cells and NAND-type memories (e.g., 2D NAND, 3D NAND) are described, the memory device may be based on any other type of nonvolatile memory or storage device, such as read-only memory (ROM), phase change memory (PCM), self-selected memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), "NOR" (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0038] The memory system may also include additional circuitry or components. In some embodiments, the memory system may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from a memory system controller and decode the addresses to access memory devices.

[0039] In some embodiments, a memory device may include a local media controller that operates with a memory system controller to perform operations on one or more memory cells of the memory device. For example, an external controller may manage the memory device externally (e.g., perform media management operations on the memory device). In some embodiments, the memory device is a managed memory device, which is a raw memory device combined with a local controller to perform media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0040] Although the non-limiting examples herein are generally described in terms of applicability to memory systems and / or memory devices, the embodiments are not limited thereto and aspects of the present disclosure may also be applied to systems on a chip, computing systems, data collection and processing, storage, networking, communications, power, artificial intelligence, control, telemetry, sensing and monitoring, digital entertainment, and other types of systems and / or devices, and thus aspects of the present disclosure may be applied to these components to provide critical timing driven AVFS as described herein.

[0041] Figure 2A An example system for adjustable frequency voltage regulation for critical timing drive according to some embodiments of the present disclosure is shown. Figure 1 , Figure 2A The same and / or similar components may be included. For example, Figure 2A Shows something like Figure 1The ATE 220 of the ATE component 120 and similar Figure 1 210 of the system on chip (SoC) 110 in the embodiment of the present invention. The ATE 220 may communicate with the SoC 210. The SoC 210 may include a design unit 222. The ATE 220 may communicate with the design unit 222. For example, the ATE 220 may communicate with the design unit 222 through the MBIST controller 212. The ATE 220 may configure the SoC 210. The SoC 210 may include a power management controller 224. The ATE 220 may communicate with the power management controller 224. For example, the ATE 220 may communicate with the power management controller 224 through the OTP memory 216. The ATE 220 may control the design unit 222 through the clock control component 228, the voltage control component 230, and the power supply 226. The temperature sensor 218 may communicate with the power management controller 224. However, the temperature sensor 218 may communicate with the power management controller 224. Figure 1 The difference is that in Figure 2A In place of monitor component 115, AC scanning controller 214 is shown for more specific performance of an AC scanning operation, which is a subset of the general monitoring operation described above.

[0042] Figure 2B An example system for frequency voltage regulation of critical timing drive according to some embodiments of the present disclosure is shown. Figure 1 and Figure 2A , Figure 2B The same and / or similar components may be included. For example, Figure 2B Shows something like Figure 1 The ATE 220 of the ATE component 120 and similar Figure 1 SoC 210 of the system on chip (SoC) 110 in the embodiment of the present invention. SoC 210 may include an ATE 220 through an MBIST controller 212 and an AC scan controller 214 (similar to Figure 2A ) controlled design unit 222. SoC210 may also include a power management controller 224, which is configured by ATE220 through OTP216 and may control a clock control component 228, a voltage control component 230, and a power supply 226. Temperature sensor 218 may communicate with power management controller 224.

[0043] However, with Figure 1 and Figure 2A The difference is that in Figure 2B2 is a circuit system 234 in communication with the AC scan controller 214. The circuit system 234 may be, for example, a circuit system associated with a non-volatile memory device, such as a NAND flash memory array in some instances. As an additional example, the memory array may be a storage class memory (SCM) array or other such memory array, such as a three-dimensional crosspoint (3D crosspoint) memory array, a ferroelectric RAM (FRAM) array, or a variable resistance memory array, such as a PCRAM, RRAM, or a spin torque transfer (STT) array, etc. The circuit system 234 may be used to store scan vectors or other test program data that the AC scan controller 214 may operate autonomously without the need for ATE 220. In addition, for example, as described above, the AC scan performed during the life cycle of the SoC 110, 210 may provide additional voltage, frequency, temperature, and / or error data that may be stored in the circuit system 234. For example, the OTP 216 may be prevented from being written (because it is a one-time programmable memory and may have been written to initially). In this case, the stored AC scan data may be accessed from another reprogrammable memory to modify the analysis of the scan data already stored in the voltage-frequency-temperature (VFT) table 232 in the OTP 216. The VFT table 232 storing the scan data may be adjusted based on the additional scan data stored in the circuit system 234 to modify the frequency and / or voltage and / or temperature and minimize and / or attempt to avoid a number of errors in the SoC 210. In some examples, the OTP 216 may be any other memory, such as a reprogrammable memory, etc.

[0044] Figure 3A An example system 331-1 including a sensor 338 is shown for adjustable voltage frequency regulation for critical timing drive according to some embodiments of the present disclosure. The example system 331-1 is an example of using a sensor 338, which is set to sample data at an earlier clock arrival under more stringent conditions than a functionally critical endpoint, which is an endpoint determined by a trigger 333-4. This example helps prevent timing of the system 331-1, such as marginal setting violations (e.g., timing violations) in the timing frequency. During operation, the sensor 338 can capture data at the data input of the trigger 333-4. The signal of the sensor 338 can be used by the power management controller 324 to adjust the voltage and / or timing frequency to operate at a specific efficiency or desired timing.

[0045] System 331-1 may include a power management controller 324. Power management controller 324 may apply dynamic voltage frequency scaling (DVFS) operations using one-time programmable (OTP) memory 116, temperature sensor 118, and any other available inputs, as will be described below. Power management controller 324 may be similar to Figure 1Similarly, the system 331-1 may include power management controller 124 similar to Figure 1 The power supply component 126, the clock control component 128 and the voltage control component 130 of the power supply component 326, the clock control component 328 and the voltage control component 330. For example Figure 1 Design units such as the design unit 122 in the embodiment of the present invention may be controlled by a power management controller 324 through a clock (“CLK”) control component 328 and a voltage control component 330 that communicate with a power supply 326. The voltage control component 330 may control the voltage of the power supply 326 according to instructions received from the power management controller 324. In some examples, the power management controller 324 may be a power management integrated circuit system (PMIC).

[0046] The signal from the clock control component 328 may be input to the delay line 336. The delay line 336 may include a number of buffers, inverters, and / or other units. Figure 3A The example is shown as three buffers, however, the example is not limited thereto. The delay line 336 can be fixed or configurable. For example, a portion of the clock tree can be a delay line. A configurable or trimmable delay line can be used in conjunction with, for example, Figure 1-2B Temperature sensors such as temperature sensors 118 and 218 in the example and Figure 1-2B Design units 122 and 222 provide better temperature compensation when paired.

[0047] An example system 331-1, which may be referred to as a device in the alternative, includes multiple flip-flops 333-1, 333-2, 333-3, 333-4, 335-1, 335-2, 335-3, which are referred to as "latches" 333-1, 333-2, 333-3, 333-4, 335-1, 335-2, 335-3 in the alternative (which are generally referred to herein as "multiple flip-flops 333 or 335" or "multiple latches 333 or 335," respectively).

[0048] like Figure 3A As shown in , the clock control component 328 is coupled to the flip-flops 333-1, 333-2, 333-3, and 333-4 via a delay line 336. The clock control component 328 can receive a clock signal from a circuit system external to the system 331-1. In some embodiments, the clock signal is asserted by the clock control component 328 to enable clock gating logic. In general, the "flip-flops" referred to herein are edge-triggered flip-flops (e.g., flip-flops that are edge-triggered devices that respond to the rising or falling edge of a timing signal) or level-sensitive flip-flops (e.g., flip-flops that are level-triggered devices that are transparent to a particular clock signal level and opaque to a different clock signal level). Although Figure 3AA plurality of flip-flops 333 are shown, but examples are not so limited. For example, the example system 331-1 can include and operate correctly with any sequential cell type latch, such as a flip-flop, a register, a register bank, a memory, and the like.

[0049] Each of the plurality of flip-flops 333, 335 has an edge-triggered clock input (shown as a sideways triangle), a data "D" input gate, a "Q" output, and either or both of a Q-bar output. As discussed herein, the first of the flip-flops 333-1 can be clocked by a delay line 336 at the clock input of the first flip-flop 333-1. In this case, through the "Q" or "Q-bar" output, the flip-flop 333-1 can be the starting point of the critical timing path 329. Similarly, the delay line 336 provides a clock to each of the flip-flops 333-2, 333-3, 333-4. In addition, in this case, through each of the corresponding "Q" or "Q-bar" outputs, each of the flip-flops 333-2, 333-3 is the starting point of the critical timing path 329. Through the "D" input, the flip-flop 333-4 can be the endpoint of the critical timing path 329. The triggers 335 - 1 , 335 - 2 are portions of the sensor 338 that sense endpoints of the critical timing path 329 .

[0050] The sensor 338 includes a plurality of flip-flops, such as a first flip-flop 335-1 ("FFs1"), a second flip-flop 335-2 ("FFs2"), and a third flip-flop 335-3 ("FFs3") (hereinafter collectively referred to as a plurality of flip-flops 335), a plurality of XOR gates 337-1, 337-2, and a delay line 358. The output from the clock control component 328 may be connected to the clock input of the flip-flop 335-1 and the delay line 358. The output of the delay line 358 may be connected to the clock input of each of the flip-flops 335-2 and 335-3. The outputs from the Q outputs of the flip-flops 335-1 and 335-2 may each be connected to the input of the XOR gate 337-1. The data outputs of the flip-flops 335-2 and 335-3 may be connected to the input of the XOR gate 337-2. The output of the XOR gate 337-1 may be connected to the input 340, which indicates a margin state, and the output of the XOR gate 337-2 may be connected to the input 339, which indicates that margin sensing occurs. Each of input 340 and input 339 may be an input to power management controller 324. Clock 311 may be connected to Figure 4-6 The clock waveform (e.g., 411, 511, 611) of the first flip-flop 335-1 ("FF1") 317-1 can be associated with Figure 4-6 The clock ("FF2") 317-2 of the second flip-flop 335-2 can be associated with the FF1 clock (e.g., 417-1, 517-1, 617-1). Figure 4-6 is associated with the FF2 clock (e.g., 417-2, 517-2, 617-2).

[0051] Figure 3B An example system 331-2 including a sensor 342 is shown for adjustable voltage frequency regulation for critical timing drive according to some embodiments of the present disclosure. The example system 331-2 is also an example of using a sensor 342, which is set to sample data at an earlier clock arrival under stricter conditions than a functionally critical endpoint, which is an endpoint represented by a trigger 333-4. This example helps prevent marginal setting violations in the timing of the system 331-2. During operation, the sensor 342 can capture data at the data input of the trigger 333-4. The signal of the sensor 342 can be used by the power management controller 324 to adjust the voltage and / or timing to operate at a specific efficiency or desired timing.

[0052] System 331-2 may include a power management controller 324. Power management controller 324 may apply dynamic voltage frequency scaling (DVFS) operations using one-time programmable (OTP) memory 116, temperature sensor 118, and any other available inputs, as will be described below. Power management controller 324 may be similar to Figure 1 Similarly, the system 331-2 may include power management controller 124 similar to Figure 1 The power supply 326, clock control component 328 and voltage control component 330 of the power supply component 126, clock control component 128 and voltage control component 130 in FIG. Figure 1 Design units such as the design unit 122 in the embodiment of the present invention may be controlled by a power management controller 324 through a clock (“CLK”) control component 328 and a voltage control component 330 that communicate with a power supply 326. The voltage control component 330 may control the voltage of the power supply 326 according to instructions received from the power management controller 324. In some examples, the power management controller 324 may be a power management integrated circuit system (PMIC).

[0053] The signal from the clock control component 328 may be input to the delay line 336. The delay line 336 may include a number of buffers, inverters, and / or other units. Figure 3B The example is shown as three buffers, however, the example is not limited thereto. The delay line 336 can be fixed or configurable. For example, a portion of the clock tree can be a delay line. A configurable or trimmable delay line can be used in conjunction with, for example, Figure 1-2B Temperature sensors such as temperature sensors 118 and 218 in the example and Figure 1 Design units 122 and 222 in the -2 provide better temperature compensation when paired.

[0054] An example system 331-2, which may be referred to as a device in the alternative, includes multiple flip-flops 333-1, 333-2, 333-3, 333-4, 344-1, 344-2, 344-3, which are referred to as "latches" 333-1, 333-2, 333-3, 333-4, 344-1, 344-2, 344-3 in the alternative (which are generally referred to herein as "multiple flip-flops 333 or 344" or "multiple latches 333 or 344," respectively).

[0055] like Figure 3B As shown in , the clock control component 328 is coupled to the flip-flops 333-1, 333-2, 333-3, and 333-4 through the delay line 336. The clock control component 328 can receive a clock signal from a circuit system external to the system 331-2. In some embodiments, the clock signal is asserted by the clock control component 328 to enable clock gating logic. In general, the "flip-flops" referred to herein are edge-triggered flip-flops (e.g., flip-flops that are edge-triggered devices that respond to the rising or falling edges of the timing signal) or level-sensitive flip-flops (e.g., flip-flops that are level-triggered devices that are transparent to a particular clock signal level and opaque to a different clock signal level).

[0056] Each of the plurality of flip-flops 333, 344 has an edge-triggered clock input (shown as a sideways triangle), a data "D" input, and a "Q" or "Q-bar" output. A delay line 336 feeds the clock input to each of the flip-flops 333-1, 333-2, 333-3, 333-4. As discussed herein, data is sampled by the flip-flops 333-1, 333-2, and 333-3. The resulting outputs of the flip-flops 333-1, 333-2, and 333-3 (in this case, from the "Q" output) are the starting point of the critical timing path 329. Through the "D" input, the flip-flop 333-4 can be the endpoint of the critical timing path 329. As discussed herein, the data is sampled by the flip-flops 333-1, 333-2, and 333-3. The resulting outputs of the flip-flops 333-1, 333-2, and 333-3 (in this case, from the "Q" output) are the starting point of the critical timing path 329. Through the "D" input, the flip-flop 333-4 can be the endpoint of the critical timing path 329. Figure 3B As shown in , flip-flops 344 - 1 , 344 - 2 , and 344 - 3 are portions of sensor 342 for sensing critical timing path 329 .

[0057] The sensor 342 includes a plurality of flip-flops, such as a first flip-flop 344-1 ("FFs1"), a second flip-flop 344-2 ("FFs2"), and a third flip-flop 344-3 ("FFs3") (hereinafter collectively referred to as a plurality of flip-flops 344), a plurality of XOR gates 343-1, 343-2, and a delay line 341. The clock output from the clock control component 328 can be connected to the clock input of each of the flip-flops 344-1, 344-2, and 344-3 of the sensor 342. The outputs from the Q outputs of the flip-flops 344-1 and 344-2 can each be connected to the input of the XOR gate 343-1. The output of the flip-flop 344-1 and the output from the Q output of the flip-flop 344-3 can be connected to the input of the XOR gate 343-2. The output of XOR gate 343 - 1 may be input 340 to power management controller 324 associated with margining, and the output of XOR gate 344 - 2 may be input 339 to power management controller 324 associated with sensing.

[0058] Figure 4 An example timing diagram 405 of adjustable voltage frequency regulation for critical timing drive according to some embodiments of the present disclosure is shown. The timing diagram 405 includes waveforms of a clock ("CLOCK") 411, a clock 417-1 of a first flip-flop ("FF1"), a clock 417-2 of a second flip-flop ("FF2"), and critical endpoint data ("DATA") 413. The timing of each of the clock 411, the data 413, the clock 417-1 of the first flip-flop, and the clock 417-2 of the second flip-flop are aligned in time so that the vertical lines across each of the waveforms, such as the waveforms of the clock 411, the clock 417-1 of the first flip-flop ("FF1"), the clock 417-2 of the second flip-flop ("FF2"), and the data 413 will be at the same time. The clock 411 shows rising edges (e.g., rising edges 419-1, 419-3 for the clock 411) and falling edges (e.g., falling edge 419-2 for the clock 411). At rising edge 419-1, time window 415 may represent the data as seen at the endpoint. During this time window 415, the data may not be valid. The time windows 415 and 457 where the data propagates through the critical path and may be invalid may be shown by the diagonal dashed lines. During this time window, the data may change sporadically and therefore may be unstable. After completing the time window 415, a valid data value (e.g., "D1") may be accurately sampled.

[0059] To further illustrate the operation of the rising edge, data 413 includes a first portion 456 (where the first data value "D0" is valid), a second portion is a time window 415 (a time window in which the data propagates through the sensed critical path), a third portion 448 (where the second data value "D1" is stable), and a fourth portion is a window 457 (e.g., a time window in which the third data value (not shown) propagates). The propagation time margin 449 refers to the time period from the rising edge to the start of the next rising edge setup time 423. The reference to D0 and D1 refers to the data sequence, where D0 is the previous data sampled (e.g., "0" or "1"), and D1 is the subsequent sampled data propagated for the next clock (e.g., "0" or "1"). The timing of these rising edges and the timing when the trigger input data remains stable are critical to ensuring that accurate data is sampled by the trigger. The second portion is the time window 415 in which the data propagates through the critical timing path so that the data can be sampled later during the third portion 448 (e.g., when the data is "D1").

[0060] In order to sample the appropriate data, the input to the flip-flop needs to be stable (not changing) for at least a period of time when the data is sampled. For example, the data input must be stable for a certain amount of time before being sampled by the clock. This amount of time is called the setup time. The setup time is the amount of time required for the input to the flip-flop to be stable before the clock edge. In addition, the hold time is the minimum amount of time required for the input to the flip-flop to remain stable after the clock edge. The hold time is similar to the setup time, but refers to events after the clock edge occurs.

[0061] As in Figure 4 As shown in FIG. 4 , the first setup time 445 may be associated with using a first trigger (eg, Figure 3A 4. The second setup time 446 may be associated with the sampling performed using the first trigger 335-1 in FIG. 4, and the second setup time 446 may be associated with the sampling performed using the second trigger (eg, Figure 3AThe first setup time 445 and the second setup time 446 are each within a third portion (e.g., window) 448 and before a third setup time 423, at which the data is actually sampled by the functional trigger 333-4. In this way, the data can be sampled by the sensor before the actual functional data is sampled to determine the state of the data and whether the margin of the functional trigger (i.e., 333-4) is excessive or optimal. For example, the margin 421 spanning from the beginning of the setup time 445 to the beginning of the data D1 stabilization (the beginning of the window 448) is an excessive margin because the time for the data to remain stable does not need to be longer than the functional trigger setup time 423 to be accurately sampled. In some previous approaches, this excessive margin is used to cover the worst case combination of associated voltages and temperatures that can be used and the corresponding delay time for transmitting data associated with those voltages and temperatures. When the first and second triggers sample the same data value (e.g., "D1"), the first and second triggers can detect this excessive margin.

[0062] In addition, as in Figure 4 , delay 447 indicates the amount of time between the clock edges associated with the first setup time 45 and the second setup time 446, which may be the same as the phase shift between the clock edges of the flip-flops 335-1 and 335-2. This phase shift is associated with the delay introduced by the delay line of the sensor 338 and represents the timing delay 447 of the sensor. Although the timing delay 447 is measured from the rising edge of the clock 417-1 to the rising edge of the clock 417-2 (assuming that the lengths of both setup times 445 and 446 are equal), examples are not limited to this. In some other examples, the timing delay may be measured from the respective starting points of each of the two setup times so that setup times with varying lengths may be calculated.

[0063] Figure 4-6 Each of the Figure 3A The delay line 358 shown and described is associated. For example, Figure 4-6 Shown with Figure 3A The delay line 358 associated with the system. Figure 3B shows a system associated with a data delay line 341, which is not Figure 4-6 Related to the timing diagram in .

[0064] Figure 5An example timing diagram 506 of adjustable voltage frequency regulation for critical timing drive according to some embodiments of the present disclosure is shown. The timing diagram 506 includes waveforms of clock ("CLOCK") 511, data ("DATA") 513, clock 517-1 of the first flip-flop ("FF1"), and clock 517-2 of the second flip-flop ("FF2"). The timing of each of the clock 511, data 513, clock 517-1 of the first flip-flop, and clock 517-2 of the second flip-flop are aligned in time so that the vertical lines across each of them will be at the same time. Similar to Figure 4 , each of the waveforms (except data) shows the rising and falling edges of the clock.

[0065] To further illustrate the operation of the rising edge, data 513 includes a first portion 556, a second portion 515, a third portion 548, and a fourth portion 557. The first portion 556 is associated with data (e.g., "D0"). At the first rising edge of clock 511, the data input changes to the second portion 515 representing invalid data that produces different data (indicated by "D1" in the third portion 548 of the waveform of data 513). The timing of these rising edges and the timing when the output data is sampled is critical to ensure that accurate data is sampled.

[0066] As in Figure 5 As shown in , a first setup time 554 may be associated with sampling using a first trigger (e.g., first trigger 335-1), and a second setup time 553 may be associated with sampling using a second trigger (e.g., second trigger 335-2). The first setup time 554 is during the second portion 515 and the second setup time 553 is during the third portion 548. In this way, the data sampled by the first trigger may be different from the data sampled by the second trigger, indicating that the margin 551 is not excessive. For example, the margin 551 (552) between the start of the third portion 548 and the start of the setup time of the functional trigger 333-4 is an optimal margin, or at least not an excessive margin. In other words, the first and second triggers (e.g., 335-1, 335-2, respectively) with different sampled data values ​​indicate that the sensor is sampling around the desired data arrival time. However, this scenario does not address the situation when the timing of both the first trigger and the second trigger is violated and erroneous different values ​​may be accidentally generated, which will be discussed further below. Furthermore, this scenario does not address the situation when the timing of a first trigger (e.g., trigger 335-1) is violated, but it samples the same data when a second trigger (e.g., trigger 335-2) is not violated. For this reason, the sense signal can be used to indicate that sensing did not occur. Additionally, as in Figure 5As shown in , delay 555 indicates the amount of time between the rising edge of clock 517-1 and the rising edge of clock 517-2. In addition, critical path maximum delay 550 refers to the time period from the rising edge of the previous clock to the start of the setup time 552 of the next clock. Figure 4-6 , but those skilled in the art will appreciate that the setup times of the respective triggers may vary, for example, depending on the type of the respective trigger. Thus, the delay of the sensor and the resulting delay may vary proportionally, for example, depending on the respective setup time of the particular type of trigger.

[0067] Figure 6 An example timing diagram 607 of adjustable voltage frequency regulation for critical timing drive according to some embodiments of the present disclosure is shown. The timing diagram 607 includes waveforms of clock ("CLOCK") 611, data ("DATA") 613, clock 617-1 of a first flip-flop, and clock 617-2 of a second flip-flop. The waveforms are aligned in time so that the vertical lines across each of them will be at the same time. Similar to Figure 4-5 , each of the waveforms, such as clock 611, clock 617-1 of the first flip-flop (e.g., Figure 3A The first trigger 335-1) and the second trigger (for example, Figure 3A Each waveform of the clock 617-2 of the second flip-flop 335-2 shows the rising edge and the falling edge of the timing diagram.

[0068] To further illustrate the operation of the rising edge, data 613 includes a first portion 656, a second portion (e.g., window) 615, a third portion 648, and a fourth portion 657. The first portion 656 is associated with a first data value ("D0"), and at the first rising edge of clock 611, the data input changes to a second data value (indicated by "D1" in the third portion 648 of data 613). The timing of these rising edges and the timing when the output data is sampled is critical to ensure that accurate or intended data is sampled.

[0069] As in Figure 6As shown in , the first setup time 664 may be associated with sampling using a first trigger (e.g., the first trigger 335-1), and the second setup time 663 may be associated with sampling using a second trigger (e.g., the second trigger 335-2). The first setup time 664 is during the second portion 615 and the second setup time 663 is also during the second portion 615. In this way, the data sampled by the first trigger may be the same as the data sampled by the second trigger, which, combined with the other trigger values ​​sampled (described further below), indicates that there is an excess margin. This sensing may result in an erroneous detection of an excess margin for sampling or an erroneous optimal margin for sampling. The erroneous optimal margin sampling may be the result of data switching during the window 615. This type of erroneous sensing may be avoided by using a power management controller to avoid setting unreal low voltage or high frequency settings, and various techniques are used to avoid it. For example, the power management controller may deploy a filter to remove accidental erroneous sampling, or the power management controller may slowly adjust the voltage and / or frequency to average the sampling and avoid the optimal point from quickly entering the erroneous sensing region. Additionally, the power management controller may enforce voltage and / or frequency limits to avoid this. Figure 7-8 The associated following description describes additional triggers for detecting and managing such conditions.

[0070] In addition, as in Figure 6 As shown in , delay 665 indicates the amount of time between the rising edge of clock 617-1 and the rising edge of clock 617-2. Additionally, critical path delay 660 refers to the time period from the previous rising edge to a point beyond the beginning of setup time 662. This timing represents a violated setup time 662, shown as timing violation 661 (e.g., which refers to the extent to which critical path delay 600 extends into 662), which can result in incorrect data being sampled by flip-flop 333-4. When both flip-flop 335-1 and flip-flop 335-2 are violated, there is a greater risk that flip-flop 333-4 is also violated. In contrast, when a timing violation consistent with setup time 662 and an optimal margin (e.g., as Figure 5 When the sum of the optimal margins 551 shown in ) is equal to the duration 667, correct data can be sampled from the flip-flops (e.g., flip-flops 335-1, 335-2).

[0071] Figure 7An example timing diagram 708 of adjustable voltage frequency regulation for critical timing drive according to some embodiments of the present disclosure is shown. A first setup time 773 of the timing diagram 708 may be associated with sampling using a first trigger (e.g., trigger 882-1), a second setup time 775 may be associated with sensing using a second trigger (e.g., trigger 882-2), and a third setup time 774 may be associated with using a third trigger (e.g., trigger 882-3). The first setup time 773 is during the second portion 715 and the second setup time 775 is also during the second portion 715. The third setup time 774 is during the third portion 748. In this way, in this example, the data sampled by the first trigger (e.g., trigger 882-1) may be the same as the data sampled by the second trigger (e.g., trigger 882-2), and the data sampled by the third trigger (e.g., trigger 882-3) may be different from the data sampled by the second trigger, indicating that there is a timing violation at the input of 833-4. In other words, when the data sampled by the second flip-flop differs from the data sampled by the third flip-flop, a timing violation may be indicated.

[0072] In addition, as in Figure 7 As shown in , the first delay 776 indicates the amount of time between the rising edge 717-1 of the clock of the first flip-flop 882-1 and the rising edge 717-2 of the clock of the second flip-flop 882-2. The second delay 777 indicates the amount of time between the rising edge 717-2 of the clock of the second flip-flop 882-2 and the rising edge 717-3 of the clock of the fourth flip-flop 817-4. In addition, the critical path period 770 refers to the time period from the rising edge of the clock to the beginning of the setup time 772 exceeding the fourth flip-flop 833-4. This timing indicates that the setup time 772 is violated, shown as a timing violation 771, which can result in incorrect data sampled by the fourth flip-flop 833-4 (e.g., the fourth flip-flop). In contrast, when a timing violation consistent with the setup time 762 and the optimal margin (e.g., as Figure 5 When the sum of the optimal margins 551 shown in ) is equal to the duration 778, correct data can be sampled from the flip-flops (e.g., flip-flops 335-1, 335-2).

[0073] As in Figure 7As shown in , timing diagram 708 includes waveforms including clock ("CLOCK") 711, data ("DATA") 713, clock 717-1 of a first flip-flop ("FF1"), clock 717-2 of a second flip-flop ("FF2"), and clock 717-3 of a third flip-flop ("FF3"). The timing of each of the waveforms, such as clock 711, clock 717-1 of a first flip-flop ("FF1"), clock 717-2 of a second flip-flop ("FF2"), clock 717-3 of a third flip-flop ("FF3"), and data 713, is aligned in time so that the vertical lines across each of the waveforms will be at the same time. Similar to Figure 4-6 , waveforms such as clock 711, clock 717-1 of the first flip-flop ("FF1"), clock 717-2 of the second flip-flop ("FF2"), and clock 717-3 of the third flip-flop ("FF3") each show rising and falling edges of the clock.

[0074] To further illustrate the operation of the rising edge, data 713 includes a first portion 756, a second portion 715, a third portion 748, and a fourth portion 757. The first portion 756 is associated with the first data value ("D0"), and at the first rising edge of clock 711, the data input changes (indicated by "D1" in the third portion 748 of data 713). The timing of these rising edges and the timing when the output data is sampled is critical to ensure that accurate data is sampled.

[0075] The following table 1 shows the data values ​​of the trigger and the Figure 7 and Figure 8 Examples of corresponding determinations of those sampled data values ​​associated with various embodiments of the embodiments described in . The first ("FFs1") trigger can be configured to determine whether the margin is excessive, the second ("FFs2") and third ("FFs3") triggers can be used to determine whether a violation has occurred, and the fourth ("FFs4") trigger can be configured to determine whether a sensing operation has occurred, and whether the result of the sensing operation is valid. For example, the fourth trigger can be configured to change the data state in response to the occurrence of the sensing operation (e.g., in response to the sensing operation being valid). Table 1 is shown as a non-limiting example, however, other configurations (e.g., using different signal combinations and / or different results based on signal combinations, etc.) are possible. For example, Table 2 shows the data values ​​of the triggers and the corresponding determinations based on the data values ​​including Figure 3A and Figure 3B Another non-limiting example of corresponding determination of those sampled data values ​​associated with the various embodiments described in .

[0076] As shown in Tables 1 and 2, an "active" designation may refer to when a sensing operation has occurred and the result of the sensing operation is valid. Conversely, an "inactive" designation may refer to when a sensing operation has not occurred (e.g., the state of the fourth flip-flop has not changed). As mentioned, a timing violation is determined by a comparison between the second flip-flop and the third flip-flop.

[0077] Table 1

[0078] FFs1 FFs2 FFs3 FFs4 violation Margin Sensing result 0 0 0 0 none over Inactive Inactive 0 0 0 1 none over In Action over 0 0 1 0 violation over In Action violation 0 0 1 1 violation over Inactive Inactive 0 1 0 0 violation Optimal Inactive Inactive 0 1 0 1 violation Optimal In Action violation 0 1 1 0 none Optimal In Action Optimal 0 1 1 1 none Optimal Inactive Inactive 1 0 0 0 none Optimal Inactive Inactive 1 0 0 1 none Optimal In Action Optimal 1 0 1 0 violation Optimal In Action violation 1 0 1 1 violation Optimal Inactive Inactive 1 1 0 0 violation over Inactive Inactive 1 1 0 1 violation over In Action violation 1 1 1 0 none over In Action over 1 1 1 1 none over Inactive Inactive

[0079] Table 2

[0080] FFs1 FFs2 FFs3 Margin Sensing result 0 0 0 over Inactive Inactive 0 0 1 over In Action over 0 1 0 Optimal In Action Optimal 0 1 1 Optimal Inactive Inactive 1 0 0 Optimal Inactive Inactive 1 0 1 Optimal In Action Optimal 1 1 0 over In Action over 1 1 1 over Inactive Inactive

[0081] Figure 7 For combination Figure 8 The example timing diagram 708 of the system 831 is described. For example, Figure 7 Shown with Figure 8 The clock 811 can be connected to the Figure 7 The clock waveform of the first flip-flop 882-1 ("FFs1") may be similar to Figure 7 The clock of the first flip-flop ("FF1") (e.g., 717-1) of the second flip-flop 882-2 ("FFs2") can be similar to Figure 7 The clock ("FF2") of the second flip-flop (e.g., 717-2) of the third flip-flop 882-3 can be similar to Figure 7 The clock of the third flip-flop (e.g., 717-3).

[0082] Figure 8 An example system 831 including a sensor 885 for adjustable voltage frequency regulation of a critical timing drive according to some embodiments of the present disclosure is shown. Example system 831 is an example of using sensor 885, wherein the sensor is set to sample data at an earlier clock arrival under stricter conditions than a functionally critical endpoint, wherein the functionally critical endpoint is an endpoint determined by a trigger 833-4. In addition, example system 831 shows that the sensor 885 includes a combination of Figure 7 Additional triggers described. This example system 831, along with other embodiments herein, reduces / avoids erroneous margin sensing (e.g., accidental erroneous margin sensing as mentioned above). During operation, sensor 885 may capture data at the data input of trigger 833-4. The signal of sensor 885 may be used by power management controller 824 to adjust voltage and / or timing to operate at a specific efficiency or desired timing.

[0083] System 831 may include a power management controller 824. Power management controller 824 may apply dynamic voltage frequency scaling (DVFS) operations using one-time programmable (OTP) memory 116, temperature sensor 118, and any other available inputs, as will be described below. Power management controller 324 may be similar to Figure 1 Similarly, the system 831 may include power management controller 124 similar to Figure 1 and 3A - Power supply 826 of power supply components 126 and 326 in B, similar to Figure 1 The clock control component 128 and the voltage control component 130 of the clock control component 828 and the voltage control component 830. For example Figure 1 Design units such as the design unit 122 in the power management controller 824 can be controlled by a power management controller 824 through a clock ("CLK") control component 828 and a voltage control component 830 that communicate with a power supply 826. The voltage control component 830 can control the voltage of the power supply 826 according to instructions received from the power management controller 824. In some examples, the power management controller 824 can be a power management integrated circuit system (PMIC).

[0084] The signal from the clock control component 828 may be input to the delay line 836. The delay line 836 may include a number of buffers, inverters, and / or other units. Figure 8 836 may be fixed or configurable. For example, a portion of the clock tree may be a delay line. A configurable or trimmable delay line may be used in conjunction with, for example, Figure 1-2B Temperature sensors such as temperature sensors 118 and 218 in the example and Figure 1-2B Design units 122 and 222 provide better temperature compensation when paired.

[0085] The example system 831, which may be referred to as a device in the alternative, includes multiple flip-flops 833-1, 833-2, 833-3, 833-4, 882-1, 882-2, 882-3, 882-4, which are referred to as "latches" 833-1, 833-2, 833-3, 833-4, 882-1, 882-2, 882-3, 882-4 (which are generally referred to as "multiple flip-flops 833 or 882" or "multiple latches 833 or 882", respectively, in this document).

[0086] like Figure 8As shown in , the clock control component 828 is coupled to the flip-flops 833-1, 833-2, 833-3, and 833-4 via a delay line 836. The clock control component 828 can receive a clock signal from a circuit system external to the system 831. In some embodiments, the clock signal is asserted by the clock control component 828 to enable clock gating logic. In general, the "flip-flops" referred to herein are edge-triggered flip-flops (e.g., flip-flops that are edge-triggered devices that respond to the rising or falling edge of a timing signal) or level-sensitive flip-flops (e.g., flip-flops that are level-triggered devices that are transparent to a particular clock signal level and opaque to a different clock signal level). Although Figure 8 A plurality of flip-flops 833 are shown, but examples are not so limited. For example, the example system 831 may include and operate correctly with any sequential cell type latch, such as a flip-flop, a register, a register bank, a memory, and the like.

[0087] Each of the plurality of flip-flops 833, 882 has an edge-triggered clock input (shown as a sideways triangle), a data "D" input gate, a "Q" output gate, and a Q-bar output gate, or both. As discussed herein, the first of the flip-flops 833-1 can be clocked by a delay line 836 at the clock input of the first flip-flop 833-1. In this case, through the "Q" or "Q-bar" output, the flip-flop 833-1 can be the starting point of the critical timing path 829. Similarly, the delay line 836 provides a clock to each of the flip-flops 833-2, 833-3, 833-4. In addition, in this case, from each of the corresponding "Q" or "Q-bar" outputs, each of the flip-flops 833-2, 833-3 is the starting point of the critical timing path 829. Through the "D" input, the flip-flop 833-4 can be the endpoint of the critical timing path 829. Triggers 882 - 1 , 882 - 2 , 882 - 3 , 882 - 4 are part of sensor 885 .

[0088] The sensor 885 includes a plurality of triggers, such as a first trigger 882-1 ("FFs1"), a second trigger 882-2 ("FFs2"), a third trigger 882-3 ("FFs3"), and a fourth trigger 882-4 ("FFs4") (hereinafter collectively referred to as a plurality of triggers 882), a plurality of XOR gates 884-1, 884-2, 884-3, and a first delay line 883-1 and a second delay line 883-2. The output from the clock control component 828 can be connected to the inputs of the trigger 882-1 and the delay line 883-1. The output of the delay line 883-1 can be connected to the clock input of the trigger 882-2. The output from the first delay line 883-1 can be connected to the input of the second delay line 883-2. The output from the second delay line 883-2 can be connected to the clock inputs of the triggers 882-3 and 882-4. The outputs from the Q outputs of flip-flops 882-1 and 882-2 may each be connected to an input of an XOR gate 884-1. The Q data output of flip-flop 882-2 and the Q data output of flip-flop 882-3 may be connected to an input of XOR gate 884-2. The Q data output of flip-flop 882-3 and the Q data output of flip-flop 882-4 may be connected to an input of XOR gate 884-3. The output of XOR gate 884-1 may be connected to an input (“MARGIN”) 840 indicating a margin state, the output of XOR gate 884-2 may be connected to an input (“VIOL”) 881 indicating a timing violation state, and XOR gate 884-3 may be connected to an input (“SENSE”) 839 indicating that margin sensing has occurred. Each of inputs 840, 881, and 839 may be connected to a power management controller 824.

[0089] Fig. 9 An example method 909 for adjustable voltage frequency regulation for critical timing drive according to some embodiments of the present disclosure is shown. Method 909 may be performed by a processing logic that may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the embodiments shown should be understood as examples only, and the processes shown may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all operations are required in every embodiment. Other process flows are possible.

[0090] At block 990, method 909 may include performing multiple sensing operations on a system on a chip (SoC) at corresponding multiple time windows each associated with a specific data value. In a digital logic circuit, a sensing operation refers to a circuit component detecting and responding to a specific digital signal on a line or a specific voltage level on a logic gate input. Sensing can be performed by several components in the circuit, including registers, flip-flops, latches, and other types of elements. Sensing operations can be used in digital circuits to control the behavior of the circuit, thereby allowing the circuit to perform specific tasks, such as making decisions, memory storage, and state control. In general, sensing operations are an important part of digital logic circuits, allowing circuit components to detect and respond to specific signals, thereby making it possible to perform desired tasks. Therefore, in some examples described herein, at least one of the multiple sensing operations is associated with a sensor that is set to arrive at an earlier clock relative to at least another of the multiple sensing operations. In some examples, at least one of the multiple sensing operations is associated with a sensor that is set to arrive at a later data relative to at least another of the multiple sensing operations. In some examples, multiple sensing operations may determine a particular data value stored in a location of a data storage element, such as a flip-flop or latch of a system on a chip (SoC).

[0091] At block 992, method 909 may include comparing at least two of the specific data values ​​associated with at least two corresponding time windows of the plurality of time windows. For example, a first sensing operation may be performed during a first time window associated with a clock cycle of a system on a chip (SoC), and a second sensing operation may be performed during a second time window associated with the clock cycle. The first time window and the second time window may be offset by a specific amount of clock or data timing. The data value sensed during the first sensing operation may be compared with the data value sensed during the second sensing operation. In response to the comparison, the voltage and / or frequency may be adjusted to adjust the margins of the plurality of sensing circuits. The margins may be adjusted so that the setup time and / or the hold time are adjusted so that the sampled data value is accurate or correct and the setup time and / or the hold time are optimal (e.g., the margin is insufficient and the margin is not excessive). For example, in some embodiments, a sampled value of a fourth trigger may be used to determine whether the margin is insufficient, and another sampled value of a different trigger (e.g., the first trigger, the second trigger, and / or the third trigger) may be used to determine whether the margin is excessive. In this manner, the approaches herein may identify whether the margin is optimal or whether the margin is not optimal (eg, excessive or insufficient).

[0092] At block 994, method 909 may include, in response to at least two of the particular data values ​​being the same data value, determining that the clock margin is above a threshold clock margin. In response to determining that the clock margin is above the threshold clock margin, timing of the SoC may be adjusted, a voltage associated with at least one operation of the SoC may be adjusted, a frequency of at least one operation of the SoC may be adjusted, or any combination thereof. For example, in response to determining that the clock margin is above the threshold clock margin, method 909 may include taking remedial action. Examples of remedial action include adjusting a voltage associated with at least one operation of the SoC, adjusting a frequency of at least one operation of the SoC, logging or otherwise storing a record of an occurrence that the clock margin is not optimal (e.g., excessive or insufficient), and / or altering an operating mode of the SoC, such as activating a safety or security protection mechanism intended to prevent data corruption, security breaches, and / or improper operation of the SoC, among other possibilities. For example, in some embodiments, a voltage and / or frequency of at least one operation of the SoC may be adjusted in response to determining that the clock margin is above the threshold clock margin.

[0093] At block 996, the method 909 may include, in response to at least two of the particular data values ​​being different data values, determining that the clock margin is below a threshold clock margin. In some examples, the method 909 may include, in response to determining that the clock margin is below the threshold clock margin, maintaining the same timing of the SoC. In other words, in response to determining that the clock margin is less than the threshold clock margin, the timing of the SoC may be maintained (e.g., the timing of the SoC is not modified).

[0094] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively convey the substance of their work to others skilled in the art. An algorithm is herein and generally considered to be a self-consistent sequence of operations that produce a desired result. Operations are those that require physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Primarily for reasons of common usage, it has proven convenient at times to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0095] It should be borne in mind, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may be directed to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0096] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each of which is connected to a computer system bus.

[0097] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0098] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments of the present disclosure. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

[0099] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively convey the substance of their work to others skilled in the art. An algorithm is herein and generally considered to be a self-consistent sequence of operations that produce a desired result. Operations are those that require physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Primarily for reasons of common usage, it has proven convenient at times to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0100] It should be borne in mind, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may be directed to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0101] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including solid state drives (SSDs), hard disk drives (HDDs), floppy disks, optical disks, CD-ROMs, and magnetic optical disks), read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0102] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with the program according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the method. The structures for various of these systems will be presented as set forth in the description below. In addition, the embodiments of the present disclosure are not described with reference to any particular programming language. It should be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0103] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a machine (e.g., computer) readable form. In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0104] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments of the present disclosure. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A method (909) for adaptive voltage-frequency regulation, comprising: performing a plurality of sensing operations on a system-on-chip (SoC) (110, 210) at a respective plurality of time windows (415, 457), wherein each time window (415, 457) of the plurality of time windows (415, 457) is associated with a particular data value (456, 448); comparing at least two of the specific data values ​​(456, 448) associated with at least two corresponding time windows (415, 457) of the plurality of time windows (415, 457); In response to the at least two of the particular data values ​​(456, 448) being the same data value, determining that a clock margin is above a threshold clock margin; as well as In response to the at least two of the particular data values ​​(456, 448) being different data values, it is determined that the clock margin is below a threshold clock margin.

2. The method of claim 1 , further comprising, in response to determining that the clock margin is above the threshold clock margin, adjusting the timing of the SoC, and in response to determining that the clock margin is below the threshold clock margin, maintaining the same timing of the SoC. 3 . The method of claim 1 , further comprising adjusting a voltage of at least one operation of the SoC in response to determining that the clock margin is above the threshold clock margin. 4 . The method of claim 1 , further comprising adjusting a clocking frequency of at least one operation of the SoC in response to determining that the clock margin is above the threshold clock margin. 5 . The method of claim 1 , further comprising adjusting a voltage and a clocking frequency of at least one operation of the SoC in response to determining that the clock margin is above the threshold clock margin.

6. The method of claim 1 , wherein at least one of the plurality of sensing operations is associated with a sensor configured as: an earlier clock arrival relative to at least another of the plurality of sensing operations; and Late data arrives relative to at least another of the plurality of sensing operations.

7. A device for adaptive voltage and frequency regulation, comprising: A controller (112, 212) configured to: performing a plurality of sensing operations on a system-on-chip (SoC) (110, 210) at a respective plurality of time windows (415, 457), wherein each time window (415, 457) of the plurality of time windows (415, 457) is associated with a particular data value (456, 448); comparing at least two of the particular data values ​​(456, 448) associated with at least two respective time windows of the plurality of time windows (415, 457); In response to the at least two of the particular data values ​​(456, 448) being the same data value, determining that a clock margin is above a threshold clock margin; as well as In response to the at least two of the particular data values ​​(456, 448) being different data values, it is determined that the clock margin is below a threshold clock margin.

8. The apparatus of claim 7, further comprising a sensor for performing the plurality of sensing operations, wherein the sensor comprises a plurality of delay lines and a plurality of flip-flops, wherein at least one of the plurality of delay lines is configured to permit sampling of a data value on at least one of the plurality of flip-flops during a particular time window associated with a timing violation.

9. The apparatus of claim 8, wherein the sensor comprises a plurality of doors.

10. The apparatus of claim 8, wherein a voltage associated with the SoC is adjusted based on the plurality of sensing operations performed by the sensor.

11. The apparatus of any one of claims 7-8, further comprising a plurality of sensors, wherein each of the plurality of sensors is associated with at least one of the plurality of time windows to determine the clock margin.

12. The apparatus of any one of claims 7-8, wherein the controller is configured to perform the plurality of sensing operations using an earlier clock arrival.

13. The apparatus of any one of claims 7-8, wherein the controller is configured to perform the plurality of sensing operations using later data arrivals.

14. A device for adaptive voltage and frequency regulation, comprising: Controller (112, 212); a voltage control component (130, 230) coupled to the controller (112, 212); as well as a clock control component (128, 228) coupled to the controller (112, 212); The controller (112, 212) is configured to: performing a plurality of sensing operations on a system-on-chip (SoC) (110, 210) at a respective plurality of time windows (415, 457), wherein each time window (415, 457) of the plurality of time windows (415, 457) is associated with a particular data value (456, 448); comparing at least two of the specific data values ​​(456, 448) associated with at least two corresponding time windows (415, 457) of the plurality of time windows (415, 457); In response to the at least two of the particular data values ​​(456, 448) being the same data value, determining that a clock margin is above a threshold clock margin and performing a remedial action; as well as In response to the at least two of the particular data values ​​(456, 448) being different data values ​​(456, 448), a clock margin is determined to be below a threshold clock margin and a remedial action is performed.

15. The apparatus of claim 14, wherein the controller is configured to sense the at least two of the particular data values ​​from corresponding flip-flops of a plurality of flip-flops, wherein the plurality of flip-flops includes at least three flip-flops.

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