Data access management method of memory device, memory controller, memory device and electronic device

Abstract

The invention relates to a method for data access management of a memory device in a predetermined communication architecture by means of an unbalanced table update size, a memory controller, a memory device and an electronic device. The method includes: using a memory controller to receive a set of first commands through a host device, using a first active block to receive a set of first data according to the set of first commands, and updating a temporary entity to logical address mapping table corresponding to the first active block; determining a selected table update size among a plurality of predetermined table update sizes according to at least one predetermined rule, wherein the plurality of predetermined table update sizes respectively represent the plurality of table entry counts; and updating at least one logic-to-entity address mapping table in the non-volatile memory according to a group of entity-to-logic table entries corresponding to the select table update size in the temporary entity-to-logic address mapping table for data access.

Description

Technical Field

[0001] The present invention relates to memory control, and more particularly to a method and related device for managing data access of a memory device in a predetermined communication architecture by means of an unbalanced table update size. Background Art

[0002] The memory device may include a flash memory for storing data, and the access management for the flash memory is quite complicated. For example, the memory device may be a memory card, a solid state drive (SSD), or an embedded storage device (e.g., an embedded storage device that complies with the universal flash storage (UFS) specification). The memory device can be used to store different files (e.g., system files and user files). Since some files may be frequently accessed, some data may become invalid data. When invalid data and some valid data are mixed in the same storage block in the memory device, a garbage collection (GC) operation is generally required to release more storage space for further use. In addition, during the access of files, internal management information may change accordingly, which results in an increase in the processing time of the related processing operations of the internal management information. There is no appropriate solution in the related art. Therefore, an innovative method and related architecture are needed to solve these problems without introducing side effects or in a way that is unlikely to introduce side effects. Summary of the invention

[0003] Therefore, one of the objectives of the present invention is to provide a method and related device for managing data access of a memory device in a predetermined communication architecture (eg, a universal flash storage communication architecture) by using an unbalanced table update size to solve the above-mentioned problem.

[0004] According to at least one embodiment of the present invention, a method for managing data access of a memory device in a predetermined communication architecture by using an unbalanced table update size is provided, wherein the method can be applied to a memory controller of the memory device, the memory device can include the memory controller and a non-volatile memory, the non-volatile memory can include at least one non-volatile memory element (e.g., one or more non-volatile memory elements), and the at least one non-volatile memory element can include multiple blocks. The method may include: using a memory controller to receive a set of first commands from a host device through a transmission interface circuit of the memory controller; using a first active block among a plurality of blocks to receive a set of first data according to the set of first commands, and updating a temporary physical-to-logical address mapping table corresponding to the first active block, wherein the set of first commands indicates a request to write the set of first data into the memory device, and the set of first data is written into the first active block; determining a selected table update size from a plurality of predetermined table update sizes according to at least one predetermined rule, wherein the plurality of predetermined table update sizes respectively represent a plurality of table entry counts; and updating at least one logical-to-physical address mapping table in a non-volatile memory according to a set of physical-to-logical table entries in the temporary physical-to-logical address mapping table corresponding to the selected table update size for data access, wherein a table entry count of the set of physical-to-logical table entries is equal to the selected table update size.

[0005] In addition to the above method, the present invention also provides a memory controller of a memory device, wherein the memory device includes a memory controller and a non-volatile memory, the non-volatile memory may include at least one non-volatile memory element (e.g., one or more non-volatile memory elements), and the at least one non-volatile memory element may include multiple blocks. In addition, the memory controller includes a processing circuit, wherein the processing circuit is used to control the memory controller according to multiple host commands from a host device to allow the host device to access the non-volatile memory through the memory controller, and to perform data access management of the memory device in a predetermined communication architecture by updating the size of the unbalanced table. The memory controller also includes a transmission interface circuit, wherein the transmission interface circuit is used to communicate with the host device. For example, a memory controller receives a set of first commands from a host device through a transmission interface circuit of the memory controller, receives a set of first data using a first active block among a plurality of blocks according to the set of first commands, and updates a temporary physical-to-logical address mapping table corresponding to the first active block, wherein the set of first commands indicates a request to write the set of first data into a memory device, and the set of first data is written into the first active block; the memory controller determines a selected table update size from a plurality of predetermined table update sizes according to at least one predetermined rule, wherein the plurality of predetermined table update sizes respectively represent a plurality of table entry counts; and the memory controller updates at least one logical-to-physical address mapping table in a non-volatile memory according to a set of physical-to-logical table entries in the temporary physical-to-logical address mapping table corresponding to the selected table update size for data access, wherein a table entry count of the set of physical-to-logical table entries is equal to the selected table update size.

[0006] In addition to the above method, the present invention also provides a memory device including the above memory controller, wherein the memory device includes: a non-volatile memory for storing information; and a memory controller coupled to the non-volatile memory and used to control the operation of the memory device.

[0007] In addition to the above method, the present invention also provides an electronic device including the above memory device, wherein the electronic device further includes a host device coupled to the memory device. The host device may include: at least one processor for controlling the operation of the host device; and a power supply circuit coupled to the at least one processor and used to provide power to the at least one processor and the memory device. In addition, the memory device provides storage space for the host device.

[0008] According to some embodiments, the device may include at least a portion (e.g., a portion or all) of an electronic device. For example, the device may include a memory controller in a memory device. For another example, the device may include a memory device. For another example, the device may include an electronic device.

[0009] According to some embodiments, a memory device may store data for a host device, wherein some of the stored data needs to be updated. To correct the problems of the prior art, the memory device may be operated according to at least one control scheme (e.g., one or more control schemes) of the method to perform related operations, in particular, an address mapping table in a non-volatile memory is updated according to a temporary address mapping table in a volatile memory in a memory controller, and a table update size is dynamically changed according to multiple entropy determination results of multiple groups of partial data of the received data.

[0010] The method and related apparatus of the present invention can ensure that the memory device can operate properly under different circumstances. For example, the memory device can use an active block to receive data, use a temporary address mapping table to manage the active block, and update the address mapping table in the non-volatile memory according to the temporary address mapping table. In particular, the table update size is dynamically changed to increase the overall performance. In addition, the method and related apparatus of the present invention can solve the problems encountered by the prior art without introducing side effects or in a way that is unlikely to introduce side effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present invention.

[0012] Figure 2 FIG. 4 is a schematic diagram of a first table update control scheme according to an embodiment of the present invention.

[0013] Figure 3A A schematic diagram of a table load operation of a data-entropy-aware table update control scheme for managing data access to a memory device in a predetermined communication architecture using an unbalanced table update size according to an embodiment of the present invention.

[0014] Figure 3B Based on Figure 3A A schematic diagram of at least a first update operation of the data entropy-aware table update control scheme of the illustrated embodiment.

[0015] Figure 3C Based on Figure 3A A schematic diagram of another update operation of the data entropy-aware table update control scheme of the illustrated embodiment.

[0016] Figure 3D Based on Figure 3A A schematic diagram of at least a second update operation of the data entropy-aware table update control scheme of the illustrated embodiment.

[0017] Figure 3E Based on Figure 3A A schematic diagram of yet another update operation of the data entropy-aware table update control scheme of the illustrated embodiment.

[0018] Figure 3F Based on Figure 3A A schematic diagram of the table saving operation of the data entropy-aware table update control scheme of the illustrated embodiment.

[0019] Figure 4 FIG. 4 is a schematic diagram of a table update size control scheme of the method according to an embodiment of the present invention.

[0020] Figure 5 FIG. 4 is a schematic diagram of a workflow of the method according to an embodiment of the present invention.

[0021]

Explanation of symbols

[0022] 10: Electronic devices

[0023] 50: Host device

[0024] 52: Processor

[0025] 54: Power supply circuit

[0026] 58,118: Transmission interface circuit

[0027] 100: memory device

[0028] 110: memory controller

[0029] 112: Microprocessor

[0030] 112C: Program code

[0031] 112M: Read-only memory

[0032] 114: Control logic circuit

[0033] 116: Random Access Memory

[0034] 116R: Reserved random access memory

[0035] 116T: Temporary logical to physical address mapping table

[0036] 117T: Temporary physical to logical address mapping table

[0037] 117TR: Physical to logical address mapping table

[0038] 118C: Universal Flash Storage Controller

[0039] 118U: Standardized communication protocol circuit

[0040] 118M:M physical layer circuit

[0041] 120: Non-volatile memory

[0042] 120T: Global logical to physical address mapping table

[0043] 122-1~122-N: Non-volatile memory element

[0044] 220: Active block

[0045] S11,S12,S13,S14A,S14B,S15,S16,S17,S18,S19,S20,S21,S22,S23: Steps DETAILED DESCRIPTION

[0047] Figure 11 is a schematic diagram of an electronic device 10 according to an embodiment of the present invention, wherein the electronic device 10 may include a host device 50 and a memory device 100. The host device 50 may include at least one processor (e.g., one or more processors; which may be collectively referred to as a processor 52), a power supply circuit 54, and a transmission interface circuit 58, wherein the processor 52 and the transmission interface circuit 58 may be coupled to each other through a bus, and may be coupled to the power supply circuit 54 to obtain power. The processor 52 may be used to control the operation of the host device 50, and the power supply circuit 54 may be used to provide power to the processor 52, the transmission interface circuit 58, and the memory device 100, and output one or more driving voltages to the memory device 100. The memory device 100 may be used to provide storage space for the host device 50, and may obtain one or more driving voltages from the host device 50 as a power supply for the memory device 100. Examples of the host device 50 may include, but are not limited to: a multi-function mobile phone, a tablet computer, a wearable device, and a personal computer, such as a desktop computer and a notebook computer. Examples of the memory device 100 may include, but are not limited to: portable memory devices (e.g., memory cards complying with SD / MMC, CF, MS, or XD specifications), solid state drives (SSDs), and different types of embedded memory devices (e.g., embedded memory devices complying with universal flash storage (UFS) specifications or embedded multi-media card (eMMC) specifications). According to the present embodiment, the memory device 100 may include a controller, such as a memory controller 110, and may further include a non-volatile (NV) memory 120 (for simplicity, in FIG. Figure 1 1, wherein the memory controller 110 is used to access the non-volatile memory 120, and the non-volatile memory 120 is used to store information. The non-volatile memory 120 may include at least one non-volatile memory element (e.g., one or more non-volatile memory elements), such as a plurality of non-volatile memory elements 122-1, 122-2, ..., and 122-N (for simplicity, the non-volatile memory elements 122-1, 122-2, ..., and 122-N are referred to as "NV memory" in FIG. 1 ). Figure 1 , respectively, as “NV memory elements” in the figure), where “N” may represent a positive integer greater than 1. For example, the non-volatile memory 120 may be a flash memory, and the plurality of non-volatile memory elements 122-1, 122-2, . . . , and 122-N may be a plurality of flash memory chips or a plurality of flash memory dies, but the present invention is not limited thereto.

[0048] like Figure 1As shown, the memory controller 110 may include a processing circuit (e.g., a microprocessor 112), a storage unit (e.g., a read-only memory (ROM) 112M; for the sake of brevity, labeled as "ROM"), a control logic circuit 114, a random access memory 116 (random access memory, RAM; for the sake of brevity, labeled as "RAM", for example, it can be implemented by a static random access memory (SRAM), but the present invention is not limited to this) and a transmission interface circuit 118, wherein at least a portion (e.g., a portion or all) of the above components may be coupled to each other via a bus. The random access memory 116 may be used to provide internal storage space for the memory controller 110 (e.g., temporarily storing information). For example, the random access memory 116 may include a retention RAM 116R, wherein the retention RAM 116R may be implemented as a first memory area (e.g., a retention memory area) that can continue to obtain power to retain the stored data when the memory device 100 (or the memory controller 110 therein) is in a power saving state (e.g., a sleep state), but the present invention is not limited to this. In addition, the read-only memory 112M of this embodiment is used to store program code 112C, and the microprocessor 112 is used to execute the program code 112C to control the access of the non-volatile memory 120. It should be noted that the program code 112C may also be stored in the random access memory 116 or any type of memory. In addition, the control logic circuit 114 may be used to control the non-volatile memory 120 and may include an error correction code (ECC) circuit (not shown). Figure 1), which can perform error correction code encoding and error correction code decoding to protect data and / or perform error correction. The transmission interface circuit 118 may include multiple sub-circuits, and the multiple sub-circuits can interact with each other to communicate. The transmission interface circuit 118 may comply with one or more communication specifications among different communication specifications (such as Serial Advanced Technology Attachment (SATA) specification, Universal Serial Bus (USB) specification, Peripheral Component Interconnect Express (PCIe) specification, embedded multimedia card specification or universal flash storage specification), and can be used for the memory device 100 to communicate with the host device 50 (or the transmission interface circuit 58 therein) according to the one or more communication specifications. Similarly, the transmission interface circuit 58 may comply with the one or more communication specifications, and can be used for the host device 50 to communicate with the memory device 100 (or the transmission interface circuit 118 therein) according to the one or more communication specifications. For example, the multiple sub-circuits of the transmission interface circuit 118 may include a universal flash storage controller 118C (labeled as a "UFS controller" for simplicity), a standardized communication protocol (Unified Protocol, commonly referred to as UniPro) circuit 118U (labeled as a "UniPro circuit" for simplicity), and a physical layer (physical layer, PHY) circuit (for example, an M physical layer (M-PHY) circuit 118M that complies with the relevant specifications of the MIPI Alliance), and the transmission interface circuit 58 can be implemented as having a circuit architecture similar to or the same as the circuit architecture of the transmission interface circuit 118 (for example, multiple corresponding sub-circuits), but the present invention is not limited to this.

[0049] In the present embodiment, the host device 50 can indirectly access the non-volatile memory 120 in the memory device 100 by transmitting a plurality of host commands and corresponding logical addresses to the memory controller 110. The memory controller 110 receives the plurality of host commands and corresponding logical addresses, and converts the plurality of host commands into a plurality of memory operation commands (which may be referred to as operation commands), and then uses the plurality of operation commands to control the non-volatile memory 120 to read or write / program memory cells or data pages at specific physical addresses in the non-volatile memory 120, etc., wherein the physical address may be associated with the logical address. For example, the memory controller 110 may generate or update at least one logical-to-physical (L2P) address mapping table to manage the relationship between the physical address and the logical address. The non-volatile memory 120 may store a global logical-to-physical address mapping table 120T for the memory controller 110 to control the memory device 100 to access the data in the non-volatile memory 120, but the present invention is not limited thereto. In addition, the memory controller 110 may generate or update at least one physical-to-logical (P2L) address mapping table. For example, the at least one physical-to-logical address mapping table may include a first physical-to-logical address mapping table (e.g., physical-to-logical address mapping table 117TR). For another example, the at least one physical-to-logical address mapping table may include a backup physical-to-logical address mapping table (not shown) in the non-volatile memory 120. Figure 1 In addition, when necessary, the memory controller 110 may refer to the at least one physical to logical address mapping table to perform certain internal management operations (such as garbage collection (GC) operations).

[0050] For better understanding, the global logical-to-physical address mapping table 120T may be located in a predetermined region (e.g., a system region) within the non-volatile memory element 122-1, but the present invention is not limited thereto. For example, the global logical-to-physical address mapping table 120T may be divided into a plurality of local logical-to-physical address mapping tables, and the plurality of local logical-to-physical address mapping tables may be stored in one or more non-volatile memory elements of the non-volatile memory elements 122-1, 122-2, and 122-N, and in particular, may be stored in the non-volatile memory elements 122-1, 122-2, and 122-N, respectively. When necessary, the memory controller 110 may load at least a portion (e.g., a portion or all) of the global logical-to-physical address mapping table 120T into the random access memory 116 or other memory. For example, the memory controller 110 may load a local logical-to-physical address mapping table (e.g., a first local logical-to-physical address mapping table) from the multiple local logical-to-physical address mapping tables into the random access memory 116 as a temporary logical-to-physical address mapping table 116T for accessing data in the non-volatile memory 120 according to the local logical-to-physical address mapping table stored as the temporary logical-to-physical address mapping table 116T, but the present invention is not limited to this. For example, the memory controller 110 may load the physical-to-logical address mapping table 117TR into a second memory area (e.g., a non-reserved memory area) of the random access memory 116 as a temporary physical-to-logical address mapping table 117T to expand the first physical-to-logical address mapping table from a first size (e.g., size M1) of the physical-to-logical address mapping table 117TR to a second size (e.g., size M2, where M2>M1) of the temporary physical-to-logical address mapping table 117T for performing the above-mentioned internal management operations.

[0051] Since the second memory area (e.g., the non-reserved memory area) is located outside the first memory area (e.g., the reserved memory area), any information in the second memory area may be lost when the memory device (or the memory controller 110 therein) is in a power saving state (e.g., a sleep state). The second memory area (e.g., the non-reserved memory area) may include a plurality of sub-areas for storing different information (e.g., buffered data, a temporary logical-to-physical address mapping table 116T, and a temporary physical-to-logical address mapping table 117T), and at least a portion of the sub-areas of the second memory area (e.g., a portion of the sub-areas or all of the sub-areas) may be considered as a data buffer. For example, a sub-area used to temporarily store buffered data may be considered as a data buffer, but the present invention is not limited thereto. According to some embodiments, the entire second memory area (e.g., the non-reserved memory area), such as a plurality of sub-areas used to temporarily store buffered data, a temporary logical-to-physical address mapping table 116T, and a temporary physical-to-logical address mapping table 117T, may be considered as a data buffer.

[0052] In addition, the at least one non-volatile memory element (e.g., one or more non-volatile memory elements, such as {122-1, 122-2, ..., 122-N}) may include a plurality of blocks, wherein the minimum unit for the memory controller 110 to perform a data erase operation on the non-volatile memory 120 is a block, and the minimum unit for the memory controller 110 to perform a data write operation on the non-volatile memory 120 is a page, but the present invention is not limited thereto. For example, any non-volatile memory element 122-n (the symbol "n" may represent any integer in the interval [1, N]) among the non-volatile memory elements 122-1, 122-2, ..., and 122-N may include a plurality of blocks, and a block within the plurality of blocks may include and record a specific number of pages, wherein the memory controller 110 may access a certain page of a certain block within the plurality of blocks according to a block address and a page address.

[0053] According to some embodiments, the memory controller 110 may configure at least one block (e.g., one or more blocks) among the multiple blocks of the at least one non-volatile memory element (e.g., one or more non-volatile memory elements, such as {122-1, 122-2, ..., 122-N}) in the non-volatile memory 120 as at least one active block (e.g., one or more active blocks) for data buffering and / or data reception, and in particular, utilize the at least one active block to receive data (e.g., host-write data) from the host device 50 for writing into the non-volatile memory 120. For better understanding, the data (e.g., host-write data, such as data to be written into the non-volatile memory 120) may include multiple sets of partial data, and the at least one active block may include a first active block. During the period of receiving the data from the host device 50 (for example, the host writes data, such as data to be written into the non-volatile memory 120), the memory controller 110 may utilize the first active block to receive and store one or more sets of partial data among the multiple sets of partial data according to at least one predetermined rule (for example, one or more predetermined rules), and generate or update a first physical-to-logical address mapping table corresponding to the first active block (for example, the physical-to-logical address mapping table 117TR or the temporary physical-to-logical address mapping table 117T, depending on different control schemes), in particular, record multiple physical-to-logical table entries in the first physical-to-logical address mapping table to indicate the physical-to-logical address mapping relationship for the first active block for subsequent processing, but the present invention is not limited to this. For example, the physical-to-logical address mapping relationship indicated by the plurality of physical-to-logical table entries may represent a physical-to-logical address mapping relationship between a plurality of logical addresses and a plurality of physical addresses, wherein the host device 50 writes one or more sets of partial data into the plurality of logical addresses, and the plurality of physical addresses indicate locations where the one or more sets of partial data are stored in the first active block. When a predetermined criterion is met (e.g., the first active block is completely programmed), the memory controller 110 may perform a set of table processing operations, and the set of table processing operations may include:

[0054] (1) a first table processing operation: updating the global logical-to-physical address mapping table 120T according to the first physical-to-logical address mapping table (e.g., the physical-to-logical address mapping table 117TR or the temporary physical-to-logical address mapping table 117T) corresponding to the first active block, and in particular, updating some logical-to-physical table entries in the global logical-to-physical address mapping table 120T according to a plurality of physical-to-logical table entries in the first physical-to-logical address mapping table to indicate the logical-to-physical address mapping relationship for the first active block;

[0055] (2) a second table processing operation: storing the plurality of physical-to-logical table entries in the temporary physical-to-logical address mapping table 117T in the physical-to-logical address mapping table 117TR; and

[0056] (3) a third table processing operation: after performing the first table processing operation (e.g., updating the global logical-to-physical address mapping table 120T according to the first physical-to-logical address mapping table) and the second table processing operation (e.g., storing the plurality of physical-to-logical table entries in the temporary physical-to-logical address mapping table 117T in the physical-to-logical address mapping table 117TR), clearing the temporary physical-to-logical address mapping table 117T (or the plurality of physical-to-logical table entries therein) for reuse of the corresponding storage space in the temporary physical-to-logical address mapping table 117T and / or the random access memory 116;

[0057] The first table processing operation may include loading a local logical-to-physical address mapping table (e.g., the first local logical-to-physical address mapping table) in the global logical-to-physical address mapping table 120T into the random access memory 116 as a temporary logical-to-physical address mapping table 116T, updating one or more logical-to-physical table entries in the temporary logical-to-physical address mapping table 116T to indicate one or more logical-to-physical address mapping relationships among a plurality of logical-to-physical address mapping relationships for the first active block, and updating the global logical-to-physical address mapping table 120T (or the local logical-to-physical address mapping table therein) according to the temporary logical-to-physical address mapping table 116T, but the present invention is not limited thereto. According to some embodiments, the above-mentioned predetermined standard may be replaced by any one of a plurality of predetermined standards to allow the memory controller 110 to perform the set of table processing operations when any of the above-mentioned standards is met. For example, the plurality of predetermined standards may include:

[0058] (1) One of the above predetermined criteria: the first active block is fully programmed; and

[0059] (2) another predetermined criterion: the number of physical-to-logical table entries recorded in the first physical-to-logical address mapping table reaches a predetermined entry count;

[0060] The predetermined entry count may represent a predetermined table size of the first physical-to-logical address mapping table. For example, when the first active block is completely programmed or the number of physical-to-logical table entries recorded in the first physical-to-logical address mapping table reaches the predetermined entry count, the memory controller 110 may perform the table processing operation.

[0061] For example, after any one of the at least one active block (e.g., the first active block) is completely programmed, the memory device 100 (or the memory controller 110 therein) may close any one of the active blocks to make the active block an inactive block, and select a blank block (e.g., an erased block) as a replacement for any one of the active blocks to receive subsequent data corresponding to the active block. In addition, the subsequent processing may include performing a garbage collection procedure to write valid data from all data in the inactive block to another blank block (e.g., another erased block). According to some embodiments, the at least one predetermined rule may be changed, and the related operations may be changed accordingly. For example, the memory controller 110 may copy a plurality of physical-to-logical table entries from the temporary physical-to-logical address mapping table 117T to the physical-to-logical address mapping table 117TR to generate or update the physical-to-logical address mapping table 117TR according to the temporary physical-to-logical address mapping table 117T.

[0062] According to some embodiments, since the physical-to-logical address mapping relationship indicated by the physical-to-logical table entry in the at least one physical-to-logical address mapping table and the logical-to-physical address mapping relationship indicated by the corresponding logical-to-physical table entry in the global logical-to-physical address mapping table 120T should be inverse address mapping relationships, the memory controller 110 may determine the latest mapping information (e.g., physical address) carried by the corresponding logical-to-physical table entry in the global logical-to-physical address mapping table 120T according to the latest mapping information (e.g., logical address) carried by the physical-to-logical table entry in the at least one physical-to-logical address mapping table. For example, the at least one physical-to-logical address mapping table may include a first physical-to-logical address mapping table (e.g., the physical-to-logical address mapping table 117TR or the temporary physical-to-logical address mapping table 117T). For another example, the at least one physical-to-logical address mapping table may include a backup physical-to-logical address mapping table in the non-volatile memory 120. In some examples, the at least one physical-to-logical address mapping table may include a first physical-to-logical address mapping table and / or a backup physical-to-logical address mapping table in the non-volatile memory 120. In addition, the memory controller 110 may utilize the plurality of local logical-to-physical address mapping tables to manage the relationship between physical addresses and logical addresses (e.g., a physical address indicating a location in the non-volatile memory 120 where host write data is stored and a logical address where the host device 50 writes the host write data). For example, the plurality of local logical-to-physical address mapping tables may be implemented as a series of local logical-to-physical address mapping tables {L2PT(1), L2PT(2), ..., L2PT(X)} corresponding to a series of logical address ranges {L_Addr_R(1), L_Addr_R(2), ..., L_Addr_R(R_CNT)}, respectively, and the series of logical address ranges {L_Addr_R(1), L_Addr_R(2), ..., L_Addr_R(R_CNT)} may be implemented as a series of consecutive logical A series of consecutive ranges of logical addresses {L_Addr(0), L_Addr(1), …, L_Addr((R_CNT*R_Size)-1)}, such as the range of R_CNT intervals [L_Addr(0), L_Addr(R_Size-1)], [L_Addr(R_Size), L_Addr((2*R_Size)-1)], … and [L_Addr((R_CNT-1)*R_Size), L_Addr((R_CNT*R_Size)-1)].

[0063] Figure 2Schematic diagram of a first table update control scheme according to an embodiment of the present invention. For example, the memory controller 110 may utilize a first active block (e.g., active block 220) to receive the plurality of partial data in the host write data (e.g., data to be written into the non-volatile memory 120), and generate or update a first physical-to-logical address mapping table (e.g., physical-to-logical address mapping table 117TR; for the sake of brevity, labeled as “P2L table”) corresponding to the active block 220, and in particular, record a physical-to-logical table entry in the physical-to-logical address mapping table 117TR to indicate the physical-to-logical address mapping relationship for the active block 220. In addition, the memory controller 110 may update the relevant logical-to-physical table entries in the global logical-to-physical address mapping table 120T (labeled as "L2P table" for simplicity) according to the physical-to-logical table entries in the physical-to-logical address mapping table 117TR in units of the first size M1, and in particular, update a group of logical-to-physical table entries in the global logical-to-physical address mapping table 120T according to a group of physical-to-logical table entries in the physical-to-logical address mapping table 117TR when the physical-to-logical address mapping table 117TR is full, wherein the memory controller 110 may remove the group of physical-to-logical table entries (for example, the physical-to-logical table entries used as a reference for updating the group of logical-to-physical table entries) from the physical-to-logical address mapping table 117TR to clear the physical-to-logical address mapping table 117TR so as to reuse the physical-to-logical address mapping table 117TR, but the present invention is not limited to this. According to some embodiments, the memory controller 110 may load physical-to-logical table entries from the physical-to-logical address mapping table 117TR to the temporary physical-to-logical address mapping table 117T to generate or update logical-to-physical table entries in the global logical-to-physical address mapping table 120T according to the temporary physical-to-logical address mapping table 117T.

[0064] FIG. 3A to FIG. 3FSchematic diagrams of a table load operation, at least one first update operation (e.g., one or more first update operations), another update operation, at least one second update operation (e.g., one or more second update operations), another update operation, and a table save operation of a data-entropy-aware table update control scheme for managing data access to a memory device in a predetermined communication architecture using an unbalanced table update size according to an embodiment of the present invention. For example, the memory controller 110 may utilize a first active block (e.g., active block 220) to receive the plurality of partial data in the host write data (e.g., data to be written to the non-volatile memory 120), and generate or update a first physical-to-logical address mapping table (e.g., temporary physical-to-logical address mapping table 117T; for brevity, labeled as “P2L table”) corresponding to the active block 220, and in particular, record a physical-to-logical table entry in the temporary physical-to-logical address mapping table 117T to indicate the physical-to-logical address mapping relationship for the active block 220. In addition, the memory controller 110 may update the relevant logical-to-physical table entries in the global logical-to-physical address mapping table 120T (labeled as “L2P table” for brevity) according to the physical-to-logical table entries in the temporary physical-to-logical address mapping table 117T in units of a selected table update size (e.g., the first size M1 or the second size M2) from among a plurality of predetermined table update sizes (e.g., the first size M1 and the second size M2), in particular, when the physical-to-logical entry count of the latest physical-to-logical table entry in the temporary physical-to-logical address mapping table 117T reaches the selected table update size. In the case of a first size M1 or a second size M2, a set of logical-to-physical table entries in the global logical-to-physical address mapping table 120T is updated according to a set of physical-to-logical table entries in the temporary physical-to-logical address mapping table 117T, wherein the memory controller 110 can remove the set of physical-to-logical table entries (e.g., the physical-to-logical table entries used as a reference for updating the set of logical-to-physical table entries) from the temporary physical-to-logical address mapping table 117T to clear the temporary physical-to-logical address mapping table 117T so as to reuse the temporary physical-to-logical address mapping table 117T.

[0065] At a first time point, the memory controller 110 may perform Figure 3AThe table load operation shown, in particular, can load the physical-to-logical address mapping table 117TR (e.g., the physical-to-logical table entries therein) from the reserved random access memory 116R to the second memory area (e.g., the non-reserved memory area) of the random access memory 116 as a temporary physical-to-logical address mapping table 117T (e.g., the physical-to-logical table entries therein). For better understanding, the first time point can represent the time point when the memory device 100 (or the memory controller 110) wakes up from a power saving state (e.g., a sleep state), wherein there will be no command (CMD) and data from the host device 50 at the first time point, but the present invention is not limited thereto.

[0066] In a first time period after the first time point, the memory controller 110 may utilize the active block 220 to receive at least one set of first partial data having low entropy among the plurality of sets of partial data (eg, one or more sets of first partial data; for simplicity, in Figure 3B ) and update the temporary physical-to-logical address mapping table 117T by recording the corresponding physical-to-logical table entry in the temporary physical-to-logical address mapping table 117T to indicate the physical-to-logical address mapping relationship between the logical address and the physical address of at least one set of the first portion of data (e.g., one or more sets of the first portion of data) in the active block 220. In addition, the memory controller 110 may perform the above Figure 3B At least one first update operation (e.g., one or more first update operations) shown, in particular, may select a table update size (e.g., a second size M2; for the sake of brevity, labeled as "M2") as a unit to update the relevant logical-to-physical table entries in the global logical-to-physical address mapping table 120T (for the sake of brevity, labeled as "L2P table") according to the physical-to-logical table entries in the temporary physical-to-logical address mapping table 117T. Since the memory controller 110 may continue to use the active block 220 to receive the above-mentioned at least one set of first portion data during the first time period and update the temporary physical-to-logical address mapping table 117T accordingly, the physical-to-logical entry count of the physical-to-logical table entries in the temporary physical-to-logical address mapping table 117T may increase accordingly and reach the selected table update size (e.g., the second size M2). In this case, the memory controller 110 may perform the above-mentioned Figure 3B The at least one first update operation is shown to clear the temporary physical-to-logical address mapping table 117T one or more times to reuse the temporary physical-to-logical address mapping table 117T.

[0067] At a first subsequent time point after the first time period, there are no commands and data from the host device 50, and if the physical-to-logical entry count of the latest physical-to-logical table entry in the temporary physical-to-logical address mapping table 117T reaches a first size M1 (labeled as “M1” for brevity), the memory controller 110 may perform Figure 3C Other update operations shown (such as the other update operation described above). At a first subsequent time point, if it is detected that the physical-to-logical entry count reaches the first size M1, the memory controller 110 may update the relevant logical-to-physical table entries in the global logical-to-physical address mapping table 120T (labeled as "L2P table" for brevity) according to the latest physical-to-logical table entries in the temporary physical-to-logical address mapping table 117T, and clear the temporary physical-to-logical address mapping table 117T once to prepare for any possible state transition. For example, there may be a period of time after the first subsequent time point when there are no new commands, and a power saving state (such as a sleep state) may be entered later. Since the memory controller 110 may have expanded the above-mentioned first physical-to-logical address mapping table from the first size M1 to the second size M2 (for example, M2>M1), the memory controller 110 may perform Figure 3C Other update operations shown (such as the other update operation described above) are used to prevent any possible errors.

[0068] In a second time period after the first time point (e.g., after the above-mentioned subsequent time point), the memory controller 110 may utilize the active block 220 to receive at least one set of second partial data having high entropy among the multiple sets of partial data (e.g., one or more sets of second partial data; for simplicity, in Figure 3D The memory controller 110 may further include a physical-to-logical table entry that is marked as “data with high entropy” in the active block 220, and a corresponding physical-to-logical table entry that is recorded in the temporary physical-to-logical address mapping table 117T to update the temporary physical-to-logical address mapping table 117T to indicate the physical-to-logical address mapping relationship between the logical address and the physical address of at least one set of the second portion of data (e.g., one or more sets of the second portion of data) in the active block 220. Figure 3DAt least one second update operation (e.g., one or more second update operations) shown, in particular, updates the relevant logical-to-physical table entries in the global logical-to-physical address mapping table 120T (e.g., labeled as "L2P table" for the sake of brevity) based on the physical-to-logical table entries in the temporary physical-to-logical address mapping table 117T in units of a selected table update size (e.g., a first size M1; labeled as "M1" for the sake of brevity). Since the memory controller 110 can continue to use the active block 220 to receive the above-mentioned at least one set of second portion data during the second time period and update the temporary physical-to-logical address mapping table 117T accordingly, the physical-to-logical entry count of the physical-to-logical table entries in the temporary physical-to-logical address mapping table 117T can be correspondingly increased and reach the selected table update size (e.g., the first size M1). In this case, the memory controller 110 can perform the above-mentioned Figure 3D The at least one second update operation is shown to clear the temporary physical-to-logical address mapping table 117T one or more times to reuse the temporary physical-to-logical address mapping table 117T.

[0069] At a second subsequent time point after the second time period, there may be no commands and data from the host device 50, and if the physical-to-logical entry count of the latest physical-to-logical table entry in the temporary physical-to-logical address mapping table 117T reaches a first size M1 (labeled as “M1” for brevity), the memory controller 110 may perform the above Figure 3E Another update operation is shown. At a second subsequent time point, if it is detected that the physical-to-logical entry count reaches the first size M1, the memory controller 110 may update the relevant logical-to-physical table entries in the global logical-to-physical address mapping table 120T (labeled as "L2P table" for brevity) according to the latest physical-to-logical table entries in the temporary physical-to-logical address mapping table 117T, and clear the temporary physical-to-logical address mapping table 117T once to prepare for any possible state transition. For example, there may be a period of time after the second subsequent time point when there are no new commands, and the power saving state (such as the sleep state) may be entered later. Since the memory controller 110 may have expanded the above-mentioned first physical-to-logical address mapping table from the first size M1 to the second size M2 (for example, M2>M1), no matter which operation was previously performed (for example Figure 3B At least one first update operation or Figure 3D At least one second update operation shown), the memory controller 110 can perform the above Figure 3E Another update operation is shown to prevent any possible errors.

[0070] At a third subsequent time point after the second subsequent time point, there may be no command and data from the host device 50, and the memory controller 110 may perform the above Figure 3F The table save operation shown, in particular, saves the temporary physical-to-logical address mapping table 117T (e.g., the physical-to-logical table entries therein) in the reserved random access memory 116R as the physical-to-logical address mapping table 117TR (e.g., the physical-to-logical table entries therein). For example, at a third subsequent time point, the memory controller 110 may decide to enter a power saving state (e.g., a sleep state).

[0071] According to some embodiments, the at least one predetermined rule may be associated with data classification for a plurality of predetermined data types, and the plurality of predetermined data types may include a first predetermined data type corresponding to a first predetermined entropy range and a second predetermined data type corresponding to a second predetermined entropy range, wherein the plurality of predetermined data types may respectively represent data of different entropy ranges, but the present invention is not limited thereto. For example, the memory controller 110 may perform data classification on the plurality of groups of partial data among the host write data (e.g., data to be written into the non-volatile memory 120) to classify the at least one group of first partial data (e.g., one or more groups of first partial data) as a first predetermined data type (e.g., low entropy data, such as data with low entropy), and classify the at least one group of second partial data (e.g., one or more groups of second partial data) as a second predetermined data type (e.g., high entropy data, such as data with high entropy). In particular, a first predetermined entropy range and a second predetermined entropy range may be defined by a predetermined entropy threshold Eth, and the memory controller 110 may detect that the entropy of the at least one set of the first portion of data is less than the predetermined entropy threshold Eth, and may detect that the entropy of the at least one set of the second portion of data is greater than the predetermined entropy threshold Eth. For example, the first predetermined entropy range may represent a first interval [0, Eth), and the second predetermined entropy range may represent a second interval [Eth, ∞), but the present invention is not limited thereto. For another example, the first predetermined entropy range may represent a first interval [0, Eth], and the second predetermined entropy range may represent a second interval (Eth, ∞). For the sake of brevity, similar contents of these embodiments will not be repeated in detail here.

[0072] According to some embodiments, the operation of the memory device 100 (or the memory controller 110 therein) may include:

[0073] (1) The memory device 100 (or the memory controller 110 therein) may receive a set of first commands from the host device 50 through the transmission interface circuit 118 of the memory controller 110, and utilize a first active block (e.g., the active block 220) to receive a set of first data according to the set of first commands, and update a temporary physical-to-logical address mapping table 117T corresponding to the active block 220, wherein the set of first commands may indicate a request to write the set of first data into the memory device 100;

[0074] (2) The memory device 100 (or the memory controller 110 therein) may determine a selected table update size from a plurality of predetermined table update sizes according to the at least one predetermined rule, wherein the plurality of predetermined table update sizes may respectively represent a plurality of table entry counts; and

[0075] (3) The memory device 100 (or the memory controller 110 therein) may update the at least one logical-to-physical address mapping table (e.g., the global logical-to-physical address mapping table 120T) in the non-volatile memory 120 according to a set of physical-to-logical table entries in the temporary physical-to-logical address mapping table 117T corresponding to the update size of the selection table for data access, wherein the table entry count of the set of physical-to-logical table entries is equal to the update size of the selection table;

[0076] Wherein, when necessary, the memory controller 110 can access data (e.g., the host write data, such as data to be written into the non-volatile memory 120) according to the global logical-to-physical address mapping table 120T, and in particular, the host device 50 can read the host write data already stored in the non-volatile memory 120 according to the relevant logical-to-physical table entries in the global logical-to-physical address mapping table 120T, but the present invention is not limited thereto. According to some embodiments, the memory device 100 (or the memory controller 110 therein) can be used to switch between the plurality of predetermined table update sizes. For example, based on the at least one predetermined rule:

[0077] (1) in response to at least one first predetermined criterion (e.g., one or more first predetermined criteria) being met, the memory controller 110 may update the at least one logical-to-physical address mapping table (e.g., the global logical-to-physical address mapping table 120T) according to the plurality of sets of first physical-to-logical table entries in the temporary physical-to-logical address mapping table 117T in units of a first predetermined table update size (e.g., the first size M1) among the plurality of predetermined table update sizes; and

[0078] (2) In response to meeting at least one second predetermined standard (e.g., one or more second predetermined standards), the memory controller 110 may update the above-mentioned at least one logical-to-physical address mapping table (e.g., the global logical-to-physical address mapping table 120T) according to multiple groups of second physical-to-logical table entries in the temporary physical-to-logical address mapping table 117T in units of a second predetermined table update size (e.g., the second size M2) among the multiple predetermined table update sizes.

[0079] For the sake of brevity, similar contents of these embodiments will not be repeated in detail.

[0080] Figure 4 is a schematic diagram of a table update size control scheme of the method according to an embodiment of the present invention, wherein the table update size control scheme can be based on Figure 4 The table update size control scheme shown is used to operate the memory device 100 (or the memory controller 110 therein).

[0081] In step S11, the memory device 100 (or the memory controller 110 therein) may move the physical-to-logical address mapping table 117TR (e.g., the physical-to-logical table entries therein) from the reserved random access memory 116R to a second memory area (e.g., a non-reserved memory area, such as a data buffer) as a temporary physical-to-logical address mapping table 117T (e.g., the physical-to-logical table entries therein) for performing the above-mentioned internal management operations (for the sake of brevity, labeled as "moving the P2L table from the reserved RAM to the data buffer").

[0082] In step S12, the memory device 100 (or the memory controller 110 therein) may begin to use the first active block (e.g., the active block 220) to receive data (e.g., the host write data, such as data to be written into the non-volatile memory 120; for the sake of brevity, it is labeled as “receiving data from the host device”). In particular, the active block 220 may be used to receive at least one group of partial data among the multiple groups of partial data (e.g., one or more groups of partial data, such as the group of first data). Therefore, the at least one group of partial data (e.g., the group of first data) may be written into the active block 220.

[0083] In step S13, the memory device 100 (or the memory controller 110 therein) may determine a selected table update size from among a plurality of predetermined table update sizes according to the at least one predetermined rule, and in particular, may perform data classification for the plurality of predetermined data types on the at least one group of partial data to determine whether the at least one group of partial data belongs to a first predetermined data type corresponding to a first predetermined entropy range or a second predetermined data type corresponding to a second predetermined entropy range (labeled as “entropy determination” for simplicity), wherein the selected table update size is selected from the plurality of predetermined table update sizes. For better understanding, the first predetermined data type and the second predetermined data type may represent sequential data and non-sequential data, respectively, but the present invention is not limited thereto.

[0084] For example, the memory controller 110 may detect that the entropy of the at least one group of partial data is less than a predetermined entropy threshold Eth, and classify the at least one group of partial data as a first predetermined data type (e.g., continuous data, such as low entropy data; for the sake of brevity, marked as "low"). In this case (e.g., when the memory controller 110 determines that the at least one group of partial data belongs to the first predetermined data type, such as low entropy data), the process proceeds to step S14B. For another example, the memory controller 110 may detect that the entropy of the at least one group of partial data is greater than a predetermined entropy threshold Eth, and classify the at least one group of partial data as a second predetermined data type (e.g., non-continuous data, such as high entropy data; for the sake of brevity, marked as "high"). In this case (e.g., when the memory controller 110 determines that the at least one group of partial data belongs to the second predetermined data type, such as high entropy data), the process proceeds to step S14A.

[0085] In step S14A, the memory device 100 (or the memory controller 110 therein) may select a table update size (e.g., a first size M1) as a unit to update the relevant logical-to-physical table entries in the global logical-to-physical address mapping table 120T according to the physical-to-logical table entries in the temporary physical-to-logical address mapping table 117T (for the sake of brevity, it is marked as "updating the L2P entry according to the P2L entry in units of M1"). In particular, when the physical-to-logical entry count of the latest physical-to-logical table entry in the temporary physical-to-logical address mapping table 117T reaches the selected table update size (e.g., the first size M1), a set of logical-to-physical table entries in the global logical-to-physical address mapping table 120T is updated according to a set of physical-to-logical table entries in the temporary physical-to-logical address mapping table 117T. For example, the operation of step S14A may be similar to or the same as the above-mentioned Figure 3D At least one second update operation (eg, one or more second update operations) is shown.

[0086] In step S14B, the memory device 100 (or the memory controller 110 therein) may select a table update size (e.g., a second size M2) as a unit to update the relevant logical-to-physical table entries in the global logical-to-physical address mapping table 120T according to the physical-to-logical table entries in the temporary physical-to-logical address mapping table 117T (for the sake of brevity, it is marked as "updating the L2P entry according to the P2L entry in units of M2"). In particular, when the physical-to-logical entry count of the latest physical-to-logical table entry in the temporary physical-to-logical address mapping table 117T reaches the selected table update size (e.g., the second size M2), a set of logical-to-physical table entries in the global logical-to-physical address mapping table 120T is updated according to a set of physical-to-logical table entries in the temporary physical-to-logical address mapping table 117T. For example, the operation of step S14B may be similar to or the same as the above-mentioned Figure 3B At least one first update operation (eg, one or more first update operations) is shown.

[0087] In step S15, the memory device 100 (or the memory controller 110 therein) may check whether the operation of receiving data (e.g., host write data, such as data to be written to the non-volatile memory 120) using the first active block (e.g., active block 220) is completed, and if so, proceed to step S16; if not, proceed to step S12.

[0088] In step S16, the memory device 100 (or the memory controller 110 therein) may check whether the physical-to-logical entry count of the latest physical-to-logical table entry in the temporary physical-to-logical address mapping table 117T reaches a first size M1 (labeled as “P2L entry count reaches M1” for brevity), and if so, proceed to step S17; if not, proceed to step S18.

[0089] In step S17, the memory device 100 (or the memory controller 110 therein) may update the relevant logical-to-physical table entry in the global logical-to-physical address mapping table 120T according to the latest physical-to-logical table entry in the temporary physical-to-logical address mapping table 117T, and clear the temporary physical-to-logical address mapping table 117T once (for brevity, marked as "update the L2P entry according to the P2L entry") to prepare for any state transition. For example, the operation of step S17 may be similar to or the same as Figure 3C For example, the operation of step S17 may be similar to or the same as Figure 3EAs shown in the above another updating operation. Since the memory controller 110 may have expanded the above first physical to logical address mapping table from the first size M1 to the second size M2 (e.g., M2>M1), no matter which operation is performed before executing the partial workflow including steps S15 to S17 (e.g., the operation of step S14B or the operation of step S14A), the memory controller 110 may perform the operation of step S17 to prepare for any state transition.

[0090] In step S18, the memory device 100 (or the memory controller 110 therein) may check whether there is any new command from the host device 50, and in particular, may wait for any new command until a predetermined waiting time period ends. If yes (for example, the memory controller 110 receives any new command before the predetermined waiting time period ends), the process proceeds to step S12; if no (for example, the memory controller 110 does not receive any command before the predetermined waiting time period ends), the process proceeds to step S19.

[0091] In step S19, the memory device 100 (or the memory controller 110 therein) may save the temporary physical-to-logical address mapping table 117T (e.g., the physical-to-logical table entries therein) in the reserved random access memory 116R as the physical-to-logical address mapping table 117TR (e.g., the physical-to-logical table entries therein), and may be suspended to enter a power saving state (e.g., a sleep state; for the sake of brevity, labeled as "save the P2L table in the reserved RAM; suspend"). For example, the operation of saving the temporary physical-to-logical address mapping table 117T in the reserved random access memory 116R mentioned in step S19 may be similar to or the same as Figure 3F The table shown saves the operation.

[0092] For example, in response to the occurrence of a predetermined event, the memory device 100 (or the memory controller 110 therein) may be awakened. In this case, the process may proceed to step S11 to prepare for the above-mentioned internal management operation.

[0093] For a better understanding, this method can be Figure 4 The process is illustrated in the flowchart, but the present invention is not limited thereto. According to some embodiments, one or more steps may be performed in Figure 4 Add, delete or modify the workflow shown.

[0094] According to some embodiments, during the operation of step S11 (eg Figure 3A), the temporary physical-to-logical address mapping table 117T may be considered as an enlarged version of the physical-to-logical address mapping table 117TR. In particular, among a plurality of predetermined table update sizes (e.g., a first size M1 and a second size M2), the second predetermined table update size (e.g., the second size M2) is larger than the first predetermined table update size (e.g., the first size M1). For example, the temporary physical-to-logical address mapping table 117T may be used to occupy a memory area of ​​the second predetermined table update size (e.g., the second size M2) in the random access memory 116 within the memory controller 110, wherein the memory controller 110 may have enlarged the above-mentioned first physical-to-logical address mapping table from the first size M1 to the second size M2 (e.g., M2>M1). In addition, before performing the operation of step S19 (e.g., Figure 3F After the table save operation shown in the figure), the physical-to-logical address mapping table 117TR can be regarded as a backup version of the temporary physical-to-logical address mapping table 117T, wherein the backup size of the temporary physical-to-logical address mapping table 117T backed up in the reserved random access memory 116R can be equal to the first predetermined table update size (e.g., the first size M1) among multiple predetermined table update sizes (e.g., the first size M1 and the second size M2). For example, the first predetermined table update size (e.g., the first size M1) can be the minimum value among multiple predetermined table update sizes (e.g., the first size M1 and the second size M2). For the sake of brevity, similar contents of these embodiments will not be repeated in detail.

[0095] According to certain embodiments, during the updating of the at least one logical-to-physical address mapping table (e.g., the global logical-to-physical address mapping table 120T) in the non-volatile memory 120 according to the set of physical-to-logical table entries corresponding to the selected table update size (e.g., the first size M1 or the second size M2) in the temporary physical-to-logical address mapping table 117T, in response to at least one predetermined criterion (e.g., one or more predetermined criteria), the memory controller 110 may update the at least one logical-to-physical address mapping table (e.g., the global logical-to-physical address mapping table 120T) according to a plurality of sets of physical-to-logical table entries in the temporary physical-to-logical address mapping table 117T respectively corresponding to the selected table update size, based on the selected table update size, wherein the set of physical-to-logical table entries corresponding to the selected table update size is a set of physical-to-logical table entries among the plurality of sets of physical-to-logical table entries. For example, the at least one predetermined criterion may represent the at least one first predetermined criterion for entering step S14A, such as the criterion that the entropy of the at least one set of partial data is greater than the predetermined entropy threshold Eth, wherein the memory controller 110 may select a table update size (e.g., a first size M1) as a unit to update the global logical-to-physical address mapping table 120T according to the multiple sets of physical-to-logical table entries (e.g., the multiple sets of first physical-to-logical table entries). For another example, the at least one predetermined criterion may represent the at least one second predetermined criterion for entering step S14B, such as the criterion that the entropy of the at least one set of partial data is less than the predetermined entropy threshold Eth, wherein the memory controller 110 may select a table update size (e.g., a second size M2) as a unit to update the global logical-to-physical address mapping table 120T according to the multiple sets of physical-to-logical table entries (e.g., the multiple sets of second physical-to-logical table entries). For the sake of brevity, similar contents of these embodiments will not be described in detail again.

[0096] Figure 5 is a schematic diagram of the workflow of the method according to an embodiment of the present invention, wherein Figure 5 The illustrated workflow is used to operate the memory device 100 (or the memory controller 110 therein).

[0097] In step S20, the memory device 100 (or the memory controller 110 therein) may receive a set of commands (e.g., the set of first commands) from the host device 50 through the transmission interface circuit 118 of the memory controller 110, and use the first active block (e.g., the active block 220) to receive at least one set of partial data (e.g., the set of first data) according to the set of commands (e.g., the set of first commands), and update the temporary physical-to-logical address mapping table 117T corresponding to the active block 220, wherein the set of commands (e.g., the set of first commands) may indicate a request to write the at least one set of partial data (e.g., the set of first data) into the memory device 100. Therefore, the at least one set of partial data (e.g., the set of first data) may be written into the first active block (e.g., the active block 220). For example, the at least one set of partial data in the operation of the above step S20 may be equal to the at least one set of partial data in the operation of the above step S12.

[0098] In step S21, the memory device 100 (or the memory controller 110 therein) may determine a selected table update size (e.g., the first size M1 or the second size M2) from among a plurality of predetermined table update sizes (e.g., the first size M1 and the second size M2) according to the at least one predetermined rule. For example, the operation of step S21 may be similar to or the same as the operation of step S13, but the present invention is not limited thereto.

[0099] In step S22, the memory device 100 (or the memory controller 110 therein) may read a set of physical-to-logical table entries corresponding to the selected table update size (e.g., the first size M1 or the second size M2) from the temporary physical-to-logical address mapping table 117T, update the at least one logical-to-physical address mapping table (e.g., the global logical-to-physical address mapping table 120T, such as a set of logical-to-physical table entries therein) according to the set of physical-to-logical table entries corresponding to the selected table update size for data access, and remove the set of physical-to-logical table entries from the temporary physical-to-logical address mapping table 117T. For example, the memory controller 110 may determine in step S21 that the selected table update size is equal to the first predetermined table update size (e.g., the first size M1), in which case the operation of step S22 may be similar to or the same as the operation of step S14A. For another example, the memory controller 110 may determine in step S21 that the selected table update size is equal to the second predetermined table update size (eg, the second size M2). In this case, the operation of step S22 may be similar to or the same as the operation of step S14B.

[0100] In step S23, the memory device 100 (or the memory controller 110 therein) may determine whether to perform the next operation according to whether there is any new command (e.g., any new command in the above step S18). If yes (e.g., the memory controller 110 receives any new command before the predetermined waiting time period ends), the process proceeds to step S20; if no (e.g., the memory controller 110 does not receive any command before the predetermined waiting time period ends), the process proceeds to step S21. Figure 5 The illustrated workflow ends. For example, the operation of step S23 may be similar to or identical to the operation of step S18.

[0101] For a better understanding, this method can be Figure 5 The process is illustrated in the flowchart, but the present invention is not limited thereto. According to some embodiments, one or more steps may be performed in Figure 5 Add, delete or modify the workflow shown. For example, Figure 4 The loop including steps S16 and S17 shown can be inserted into Figure 5 In addition, steps S11 and S19 can be added as Figure 5 The new initial step and the new final step in the workflow shown are used to form additional loops (e.g. Figure 4 The maximum loop shown includes steps S11, S19, etc.). For the sake of brevity, similar contents of these embodiments will not be described in detail again.

[0102] According to certain embodiments, any one of the group of first commands may carry first information associated with any one of the data to be written. In particular, any one of the data to be written may include first data corresponding to any one of the commands in the group of first data. Since the group of first commands may indicate a request to write the group of first data into the memory device 100, any one of the commands may indicate a request to write the first data into the memory device 100. For example, the first information associated with any one of the data to be written (e.g., the first data) may include at least one first logical address indicating at least one first logical address area, and any one of the commands may indicate a request to write any one of the data to be written (e.g., the first data) into the at least one first logical address area. In addition, the memory device 100 (or the memory controller 110 therein) may perform a first check operation (e.g., the operation of step S13) on the first information to generate a first judgment result (e.g., the judgment result of step S13 for the first data is "high", or the judgment result of step S13 for the first data is "low") for determining the selection table update size, wherein the first judgment result may indicate that the first data belongs to a predetermined data type among the plurality of predetermined data types (e.g., the first predetermined data type or the second predetermined data type). For example, the first judgment result may represent a judgment result of step S13 for the first data is "high", which indicates that the first data belongs to the second predetermined data type (e.g., high entropy data). In this case, in response to the first judgment result (e.g., the judgment result of step S13 for the first data is "high"), the memory controller 110 may determine that the selection table update size is equal to the first predetermined table update size (e.g., the first size M1). For another example, the first judgment result may represent a judgment result of step S13 for the first data of "low", which indicates that the first data belongs to a first predetermined data type (e.g., low entropy data). In this case, in response to the first judgment result (e.g., the judgment result of step S13 for the first data of "low"), the memory controller 110 may determine that the selected table update size is equal to the second predetermined table update size (e.g., the second size M2). In addition, the memory controller 110 may be used to generate the first judgment result based on the at least one first logical address mentioned above, but the present invention is not limited to this. According to some embodiments, the first information may further include a first data length of the first data, and the memory controller 110 may be used to generate the first judgment result based on the first data length. For the sake of brevity, similar contents of these embodiments will not be repeated in detail here.

[0103] According to some embodiments, the memory controller 110 may record a null entry having a preset value (e.g., a predetermined value that does not indicate any mapping information) in the first physical-to-logical address mapping table (e.g., the physical-to-logical address mapping table 117TR or the temporary physical-to-logical address mapping table 117T) as a cleared entry to indicate that the location where the null entry is recorded has been cleared for further use, wherein the memory controller 110 may record a new entry at the location later when necessary, but the present invention is not limited thereto. For the sake of brevity, similar contents of these embodiments will not be described in detail again.

[0104] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A method for managing data access of a memory device in a predetermined communication architecture by updating a size of an unbalanced table, the method being applied to a memory controller of the memory device, the memory device comprising the memory controller and a non-volatile memory, the non-volatile memory comprising at least one non-volatile memory element, the at least one non-volatile memory element comprising a plurality of blocks, the method comprising: Using the memory controller to receive a set of first commands from a host device through a transmission interface circuit of the memory controller, using a first active block among the plurality of blocks to receive a set of first data according to the set of first commands, and updating a temporary physical-to-logical address mapping table corresponding to the first active block, wherein the set of first commands indicates a request to write the set of first data into the memory device, and the set of first data is written into the first active block; determining a selected table update size from a plurality of predetermined table update sizes according to at least one predetermined rule, wherein the plurality of predetermined table update sizes respectively represent a plurality of table entry counts; as well as At least one logical-to-physical address mapping table in the non-volatile memory is updated according to a set of physical-to-logical table entries in the temporary physical-to-logical address mapping table corresponding to the selection table update size for data access, wherein a table entry count of the set of physical-to-logical table entries is equal to the selection table update size.

2. The method according to claim 1, characterized in that , a backup size of backing up the temporary entity to logical address mapping table is equal to a first predetermined table update size among the multiple predetermined table update sizes.

3. The method according to claim 2, characterized in that , the first predetermined table update size is a minimum value of the multiple predetermined table update sizes.

4. The method according to claim 2, characterized in that , a second predetermined table update size among the multiple predetermined table update sizes is larger than the first predetermined table update size; and the temporary physical to logical address mapping table is used to occupy a memory area of ​​the second predetermined table update size in a random access memory within the memory controller.

5. The method according to claim 1, characterized in that The step of updating the at least one logical to physical address mapping table in the non-volatile memory according to the set of physical to logical table entries corresponding to the selection table update size in the temporary physical to logical address mapping table further comprises: In response to reaching at least one predetermined criterion, the at least one logical-to-physical address mapping table in the non-volatile memory is updated based on multiple groups of physical-to-logical table entries in the temporary physical-to-logical address mapping table that respectively correspond to the selection table update size, with the selection table update size as a unit, wherein the group of physical-to-logical table entries is a group of physical-to-logical table entries among the multiple groups of physical-to-logical table entries.

6. The method according to claim 1, characterized in that , the memory controller is used to switch between the plurality of predetermined table update sizes, wherein: In response to meeting at least a first predetermined criterion, the memory controller updates the at least one logical-to-physical address mapping table according to a plurality of first physical-to-logical table entries in the temporary physical-to-logical address mapping table in units of a first predetermined table update size among the plurality of predetermined table update sizes; and In response to meeting at least a second predetermined criterion, the memory controller updates the at least one logical-to-physical address mapping table according to multiple sets of second physical-to-logical table entries in the temporary physical-to-logical address mapping table in units of a second predetermined table update size among the plurality of predetermined table update sizes.

7. The method according to claim 1, characterized in that , the at least one predetermined rule is associated with data classification for a plurality of predetermined data types; any one of the group of first commands carries first information associated with any one of the data to be written, the any one of the data to be written contains first data in the group of first data corresponding to the any one of the commands, the first information includes at least one first logical address for indicating at least one first logical address region, and the any one of the commands indicates a requirement to write the any one of the data to be written into the at least one first logical address region; And the method further includes: A first check operation is performed on the first information to generate a first judgment result for determining the update size of the selection table, wherein the first judgment result indicates whether the first data belongs to a predetermined data type among the plurality of predetermined data types.

8. The method according to claim 7, characterized in that The first information further includes a first data length of the first data, and the memory controller is used to generate the first judgment result according to the first data length.

9. The method according to claim 7, characterized in that , the memory controller is used to generate the first judgment result according to the at least one first logical address.

10. The method according to claim 1, characterized in that , the at least one predetermined rule is associated with data classification for multiple predetermined data types, and the multiple predetermined data types include a first predetermined data type and a second predetermined data type, wherein the first predetermined data type and the second predetermined data type represent continuous data and non-continuous data, respectively.

11. The method according to claim 1, characterized in that , the at least one predetermined rule is associated with data classification for multiple predetermined data types, and the multiple predetermined data types include a first predetermined data type corresponding to a first predetermined entropy range and a second predetermined data type corresponding to a second predetermined entropy range, wherein the multiple predetermined data types respectively represent data of different entropy ranges.

12. The method according to claim 1, characterized in that The step of updating the at least one logical to physical address mapping table in the non-volatile memory according to the set of physical to logical table entries corresponding to the selection table update size in the temporary physical to logical address mapping table further comprises: reading the set of physical-to-logical table entries corresponding to the selection table update size from the temporary physical-to-logical address mapping table; updating a set of logical-to-physical table entries in the at least one logical-to-physical address mapping table according to the set of physical-to-logical table entries; and The set of physical-to-logical table entries is removed from the temporary physical-to-logical address mapping table.

13. A memory controller of a memory device, the memory device comprising the memory controller and a non-volatile memory, the non-volatile memory comprising at least one non-volatile memory element, the at least one non-volatile memory element comprising a plurality of blocks, the memory controller comprising: a processing circuit for controlling the memory controller according to a plurality of host commands from a host device to allow the host device to access the non-volatile memory through the memory controller, wherein the processing circuit is used to perform data access management of the memory device in a predetermined communication architecture by means of an unbalanced table update size; as well as a transmission interface circuit for communicating with the host device; in: The memory controller receives a set of first commands from the host device through the transmission interface circuit of the memory controller, receives a set of first data using a first active block among the plurality of blocks according to the set of first commands, and updates a temporary physical-to-logical address mapping table corresponding to the first active block, wherein the set of first commands indicates a request to write the set of first data into the memory device, and the set of first data is written into the first active block; The memory controller determines a selected table update size from a plurality of predetermined table update sizes according to at least one predetermined rule, wherein the plurality of predetermined table update sizes represent a plurality of table entry counts respectively; and The memory controller updates at least one logical-to-physical address mapping table in the non-volatile memory according to a set of physical-to-logical table entries in the temporary physical-to-logical address mapping table corresponding to the selection table update size for data access, wherein a table entry count of the set of physical-to-logical table entries is equal to the selection table update size.

14. A memory device comprising the memory controller according to claim 13, wherein the memory device comprises: The non-volatile memory is used to store information; and The memory controller is coupled to the non-volatile memory and is used to control the operation of the memory device.

15. An electronic device comprising the memory device of claim 14, and further comprising: The host device is coupled to the memory device, wherein the host device includes: at least one processor for controlling the operation of the host device; as well as a power supply circuit coupled to the at least one processor and configured to provide power to the at least one processor and the memory device; The memory device provides storage space for the host device.

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