Method of data access management of a memory device, memory controller, memory device, and electronic device

Abstract

The present invention relates to a method for data access management of a memory device in a predetermined communication architecture by means of non-equilibrium table update size, a memory controller, a memory device and an electronic device. The method of the present invention comprises: receiving a set of first commands from a host device by means of a memory controller, receiving a set of first data by means of a first active block according to the set of first commands, and updating a temporary physical-to-logical address mapping table corresponding to the first active block; determining a selected table update size among a plurality of predetermined table update sizes according to at least one predetermined rule, wherein the plurality of predetermined table update sizes respectively represent a plurality of table entry counts; and updating at least one logical-to-physical address mapping table in a non-volatile memory according to a set of physical-to-logical table entries corresponding to the selected table update size in the temporary physical-to-logical address mapping table for data access.

Description

Technical Field

[0001] This invention relates to memory control, and more particularly to a method and related apparatus for managing data access to a memory device in a predetermined communication architecture by means of updating the size of an unbalanced table. Background Technology

[0002] Memory devices may include flash memory for storing data, and the access management of flash memory is quite complex. For example, a memory device can be a memory card, a solid-state drive (SSD), or an embedded storage device (such as an embedded storage device conforming to the Universal Flash Storage (UFS) specification). Memory devices can be used to store different files (such as system files and user files). Because some files may be accessed frequently, some data may become invalid. When invalid data is mixed with some valid data in the same storage block within the memory device, garbage collection (GC) operations are generally required to free up more storage space for further use. Furthermore, during file access, internal management information may change accordingly, leading to an increase in the processing time of related internal management information processing operations. There are no suitable solutions in the relevant technologies; therefore, an innovative method and related architecture are needed to solve these problems without introducing side effects or in a way that is unlikely to introduce side effects. Summary of the Invention

[0003] Therefore, one of the objectives of this invention is to provide a method and related apparatus for managing data access to memory devices in a predetermined communication architecture (e.g., a general flash memory communication architecture) by means of updating the size of an unbalanced table, in order to solve the above-mentioned problems.

[0004] According to at least one embodiment of the present invention, a method is provided for data access management of a memory device in a predetermined communication architecture by means of an unbalanced table update size, wherein the method can be applied to a memory controller of the memory device, the memory device may include a memory controller and a non-volatile memory, the non-volatile memory may include at least one non-volatile memory element (e.g., one or more non-volatile memory elements), and the at least one non-volatile memory element may include a plurality of blocks. The method may include: receiving a set of first commands from a host device via a transmission interface circuit of a memory controller; receiving a set of first data using a first active block among a plurality of blocks according to the set of first commands; and updating a temporary entity-to-logical address mapping table corresponding to the first active block, wherein the set of first commands indicates that the set of first data is written to a memory device, and the set of first data is written to the first active block; determining a selectable table update size among a plurality of predetermined table update sizes according to at least one predetermined rule, wherein the plurality of predetermined table update sizes represent a plurality of table entry counts; and updating at least one logical-to-entity address mapping table in non-volatile memory for data access based on a set of entity-to-logical table entries in the temporary entity-to-logical address mapping table corresponding to the selectable table update size, wherein the table entry count of the set of entity-to-logical table entries is equal to the selectable table update size.

[0005] In addition to the methods described above, the present invention also provides a memory controller for a memory device, wherein the memory device includes a memory controller and a non-volatile memory. The non-volatile memory may include at least one non-volatile memory element (e.g., one or more non-volatile memory elements), and the at least one non-volatile memory element may include multiple blocks. Furthermore, the memory controller includes processing circuitry configured to control the memory controller according to multiple host commands from a host device, allowing the host device to access the non-volatile memory through the memory controller and to perform data access management of the memory device in a predetermined communication architecture by updating the size using an unbalanced table. The memory controller further includes a transmission interface circuitry configured to communicate with the host device. For example, the memory controller receives a set of first commands from the host device through the memory controller's transmission interface circuitry. Based on the set of first commands, it uses a first active block among multiple blocks to receive a set of first data and updates a temporary entity-to-logical address mapping table corresponding to the first active block. The set of first commands instructs that the set of first data be written to the memory device, and the set of first data is written to the first active block. The memory controller determines a select table update size among multiple predetermined table update sizes according to at least one predetermined rule. The multiple predetermined table update sizes represent multiple table entry counts. The memory controller updates at least one logical-to-entity address mapping table in non-volatile memory based on a set of entity-to-logical table entries in the temporary entity-to-logical address mapping table corresponding to the select table update size for data access. The table entry count of the set of entity-to-logical table entries is equal to the select table update size.

[0006] In addition to the methods described above, the present invention also provides a memory device including the memory controller described above, wherein the memory device includes: a non-volatile memory for storing information; and a memory controller coupled to the non-volatile memory and used to control the operation of the memory device.

[0007] In addition to the methods described above, the present invention also provides an electronic device including the aforementioned memory device, wherein the electronic device further includes a host device coupled to the memory device. The host device may include: at least one processor for controlling the operation of the host device; and a power supply circuit coupled to the at least one processor for providing power to the at least one processor and the memory device. Furthermore, the memory device provides storage space to the host device.

[0008] According to some embodiments, the device may include at least a portion (e.g., a portion or all) of an electronic device. For example, the device may include a memory controller within a memory device, or the device may include a memory device, or the device may include an electronic device.

[0009] According to some embodiments, the memory device can store data for a host device, wherein some data in the stored data needs to be updated. To correct the problems of the prior art, the memory device can be operated to perform related operations according to at least one control scheme (e.g., one or more control schemes) of the method, in particular, updating an address mapping table in a non-volatile memory according to a temporary address mapping table in a volatile memory within a memory controller, and dynamically changing the table update size according to multiple entropy judgment results of multiple sets of partial data of received data.

[0010] The method and related apparatus of the present invention ensure that the memory device can operate appropriately under various conditions. For example, the memory device can utilize an active block for data reception, manage the active block using a temporary address mapping table, and update the address mapping table in non-volatile memory according to the temporary address mapping table. In particular, the table update size can be dynamically changed to increase overall performance. Furthermore, the method and related apparatus of the present invention can solve the problems encountered in the prior art without introducing side effects or in a way that is unlikely to introduce side effects. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of an electronic device according to an embodiment of the present invention.

[0012] Figure 2 This is a schematic diagram of a first table update control scheme according to an embodiment of the present invention.

[0013] Figure 3A This is a schematic diagram of the table loading operation of a data-entropy-aware table update control scheme according to an embodiment of the present invention, which uses an unbalanced table to update the size of the update and manage the data access of a memory device in a predetermined communication architecture.

[0014] Figure 3B Based on Figure 3A The diagram illustrates at least one first update operation of the data entropy sensing table update control scheme of the embodiment shown.

[0015] Figure 3C Based on Figure 3A This is a schematic diagram of another update operation of the data entropy sensing table update control scheme in the illustrated embodiment.

[0016] Figure 3D Based on Figure 3A The diagram illustrates at least one second update operation of the data entropy sensing table update control scheme in the embodiment shown.

[0017] Figure 3E Based on Figure 3A The diagram illustrates another update operation of the data entropy sensing table update control scheme in the illustrated embodiment.

[0018] Figure 3F Based on Figure 3A The diagram illustrates the table saving operation of the data entropy-aware table update control scheme in the embodiment shown.

[0019] Figure 4 This is a schematic diagram of a table update size control scheme according to an embodiment of the present invention.

[0020] Figure 5 This is a schematic diagram illustrating the workflow of a method according to an embodiment of the present invention.

[0021] [Symbol Explanation]

[0022] 10: Electronic devices

[0023] 50: Main unit

[0024] 52: Processor

[0025] 54: Power Supply Circuit

[0026] 58,118: Transmission interface circuit

[0027] 100: Memory device

[0028] 110: Memory controller

[0029] 112: Microprocessor

[0030] 112C: Program Code

[0031] 112M: Read-Only Memory

[0032] 114: Control Logic Circuit

[0033] 116: Random Access Memory

[0034] 116R: Reserved Random Access Memory

[0035] 116T: Temporary Logic to Entity Address Mapping Table

[0036] 117T: Temporary Entity to Logical Address Mapping Table

[0037] 117TR: Entity-to-Logical Address Mapping Table

[0038] 118C: Universal Flash Storage Controller

[0039] 118U: Standardized Communication Protocol Circuit

[0040] 118M:M physical layer circuit

[0041] 120: Non-volatile memory

[0042] 120T: Global Logical to Entity Address Mapping Table

[0043] 122-1~122-N: Non-volatile memory elements

[0044] 220: Active Block

[0045] S11, S12, S13, S14A, S14B, S15, S16, S17, S18, S19, S20, S21, S22, S23: Steps Background Technology Detailed Implementation

[0047] Figure 1This is a schematic diagram of an electronic device 10 according to an embodiment of the present invention, wherein the electronic device 10 may include a host device 50 and a memory device 100. The host device 50 may include at least one processor (e.g., one or more processors; collectively referred to as processor 52), a power supply circuit 54, and a transmission interface circuit 58, wherein the processor 52 and the transmission interface circuit 58 may be coupled to each other via a bus and may be coupled to the power supply circuit 54 to obtain power. The processor 52 may be used to control the operation of the host device 50, and the power supply circuit 54 may be used to provide power to the processor 52, the transmission interface circuit 58, and the memory device 100, and output one or more drive voltages to the memory device 100. The memory device 100 may be used to provide storage space to the host device 50 and may obtain one or more drive voltages from the host device 50 as power for the memory device 100. Examples of the host device 50 may include, but are not limited to, multi-functional mobile phones, tablet computers, wearable devices, and personal computers, such as desktop computers and laptop computers. Examples of memory device 100 may include, but are not limited to: portable memory devices (e.g., memory cards conforming to SD / MMC, CF, MS, or XD specifications), solid-state drives (SSDs), and different types of embedded memory devices (e.g., embedded memory devices conforming to universal flash storage (UFS) or embedded multimedia card (eMMC) specifications). According to this embodiment, memory device 100 may include a controller, such as memory controller 110, and may further include non-volatile (NV) memory 120 (for simplicity, NV memory 120 is referred to as such in the original text). Figure 1 (Referring to "NV memory"), wherein the memory controller 110 is used to access the non-volatile memory 120, and the non-volatile memory 120 is used to store information. The non-volatile memory 120 may include at least one non-volatile memory element (e.g., one or more non-volatile memory elements), such as a plurality of non-volatile memory elements 122-1, 122-2, ..., and 122-N (for simplicity, ... Figure 1 The non-volatile memory 120 can be a flash memory, and the multiple non-volatile memory elements 122-1, 122-2, ..., and 122-N can be multiple flash memory wafers or multiple flash memory dies, but the present invention is not limited thereto.

[0048] like Figure 1As shown, the memory controller 110 may include a processing circuit (e.g., a microprocessor 112), a storage unit (e.g., a read-only memory (ROM) 112M; for simplicity, it is labeled "ROM"), a control logic circuit 114, a random access memory (RAM; for simplicity, it is labeled "RAM", for example, it can be implemented by static random access memory (SRAM), but the invention is not limited thereto), and a transmission interface circuit 118, wherein at least a portion (e.g., some or all) of the above components can be coupled to each other via a bus. Random access memory 116 can be used to provide internal storage space to memory controller 110 (e.g., to temporarily store information). For example, random access memory 116 may include retention RAM 116R, which can be implemented as a first memory region (e.g., a retention memory region) that can continuously receive power to retain stored data when memory device 100 (or its memory controller 110) is in a power-saving state (e.g., a sleep state). However, the invention is not limited to this. Furthermore, read-only memory 112M in this embodiment is used to store program code 112C, and microprocessor 112 is used to execute program code 112C to control access to non-volatile memory 120. Note that program code 112C can also be stored in random access memory 116 or any type of memory. Additionally, control logic circuitry 114 can be used to control non-volatile memory 120 and may include an error correction code (ECC) circuit (not shown). Figure 1The transmission interface circuit 118 can perform error correction code encoding and decoding to protect data and / or perform error correction. The transmission interface circuit 118 may include multiple sub-circuits, and these sub-circuits can interact with each other to communicate. The transmission interface circuit 118 may conform to one or more communication specifications (e.g., Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCIe), Embedded Multimedia Card, or Universal Flash Storage), and can enable the memory device 100 to communicate with the host device 50 (or its transmission interface circuit 58) according to these one or more communication specifications. Similarly, the transmission interface circuit 58 may conform to these one or more communication specifications, and can enable the host device 50 to communicate with the memory device 100 (or its transmission interface circuit 118) according to these one or more communication specifications. For example, the plurality of sub-circuits of the transmission interface circuit 118 may include a universal flash storage controller 118C (referred to as "UFS controller" for simplicity), a standardized communication protocol (UniPro) circuit 118U (referred to as "UniPro circuit" for simplicity), and a physical layer (PHY) circuit (e.g., an M-PHY circuit 118M conforming to relevant MIPI Alliance specifications). The transmission interface circuit 58 may be implemented with a circuit architecture similar to or the same as that of the transmission interface circuit 118 (e.g., a plurality of corresponding sub-circuits), but the present invention is not limited thereto.

[0049] In this embodiment, the host device 50 can indirectly access the non-volatile memory 120 within the memory device 100 by transmitting multiple host commands and corresponding logical addresses to the memory controller 110. The memory controller 110 receives multiple host commands and corresponding logical addresses, and converts each host command into multiple memory operation commands (which can be simply referred to as operation commands). The multiple operation commands are then used to control the non-volatile memory 120 to read, write / program, etc., memory cells or data pages at specific physical addresses within the non-volatile memory 120, where physical addresses can be associated with logical addresses. For example, the memory controller 110 can generate or update at least one logical-to-physical (L2P) address mapping table to manage the relationship between physical addresses and logical addresses. The non-volatile memory 120 can store a global logical-to-physical address mapping table 120T for the memory controller 110 to control the memory device 100 to access data in the non-volatile memory 120. However, the present invention is not limited to this. Furthermore, the memory controller 110 can generate or update at least one physical-to-logical (P2L) address mapping table. For example, the at least one P2L address mapping table may include a first physical-to-logical address mapping table (e.g., physical-to-logical address mapping table 117TR). Alternatively, the at least one P2L address mapping table may include a backup physical-to-logical address mapping table in the non-volatile memory 120 (not shown in the diagram). Figure 1 (In the middle), such as a backup version of the first entity-to-logical address mapping table. In addition, when needed, the memory controller 110 may refer to the above-mentioned at least one entity-to-logical address mapping table to perform certain internal management operations (such as garbage collection (GC) operations).

[0050] For better understanding, the global logic-to-physical address mapping table 120T may be located in a predetermined region (e.g., a system region) within the non-volatile memory element 122-1, but the invention is not limited thereto. For example, the global logic-to-physical address mapping table 120T may be divided into multiple local logic-to-physical address mapping tables, and these multiple local logic-to-physical address mapping tables may be stored in one or more non-volatile memory elements 122-1, 122-2, and 122-N, in particular, they may be stored in non-volatile memory elements 122-1, 122-2, and 122-N respectively. When needed, the memory controller 110 may load at least a portion (e.g., part or all) of the global logic-to-physical address mapping table 120T into the random access memory 116 or other memory. For example, the memory controller 110 may load one of the plurality of local logic-to-physical address mapping tables (e.g., a first local logic-to-physical address mapping table) into the random access memory 116 as a temporary logic-to-physical address mapping table 116T, so that data in the non-volatile memory 120 can be accessed according to the local logic-to-physical address mapping table stored as the temporary logic-to-physical address mapping table 116T. However, the present invention is not limited thereto. For example, the memory controller 110 may load the entity-to-logical address mapping table 117TR into a second memory region (e.g., a non-reserved memory region) of the random access memory 116 as a temporary entity-to-logical address mapping table 117T, and expand the first entity-to-logical address mapping table from a first size (e.g., size M1) of the entity-to-logical address mapping table 117TR to a second size (e.g., size M2, where M2>M1) of the temporary entity-to-logical address mapping table 117T for the aforementioned internal management operations.

[0051] Because the second memory region (e.g., a non-reserved memory region) is located outside the first memory region (e.g., a reserved memory region), any information in the second memory region may be lost when the memory device (or its memory controller 110) is in a power-saving state (e.g., a sleep state). The second memory region (e.g., a non-reserved memory region) may include multiple sub-regions for storing different information (e.g., buffered data, a temporary logical-to-physical address mapping table 116T, and a temporary physical-to-logical address mapping table 117T), and at least a portion of the sub-regions of the second memory region (e.g., a portion or all of the sub-regions) can be considered as a data buffer. For example, a sub-region used to temporarily store buffered data can be considered a data buffer, but the invention is not limited thereto. According to some embodiments, the entire second memory region (e.g., the non-reserved memory region), such as the multiple sub-regions used to temporarily store buffered data, the temporary logical-to-physical address mapping table 116T, and the temporary physical-to-logical address mapping table 117T, can be considered as a data buffer.

[0052] Furthermore, the aforementioned at least one non-volatile memory element (e.g., one or more non-volatile memory elements, such as {122-1, 122-2, ..., 122-N}) may contain multiple blocks, wherein the smallest unit for the memory controller 110 to perform data erasure operations on the non-volatile memory 120 is a block, and the smallest unit for the memory controller 110 to perform data write operations on the non-volatile memory 120 is a page; however, the present invention is not limited thereto. For example, any one of the non-volatile memory elements 122-1, 122-2, ..., and 122-N, 122-n (the symbol “n” can represent any integer in the interval [1, N]), may contain multiple blocks, and one block within these multiple blocks may contain and record a specific number of pages, wherein the memory controller 110 may access a specific page of a specific block within these multiple blocks according to a block address and a page address.

[0053] According to some embodiments, the memory controller 110 may configure at least one block (e.g., one or more blocks) of the plurality of blocks of the at least one non-volatile memory element (e.g., one or more non-volatile memory elements, such as {122-1, 122-2, ..., 122-N}) in the non-volatile memory 120 as at least one active block for data buffering and / or data reception, in particular, to receive data (e.g., host-write data) from the host device 50 for writing to the non-volatile memory 120 using the at least one active block. For better understanding, the data (e.g., host-write data, such as data to be written to the non-volatile memory 120) may include multiple sets of partial data, and the at least one active block may include a first active block. During the period when the host device 50 receives the data (e.g., host write data, such as data to be written to non-volatile memory 120), the memory controller 110 may use the first active block to receive and store one or more sets of partial data according to at least one predetermined rule (e.g., one or more predetermined rules), and generate or update a first entity-to-logic address mapping table (e.g., entity-to-logic address mapping table 117TR or temporary entity-to-logic address mapping table 117T, depending on the control scheme) corresponding to the first active block. In particular, multiple entity-to-logic table entries are recorded in the first entity-to-logic address mapping table to indicate the entity-to-logic address mapping relationship for the first active block for subsequent processing, but the invention is not limited thereto. For example, the entity-to-logical address mappings indicated by the multiple entity-to-logical table entries can represent entity-to-logical address mappings between multiple logical addresses and multiple entity addresses, wherein the host device 50 writes one or more sets of partial data into the multiple logical addresses, and the multiple entity addresses indicate the location of the one or more sets of partial data stored in the first active block. When a predetermined criterion is met (e.g., the first active block is fully programmed), the memory controller 110 can perform a set of table processing operations, and the set of table processing operations may include:

[0054] (1) A first table processing operation: Update the global logical-to-entity address mapping table 120T according to the first entity-to-logical address mapping table (e.g., entity-to-logical address mapping table 117TR or temporary entity-to-logical address mapping table 117T) corresponding to the first active block. In particular, update certain logical-to-entity table entries in the global logical-to-entity address mapping table 120T according to multiple entity-to-logical table entries in the first entity-to-logical address mapping table to indicate logical-to-entity address mapping relationships for the first active block.

[0055] (2) Second table processing operation: Store multiple entity-to-logical table entries in the temporary entity-to-logical address mapping table 117T in the entity-to-logical address mapping table 117TR; and

[0056] (3) A third table processing operation: After performing the first table processing operation (e.g., updating the global logical-to-entity address mapping table 120T according to the first entity-to-logical address mapping table) and the second table processing operation (e.g., storing multiple entity-to-logical table entries in the temporary entity-to-logical address mapping table 117T in the entity-to-logical address mapping table 117TR), the temporary entity-to-logical address mapping table 117T (or multiple entity-to-logical table entries therein) is cleared for reuse of the temporary entity-to-logical address mapping table 117T and / or the corresponding storage space in the random access memory 116;

[0057] The first table processing operation may include loading a local logical-to-physical address mapping table (e.g., a first local logical-to-physical address mapping table) within the global logical-to-physical address mapping table 120T into the random access memory 116 as a temporary logical-to-physical address mapping table 116T, updating one or more logical-to-physical table entries in the temporary logical-to-physical address mapping table 116T to indicate one or more logical-to-physical address mapping relationships among a plurality of logical-to-physical address mapping relationships for the first active block, and updating the global logical-to-physical address mapping table 120T (or the local logical-to-physical address mapping table therein) according to the temporary logical-to-physical address mapping table 116T. However, the present invention is not limited thereto. According to some embodiments, the aforementioned predetermined criterion may be replaced by any one of a plurality of predetermined criteria to allow the memory controller 110 to perform the table processing operation when any one of the aforementioned criteria is met. For example, the plurality of predetermined criteria may include:

[0058] (1) One of the aforementioned predetermined criteria: the first active block is fully programmed; and

[0059] (2) Another predetermined criterion: The number of entity-to-logical table entries recorded in the first entity-to-logical address mapping table reaches a predetermined entry count;

[0060] The predetermined entry count may represent a predetermined table size of the first entity-to-logical address mapping table. For example, the memory controller 110 may perform the table processing operation when the number of entity-to-logical table entries in the first entity-to-logical address mapping table, which is either fully programmed or recorded in the first active block, reaches the predetermined entry count.

[0061] For example, after any one of the at least one active blocks (e.g., the first active block) has been fully programmed, the memory device 100 (or its memory controller 110) may close the active block to make it an inactive block, and select a blank block (e.g., an erased block) as a replacement for any one of the plurality of active blocks for subsequent data reception corresponding to that active block. Furthermore, the subsequent processing may include performing a garbage collection procedure to write valid data from all data in the inactive block to another blank block (e.g., another erased block). According to some embodiments, the at least one predetermined rule may be changed, and the related operations may be changed accordingly. For example, the memory controller 110 may copy multiple entity-to-logical table entries from the temporary entity-to-logical address mapping table 117T to the entity-to-logical address mapping table 117TR to generate or update the entity-to-logical address mapping table 117TR based on the temporary entity-to-logical address mapping table 117T.

[0062] According to some embodiments, since the entity-to-logical address mapping relationships indicated by the entity-to-logical table entries in the at least one entity-to-logical address mapping table and the logical-to-entity address mapping relationships indicated by the relevant logical-to-entity table entries in the global logical-to-entity address mapping table 120T should be inverse address mapping relationships to each other, the memory controller 110 can determine the latest mapping information (e.g., entity address) carried by the latest mapping information (e.g., logical address) carried by the entity-to-logical table entries in the at least one entity-to-logical address mapping table based on the latest mapping information (e.g., logical address) carried by the entity-to-logical table entries in the at least one entity-to-logical address mapping table. For example, the at least one entity-to-logical address mapping table may include a first entity-to-logical address mapping table (e.g., entity-to-logical address mapping table 117TR or temporary entity-to-logical address mapping table 117T). As another example, the at least one entity-to-logical address mapping table may include a backup entity-to-logical address mapping table in the non-volatile memory 120. In some examples, the aforementioned at least one entity-to-logical address mapping table may include a first entity-to-logical address mapping table and / or a backup entity-to-logical address mapping table in the non-volatile memory 120. Furthermore, the memory controller 110 may utilize these plurality of local logical-to-entity address mapping tables to manage the relationship between entity addresses and logical addresses (e.g., the entity address indicating the location where host writes data to be stored in the non-volatile memory 120 and the logical address at which host device 50 writes host write data). For example, the plurality of local logical-to-entity address mapping tables may be implemented as a series of local logical-to-entity address mapping tables {L2PT(1), L2PT(2), ..., L2PT(X)} corresponding to a series of logical address ranges {L_Addr_R(1), L_Addr_R(2), ..., L_Addr_R(R_CNT)}, and the series of logical address ranges {L_Addr_R(1), L_Addr_R(2), ..., L_Addr_R(R_CNT)} may be implemented as a series of consecutive logical... The range of the logical address {L_Addr(0),L_Addr(1),…,L_Addr((R_CNT*R_Size)-1)}, such as the range of R_CNT intervals [L_Addr(0),L_Addr(R_Size-1)], [L_Addr(R_Size),L_Addr((2*R_Size)-1)],… and [L_Addr((R_CNT-1)*R_Size),L_Addr((R_CNT*R_Size)-1)].

[0063] Figure 2This is a schematic diagram of a first table update control scheme according to an embodiment of the present invention. For example, the memory controller 110 may use a first active block (e.g., active block 220) to receive multiple sets of partial data in host-written data (e.g., data to be written to non-volatile memory 120), and generate or update a first entity-to-logic address mapping table (e.g., entity-to-logic address mapping table 117TR; for simplicity, denoted as "P2L table") corresponding to active block 220. In particular, entity-to-logic table entries are recorded in entity-to-logic address mapping table 117TR to indicate the entity-to-logic address mapping relationship for active block 220. Furthermore, the memory controller 110 can update the relevant logical-to-entity table entries in the global logical-to-entity address mapping table 120T (denoted as "L2P table" for brevity) based on the entity-to-logical table entries in the entity-to-logical address mapping table 117TR, using a first size M1 as the unit. In particular, when the entity-to-logical address mapping table 117TR is full, a set of logical-to-entity table entries in the global logical-to-entity address mapping table 120T can be updated based on a set of entity-to-logical table entries in the entity-to-logical address mapping table 117TR. The memory controller 110 can clear the entity-to-logical address mapping table 117TR by removing the set of entity-to-logical table entries (e.g., entity-to-logical table entries used as references for updating the set of logical-to-entity table entries) from the entity-to-logical address mapping table 117TR to reuse the entity-to-logical address mapping table 117TR, but the invention is not limited thereto. According to some embodiments, the memory controller 110 may load entity-to-logical table entries from entity-to-logical address mapping table 117TR to temporary entity-to-logical address mapping table 117T to generate or update logical-to-entity table entries in global logical-to-entity address mapping table 120T based on temporary entity-to-logical address mapping table 117T.

[0064] Figures 3A to 3FThese are schematic diagrams illustrating a data-entropy-aware table update control scheme for managing data access to a memory device in a predetermined communication architecture using an unbalanced table update size, according to an embodiment of the present invention. The diagrams depict table loading operations, at least one first update operation (e.g., one or more first update operations), another update operation, at least one second update operation (e.g., one or more second update operations), yet another update operation, and a table saving operation. For example, the memory controller 110 may utilize a first active block (e.g., active block 220) to receive multiple sets of partial data from host-written data (e.g., data to be written to non-volatile memory 120), and generate or update a first entity-to-logical address mapping table (e.g., a temporary entity-to-logical address mapping table 117T; denoted as a "P2L table" for simplicity) corresponding to active block 220. Specifically, entity-to-logical table entries are recorded in the temporary entity-to-logical address mapping table 117T to indicate the entity-to-logical address mapping relationship for active block 220. Furthermore, the memory controller 110 can select one of a plurality of predetermined table update sizes (e.g., the first size M1 or the second size M2) to update the relevant logical-to-entity table entries in the global logical-to-entity address mapping table 120T (labeled "L2P table" for brevity) based on the entity-to-logical table entries in the temporary entity-to-logical address mapping table 117T, in units of entity-to-logical table entries in the temporary entity-to-logical address mapping table 117T. In particular, when the entity-to-logical table entry count of the latest entity-to-logical table entry in the temporary entity-to-logical address mapping table 117T reaches the select table update... In the case of a size (e.g., a first size M1 or a second size M2), a set of logical-to-entity table entries in the global logical-to-entity address mapping table 120T is updated based on a set of entity-to-logical table entries in the temporary entity-to-logical address mapping table 117T. The memory controller 110 may remove the set of entity-to-logical table entries (e.g., entity-to-logical table entries used as a reference for updating the set of logical-to-entity table entries) from the temporary entity-to-logical address mapping table 117T to clear the temporary entity-to-logical address mapping table 117T for reuse.

[0065] At the first time point, the memory controller 110 can perform... Figure 3AThe table loading operation shown, in particular, can load the entity-to-logical address mapping table 117TR (e.g., entity-to-logical table entries therein) from reserved random access memory 116R into a second memory region (e.g., a non-reserved memory region) of random access memory 116 as a temporary entity-to-logical address mapping table 117T (e.g., entity-to-logical table entries therein). For better understanding, the first time point can represent the time point at which memory device 100 (or memory controller 110) wakes up from a power-saving state (e.g., sleep state), where there are no commands (CMDs) and data from host device 50 at the first time point, but the invention is not limited thereto.

[0066] In the first time period following the first time point, the memory controller 110 may utilize the active block 220 to receive at least one set of first partial data with low entropy from among the multiple sets of partial data (e.g., one or more sets of first partial data; for simplicity, in Figure 3B The data is marked as "data with low entropy" and the temporary entity-to-logical address mapping table 117T is updated by recording the corresponding entity-to-logical table entries in the temporary entity-to-logical address mapping table 117T, so as to indicate the entity-to-logical address mapping relationship between the logical address and the entity address of at least one set of first part data (e.g., one or more sets of first part data) in the active block 220. In addition, the memory controller 110 can perform the above-mentioned... Figure 3B At least one first update operation (e.g., one or more first update operations) is shown, in particular, the corresponding logical-to-entity table entries in the global logical-to-entity address mapping table 120T (labeled "L2P table" for simplicity) can be updated based on the entity-to-logical table entries in the temporary entity-to-logical address mapping table 117T, using the table update size (e.g., a second size M2; denoted as "M2" for simplicity) as the unit. Since the memory controller 110 can continuously utilize the active block 220 to receive the aforementioned at least one set of first portion data and correspondingly update the temporary entity-to-logical address mapping table 117T during the first time period, the entity-to-logical table entry count in the temporary entity-to-logical address mapping table 117T can correspondingly increase and reach the selected table update size (e.g., the second size M2). In this case, the memory controller 110 can perform the above... Figure 3B The first update operation shown clears the temporary entity to logical address mapping table 117T once or more to reuse the temporary entity to logical address mapping table 117T.

[0067] At the first subsequent time point after the first time period, there will be no commands or data from the host device 50, and if the entity-to-logical entry count of the latest entity-to-logical table entry in the temporary entity-to-logical address mapping table 117T reaches the first size M1 (denoted as "M1" for simplicity), the memory controller 110 may perform... Figure 3C Other update operations shown (such as the other update operation described above). At the first subsequent time point, if the entity-to-logic entry count is detected to reach the first size M1, the memory controller 110 can update the relevant logical-to-entity table entries in the global logical-to-entity address mapping table 120T (labeled "L2P table" for simplicity) according to the latest entity-to-logic table entry in the temporary entity-to-logic address mapping table 117T, and clear the temporary entity-to-logic address mapping table 117T once to prepare for any possible state transition. For example, there may be a period of time after the first subsequent time point where no new commands are given, and the power-saving state (e.g., sleep state) may not be entered until later. Since the memory controller 110 may have expanded the aforementioned first entity-to-logic address mapping table from the first size M1 to the second size M2 (e.g., M2>M1), the memory controller 110 can perform... Figure 3C Other update operations (such as the other update operation described above) are used to prevent any possible errors.

[0068] In a second time period following the first time point (e.g., after the aforementioned subsequent time point), the memory controller 110 may utilize the active block 220 to receive at least one set of second partial data with high entropy from among the multiple sets of partial data (e.g., one or more sets of second partial data; for simplicity, in Figure 3D The data is marked as "high-entropy data" and the corresponding entity-to-logic table entry is recorded in the temporary entity-to-logic address mapping table 117T to update the temporary entity-to-logic address mapping table 117T, so as to indicate the entity-to-logic address mapping relationship between the logical address and the entity address of at least one set of second part data (e.g., one or more sets of second part data) in the active block 220. In addition, the memory controller 110 can perform the above-mentioned... Figure 3DThe at least one second update operation shown (e.g., one or more second update operations), in particular, updates the relevant logical-to-entity table entries in the global logical-to-entity address mapping table 120T (labeled "L2P table" for simplicity) based on the entity-to-logical table entries in the temporary entity-to-logical address mapping table 117T, in units of the selection table update size (e.g., the first size M1; denoted as "M1" for simplicity). Since the memory controller 110 can continuously utilize the active block 220 to receive the aforementioned at least one set of second-part data and correspondingly update the temporary entity-to-logical address mapping table 117T during the second time period, the entity-to-logical entry count of the entity-to-logical table entries in the temporary entity-to-logical address mapping table 117T can correspondingly increase and reach the selection table update size (e.g., the first size M1). In this case, the memory controller 110 can perform the above... Figure 3D The temporary entity to logical address mapping table 117T is cleared once or more by at least one second update operation to reuse the temporary entity to logical address mapping table 117T.

[0069] At the second subsequent time point after the second time period, there may be no commands or data from the host device 50, and if the entity-to-logic entry count of the latest entity-to-logic table entry in the temporary entity-to-logic address mapping table 117T reaches the first size M1 (denoted as "M1" for simplicity), the memory controller 110 may perform the above-mentioned... Figure 3E Another update operation is shown. At the second subsequent time point, if the entity-to-logic entry count is detected to reach the first size M1, the memory controller 110 can update the relevant logical-to-entity table entries in the global logical-to-entity address mapping table 120T (labeled "L2P table" for simplicity) according to the latest entity-to-logic table entry in the temporary entity-to-logic address mapping table 117T, and clear the temporary entity-to-logic address mapping table 117T once to prepare for any possible state transition. For example, there may be a period of time after the second subsequent time point where no new commands are given, and the power-saving state (e.g., sleep state) may not be entered until later. Since the memory controller 110 may have already expanded the aforementioned first entity-to-logic address mapping table from the first size M1 to the second size M2 (e.g., M2>M1), regardless of any previous operation (e.g., ... Figure 3B At least one first update operation shown or Figure 3D The memory controller 110 can perform the above-described operation (at least one second update operation as shown). Figure 3E The following update operation is shown to prevent any possible errors.

[0070] At the third subsequent time point after the second subsequent time point, there may be no commands or data from the host device 50, and the memory controller 110 may perform the above-mentioned... Figure 3F The table saving operation shown specifically involves saving the temporary entity-to-logical address mapping table 117T (e.g., entity-to-logical table entries therein) to the reserved random access memory 116R as the entity-to-logical address mapping table 117TR (e.g., entity-to-logical table entries therein). For example, at a third subsequent time point, the memory controller 110 may decide to enter a power-saving state (e.g., a sleep state).

[0071] According to some embodiments, the aforementioned at least one predetermined rule may be associated with data classification for multiple predetermined data types, and the multiple predetermined data types may include a first predetermined data type corresponding to a first predetermined entropy range and a second predetermined data type corresponding to a second predetermined entropy range, wherein the multiple predetermined data types may respectively represent data with different entropy ranges, but the present invention is not limited thereto. For example, the memory controller 110 may classify the multiple sets of partial data in host-written data (e.g., data to be written to non-volatile memory 120) to classify the aforementioned at least one set of first partial data (e.g., one or more sets of first partial data) as a first predetermined data type (e.g., low-entropy data, such as data with low entropy) and the aforementioned at least one set of second partial data (e.g., one or more sets of second partial data) as a second predetermined data type (e.g., high-entropy data, such as data with high entropy). In particular, a first predetermined entropy range and a second predetermined entropy range can be defined by a predetermined entropy threshold Eth, and the memory controller 110 can detect that the entropy system of at least one set of first partial data is less than the predetermined entropy threshold Eth, and can detect that the entropy system of at least one set of second partial data is greater than the predetermined entropy threshold Eth. For example, the first predetermined entropy range can represent a first interval [0, Eth), and the second predetermined entropy range can represent a second interval [Eth, ∞), but the present invention is not limited thereto. For another example, the first predetermined entropy range can represent a first interval [0, Eth], and the second predetermined entropy range can represent a second interval (Eth, ∞). For the sake of brevity, similar contents of these embodiments will not be described in detail here.

[0072] According to some embodiments, the operation of the memory device 100 (or the memory controller 110 therein) may include:

[0073] (1) The memory device 100 (or the memory controller 110 therein) can receive a set of first commands from the host device 50 through the transmission interface circuit 118 of the memory controller 110, and according to the set of first commands, use the first active block (e.g., active block 220) to receive a set of first data and update the temporary entity to logical address mapping table 117T corresponding to the active block 220, wherein the set of first commands can indicate that the set of first data is required to be written into the memory device 100;

[0074] (2) The memory device 100 (or the memory controller 110 therein) can determine a selectable table update size from a plurality of predetermined table update sizes according to at least one predetermined rule, wherein the plurality of predetermined table update sizes can each represent a plurality of table entry counts; and

[0075] (3) The memory device 100 (or the memory controller 110 therein) may update at least one logic-to-entity address mapping table (e.g., global logic-to-entity address mapping table 120T) in the non-volatile memory 120 according to a set of entity-to-logic table entries in the temporary entity-to-logic address mapping table 117T corresponding to the pick-up table update size, for data access, wherein the table entry count of the set of entity-to-logic table entries is equal to the pick-up table update size;

[0076] When needed, the memory controller 110 can access data (e.g., host write data, such as data to be written to non-volatile memory 120) according to the global logic-to-entity address mapping table 120T. Specifically, it can read host write data already stored in non-volatile memory 120 for the host device 50 according to relevant logic-to-entity table entries in the global logic-to-entity address mapping table 120T, but the invention is not limited thereto. According to some embodiments, the memory device 100 (or the memory controller 110 therein) can be used to switch between the multiple predetermined table update sizes. For example, based on at least one of the predetermined rules described above:

[0077] (1) In response to the attainment of at least one first predetermined criterion (e.g., one or more first predetermined criterions), the memory controller 110 may update the at least one logical-to-entity address mapping table (e.g., global logical-to-entity address mapping table 120T) based on multiple sets of first entity-to-logical table entries in the temporary entity-to-logical address mapping table 117T in units of one of the multiple predetermined table update sizes (e.g., first size M1); and

[0078] (2) In response to the attainment of at least one second predetermined criterion (e.g., one or more second predetermined criterions), the memory controller 110 may update the at least one logical to entity address mapping table (e.g., global logical to entity address mapping table 120T) based on multiple sets of second entity to logical table entries in the temporary entity to logical address mapping table 117T in units of one of the multiple predetermined table update sizes (e.g., second size M2).

[0079] For the sake of brevity, similar details of these embodiments will not be described in detail here.

[0080] Figure 4 This is a schematic diagram of a table update size control scheme according to an embodiment of the present invention, wherein the table update size can be controlled according to... Figure 4 The table shows an update size control scheme for operating memory device 100 (or memory controller 110 therein).

[0081] In step S11, the memory device 100 (or the memory controller 110 therein) may move the entity-to-logical address mapping table 117TR (e.g., entity-to-logical table entries therein) from the reserved random access memory 116R to a second memory region (e.g., a non-reserved memory region, such as a data buffer) as a temporary entity-to-logical address mapping table 117T (e.g., entity-to-logical table entries therein) for the aforementioned internal management operation (for brevity, this is labeled as "moving the P2L table from reserved RAM to the data buffer").

[0082] In step S12, the memory device 100 (or its memory controller 110) may begin to receive data (e.g., host write data, such as data to be written to the non-volatile memory 120; for simplicity, denoted as "receiving data from the host device") using a first active block (e.g., active block 220). In particular, active block 220 may be used to receive at least one set of partial data (e.g., one or more sets of partial data, such as the first set of data). Therefore, the at least one set of partial data (e.g., the first set of data) may be written to active block 220.

[0083] In step S13, the memory device 100 (or its memory controller 110) can determine the selected table update size from among multiple predetermined table update sizes according to at least one predetermined rule. Specifically, it can classify the at least one set of partial data for the multiple predetermined data types to determine whether the at least one set of partial data belongs to a first predetermined data type corresponding to a first predetermined entropy range or a second predetermined data type corresponding to a second predetermined entropy range (for simplicity, this is labeled "entropy judgment"). The selected table update size is chosen from among the multiple predetermined table update sizes. For better understanding, the first predetermined data type and the second predetermined data type can represent sequential data and non-sequential data, respectively, but the invention is not limited thereto.

[0084] For example, the memory controller 110 can detect that the entropy coefficient of at least one set of partial data is less than a predetermined entropy threshold Eth, and classify the at least one set of partial data into a first predetermined data type (e.g., continuous data, such as low-entropy data; for simplicity, denoted as "low"). In this case (e.g., when the memory controller 110 determines that the at least one set of partial data belongs to the first predetermined data type, such as low-entropy data), the process proceeds to step S14B. As another example, the memory controller 110 can detect that the entropy coefficient of at least one set of partial data is greater than a predetermined entropy threshold Eth, and classify the at least one set of partial data into a second predetermined data type (e.g., non-continuous data, such as high-entropy data; for simplicity, denoted as "high"). In this case (e.g., when the memory controller 110 determines that the at least one set of partial data belongs to the second predetermined data type, such as high-entropy data), the process proceeds to step S14A.

[0085] In step S14A, the memory device 100 (or its memory controller 110) may select a table update size (e.g., a first size M1) as a unit to update the relevant logical-to-entity table entries in the global logical-to-entity address mapping table 120T based on the entity-to-logical table entries in the temporary entity-to-logical address mapping table 117T (for simplicity, this is labeled "updating L2P entries based on P2L entries in units of M1"). In particular, when the entity-to-logical entry count of the latest entity-to-logical table entry in the temporary entity-to-logical address mapping table 117T reaches the selected table update size (e.g., the first size M1), a set of logical-to-entity table entries in the global logical-to-entity address mapping table 120T is updated based on a set of entity-to-logical table entries in the temporary entity-to-logical address mapping table 117T. For example, the operation of step S14A may be similar to or the same as described above. Figure 3D At least one second update operation (e.g., one or more second update operations) is shown.

[0086] In step S14B, the memory device 100 (or its memory controller 110) may select a table update size (e.g., a second size M2) as a unit to update the relevant logical-to-entity table entries in the global logical-to-entity address mapping table 120T based on the entity-to-logical table entries in the temporary entity-to-logical address mapping table 117T (for simplicity, this is labeled "updating L2P entries based on P2L entries in units of M2"). In particular, when the entity-to-logical entry count of the latest entity-to-logical table entry in the temporary entity-to-logical address mapping table 117T reaches the selected table update size (e.g., the second size M2), a set of logical-to-entity table entries in the global logical-to-entity address mapping table 120T is updated based on a set of entity-to-logical table entries in the temporary entity-to-logical address mapping table 117T. For example, the operation of step S14B may be similar to or the same as described above. Figure 3B At least one first update operation (e.g., one or more first update operations) is shown.

[0087] In step S15, the memory device 100 (or its memory controller 110) may check whether the operation of receiving data (e.g., host write data, such as data to be written to non-volatile memory 120) using the first active block (e.g., active block 220) has been completed. If yes, proceed to step S16; if no, proceed to step S12.

[0088] In step S16, the memory device 100 (or the memory controller 110 therein) may check whether the entity-to-logic entry count of the latest entity-to-logic table entry in the temporary entity-to-logic address mapping table 117T has reached the first size M1 (for simplicity, it is marked as "P2L entry count has reached M1"). If yes, proceed to step S17; if no, proceed to step S18.

[0089] In step S17, the memory device 100 (or its memory controller 110) may update the relevant logical-to-entity table entries in the global logical-to-entity address mapping table 120T according to the latest entity-to-logical table entry in the temporary entity-to-logical address mapping table 117T, and clear the temporary entity-to-logical address mapping table 117T once (for brevity, this is labeled "updating L2P entries according to P2L entries") to prepare for any state transition. For example, the operation of step S17 may be similar to or the same as... Figure 3C Other update operations shown (such as the other update operation described above). For example, the operation of step S17 may be similar to or the same as... Figure 3EThe above-described update operation is shown. Since the memory controller 110 may have expanded the first entity-to-logical address mapping table from the first size M1 to the second size M2 (e.g., M2>M1), the memory controller 110 can perform the operation of step S17 to prepare for any state transition, regardless of which operation was performed before executing the part of the workflow that includes steps S15 to S17 (e.g., the operation of step S14B or the operation of step S14A).

[0090] In step S18, the memory device 100 (or its memory controller 110) may check for any new command from the host device 50, and in particular, may wait for any new command until a predetermined waiting time period ends. If yes (e.g., the memory controller 110 receives any new command before the predetermined waiting time period ends), proceed to step S12; if no (e.g., the memory controller 110 does not receive a command before the predetermined waiting time period ends), proceed to step S19.

[0091] In step S19, the memory device 100 (or its memory controller 110) may store a temporary entity-to-logical address mapping table 117T (e.g., entity-to-logical table entries therein) in reserved random access memory 116R as an entity-to-logical address mapping table 117TR (e.g., entity-to-logical table entries therein), and may pause to enter a power-saving state (e.g., sleep state; for brevity, labeled "store P2L table in reserved RAM; pause"). For example, the operation of storing the temporary entity-to-logical address mapping table 117T in reserved random access memory 116R mentioned in step S19 may be similar to or the same as... Figure 3F The table shown is saved.

[0092] For example, in response to the occurrence of a predetermined event, the memory device 100 (or its memory controller 110) can be woken up. In this case, step S11 can be entered to prepare for the aforementioned internal management operation.

[0093] To better understand this method, it can be used by... Figure 4 The workflow shown is intended to illustrate the invention, but the invention is not limited thereto. According to some embodiments, one or more steps may be performed... Figure 4 Add, delete, or modify within the workflow shown.

[0094] According to some embodiments, during the operation of step S11 (e.g.) Figure 3AAfter the table loading operation shown, the temporary entity-to-logical address mapping table 117T can be considered an expanded version of the entity-to-logical address mapping table 117TR. Specifically, among multiple predetermined table update sizes (e.g., a first size M1 and a second size M2), the second predetermined table update size (e.g., the second size M2) is larger than the first predetermined table update size (e.g., the first size M1). For example, the temporary entity-to-logical address mapping table 117T can be used to occupy a memory region in the random access memory 116 within the memory controller 110 for the second predetermined table update size (e.g., the second size M2), where the memory controller 110 may have expanded the aforementioned first entity-to-logical address mapping table from the first size M1 to the second size M2 (e.g., M2 > M1). Furthermore, during the operation of step S19 (e.g., ... Figure 3F After the table saving operation shown, the entity-to-logical address mapping table 117TR can be considered as a backup version of the temporary entity-to-logical address mapping table 117T. The backup size of the temporary entity-to-logical address mapping table 117T backed up to the reserved random access memory 116R can be equal to the first predetermined table update size (e.g., the first size M1) among a plurality of predetermined table update sizes (e.g., the first size M1 and the second size M2). For example, the first predetermined table update size (e.g., the first size M1) can be the minimum among a plurality of predetermined table update sizes (e.g., the first size M1 and the second size M2). For the sake of brevity, similar details regarding these embodiments will not be described in detail here again.

[0095] According to certain embodiments, during the updating of at least one logic-to-entity address mapping table (e.g., global logic-to-entity address mapping table 120T) in non-volatile memory 120 based on the set of entity-to-logic table entries in temporary entity-to-logic address mapping table 117T corresponding to the select table update size (e.g., a first size M1 or a second size M2), in accordance with at least one predetermined criterion (e.g., one or more predetermined criteria), memory controller 110 may update the at least one logic-to-entity address mapping table (e.g., global logic-to-entity address mapping table 120T) in units of select table update size based on multiple sets of entity-to-logic table entries in temporary entity-to-logic address mapping table 117T respectively corresponding to the select table update size, wherein the set of entity-to-logic table entries corresponding to the select table update size is one of the multiple sets of entity-to-logic table entries. For example, the aforementioned at least one predetermined standard may represent the aforementioned at least one first predetermined standard for proceeding to step S14A, such as the standard that the entropy system of the aforementioned at least one set of partial data is greater than a predetermined entropy threshold Eth, wherein the memory controller 110 may select a table update size (e.g., a first size M1) as the unit to update the global logical-to-entity address mapping table 120T according to the plurality of sets of entity-to-logical table entries (e.g., the plurality of sets of first entity-to-logical table entries). As another example, the aforementioned at least one predetermined standard may represent the aforementioned at least one second predetermined standard for proceeding to step S14B, such as the standard that the entropy system of the aforementioned at least one set of partial data is less than a predetermined entropy threshold Eth, wherein the memory controller 110 may select a table update size (e.g., a second size M2) as the unit to update the global logical-to-entity address mapping table 120T according to the plurality of sets of entity-to-logical table entries (e.g., the plurality of sets of second entity-to-logical table entries). For the sake of brevity, similar content of these embodiments will not be described in detail here again.

[0096] Figure 5 This is a schematic diagram illustrating the workflow of a method according to an embodiment of the present invention, wherein it can be based on Figure 5 The workflow shown is used to operate the memory device 100 (or the memory controller 110 therein).

[0097] In step S20, the memory device 100 (or its memory controller 110) receives a set of commands (e.g., the first set of commands) from the host device 50 via the transmission interface circuit 118 of the memory controller 110. Based on these commands, the first active block (e.g., active block 220) is used to receive at least one set of partial data (e.g., the first set of data), and the temporary entity-to-logical address mapping table 117T corresponding to active block 220 is updated. The commands (e.g., the first set of commands) may indicate a request to write the at least one set of partial data (e.g., the first set of data) into the memory device 100. Therefore, the at least one set of partial data (e.g., the first set of data) can be written into the first active block (e.g., active block 220). For example, the at least one set of partial data in step S20 may be equal to the at least one set of partial data in step S12.

[0098] In step S21, the memory device 100 (or its memory controller 110) may determine, according to at least one of the predetermined rules, the selected table update size (e.g., the first size M1 or the second size M2) among a plurality of predetermined table update sizes (e.g., the first size M1 and the second size M2). For example, the operation of step S21 may be similar to or the same as the operation of step S13, but the present invention is not limited thereto.

[0099] In step S22, the memory device 100 (or its memory controller 110) may read a set of entity-to-logic table entries corresponding to the select table update size (e.g., a first size M1 or a second size M2) from the temporary entity-to-logic address mapping table 117T, update at least one logical-to-entity address mapping table (e.g., the global logical-to-entity address mapping table 120T, such as a set of logical-to-entity table entries therein) for data access according to the set of entity-to-logic table entries corresponding to the select table update size, and remove the set of entity-to-logic table entries from the temporary entity-to-logic address mapping table 117T. For example, the memory controller 110 may determine in step S21 that the select table update size is equal to a first predetermined table update size (e.g., a first size M1). In this case, the operation of step S22 may be similar to or the same as the operation of step S14A. For example, the memory controller 110 may determine in step S21 that the selection table update size is equal to the second predetermined table update size (e.g., the second size M2). In this case, the operation of step S22 may be similar to or the same as the operation of step S14B.

[0100] In step S23, the memory device 100 (or its memory controller 110) may determine whether to proceed to the next operation based on whether there is any new command (e.g., any new command in step S18 above). If yes (e.g., the memory controller 110 receives any new command before the end of the predetermined waiting time period), proceed to step S20; if no (e.g., the memory controller 110 does not receive a command before the end of the predetermined waiting time period), Figure 5 The workflow shown is now complete. For example, the operation in step S23 may be similar to or the same as the operation in step S18.

[0101] To better understand this method, it can be used by... Figure 5 The workflow shown is intended to illustrate the invention, but the invention is not limited thereto. According to some embodiments, one or more steps may be performed... Figure 5 Add, delete, or modify within the workflow shown. For example, Figure 4 The loop shown, which includes steps S16 and S17, can be inserted into Figure 5 The process shown is between steps S22 and S23. Additionally, steps S11 and S19 can be added as... Figure 5 The workflow shown includes new starting and ending steps to form additional loops (e.g., Figure 4 The example shown includes the maximum loop containing steps S11, S19, etc. For the sake of brevity, similar details of these embodiments will not be described again here.

[0102] According to some embodiments, any one of the first commands in the set may also carry first information associated with any piece of data to be written. In particular, the aforementioned piece of data to be written may include first data corresponding to any one of the commands in the set of first data. Since the set of first commands may instruct the writing of the set of first data into the memory device 100, any one of the commands may instruct the writing of the first data into the memory device 100. For example, the first information associated with any piece of data to be written (e.g., the first data) may include at least one first logical address for indicating at least one first logical address region, and any one of the commands may instruct the writing of any piece of data to be written (e.g., the first data) into the at least one first logical address region. Furthermore, the memory device 100 (or its memory controller 110) may perform a first check operation (e.g., the operation of step S13) on the first information to generate a first judgment result (e.g., a judgment result of "high" for the first data in step S13, or a judgment result of "low" for the first data in step S13) to determine the selection table update size, wherein the first judgment result may indicate that the first data belongs to a certain predetermined data type among a plurality of predetermined data types (e.g., a first predetermined data type or a second predetermined data type). For example, the first judgment result may represent a judgment result of "high" for the first data in step S13, indicating that the first data belongs to a second predetermined data type (e.g., high-entropy data). In this case, in response to the first judgment result (e.g., a judgment result of "high" for the first data in step S13), the memory controller 110 may determine that the selection table update size is equal to the first predetermined table update size (e.g., the first size M1). For example, the first judgment result may represent the judgment result of step S13 for the first data as "low," indicating that the first data belongs to a first predetermined data type (e.g., low-entropy data). In this case, in response to the first judgment result (e.g., the judgment result of step S13 for the first data as "low"), the memory controller 110 may determine that the selected table update size is equal to the second predetermined table update size (e.g., the second size M2). Furthermore, the memory controller 110 may be used to generate the first judgment result based on the aforementioned at least one first logical address, but the invention is not limited thereto. According to some embodiments, the first information may further include a first data length of the first data, and the memory controller 110 may be used to generate the first judgment result based on the first data length. For the sake of brevity, similar details of these embodiments will not be described in detail here.

[0103] According to some embodiments, the memory controller 110 may record a null entry with a preset value (e.g., a predetermined value indicating no mapping information) in a first entity-to-logical address mapping table (e.g., entity-to-logical address mapping table 117TR or temporary entity-to-logical address mapping table 117T) as a cleared entry, indicating that the location where the null entry was recorded has been cleared for further use. The memory controller 110 may later record a new entry at that location if needed, but the invention is not limited thereto. For the sake of brevity, similar descriptions of these embodiments will not be repeated here.

[0104] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

Claims

1. A method for managing data access to a memory device in a predetermined communication architecture by means of an unbalanced table update size, the method being applied to a memory controller of the memory device, the memory device including the memory controller and a non-volatile memory, the non-volatile memory including at least one non-volatile memory element, the at least one non-volatile memory element including a plurality of blocks, the method comprising: The memory controller is used to receive a set of first commands from a host device through a transmission interface circuit of the memory controller. According to the set of first commands, a set of first data is received using a first active block among the plurality of blocks, and a temporary entity-to-logical address mapping table corresponding to the first active block is updated. The set of first commands indicates that the set of first data is written to the memory device, and the set of first data is written to the first active block. A table update size is selected from a plurality of predetermined table update sizes based on at least one predetermined rule, wherein the plurality of predetermined table update sizes represent a plurality of table entry counts. as well as At least one logical-to-physical address mapping table in the non-volatile memory is updated for data access based on a set of entity-to-logical table entries in the temporary entity-to-logical address mapping table corresponding to the select table update size, wherein the entry count of one of the set of entity-to-logical table entries is equal to the select table update size.

2. The method as described in claim 1, characterized in that... The backup size of the temporary entity to the logical address mapping table is equal to the first of the multiple pre-defined table update sizes.

3. The method as described in claim 2, characterized in that... The update size of the first reservation table is the minimum of the update sizes of the plurality of reservation tables.

4. The method as described in claim 2, characterized in that... The second predetermined table update size among the plurality of predetermined table update sizes is greater than the first predetermined table update size; and the temporary entity-to-logical address mapping table occupies a memory region of the second predetermined table update size in a random access memory within the memory controller.

5. The method as described in claim 1, characterized in that... The step of updating the at least one logical-to-entity address mapping table in the non-volatile memory according to the set of entity-to-logical table entries corresponding to the select table update size in the temporary entity-to-logical address mapping table further includes: In response to reaching at least one predetermined criterion, the at least one logical-to-entity address mapping table in the non-volatile memory is updated in units of the select table update size based on multiple sets of entity-to-logical table entries in the temporary entity-to-logical address mapping table, each corresponding to the select table update size, wherein the set of entity-to-logical table entries is one set of entity-to-logical table entries among the multiple sets of entity-to-logical table entries.

6. The method as described in claim 1, characterized in that... The memory controller is used to switch between the multiple predetermined table update sizes, wherein: In response to reaching at least one first predetermined criterion, the memory controller updates the at least one logical-to-entity address mapping table based on multiple sets of first entity-to-logical table entries in the temporary entity-to-logical address mapping table, using one of the multiple predetermined table update sizes as units; and In response to the attainment of at least one second predetermined criterion, the memory controller updates the at least one logical-to-entity address mapping table based on multiple sets of second entity-to-logical table entries in the temporary entity-to-logical address mapping table, using one of the second predetermined table update sizes among the plurality of predetermined table update sizes.

7. The method as described in claim 1, characterized in that... The at least one predetermined rule is associated with a data classification for multiple predetermined data types; any one of the first commands in the group carries first information associated with any piece of data to be written, the any piece of data to be written contains first data in the group of first data corresponding to the any one command, the first information includes at least one first logical address to indicate at least one first logical address region, and the any one command indicates that the any piece of data to be written should be written to the at least one first logical address region; The method also includes: A first check operation is performed on the first information to generate a first judgment result, which is used to determine the update size of the selection table, wherein the first judgment result indicates whether the first data belongs to a predetermined data type among the plurality of predetermined data types.

8. The method as described in claim 7, characterized in that The first information further includes a first data length of the first data, and the memory controller uses the first data length to generate the first judgment result.

9. The method as described in claim 7, characterized in that... The memory controller is used to generate the first determination result based on the at least one first logical address.

10. The method as described in claim 1, characterized in that... The at least one predetermined rule is associated with a data classification for multiple predetermined data types, and the multiple predetermined data types include a first predetermined data type and a second predetermined data type, wherein the first predetermined data type and the second predetermined data type represent continuous data and non-continuous data, respectively.

11. The method as described in claim 1, characterized in that... The at least one predetermined rule is associated with a data classification for multiple predetermined data types, and the multiple predetermined data types include a first predetermined data type corresponding to a first predetermined entropy range and a second predetermined data type corresponding to a second predetermined entropy range, wherein the multiple predetermined data types represent data with different entropy ranges.

12. The method as described in claim 1, characterized in that... The step of updating the at least one logical-to-entity address mapping table in the non-volatile memory according to the set of entity-to-logical table entries corresponding to the select table update size in the temporary entity-to-logical address mapping table further includes: Read the group of entity-to-logical table entries corresponding to the select table update size from the temporary entity-to-logical address mapping table; Update a set of logical-to-entity table entries in the at least one logical-to-entity address mapping table based on the set of entity-to-logical table entries; and Remove the group of entity-to-logical table entries from the temporary entity-to-logical address mapping table.

13. A memory controller for a memory device, the memory device including the memory controller and a non-volatile memory, the non-volatile memory including at least one non-volatile memory element, the at least one non-volatile memory element including a plurality of blocks, the memory controller including: A processing circuit is configured to control the memory controller according to a plurality of host commands from a host device to allow the host device to access the non-volatile memory through the memory controller, wherein the processing circuit is configured to perform data access management of the memory device in a predetermined communication architecture by means of unbalanced table update size. as well as A transmission interface circuit for communicating with the host device; in: The memory controller receives a set of first commands from the host device through the transmission interface circuit of the memory controller, and according to the set of first commands, uses a first active block among the plurality of blocks to receive a set of first data, and updates a temporary entity-to-logical address mapping table corresponding to the first active block, wherein the set of first commands indicates that the set of first data is written to the memory device, and the set of first data is written to the first active block; The memory controller determines a selectable table update size from a plurality of predetermined table update sizes according to at least one predetermined rule, wherein the plurality of predetermined table update sizes represent a plurality of table entry counts; and The memory controller updates at least one logical-to-physical address mapping table in the non-volatile memory for data access based on a set of entity-to-logical table entries in the temporary entity-to-logical address mapping table corresponding to the select table update size, wherein the entry count of one of the set of entity-to-logical table entries is equal to the select table update size.

14. A memory device comprising the memory controller of claim 13, wherein the memory device comprises: This non-volatile memory is used to store information; and The memory controller is coupled to the non-volatile memory and is used to control the operation of the memory device.

15. An electronic device comprising the memory device of claim 14, and further comprising: The host device is coupled to the memory device, wherein the host device includes: At least one processor is used to control the operation of the host device; as well as A power supply circuit is coupled to the at least one processor and is used to provide power to the at least one processor and the memory device; The memory device provides storage space to the host device.

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