Methods for data access management of memory devices, memory controllers for memory devices, memory devices, and electronic devices.

Abstract

This invention relates to a method for managing data access to a memory device in a predetermined communication architecture using multi-table checks, a memory controller for the memory device, the memory device itself, and an electronic device. The method includes: receiving a first command from a host device via a memory controller, wherein the first command indicates a request to read first data located at a first logical address; checking at least one logical-to-physical address mapping table to generate a first check result; initiating a first read operation based on the first check result; checking a temporary physical-to-logical address mapping table corresponding to a first active block to generate a second check result, for selectively performing a second read operation based on the second check result; and returning the first data to the host device, wherein the first data was read based on one of the check results, the first check result and the second check result.

Description

Technical Field

[0001] This invention relates to memory control, and more particularly to a method and related apparatus for managing data access to a memory device in a predetermined communication architecture by means of multi-table checks. Background Technology

[0002] Memory devices may include flash memory for storing data, and access management for flash memory is quite complex. For example, a memory device can be a memory card, a solid-state drive (SSD), or an embedded storage device (such as an embedded storage device conforming to the Universal Flash Storage (UFS) specification). Memory devices can be used to store different files (such as system files and user files) in the host's file system. Because some files may be accessed frequently, some data may become invalid. When invalid data is mixed with some valid data in the same storage block within the memory device, garbage collection (GC) operations are generally required to free up more storage space for further use. Furthermore, during file access, internal management information may change accordingly. Since the access processing of some internal management information may not be completed, the memory device needs to perform a search operation before reading any data from the flash memory, which increases the total processing time of the read operation. There is no suitable way to handle this in the prior art, therefore, there is a great need for an innovative approach and related architecture to solve these problems without introducing side effects or in a way that is unlikely to introduce side effects. Summary of the Invention

[0003] Therefore, one of the objectives of this invention is to provide a method and related apparatus for managing data access to memory devices in a predetermined communication architecture (e.g., a general flash memory communication architecture) using multi-table checks, in order to solve the aforementioned problems.

[0004] At least one embodiment of the present invention provides a method for managing data access to a memory device in a predetermined communication architecture using multi-table checks. The method is applicable to a memory controller of the memory device, which may include the memory controller and a non-volatile memory. The non-volatile memory may include at least one non-volatile memory element (e.g., one or more non-volatile memory elements), and the at least one non-volatile memory element may include multiple blocks. The method may include: receiving a first command from a host device via a transmission interface circuit of the memory controller, wherein the first command indicates a request to read first data located at a first logical address; checking at least one logical-to-physical address mapping table to generate a first check result; initiating a first read operation based on the first check result; checking a temporary physical-to-logical address mapping table corresponding to a first active block to generate a second check result, for selectively performing a second read operation based on the second check result; and transmitting the first data back to the host device, wherein the first data was read based on one of the check results of the first and second checks.

[0005] In addition to the methods described above, the present invention also provides a memory controller for a memory device, wherein the memory device includes a memory controller and a non-volatile memory. The non-volatile memory may include at least one non-volatile memory element (e.g., one or more non-volatile memory elements), and the at least one non-volatile memory element may include multiple blocks. Furthermore, the memory controller includes processing circuitry configured to control the memory controller according to multiple host commands from a host device, allowing the host device to access the non-volatile memory through the memory controller, and to perform data access management of the memory device in a predetermined communication architecture using multi-table checks. The memory controller further includes a transmission interface circuitry configured to communicate with the host device. For example, the memory controller receives a first command from the host device through the memory controller's transmission interface circuit, wherein the first command indicates a request to read first data located at a first logical address; the memory controller checks at least one logical-to-physical address mapping table to generate a first check result, begins a first read operation based on the first check result, and checks a temporary physical-to-logical address mapping table corresponding to a first active block to generate a second check result, so as to selectively perform a second read operation based on the second check result; and the memory controller sends the first data back to the host device, wherein the first data was read based on one of the check results of the first check result and the second check result.

[0006] In addition to the methods described above, the present invention also provides a memory device including the memory controller described above, wherein the memory device includes: a non-volatile memory for storing information; and a memory controller coupled to the non-volatile memory and used to control the operation of the memory device.

[0007] In addition to the methods described above, the present invention also provides an electronic device including the aforementioned memory device, wherein the electronic device further includes a host device coupled to the memory device. The host device may include: at least one processor for controlling the operation of the host device; and a power supply circuit coupled to the at least one processor for providing power to the at least one processor and the memory device. Furthermore, the memory device provides storage space to the host device.

[0008] According to some embodiments, the device may include at least a portion (e.g., a portion or all) of an electronic device. For example, the device may include a memory controller within a memory device, or the device may include a memory device, or the device may include an electronic device.

[0009] According to some embodiments, the memory device can store data for a host device, wherein some data in the stored data needs to be updated. To correct problems in the prior art, the memory device can be operated according to at least one control scheme (e.g., one or more control schemes) to perform related operations, specifically, attempting to access stored data according to a first address mapping table of a first type among two different address mapping tables of different types, and simultaneously attempting to access stored data according to a second address mapping table of a second type among the two different address mapping tables, and only continuing one of the first operation of attempting to access stored data according to the first address mapping table and the second operation of attempting to access stored data according to the second address mapping table, depending on which of the first and second operations is correct, to retrieve stored data from the correct location in the non-volatile memory as quickly as possible.

[0010] The method and related apparatus of the present invention ensure that the memory device can operate appropriately under various conditions. For example, when the host device receives a host command indicating a read request, the memory device can begin subsequent processing by referring to two different address mapping tables of different types, thereby reducing the expected total processing time for reading data from non-volatile memory starting from the time the host command is received (e.g., the point in time when the host command is received), and thus increasing overall performance. For example, over time, the memory device can perform multiple read operations on the host device and efficiently complete most of these read operations, thereby reducing the average processing time of these multiple read operations. Furthermore, the method and related apparatus of the present invention can solve the problems encountered in the prior art without introducing side effects or in a way that is unlikely to introduce side effects. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of an electronic device according to an embodiment of the present invention.

[0012] Figure 2 This is a schematic diagram of a first table processing control scheme according to an embodiment of the present invention.

[0013] Figure 3 This is a schematic diagram of a search time hidden table processing control scheme for a method of managing data access to a memory device in a predetermined communication architecture using multi-table checks, according to an embodiment of the present invention.

[0014] Figure 4 This is a schematic diagram illustrating the workflow of a method according to an embodiment of the present invention.

[0015] Figure 5 This is a schematic diagram of a block expansion control scheme according to an embodiment of the present invention.

[0016]

Explanation of symbols

[0017] 10: Electronic devices

[0018] 50: Main unit

[0019] 52: Processor

[0020] 54: Power Supply Circuit

[0021] 58,118: Transmission interface circuit

[0022] 100: Memory device

[0023] 110: Memory controller

[0024] 112: Microprocessor

[0025] 112C: Program Code

[0026] 112M: Read-Only Memory

[0027] 114: Control Logic Circuit

[0028] 116: Random Access Memory

[0029] 116T: Temporary Logic to Entity Address Mapping Table

[0030] 117T: Temporary Entity to Logical Address Mapping Table

[0031] 118C: Universal Flash Storage Controller

[0032] 118U: Standardized Communication Protocol Circuit

[0033] 118M:M physical layer circuit

[0034] 120: Non-volatile memory

[0035] 120T: Global Logical to Entity Address Mapping Table

[0036] 122-1~122-N: Non-volatile memory elements

[0037] 220: Active Block

[0038] 227T: Entity-to-Logical Address Mapping Table

[0039] S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23: Steps

[0040] {PG(0)},{PG(1)}: Page

[0041] {BLK(0)},{BLK(1)}: Blocks

[0042] XPG(0), XPG(1): Super Page

[0043] XBLK(0),XBLK(1): Superblock Detailed Implementation

[0044] Figure 1This is a schematic diagram of an electronic device 10 according to an embodiment of the present invention, wherein the electronic device 10 may include a host device 50 and a memory device 100. The host device 50 may include at least one processor (e.g., one or more processors; collectively referred to as processor 52), a power supply circuit 54, and a transmission interface circuit 58, wherein the processor 52 and the transmission interface circuit 58 may be coupled to each other via a bus and may be coupled to the power supply circuit 54 to obtain power. The processor 52 may be used to control the operation of the host device 50, and the power supply circuit 54 may be used to provide power to the processor 52, the transmission interface circuit 58, and the memory device 100, and output one or more drive voltages to the memory device 100. The memory device 100 may be used to provide storage space to the host device 50 and may obtain one or more drive voltages from the host device 50 as power for the memory device 100. Examples of the host device 50 may include, but are not limited to, multi-functional mobile phones, tablet computers, wearable devices, and personal computers, such as desktop computers and laptop computers. Examples of memory device 100 may include, but are not limited to: portable memory devices (e.g., memory cards conforming to SD / MMC, CF, MS, or XD specifications), solid-state drives (SSDs), and different types of embedded memory devices (e.g., embedded memory devices conforming to universal flash storage (UFS) or embedded multimedia card (eMMC) specifications). According to this embodiment, memory device 100 may include a controller, such as memory controller 110, and may further include non-volatile (NV) memory 120 (for simplicity, NV memory 120 is referred to as such in the original text). Figure 1 (Referring to "NV memory"), wherein the memory controller 110 is used to access the non-volatile memory 120, and the non-volatile memory 120 is used to store information. The non-volatile memory 120 may include at least one non-volatile memory element (e.g., one or more non-volatile memory elements), such as a plurality of non-volatile memory elements 122-1, 122-2, ..., and 122-N (for simplicity, ... Figure 1 The non-volatile memory 120 can be a flash memory, and the multiple non-volatile memory elements 122-1, 122-2, ..., and 122-N can be multiple flash memory wafers or multiple flash memory dies, but the present invention is not limited thereto.

[0045] like Figure 1As shown, the memory controller 110 may include a processing circuit (e.g., a microprocessor 112), a storage unit (e.g., a read-only memory (ROM) 112M; for simplicity, denoted as "ROM"), a control logic circuit 114, a random access memory (RAM; for simplicity, denoted as "RAM," which may be implemented using static random access memory (SRAM), but the invention is not limited thereto), and a transmission interface circuit 118, wherein at least some (e.g., some or all) of the above components can be coupled to each other via a bus. The random access memory 116 can be used to provide internal storage space to the memory controller 110 (e.g., to temporarily store information). Furthermore, in this embodiment, the read-only memory 112M is used to store program code 112C, and the microprocessor 112 is used to execute program code 112C to control access to the non-volatile memory 120. It should be noted that program code 112C may also be stored in the random access memory 116 or any type of memory. Furthermore, the control logic circuit 114 can be used to control the non-volatile memory 120 and may include an error correction code (ECC) circuit (not shown). Figure 1The transmission interface circuit 118 can perform error correction code encoding and decoding to protect data and / or perform error correction. The transmission interface circuit 118 may include multiple sub-circuits that can interact with each other to communicate. The transmission interface circuit 118 may conform to one or more communication specifications (e.g., Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCIe), Embedded Multimedia Card, or Universal Flash Storage), and can enable the memory device 100 to communicate with the host device 50 (or its transmission interface circuit 58) according to these specifications. Similarly, the transmission interface circuit 58 may conform to these specifications and can enable the host device 50 to communicate with the memory device 100 (or its transmission interface circuit 118) according to these specifications. For example, the plurality of sub-circuits of the transmission interface circuit 118 may include a general-purpose flash memory controller 118C (referred to as "UFS controller" for simplicity), a standardized communication protocol (UniPro) circuit 118U (referred to as "UniPro circuit" for simplicity), and a physical layer (PHY) circuit (e.g., an M-PHY circuit 118M conforming to relevant MIPI Alliance specifications). The transmission interface circuit 58 may be implemented with a circuit architecture similar to or the same as that of the transmission interface circuit 118 (e.g., a plurality of corresponding sub-circuits), but the present invention is not limited thereto.

[0046] In this embodiment, the host device 50 can indirectly access the non-volatile memory 120 within the memory device 100 by transmitting multiple host commands and corresponding logical addresses to the memory controller 110. The memory controller 110 receives multiple host commands and corresponding logical addresses, and converts each host command into multiple memory operation commands (which can be simply referred to as operation commands). The multiple operation commands are then used to control the non-volatile memory 120 to read, write / program, etc., memory cells or data pages at specific physical addresses within the non-volatile memory 120, where physical addresses can be associated with logical addresses. For example, the memory controller 110 can generate or update at least one logical-to-physical (L2P) address mapping table to manage the relationship between physical addresses and logical addresses. The non-volatile memory 120 can store a global logical-to-physical address mapping table 120T for the memory controller 110 to control the memory device 100 to access data in the non-volatile memory 120. However, the present invention is not limited to this. In addition, the memory controller 110 may generate or update at least one physical-to-logical (P2L) address mapping table (e.g., temporary physical-to-logical address mapping table 117T). For example, when needed, the memory controller 110 may refer to the temporary physical-to-logical address mapping table 117T to perform certain internal management operations (e.g., garbage collection (GC) operations).

[0047] For better understanding, the global logic-to-physical address mapping table 120T may be located in a predetermined region (e.g., a system region) within the non-volatile memory element 122-1, but the invention is not limited thereto. For example, the global logic-to-physical address mapping table 120T may be divided into multiple local logic-to-physical address mapping tables, and these multiple local logic-to-physical address mapping tables may be stored in one or more non-volatile memory elements 122-1, 122-2, and 122-N, in particular, they may be stored in non-volatile memory elements 122-1, 122-2, and 122-N respectively. When needed, the memory controller 110 may load at least a portion (e.g., part or all) of the global logic-to-physical address mapping table 120T into the random access memory 116 or other memory. For example, the memory controller 110 may load one of the plurality of local logic-to-physical address mapping tables (e.g., a first local logic-to-physical address mapping table) into the random access memory 116 as a temporary logic-to-physical address mapping table 116T, so that data in the non-volatile memory 120 can be accessed according to the local logic-to-physical address mapping table stored as the temporary logic-to-physical address mapping table 116T. However, the present invention is not limited thereto.

[0048] The memory region of the random access memory 116 may include multiple sub-regions for temporarily storing different information (e.g., buffered data, temporary logical-to-physical address mapping table 116T, and temporary physical-to-logical address mapping table 117T), and at least a portion of these multiple sub-regions (e.g., a portion or all of the sub-regions) of the memory region may be considered as a data buffer. For example, the sub-region used to temporarily store buffered data may be considered as a data buffer, but the invention is not limited thereto. According to some embodiments, all of the memory region (e.g., the multiple sub-regions used to store buffered data, temporary logical-to-physical address mapping table 116T, and temporary physical-to-logical address mapping table 117T) may be considered as a data buffer.

[0049] Furthermore, the aforementioned at least one non-volatile memory element (e.g., one or more non-volatile memory elements, such as {122-1, 122-2, ..., 122-N}) may contain multiple blocks, wherein the smallest unit for the memory controller 110 to perform data erasure operations on the non-volatile memory 120 is a block, and the smallest unit for the memory controller 110 to perform data write operations on the non-volatile memory 120 is a page; however, the present invention is not limited thereto. For example, any one of the non-volatile memory elements 122-1, 122-2, ..., and 122-N, 122-n (the symbol “n” can represent any integer in the interval [1, N]), may contain multiple blocks, and one block within these multiple blocks may contain and record a specific number of pages, wherein the memory controller 110 may access a specific page of a specific block within these multiple blocks according to a block address and a page address.

[0050] According to some embodiments, the memory controller 110 may monitor the effective page counts of the plurality of blocks individually for use in subsequent processing (e.g., garbage collection operations). For data reception, the memory controller 110 may configure at least one block (e.g., one or more blocks) of the plurality of blocks from at least one non-volatile memory element (e.g., one or more non-volatile memory elements, such as {122-1, 122-2, ..., 122-N}) in the non-volatile memory 120 as at least one active block, and use the at least one active block to receive and store data (such as host-write data) from the host device 50. For example, the data (e.g., host write data, such as data to be written to non-volatile memory 120) may contain multiple arrays of partial data, and the aforementioned at least one active block may include a first active block, wherein the temporary entity-to-logical address mapping table 117T may correspond to the first active block. In particular, relevant mapping information may be stored for the first active block to indicate entity-to-logical address mapping relationships. Furthermore, the memory controller 110 may maintain (e.g., generate or update) the temporary entity-to-logical address mapping table 117T for related internal management.

[0051] Figure 2This is a schematic diagram of a first table processing control scheme according to an embodiment of the present invention. During the period when the host device 80 receives and stores data (e.g., host write data, such as data to be written to non-volatile memory 120), the memory controller 110 may utilize a first active block (e.g., active block 220) to receive and store one or more sets of partial data from the complex array partial data, and record the relevant mapping information (e.g., entity-to-logical table entries) in a temporary entity-to-logical address mapping table 117T corresponding to active block 220 (for simplicity, in...). Figure 2 The entity-to-logical address mapping for active block 220 is indicated in the "P2L table". The entity-to-logical address mapping indicated by the entity-to-logical table entries may include an entity-to-logical address mapping between a logical address and an entity address, wherein the host device 50 writes one or more sets of partial data to the logical address, and the entity address indicates the location where the one or more sets of partial data are stored in active block 220. When a first predetermined criterion is met (e.g., active block 220 is fully programmed), the memory controller 110 may perform a set of table processing operations, which may include:

[0052] (1) First table processing operation: According to the temporary entity to logical address mapping table 117T corresponding to active block 220 (for simplicity, in... Figure 2 The global logical-to-entity address mapping table 120T (labeled as "P2L table") is updated to save space. Figure 2 (marked as "L2P table"), in particular, according to the entity-to-logical table entries in the temporary entity-to-logical address mapping table 117T (for brevity, in... Figure 2 (Marked as "P2L project") to update certain logical-to-entity table entries in the global logical-to-entity address mapping table 120T (for brevity, in...) Figure 2 (marked as "L2P project") to indicate the logical-to-entity address mapping for active block 220;

[0053] (2) Second table processing operation: Store the temporary entity-to-logical address mapping table 117T in non-volatile memory 120 to generate or update a first entity-to-logical address mapping table (e.g., entity-to-logical address mapping table 227T, for simplicity, in...). Figure 2 (marked as "P2L table"), for example, by writing all entity-to-logical table entries recorded in the temporary entity-to-logical address mapping table 117T to the entity-to-logical address mapping table 227T to perform the above-mentioned subsequent processing, wherein the entity-to-logical address mapping table 227T can be regarded as a backup version of the temporary entity-to-logical address mapping table 117T; and

[0054] (3) A third table processing operation: After performing the first table processing operation (e.g., updating the global logical-to-entity address mapping table 120T according to the temporary entity-to-logical address mapping table 117T) and the second table processing operation (e.g., storing the temporary entity-to-logical address mapping table 117T in the non-volatile memory 120), the temporary entity-to-logical address mapping table 117T (e.g., the entity-to-logical table entries therein) is cleared to reuse the corresponding storage space in the temporary entity-to-logical address mapping table 117T and / or the random access memory 116; however, the present invention is not limited thereto. According to some embodiments, the first table processing operation may include loading a local logical-to-physical address mapping table (e.g., a first local logical-to-physical address mapping table) within the global logical-to-physical address mapping table 120T into random access memory 116 as a temporary logical-to-physical address mapping table 116T, updating one or more logical-to-physical table entries in the temporary logical-to-physical address mapping table 116T to indicate one or more logical-to-physical address mapping relationships among a plurality of logical-to-physical address mapping relationships for the active block 220, and updating the global logical-to-physical address mapping table 120T (e.g., the local logical-to-physical address mapping table therein) based on the temporary logical-to-physical address mapping table 116T. According to some embodiments, the first predetermined criterion may be replaced by any one of a plurality of predetermined criteria to allow the memory controller 110 to perform the table processing operation when any of the aforementioned criteria is met. For example, the plurality of predetermined criteria may include:

[0055] (1) The first predetermined standard: active block 220 is fully programmed; and

[0056] (2) A second predetermined criterion: The number of entity-to-logical table entries recorded in the temporary entity-to-logical address mapping table 117T reaches a predetermined entry count;

[0057] The predetermined item count may represent a predetermined table size for the temporary entity-to-logical address mapping table 117. For example, the memory controller 110 may perform the table processing operation when the number of entity-to-logical table items in the temporary entity-to-logical address mapping table 117T, when the active block 220 is fully programmed or recorded, reaches the predetermined item count.

[0058] After any one of the at least one active block (e.g., active block 220) has been fully programmed, the memory device 100 (or its memory controller 110) may close the active block to make it an inactive block, and select a blank block (e.g., an erased block) as its replacement for subsequent processing corresponding to the active block. Furthermore, the subsequent processing may include performing a garbage collection procedure to write valid data from all data in the inactive block to another blank block (e.g., another erased block), but the invention is not limited thereto.

[0059] According to some embodiments, since the entity-to-logical address mapping relationships indicated by the entity-to-logical table entries in the at least one entity-to-logical address mapping table (e.g., temporary entity-to-logical address mapping table 117T or entity-to-logical address mapping table 227T) and the logical-to-entity address mapping relationships indicated by the relevant logical-to-entity table entries in the global logical-to-entity address mapping table 120T should be inverse address mapping relationships to each other, the memory controller 110 can determine the latest mapping information (e.g., physical address) carried by the relevant logical-to-entity table entries in the global logical-to-entity address mapping table 120T based on the latest mapping information (e.g., logical address) carried by the entity-to-logical table entries in the at least one entity-to-logical address mapping table. Furthermore, the memory controller 110 can utilize these plurality of local logical-to-entity address mapping tables to manage the relationship between physical addresses and logical addresses (e.g., the physical address indicating the location where host-written data is stored in non-volatile memory 120 and the logical address where host device 50 writes host-written data). For example, the multiple local logic-to-entity address mapping tables can be implemented as a series of local logic-to-entity address mapping tables {L2PT(1), L2PT(2), ..., L2PT(X)} corresponding to a series of logical address ranges {L_Addr_R(1), L_Addr_R(2), ..., L_Addr_R(R_CNT)}, and the series of logical address ranges {L_Addr_R(1), L_Addr_R(2), ..., L_Addr_R(R_CNT)} can be implemented as a series of consecutive logical... The range of the logical address {L_Addr(0),L_Addr(1),…,L_Addr((R_CNT*R_Size)-1)}, such as the range of R_CNT intervals [L_Addr(0),L_Addr(R_Size-1)], [L_Addr(R_Size),L_Addr((2*R_Size)-1)],… and [L_Addr((R_CNT-1)*R_Size),L_Addr((R_CNT*R_Size)-1)].

[0060] According to some embodiments, the memory device 100 (or the memory controller 110 therein) may update the global logical-to-physical address mapping table 120T according to at least one entity-to-logical address mapping table (e.g., temporary entity-to-logical address mapping table 117T or entity-to-logical address mapping table 227T), wherein the address mapping relationships indicated by the at least one entity-to-logical address mapping table (e.g., temporary entity-to-logical address mapping table 117T or entity-to-logical address mapping table 227T) are generally newer than the address mapping relationships indicated by the global logical-to-physical address mapping table 120T. For example, in one embodiment, the memory device 100 (or the memory controller 110 therein) may operate according to a search and read control scheme, in particular, a search operation may be performed on the at least one entity-to-logical address mapping table (e.g., temporary entity-to-logical address mapping table 117T or entity-to-logical address mapping table 227T) before reading any data from the non-volatile memory 120, but the invention is not limited thereto. To better understand, assume that regardless of whether the logical address L_Addr is found in the temporary entity-to-logical address mapping table 117T, the expected value of the time to search for a target logical address (e.g., logical address L_Addr) in the temporary entity-to-logical address mapping table 117T is equal to a search time T_search (e.g., 15 microseconds), and the expected value of the time to read any of the aforementioned data from the non-volatile memory 120 is equal to a read time T_read, such as a busy time tR (e.g., 68 microseconds). Therefore, the memory device 100 (or its memory controller 110) operating according to this search and read control scheme may require at least the search and read time (T_search + T_read) to prepare any of the aforementioned data in the memory controller 110 for transmission back to the host device 50. In some other embodiments, the memory device 100 (or the memory controller 110 therein) may operate according to at least one other control scheme (e.g., one or more other control schemes) to hide the search time T_search during the read time T_read to increase overall performance.

[0061] Figure 3 This is a schematic diagram of a search-time-hidden table processing control scheme for a method of managing data access to a memory device in a predetermined communication architecture using multi-table checks, according to an embodiment of the present invention. The memory device 100 (or its memory controller 110) can, according to... Figure 3 The search time hidden table processing control scheme shown is used for operation.

[0062] In step S10, the memory device 100 (or memory controller 110) may receive one of a plurality of host commands from the host device 50.

[0063] In step S11, the memory device 100 (or memory controller 110) may check whether the host command (e.g., the host command received from the host device 50 in step S10) is a first command (e.g., a read command; for brevity, ...). Figure 3 If the command is marked as "read", proceed to step S12; otherwise, proceed to step S19. For example, the first command may carry first information associated with the first data to be written, and the first information may include a first logical address (e.g., logical address L_Addr), wherein the first command may indicate a request to read the first data from logical address L_Addr, but the invention is not limited thereto. In addition to the first logical address (e.g., logical address L_Addr), the first information may also include a first data length (e.g., length LENGTH) of the first data to indicate a first logical address region starting from the first logical address (e.g., a logical address region L_Addr_Region starting from logical address L_Addr and having length LENGTH), wherein the first command may indicate a request to read the first data from the first logical address region (e.g., logical address region L_Addr_Region).

[0064] In step S12, the memory device 100 (or memory controller 110) may perform a first logical-to-physical address mapping operation on the logical address L_Addr according to the global logical-to-physical address mapping table 120T (for simplicity, in...). Figure 3 (marked as "L2P mapping") to obtain a first entity address P_Addr1 associated with the logical address L_Addr.

[0065] In step S13, the memory device 100 (or memory controller 110) may use a first non-volatile read command (e.g., a flash read command) among the plurality of operation commands to trigger the non-volatile memory 120 to begin reading at the first physical address P_Addr1 associated with the logical address L_Addr (e.g., reading data stored at the first physical address P_Addr1 from the non-volatile memory 120), and in the temporary physical-to-logical address mapping table 117T corresponding to the active block 220 (for simplicity, in... Figure 3 The same logical address L_Addr is searched in the table marked "P2L" to attempt to obtain any entity address (e.g., a second entity address P_Addr2) associated with the logical address L_Addr according to the temporary entity-to-logical address mapping table 117T.

[0066] In step S14, the memory device 100 (or memory controller 110) may check whether the logical address L_Addr is found in the temporary entity-to-logical address mapping table 117T (for better understanding, in...). Figure 3 If the first logical address is found (e.g., the temporary entity to logical address mapping table 117T is found), proceed to step S15; otherwise, proceed to step S17.

[0067] In step S15, the memory device 100 (or memory controller 110) may use one of the plurality of operation commands, a second non-volatile read command (e.g., another flash read command), to trigger the non-volatile memory 120 to begin reading at the second physical address P_Addr2 associated with the logical address L_Addr (e.g., reading data stored at the second physical address P_Addr2 from the non-volatile memory 120).

[0068] In step S16, the memory device 100 (or memory controller 110) may send the data read from the second physical address P_Addr2 back to the host device 50 as the first data.

[0069] In step S17, the memory device 100 (or memory controller 110) may send the data read from the first physical address P_Addr1 back to the host device 50 as the first data.

[0070] In step S18, the memory device 100 (or memory controller 110) may check for any new host-side event (e.g., any new command) from the host device 50; for brevity, Figure 3 (marked as "new command"), specifically, waiting for any of the aforementioned new host events until a predetermined waiting time expires; if yes (e.g., the memory controller 110 detects any of the aforementioned new host events before the predetermined waiting time expires), proceed to step S10; if no (e.g., the memory controller 110 does not detect a new host event before the predetermined waiting time expires), then... Figure 3 The workflow shown has ended.

[0071] In step S19, the memory device 100 (or memory controller 110) may perform other processing according to host commands (e.g., host commands received from host device 50 in step S10).

[0072] The memory device 100 (or its memory controller 110) can perform the operation of step S12 very quickly, and can then trigger the non-volatile memory 120 using the first non-volatile read command and simultaneously (or nearly simultaneously) begin searching for the logical address L_Addr in the temporary entity-to-logical address mapping table 117T in step S13, thereby hiding the search time T_search (e.g., 15 microseconds) within the read time T_read (e.g., 68 microseconds), and thus increasing overall performance. Assume that the hit rate of the search operation in step S13 is equal to P%, where "P" can represent a positive value in the interval [0, 100]. The expected time for the memory device 100 (or its memory controller 110) to respond to a first command (e.g., a read command) to prepare the first data in the memory controller 110 for transmission back to the host device 50 can be equal to the total processing time T_total as follows: T_total = ((100-P)%*T_read) + (P%*(2*T_read));

[0073] The hit rate P% will be very low. For example, P=1, and the total processing time T_total can be rewritten as follows: T_total = (99% * T_read) + (1% * (2 * T_read)) = (1.01 * T_read);

[0074] The total processing time T_total (e.g., 68.68 microseconds) is roughly equal to the read time T_read (e.g., 68 microseconds).

[0075] To better understand this method, it can be achieved through... Figure 3 The workflow shown is intended to illustrate the invention, but the invention is not limited thereto. According to some embodiments, one or more steps may be performed... Figure 3 Add, delete, or modify within the workflow shown.

[0076] Figure 4 This is a schematic diagram illustrating the workflow of a method according to an embodiment of the present invention. The memory device 100 (or its memory controller 110) can, according to... Figure 4 Follow the workflow shown.

[0077] In step S20, the memory device 100 (or memory controller 110) may receive a first command from the host device 50 through the transmission interface circuit 118 of the memory controller 110, wherein the first command may indicate a request to read first data located at a first logical address (e.g., logical address L_Addr).

[0078] In step S21, the memory device 100 (or memory controller 110) may check at least one logic-to-entity address mapping table (e.g., global logic-to-entity address mapping table 120T) to generate a first check result, initiate a first read operation based on the first check result, and check the temporary entity-to-logic address mapping table 117T corresponding to the active block 220 to generate a second check result, so as to selectively perform a second read operation based on the second check result. For example, the operation of step S21 may include:

[0079] (1) The memory device 100 (or memory controller 110) may check the at least one logic-to-physical address mapping table (e.g., global logic-to-physical address mapping table 120T) by performing step S12 to obtain the first physical address P_Addr1 associated with the logical address L_Addr from the global logic-to-physical address mapping table 120T as the first check result, wherein the at least one logic-to-physical address mapping table (e.g., global logic-to-physical address mapping table 120T) can be used to map the logical address L_Addr to the first physical address P_Addr1, so that the memory controller 110 can perform a first read operation based on the first physical address P_Addr1. In particular, in step S13, the flash memory 120 is triggered using a first non-volatile read command (e.g., a flash read command) to start reading at the first physical address P_Addr1 associated with the logical address L_Addr; and

[0080] (2) The memory device 100 (or memory controller 110) may search for the logical address L_Addr in the temporary entity-to-logical address mapping table 117T as mentioned in step S13 to check the temporary entity-to-logical address mapping table 117T corresponding to the active block 220, in order to attempt to obtain any of the above-mentioned entity addresses (e.g., the second entity address P_Addr2) associated with the logical address L_Addr according to the temporary entity-to-logical address mapping table 117T, as a second check result;

[0081] Whether a second read operation is performed depends on whether the logical address L_Addr is found in the temporary entity-to-logical address mapping table 117T.

[0082] For example, if the logical address L_Addr is found in the temporary entity-to-logical address mapping table 117T (e.g., the result of step S14 is "yes"), the memory controller 110 can perform a second read operation based on any of the aforementioned entity addresses associated with the logical address L_Addr (e.g., the second entity address P_Addr2). In particular, the flash memory 120 is triggered using a second non-volatile read command (e.g., another flash read command) to begin reading at the second entity address P_Addr2 associated with the logical address L_Addr (step S15); otherwise (e.g., the result of step S14 is "no"), the memory controller 110 can prevent the second read operation from being performed. Furthermore, the second check result can indicate whether the logical address L_Addr is found in the temporary entity-to-logical address mapping table 117T for determining whether to perform the second read operation, but the invention is not limited thereto. According to some embodiments, if a logical address L_Addr is found in the temporary entity-to-logical address mapping table 117T (e.g., the judgment result of step S14 is "yes"), the memory controller can use it to determine any of the above-mentioned entity addresses associated with the logical address L_Addr (e.g., the second entity address P_Addr2) as the second check result; otherwise (e.g., the judgment result of step S14 is "no"), the memory controller 110 can use it to determine a null entity address P_Addr_Null that is not associated with a logical address as the second check result, wherein the null entity address P_Addr_Null may represent an invalid entity address (e.g., a null value) and will not be associated with any logical address. For example, the memory controller 110 may call one of its multiple functions, a search function, to search for the logical address L_Addr in the temporary entity-to-logical address mapping table 117T (step S13), and the search function may return a second check result (e.g., the second entity address P_Addr2 or the null entity address P_Addr_Null).

[0083] In step S22, the memory device 100 (or memory controller 110) may send the first data back to the host device 50, wherein the first data may be read based on one of the first check result and the second check result. For example, if the logical address L_Addr is found in the temporary entity-to-logical address mapping table 117T (e.g., the judgment result of step S14 is "yes"), the memory controller 110 can obtain the second check result (e.g., the second entity address P_Addr2) and perform a second read operation based on the second entity address P_Addr2. In particular, the non-volatile memory 120 can be triggered using a second non-volatile read command (e.g., other flash read commands) to start reading at the second entity address P_Addr2 associated with the logical address L_Addr (step S15), and the data read at the second entity address P_Addr2 is sent back to the host device 50 as first data (step S16); otherwise (e.g., the judgment result of step S14 is "no"), the memory controller 110 can send the data read at the first entity address P_Addr1 back to the host device 50 as first data (step S17).

[0084] In step S23, the memory device 100 (or memory controller 110) may determine whether to proceed with the next operation based on whether there is any new host event (e.g., any new host event in step S18, such as any of the aforementioned new commands). If yes (e.g., the memory controller 110 detects any of the aforementioned new host events before the predetermined waiting time expires), proceed to step S20; if no (e.g., the memory controller 110 does not detect any host event before the predetermined waiting time expires), then... Figure 4 The workflow shown is now complete. For example, step S23 is similar to or the same as step S18.

[0085] For example, a first time period T1(t11,t12) (e.g., read time T_read, such as 68 microseconds) between a first start time t11 when the memory controller 110 begins checking at least one of the aforementioned logical-to-physical address mapping tables (e.g., global logical-to-physical address mapping table 120T) and a first end time t12 when the memory controller 110 completes the first read operation is typically greater than a second time period T2(t21,t22) (e.g., search time T_search, such as 15 microseconds) between a second start time t21 when the memory controller 110 begins checking the temporary physical-to-logical address mapping table 117T and a second end time t22 when the memory controller 110 completes checking the temporary physical-to-logical address mapping table 117T is typically greater than a second time period T2(t21,t22) (e.g., search time T_search, such as 15 microseconds) when the memory controller 110 completes checking the temporary physical-to-logical address mapping table 117T is typically checking the temporary physical-to-logical address mapping table 117T. The memory controller 110 can be used to control the second start time point t21 to be equal to or later than the first start time point t11, so as to hide the second time period T2(t21,t22) within the first time period T1(t11,t12) for checking the temporary entity-to-logical address mapping table 117T. Furthermore, the first time period T1(t11,t12) used to check at least one of the aforementioned logical-to-entity address mapping tables (e.g., the global logical-to-entity address mapping table 120T) and to perform the first read operation may include the second time period T2(t21,t22) used to check the temporary entity-to-logical address mapping table 117T. For the sake of brevity, similar details of this embodiment will not be described in detail here.

[0086] To better understand this method, it can be achieved through... Figure 4 The workflow shown is intended to illustrate the invention, but the invention is not limited thereto. According to some embodiments, one or more steps may be performed... Figure 4 Add, delete, or modify within the workflow shown.

[0087] According to some embodiments, the first check result may represent the first entity address P_Addr1 associated with the logical address L_Addr as indicated by the at least one logical-to-entity address mapping table (e.g., global logical-to-entity address mapping table 120T). Furthermore, depending on whether the logical address L_Addr is found in the temporary entity-to-logical address mapping table 117T, the memory controller 110 may determine a selected entity address from at least one candidate entity address (e.g., one or more candidate entity addresses) for reading data at that selected entity address as first data, wherein the selected entity address may be selected from the at least one candidate entity address, and the at least one candidate entity address may contain the first entity address P_Addr1. For example, if a logical address L_Addr is found in the temporary entity-to-logical address mapping table 117T, the second check result may represent the second entity address P_Addr2 associated with the logical address L_Addr as indicated by the temporary entity-to-logical address mapping table 117T, wherein the aforementioned at least one candidate entity address may also include the second entity address P_Addr2; otherwise, the aforementioned at least one candidate entity address may only include the first entity address P_Addr1. For the sake of brevity, similar details of these embodiments will not be described in detail here.

[0088] Figure 5 This is a schematic diagram of a block expansion control scheme according to an embodiment of the present invention. For example, the plurality of non-volatile memory elements 122-1, 122-2, ..., and 122-N can be implemented as a plurality of flash memory wafers (e.g., wafer #0 and wafer #1) or a plurality of flash memory dies (e.g., die #0 and die #1), wherein the plurality of non-volatile memory elements 122-1, 122-2, ..., and 122-N may include at least two memory elements 122-1 and 122-2 (e.g., wafer #0 and wafer #1, or die #0 and die #1; for simplicity, ...). Figure 5 The wafers are labeled "Wafer / Die #0" and "Wafer / Die #1" respectively, but the invention is not limited thereto. According to some embodiments, the wafer count of the plurality of flash memory wafers or the die count of the plurality of flash memory dies may vary.

[0089] The aforementioned plurality of non-volatile memory elements 122-1, 122-2, ..., and any one of the non-volatile memory elements 122-n (e.g., any one of wafers #0 and #1, or any one of bare dies #0 and #1) may contain a plurality of planes (e.g., plane #0 and plane #1), wherein any one of the planes #0 and #1 of the aforementioned non-volatile memory elements 122-n (e.g., any one of wafers #0 and #1, or any one of bare dies #0 and #1) may contain its own block {BLK}, such as block {BLK(0), BLK(1), ...}. Under the control of the memory controller 110, the memory device 100 can combine a set of first corresponding blocks {BLK(0)} in all planes (e.g., plane #0 and plane #1) of all non-volatile memory elements (e.g., wafer #0 and wafer #1, or bare die #0 and bare die #1) into a first superblock XBLK(0), but the present invention is not limited thereto. For example, the memory device 100 can combine multiple sets of corresponding blocks {BLK} (e.g., blocks {{BLK(0)}, {BLK(1)}, ...}) in all planes (e.g., plane #0 and plane #1) of all non-volatile memory elements (e.g., wafer #0 and wafer #1, or bare die #0 and bare die #1) into multiple superblocks {XBLK} (e.g., superblocks {XBLK(0), XBLK(1), ...}). Furthermore, the memory controller 110 can access (e.g., read or write) multiple sets of corresponding blocks {BLK} (e.g., blocks {{BLK(0)}, {BLK(1)}, ...}) within the superblock {XBLK(0), XBLK(1), ...} based on multiple physical block addresses (PBA) {XBlk} (e.g., physical block addresses {XBlk(0), XBlk(1), ...}), and in particular, it can access (e.g., read or write) corresponding pages {PG} (e.g., pages {PG(0), PG(1), ...}) within the superblock {XBLK(0), XBLK(1), ...} based on the physical block address {XBlk} and the associated physical page address (PPA) {XPg} (e.g., physical page addresses {XPg(0), XPg(1), ...}). For better understanding, assume that "r0" and "r1" can be non-negative integers. Figure 5The blocks {BLK(r0)} in the same row shown (e.g., blocks {BLK(0)} in the first row and blocks {BLK(1)} in the second row) can represent a set of corresponding blocks {BLK(r0)} accessed by the same entity block address XBlk(r0), and in particular, can be considered as one of the multiple superblocks {XBLK}. For blocks {BLK(r0)} in this row, Figure 5 The pages {PG(r1)} in the same row shown (e.g., the pages {PG(0)} in the first row and the pages {PG(1)} in the second row) can represent a set of corresponding pages {PG(r1)} accessed by the same entity page address XPg(r1), and in particular, can be one of multiple superpages {XPG} (e.g., superpages {XPG(0), XPG(1), ...}).

[0090] Table 1

[0091] Logical address physical address LBA0 XBlk(5), XPg(0) LBA1 XBlk(5), XPg(1) LBA2 XBlk(5), XPg(2) LBA3 XBlk(5), XPg(3) LBA4 XBlk(5), XPg(4) LBA5 XBlk(5), XPg(5) LBA6 XBlk(5), XPg(6) LBA7 XBlk(5), XPg(7) LBA8 XBlk(6), XPg(19) LBA9 XBlk(5), XPg(9) LBA10 XBlk(14), XPg(17) LBA11 XBlk(5), XPg(11) LBA12 XBlk(5), XPg(12) LBA13 XBlk(5), XPg(13) LBA14 XBlk(5), XPg(14) LBA15 XBlk(5), XPg(15) … …

[0092] Table 2

[0093]

[0094]

[0095] Table 1 illustrates an example of a local logical-to-entity address mapping table (e.g., the first local logical-to-entity address mapping table, which may correspond to a certain logical address range) within the global logical-to-entity address mapping table 120T, while Table 2 illustrates an example of a temporary entity-to-logical address mapping table 117T. The symbol “…” indicates that certain table contents may be deleted, but the invention is not limited thereto. According to some embodiments, the contents, format, etc., of the local logical-to-entity address mapping table shown in Table 1 and / or the contents, format, etc., of the temporary entity-to-logical address mapping table 117T shown in Table 2 may vary. For example, since the sorting and / or arrangement of the contents in Table 1 can correspond to logical addresses {LBA0,LBA1,LBA2,LBA3,LBA4,LBA5,LBA6,LBA7,LBA8,LBA9,LBA10,LBA11,LBA12,LBA13,LBA14,LBA15,…} (e.g., logical block address (LBA){0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,…}), the "Logical Address" field in Table 1 can be deleted. For example, since the sorting and / or arrangement of the table contents in Table 2 can correspond to entity addresses XPg(0), XPg(1), XPg(2), XPg(3), XPg(4), XPg(5), XPg(6), XPg(7), XPg(8), ...} (e.g., entity page addresses {0,1,2,3,4,5,6,7,8,...}), the column "Entity Address" in Table 2 can be deleted.

[0096] Based on the block expansion control scheme, the memory device 100 (or the memory controller 110 therein) can access the plurality of superblocks {XBLK} (e.g., their superpages {XPG}) to access the corresponding block {BLK} (e.g., their corresponding page). In particular, the host device 50 can store data in one or more of the plurality of superblocks {XBLK} (e.g., their superpages {XPG}) and read the stored data from the one or more superblocks {XBLK} (e.g., their superpages {XPG}) for transmission back to the host device 50. For example, L_Addr = LBA13, and the first command mentioned in step S20 may indicate a request to read the first data located at logical address L_Addr (e.g., logical address LBA13). The memory device 100 (or the memory controller 110 therein) may check the above-mentioned at least one logical-to-physical address mapping table (e.g., the local logical-to-physical address mapping table shown in Table 1) to generate a first check result, and start performing a first read operation based on the first check result (step S21). Furthermore, the memory device 100 (or the memory controller 110 therein) may check the temporary entity-to-logical address mapping table 117T (e.g., the temporary entity-to-logical address mapping table 117T shown in Table 2) corresponding to a certain active superblock (e.g., active superblock #18) to generate a second check result, so as to selectively perform a second read operation based on the second check result (step S21), wherein the aforementioned at least one active block (e.g., active block 220) may be implemented by at least one superblock (e.g., active superblock XBLK(18) located at entity block address XBlk(18)).

[0097] Since the logical address L_Addr (e.g., logical address LBA13) is found in the temporary entity-to-logical address mapping table 117T shown in Table 2, the latest address mapping relationship for the logical address L_Addr (e.g., logical address LBA13) is indicated by the entity-to-logical item (6, LBA13) in the temporary entity-to-logical address mapping table 117T shown in Table 2 (e.g., the temporary entity-to-logical address mapping table 117T corresponding to active superblock #18), rather than by the logical-to-entity item (LBA13, (XBlk(5), XPg(13))) in the local logical-to-entity address mapping table shown in Table 1. Therefore, the memory device 100 (or its memory controller 110) can obtain a second physical address P_Addr2 (e.g., physical address (XBlk(18), XPg(6)), which may contain the physical block address XBlk(18) and the physical page address XPg(6)) and perform a second read operation based on the second physical address P_Addr2 (e.g., physical address (XBlk(18), XPg(6))). In particular, a second non-volatile read command (e.g., other flash read command) can be used to trigger the non-volatile memory 120 to start reading at physical address (XBlk(18), XPg(6)) and return the data read at physical address (XBlk(18), XPg(6)) to the host device 50 as first data. For the sake of brevity, similar content in this embodiment will not be described in detail here again.

[0098] According to some embodiments, since the memory controller 110 can load the local logic-to-physical address mapping table (e.g., the first local logic-to-physical address mapping table) within the global logic-to-physical address mapping table 120T into the random access memory 116 as a temporary logic-to-physical address mapping table 116T, the temporary logic-to-physical address mapping table 116T can be implemented as the local logic-to-physical address mapping table shown in Table 1. For the sake of brevity, similar details of these embodiments will not be described in detail here.

[0099] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A method for managing data access to a memory device in a predetermined communication architecture using multi-table checks, the method being applied to a memory controller of the memory device, the memory device including the memory controller and a non-volatile memory, the non-volatile memory including at least one non-volatile memory element, the at least one non-volatile memory element including a plurality of blocks, the method comprising: The memory controller is used to receive a first command from a host device through a transmission interface circuit of the memory controller, wherein the first command indicates a request to read first data located at a first logical address. The system checks at least one logical-to-entity address mapping table to generate a first check result, initiates a first read operation based on the first check result, and checks a temporary entity-to-logical address mapping table corresponding to a first active block to generate a second check result, for selectively performing a second read operation based on the second check result; and The first data is sent back to the host device, wherein the first data is read based on one of the first check result and the second check result.

2. The method as described in claim 1, characterized in that, The steps of checking the at least one logical-to-entity address mapping table to produce the first check result include: The at least one logical-to-entity address mapping table is checked to obtain a first entity address associated with the first logical address from the at least one logical-to-entity address mapping table, as the first check result, wherein the at least one logical-to-entity address mapping table is used to map the first logical address to the first entity address.

3. The method as described in claim 1, characterized in that, The step of checking the temporary entity-to-logical address mapping table corresponding to the first active block to generate the second check result includes: By searching the first logical address in the temporary entity-to-logical address mapping table to check the temporary entity-to-logical address mapping table corresponding to the first active block, an attempt is made to obtain any entity address associated with the first logical address based on the temporary entity-to-logical address mapping table as the second check result; Whether or not the second read operation is performed depends on whether the first logical address is found in the temporary entity-to-logical address mapping table.

4. The method as described in claim 3, characterized in that, If the first logical address is found in the temporary entity-to-logical address mapping table, the memory controller is used to perform the second read operation based on any entity address associated with the first logical address; Otherwise, the memory controller is used to prevent the second read operation from being performed.

5. The method as described in claim 3, characterized in that, The second check result indicates whether the first logical address is found in the temporary entity-to-logical address mapping table, in order to determine whether to perform the second read operation.

6. The method as described in claim 3, characterized in that, If the first logical address is found in the temporary entity-to-logical address mapping table, the memory controller determines the entity address associated with the first logical address as the second check result; otherwise, the memory controller determines an empty entity address not associated with a logical address as the second check result.

7. The method as described in claim 1, characterized in that, The first check result represents a first entity address associated with the first logical address as indicated by the at least one logical-to-entity address mapping table; and based on whether the first logical address is found in the temporary entity-to-logical address mapping table, the memory controller determines a selected entity address from at least one candidate entity addresses for reading data at the selected entity address as the first data, wherein the selected entity address is selected from the at least one candidate entity address, and the at least one candidate entity address contains the first entity address.

8. The method as described in claim 7, characterized in that, If the first logical address is found in the temporary entity-to-logical address mapping table, the second check result represents a second entity address associated with the first logical address as indicated by the temporary entity-to-logical address mapping table, wherein the at least one candidate entity address also contains the second entity address; otherwise, the at least one candidate entity address contains only the first entity address.

9. The method as described in claim 1, characterized in that, A first time period between a first start time point when the memory controller begins checking the at least one logical-to-physical address mapping table and a first end time point when the memory controller completes the first read operation is greater than a second time period between a second start time point when the memory controller begins checking the temporary physical-to-logical address mapping table and a second end time point when the memory controller completes checking the temporary physical-to-logical address mapping table, wherein the memory controller controls the second start time point to be equal to or later than the first start time point to hide the second time period within the first time period for checking the temporary physical-to-logical address mapping table.

10. The method as described in claim 1, characterized in that, A first time period between a first start time point when the memory controller begins checking the at least one logical-to-physical address mapping table and a first end time point when the memory controller completes the first read operation is greater than a second time period between a second start time point when the memory controller begins checking the temporary physical-to-logical address mapping table and a second end time point when the memory controller completes checking the temporary physical-to-logical address mapping table, wherein the first time period used to check the at least one logical-to-physical address mapping table and to perform the first read operation includes the second time period used to check the temporary physical-to-logical address mapping table.

11. A memory controller for a memory device, the memory device including the memory controller and a non-volatile memory, the non-volatile memory including at least one non-volatile memory element, the at least one non-volatile memory element including a plurality of blocks, the memory controller including: A processing circuit is used to control the memory controller according to a plurality of host commands from a host device, so as to allow the host device to access the non-volatile memory through the memory controller, wherein the processing circuit is used to perform data access management of the memory device in a predetermined communication architecture by means of multi-table checks. as well as A transmission interface circuit for communicating with the host device; in: The memory controller receives a first command from the host device through the memory controller's transmission interface circuit, wherein the first command indicates a request to read first data located at a first logical address; The memory controller checks at least one logical-to-physical address mapping table to generate a first check result, initiates a first read operation based on the first check result, and checks a temporary physical-to-logical address mapping table corresponding to a first active block to generate a second check result, for selectively initiating a second read operation based on the second check result; and The memory controller sends the first data back to the host device, wherein the first data is read based on one of the first check result and the second check result.

12. A memory device comprising the memory controller of claim 11, wherein the memory device comprises: This non-volatile memory is used to store information; and The memory controller is coupled to the non-volatile memory and is used to control the operation of the memory device.

13. An electronic device comprising the memory device of claim 12, and further comprising: The host device is coupled to the memory device, wherein the host device includes: At least one processor is used to control the operation of the host device; as well as A power supply circuit is coupled to the at least one processor and is used to provide power to the at least one processor and the memory device; The memory device provides storage space to the host device.

Images