Electrical mirroring implemented by the NAND flash controller

Abstract

A system, apparatus, and method for electronic mirroring implemented by a storage controller in a nonvolatile storage system are provided. In one embodiment, the nonvolatile storage system may include multiple nonvolatile storage devices and a storage controller. The storage controller may be configured to perform an electronic mirroring configuration process, which includes: determining a system topology of the nonvolatile storage system and which targets are located in the mirrored nonvolatile storage devices; and setting corresponding register bits in the storage controller for all targets in all mirrored nonvolatile storage devices in the multiple nonvolatile storage devices.

Description

[0001] This application is a divisional application of the invention application with application date of November 30, 2020, application number 202011378509.1, and invention name “Electronic mirroring implemented by NAND flash memory controller”. Technical Field

[0002] The present disclosure relates to the architecture and implementation of a NAND flash memory controller, and more particularly to a multi-branch multi-load NAND interface topology in which multiple NAND flash memory devices share a common data bus with the NAND controller. Background Art

[0003] The advent of solid-state drives (SSDs) has driven the development of modern computing systems, offering significantly higher speeds and latency than traditional hard drives. Unlike hard drives, which rely on magnetism to store data, SSDs use NAND flash memory devices for data storage. NAND flash memory devices are a family of integrated circuits manufactured using advanced process and assembly techniques, enabling multiple layers of memory cells to be stacked vertically into a smaller package, thus achieving high storage capacity.

[0004] A typical SSD consists of a controller and multiple NAND flash memory devices connected on a printed circuit board (PCB) in a standard form factor suitable for various consumer or enterprise applications. The interface between the controller and NAND flash memory devices is grouped into channels, with modern controllers typically featuring 4, 8, or 16 NAND channels. To achieve higher storage capacities, SSDs must integrate more NAND flash memory devices onto the PCB, resulting in multiple NAND devices sharing a single channel. As a result, high-density SSD designs often employ a multi-load or multi-drop PCB topology. Summary of the Invention

[0005] Typical high-capacity SSD multi-load PCBs, whether in an M.2 or U.2 form factor, typically employ a so-called clamshell topology for the NAND flash devices. In this topology, the NAND devices on one side of the PCB can completely overlap with the NAND devices on the other side. Because the pins of the NAND devices may be located on one side of the NAND device, one of the two NAND devices can be mounted and positioned flipped. The pin order of the flipped NAND device will completely mirror the pin order of the non-flipped NAND device. For example, with respect to the zero-based indexing of the eight-bit data bus of DQ[0…7], this means that DQ[0] of the flipped NAND device will align with DQ[7] of the non-flipped NAND device, DQ[1] of the flipped NAND device will align with DQ[6] of the non-flipped NAND device, and so on.

[0006] However, this setup presents challenges for PCB layout and signal integrity. For example, the same DQ pins of a flipped NAND device and a non-flipped NAND device will always be in mirror-symmetric positions relative to the centerline of the NAND device. That is, for example, DQ[0] of the flipped NAND device and DQ[0] of the non-flipped NAND device will be on opposite sides of the symmetric position relative to the centerline of the NAND device. DQ[1] of the flipped NAND device and DQ[1] of the non-flipped NAND device will be on opposite sides of the symmetric position relative to the centerline of the NAND device, and so on. As a result, if two NAND devices arranged in a flip topology share a channel, then the same two DQ pins (e.g., DQ[0] of the flipped NAND device and DQ[0] of the non-flipped NAND device) are normally connected by multiple vias placed along the centerline of the NAND device, and there will be two relatively long traces from the vias to the pins. These trace lengths are typically in the range of 300-mil to 500-mil. On the other hand, the signal integrity specifications for high-speed NAND interfaces require that these traces be as short as possible, with a maximum length of less than 200 mils. Having such long trace lengths often results in NAND performance degradation by one or two speed grades, which is especially challenging for high-capacitance NAND devices with heavy capacitive loading.

[0007] One approach to addressing the signal integrity degradation issue may be to have two sets of pin maps for the same NAND device: a regular pin map and an inverted pin map. The inverted pin map can have an inverted data pin order. That is, the DQ[7] data pin in the inverted pin map can be set at the location of the DQ[0] data pin in the regular pin map, the DQ[6] data pin in the inverted pin map can be set at the location of the DQ[1] data pin in the regular pin map, and so on. Thus, a NAND device with a regular pin map can be matched with a NAND device with an inverted pin map, and the data pins of the two NAND devices can be matched and mirrored on both sides of the PCB. This will allow the via to be set next to the pin, and a very short trace of about 20 mils in length can be routed from the via to the data pin. This solution will greatly improve the PCB layout quality and address the signal integrity degradation issue mentioned above to help enable the system to achieve higher NAND interface speeds. This technique of inverting or mirroring the NAND data pin order can be called electrical mirroring.

[0008] Existing solutions use a dedicated electrical mirroring command sent from the controller to the NAND flash device immediately after device initialization. Upon receiving this command, the NAND device configures itself into mirroring mode, where the DQ pins are reversed from the normal pinout. That is, pin DQ0 is now configured internally as DQ7 within the NAND device, DQ1 becomes DQ6, and so on. However, the NAND device must be configured to support this electrical mirroring functionality.

[0009] Furthermore, the electronic mirroring configuration command has zero fault tolerance. This message must be sent immediately after initialization. Because it is sent before any device training and commissioning, the potential for error and failure is very high. In the event of a failure, since the NAND device lacks any reset mechanism, the entire NAND device becomes inaccessible until the next power cycle. Furthermore, no client or enterprise system user would want to cycle power. In practice, due to the high failure rate, the use of this electronic mirroring feature is generally avoided.

[0010] Therefore, there is a need in the art for a more flexible and powerful electrical mirroring technique. A new electrical mirroring technique can be developed and implemented in a NAND flash memory controller. In various embodiments, a NAND device that requires mirroring has its data pins connected to the data pins of the controller in an inverted order. The controller can use firmware to determine whether electrical mirroring is enabled or disabled for each individual NAND device, and can use firmware to configure a set of registers having bits corresponding to each individual NAND device set by the firmware during a configuration process (e.g., power-on initialization). Once electrical mirroring is enabled for a NAND device, the controller can reverse the order of the data bits before sending data to a NAND device with inverted data pins, and can also reverse data received from a NAND device with inverted data pins.

[0011] In an exemplary embodiment, a method is provided that may include determining a system topology of a nonvolatile storage system and which targets are located in mirrored nonvolatile storage devices, and setting corresponding register bits in a storage controller for all targets in all mirrored nonvolatile storage devices.

[0012] In another exemplary embodiment, a nonvolatile storage system is provided. The nonvolatile storage system may include multiple nonvolatile storage devices and a storage controller. The storage controller may be configured to perform an electronic mirroring configuration process, the electronic mirroring configuration process including: determining a system topology of the nonvolatile storage system and which targets are located in mirrored nonvolatile storage devices, and setting corresponding register bits in the storage controller for all targets in all mirrored nonvolatile storage devices of the multiple nonvolatile storage devices.

[0013] In yet another exemplary embodiment, a non-transitory machine-readable medium is provided. The non-transitory machine-readable medium may have computer instructions that, when executed by a hardware processor, cause the hardware processor to determine a system topology of a non-volatile storage system and which targets are located in mirrored non-volatile storage devices, and set corresponding register bits in a storage controller for all targets in all mirrored non-volatile storage devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A non-volatile storage system according to an embodiment of the present disclosure is schematically shown.

[0015] Figure 2 The figure schematically shows a mirroring configuration of two non-volatile storage devices according to one embodiment of the present disclosure.

[0016] Figure 3 The figure schematically shows details of a mirror configuration of two non-volatile storage devices according to one embodiment of the present disclosure.

[0017] Figure 4 A 2-channel non-volatile storage system according to an embodiment of the present disclosure is schematically shown.

[0018] Figure 5 The figure schematically shows read and write signaling for a 2-channel non-volatile memory system according to one embodiment of the present disclosure.

[0019] Figure 6 is a flowchart of an electronic mirror configuration process according to one embodiment of the present disclosure.

[0020] Figure 7 FIG. 1 is a flowchart of a process of writing operations to a mirrored NAND device according to one embodiment of the present disclosure.

[0021] Figure 8 FIG. 1 is a flowchart of a process for reading operations from a mirrored NAND device according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] Now, the specific embodiment according to the present application will be described in detail with reference to the accompanying drawings. For consistency, the same elements in various figures are represented by the same reference numerals.

[0023] The present disclosure provides systems and methods for performing electrical mirroring by a storage controller. In various embodiments, a non-volatile storage device in a non-volatile storage system such as an SSD can have its data pins connected to the data pins of the storage controller in an inverted order. The controller can allow the firmware to determine whether electrical mirroring is enabled or disabled for each individual non-volatile storage device and implement a set of registers (e.g., power-on initialization) with bits corresponding to each individual non-volatile storage device that the firmware will set during configuration. Once electrical mirroring is enabled for the non-volatile storage device, the controller can reverse the order of the data bits before sending them to the non-volatile storage device using the inverted data pins, and can also reverse the order of the data bits received from the non-volatile storage device with inverted data pins.

[0024] As used herein, a non-volatile memory device can be a computer storage device that can retain stored information after power is removed and can retrieve the stored information after power is restored (turned off and back on). Non-volatile memory devices can include NAND flash memory, NOR flash memory, magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), phase change random access memory (PCRAM), Nano-RAM, etc. NAND flash memory can be used as an example to demonstrate the electrical mirroring technology implemented by the controller. However, other types of non-volatile memory devices can be used to implement the technology according to various embodiments of the present disclosure.

[0025] Figure 1 A nonvolatile storage system 100 according to one embodiment of the present disclosure is schematically shown. The nonvolatile storage system 100 may include a nonvolatile storage controller 102 and multiple nonvolatile memories (NVMs) 104. When the nonvolatile storage system 100 is coupled to a host, the nonvolatile storage system 100 may provide data storage and / or access to stored data to the host. The multiple NVMs 104 may be, for example, NAND devices. In some embodiments, a NAND device may include one NAND target that may be controlled by a chip enable (CE) signal. In some other embodiments, a NAND device may include multiple NAND targets (e.g., two targets), each of which may have its own CE signal. As used herein, a storage target in an NVM storage device may be a unit of the storage device accessed via a chip enable signal and may be referred to simply as a target. The multiple NVMs 104 may be connected to the nonvolatile storage controller 102 via multiple channels, where each target is connected to one channel and one channel is shared by multiple targets.

[0026] At least two of the plurality of NVMs 104 can be placed in a mirrored configuration, wherein one of the two NVMs is on one side of the PCB and the other of the two NVMs is on the same location but on the opposite side of the PCB. The data pins of one of the two NVMs in the mirrored configuration can be connected to the data bus of the channel in a regular order, while the data pins of the other NVM in the mirrored configuration can be connected to the data bus of the channel in an inverted order. As used herein, when the data pins of an NVM are connected to the data bus in an inverted order, the NVM may be referred to as being connected in an inverted order, and such an invertedly connected NVM may also be referred to as a flipped NVM, a mirrored NVM, or an NVM in mirror mode. Additionally, an NVM connected in a regular data bit order may be referred to as a non-flipped NVM or a non-mirrored NVM.

[0027] The non-volatile storage controller 102 may include a processor 106, a non-volatile computer-readable storage medium 108, and a plurality of registers 110. The processor 106 may be a computer processor, such as, but not limited to, a microprocessor or a microcontroller. In some embodiments, each of the plurality of registers 110 may have a plurality of bits, such that each target in the plurality of NVMs 104 may have a corresponding bit in the plurality of registers 110. The plurality of registers 110 may be configured to indicate which target in the plurality of NVMs 104 may be connected in reverse order. In at least one embodiment, some or all of the processor 106, the storage medium 108, and the registers 110 may be integrated into a single integrated circuit (IC) chip.

[0028] In one embodiment, each register in the plurality of registers 110 may be assigned to a channel (e.g., one register per channel), and each register bit may be assigned to a target of an NVM device of the channel (e.g., one bit per CE). In an example implementation, the register may be referred to as DQ_MIRROR_EN, as shown in Table 1 below, where a bit may be set (e.g., to 1) to enable electrical mirroring mode for the corresponding NAND target.

[0029]

[0030]

[0031] Table 1 Register definition of DQ_MIRROR_EN

[0032] In the example of Table 1, the register may be 16 bits wide. Each bit corresponds to a NAND target, so a 16-bit register can support up to 16 targets per channel. The register bits can be set based on the system topology. Once the DQ_MIRROR_EN register bit is set to 1, the controller 102 can be notified that the corresponding NAND device (e.g., the NAND device containing the corresponding target) has data pins connected in reverse order, so the controller may need to internally reverse the data bit order before sending data or after receiving data.

[0033] It should be noted that this example uses a register bit set to one (1) to indicate that the corresponding NVM targets can be connected in reverse order, but in some embodiments, a register bit set to zero (0) can be used to indicate that the corresponding NVM targets are connected in reverse order. In addition, it should be noted that the bit width of the register can be different compared to the data bus. In the example shown above, the data bus can have an 8-bit width, but the register can have a 16-bit width.

[0034] In some embodiments, register bits of the plurality of registers 110 corresponding to the inverted-connected NVMs in the plurality of NVMs 104 may be set during an electrical mirror configuration process. For example, the electrical mirror configuration process may be part of an initialization process of the non-volatile storage system 100 that is executed when the non-volatile storage system 100 is powered on or reset. During the electrical mirror configuration process, the processor 106 may execute computer instructions (e.g., firmware) stored in the non-transitory computer-readable storage medium 108 to determine a system topology and set register bits based on the determined system topology. In some embodiments, the non-transitory computer-readable storage medium 108 may be a read-only memory (e.g., an erasable programmable read-only memory or other suitable ROM) typically used to store firmware, which may be low-level software instructions that, when executed by the processor 106, enable the processor 106 to directly access registers of the controller to configure, control, and program the behavior of the controller and the system.

[0035] In one embodiment, the processor 106 may execute computer instructions stored in the non-transitory computer-readable storage medium 108 to determine which NVMs in the plurality of NVMs may be connected in reversed order and set bits corresponding to the destinations in the NVMs connected in reversed order in the plurality of registers 110. For example, the firmware may be programmed to designate one side as the normal order connection side (e.g., the top side) and the other side as the reverse order connection side (e.g., the bottom side), and the processor 106 may determine which NVMs in the plurality of NVMs 104 may be located on the normal order connection side and which NVMs in the plurality of NVMs 104 may be located on the reverse order connection side.

[0036] During operation of the nonvolatile storage system 100, the nonvolatile storage controller 102 can be configured to reverse the data bit order before sending data to a reverse-connected target and after receiving data from a reverse-connected target. In one embodiment, the processor 106 can execute software instructions to check the register 110 to determine whether the target is reverse-connected and perform a data reverse operation if necessary. If the NAND target is connected in normal order, data can be sent to and received from the nonvolatile storage controller 102 without any data reverse operation.

[0037] If the NAND target is connected in reverse order (e.g., the electrical mirror register bit is enabled), for a write operation, the non-volatile memory controller 102 can reverse the data bit order from DQ[7:0] to DQ[0:7] before sending the data to the data bus. That is, the non-volatile memory controller 102 can swap data bits DQ[0] and DQ[7], swap data bits DQ[1] and DQ[6], and so on for all data bits. The NAND device can receive data in the original order of DQ[7:0]. That is, because the data pins of the NAND device are connected to the data bus in a reversed order, the data pin DQ[0] of the NAND device can receive the data bit of DQ[0] in the non-volatile memory controller before the reverse operation, the data pin DQ[1] of the NAND device can receive the data bit of DQ[1] in the non-volatile memory controller 102 before the reverse operation, and so on.

[0038] For a read operation with a mirrored NAND device, the non-volatile memory controller 102 may receive data for DQ[7:0] in reverse order as DQ[0:7]. The non-volatile memory controller 102 may determine that the received data is in reversed data bit order by checking the corresponding register bits in the register 110, and then perform data bit order reversal to restore the data to the original order DQ[7:0].

[0039] Figure 2 Schematically illustrates two non-volatile memory devices 204 and 206 in a mirrored configuration in accordance with one embodiment of the present disclosure. The two non-volatile memory devices 204 and 206 can each be attached to the same location on a substrate or base 202 but on opposite sides. That is, the two non-volatile memory devices 204 and 206 can overlap each other in a clamshell topology. The substrate 202 can be a printed circuit board (PCB) or other suitable substrate. The two non-volatile memory devices 204 and 206 can be two of the plurality of NVMs 104, and the substrate 202 can be a PCB in the non-volatile memory system 100.

[0040] Figure 3 Schematically illustrates details of two non-volatile storage devices 204 and 206 in a mirrored configuration according to one embodiment of the present disclosure. Figure 3 In the example shown, the data bus of the channel can be 8 bits. However, in other embodiments, the data bus of the channel can be 16 bits, 32 bits, or another suitable number of bits. The non-volatile memory device 204 can be located on the top side of the PCB 202 and have data pins DQ[0] 302, DQ[1] 304, DQ[2] 306, DQ[3] 308, DQ[4] 310, DQ[5] 312, DQ[6] 314, and DQ[7] 316. The data pins DQ[0] 302, DQ[1] 304, DQ[2] 306, DQ[3] 308, DQ[4] 310, DQ[5] 312, DQ[6] 314, and DQ[7] 316 can be below the non-volatile memory device 204 and are shown in dashed lines. The non-volatile memory device 206 may be located on the bottom side of the PCB 202 and have data pins DQ[0] 318, DQ[1] 320, DQ[2] 324, DQ[3] 326, DQ[4] 328, DQ[5] 330, DQ[6] 332, and DQ[7] 334. The non-volatile memory device 206 and its data pins DQ[0] 318, DQ[1] 320, DQ[2] 324, DQ[3] 326, DQ[4] 328, DQ[5] 330, DQ[6] 332, and DQ[7] 334 may also be shown with dashed lines.

[0041] exist Figure 3In a mirror configuration, DQ[0]302 of the nonvolatile storage device 204 may be in a mirror position of DQ[7]334 of the nonvolatile storage device 206, DQ[1]304 of the nonvolatile storage device 204 may be in a mirror position of DQ[6]332 of the nonvolatile storage device 206, DQ[2]306 of the nonvolatile storage device 204 may be in a mirror position of DQ[5]330 of the nonvolatile storage device 206, and DQ[3]308 of the nonvolatile storage device 204 may be in a mirror position of DQ[4]328 of the nonvolatile storage device 206. Like positions, DQ[4] 310 of the nonvolatile memory device 204 may be in a mirror position of DQ[3] 326 of the nonvolatile memory device 206, DQ[5] 312 of the nonvolatile memory device 204 may be in a mirror position of DQ[2] 324 of the nonvolatile memory device 206, DQ[6] 314 of the nonvolatile memory device 204 may be in a mirror position of DQ[1] 320 of the nonvolatile memory device 206, and DQ[7] 316 of the nonvolatile memory device 204 may be in a mirror position of DQ[0] 318 of the nonvolatile memory device 206. As used herein, mirror positions may refer to the same position but opposite sides of a PCB.

[0042] like Figure 3 As shown, DQ[0] 302 of non-volatile memory device 204 can be connected to via 336 via trace 340, and DQ[7] 334 of non-volatile memory device 206 can be connected to via 336 via trace 342. Via 336 can be connected to trace 348 of DQ[0] of the channel's data bus. DQ[7] 316 of non-volatile memory device 204 can be connected to via 338 via trace 344, and DQ[0] 318 of non-volatile memory device 206 can be connected to via 338 via trace 346. Via 338 can be connected to trace 350 of DQ[7] of the channel's data bus. Because each pair of data pins connected by the vias can be in mirrored positions, the traces connecting the data pins to the vias (e.g., traces 340, 342, 344, and 346) can be very short. This can allow for high-quality PCB layouts and higher-speed NAND interfaces. Data connections can be made at Figure 3 202. It should be noted that for simplicity, the Figure 3 Other data connections (e.g., vias and traces for other data pins) can be omitted.

[0043] Figure 4A 2-channel non-volatile memory system 400 according to one embodiment of the present disclosure is schematically illustrated. The 2-channel non-volatile memory system 400 may include a NAND controller 402, a first NAND device 404.1, and a second NAND device 404.2. The first NAND device 404.1 and the second NAND device 404.2 may be in a mirrored configuration. For example, the first NAND device 404.1 may be on the top side of a PCB, while the second NAND device 404.2 may be on the bottom side of the PCB. The 2-channel non-volatile memory system 400 may be an embodiment of the non-volatile memory system 100.

[0044] The first NAND device 404.1 may include two NAND targets: NAND target 406.1 and NAND target 406.2. The second NAND device 404.2 may also include two NAND targets: NAND target 406.3 and NAND target 406.4. The NAND target 406.1 of the first NAND device 404.1 and the NAND target 406.3 of the second NAND device 404.2 may be connected to a first channel 410.1. The NAND target 406.2 of the first NAND device 404.1 and the NAND target 406.4 of the second NAND device 404.2 may be connected to a second channel 410.2. The NAND target 406.1 may be selected for data operations via a CE signal on a CE signal line 408.1. The NAND target 406.2 may be selected for data operations via a CE signal on a CE signal line 408.2. The NAND target 406.3 may be selected for data operations via a CE signal on a CE signal line 408.3. NAND target 406.4 may be selected for data operations via a CE signal on CE signal line 408.4. In one embodiment, NAND device 404.2 may be a mirrored device. That is, the data pins of NAND device 404.2 may be connected to the data buses for channels 410.1 and 410.2 in reverse order.

[0045] It should be noted that each channel can have its own data bus. In some embodiments, the NAND memory device may have two sets of data pins for the two channels, and the two sets of data pins may be independent of each other. Figure 4In the example of , a NAND memory device may have two targets, so each target in one device may be coupled to one channel. In some other embodiments, the NAND memory device may have more than two targets, and some targets may share a set of data pins for the data bus. For example, if the device has 4 targets, then each 2 targets may share a set of data pins for the data bus of the channel. If the device has 8 targets, then each 4 targets may share a set of data pins for the data bus of the channel. However, regardless of the number of targets in the NAND memory device, if the NAND memory device is located on a side of a PCB that requires the data pins of the NAND memory device to be connected in a reversed order, then all targets in the NAND memory device may have corresponding register bits set in the controller to indicate that they are connected in reverse order.

[0046] In one embodiment, NAND controller 402 may include two electrical mirror registers: one for channel 410.1 and another for channel 410.2. In the electrical mirror register for channel 410.1, a bit corresponding to NAND target 406.3 may be set during electrical mirror configuration. Additionally, in the electrical mirror register for channel 410.2, a bit corresponding to NAND target 406.4 may be set during electrical mirror configuration. For both write and read operations, NAND controller 402 may check the electrical mirror registers to determine whether the NAND targets are connected in reverse and whether a data bit order reversal operation is necessary.

[0047] Figure 5 Schematically shows a method for Figure 4 8. The 2-channel non-volatile storage system 400 of FIG. 5 illustrates read and write signaling for the 2-channel non-volatile storage system 400. Signal line 502 may represent a cycle type. Signal block 516 may represent a write cycle to a NAND target with normal data bit order (e.g., a CE signal on CE signal line 408.1 or 408.2). Signal block 518 may represent a write cycle to a NAND target with inverted data bit order (e.g., a CE signal on CE signal line 408.3 or 408.4). Signal block 520 may represent a read cycle from a NAND target with normal data bit order (e.g., a CE signal on CE signal line 408.1 or 408.2). Signal block 522 may represent a read cycle from a NAND target with inverted data bit order (e.g., a CE signal on CE signal line 408.3 or 408.4).

[0048] Signal line 504 may represent data in NAND controller 402. In blocks 524, 526, 528, and 530, the data in NAND controller 402 is all in regular bit order (eg, DQ[7:0]).

[0049] Signal line 506 may represent data on a data bus. In block 532, the data on the data bus may be in normal data bit order because the cycle type is a write operation cycle of a normal data bit sequence NAND target. In block 534, the data on the data cycle may be in reversed data bit order (e.g., DQ[0:7]) because the cycle type is a write operation cycle of a NAND target in a mirrored NAND device. In block 536, the data on the data bus may be in normal data bit order because the cycle type is a read operation cycle of a normal data bit sequence NAND target. In block 538, the data on the data bus may be in reversed data bit order because the cycle type is a read operation cycle of a NAND target in a mirrored NAND device.

[0050] Signal line 508 may represent data on NAND device 404.1, and signal line 510 may represent data on NAND device 404.2. In blocks 540 and 542, the data in NAND device 404.1 may be in normal data bit order. Because NAND controller 402 may reverse the data bit order before sending data to and after receiving data from the mirrored NAND device, the data in NAND device 404.2 may also be in normal data bit order in blocks 544 and 546. Signal line 512 may represent a CE signal line (e.g., CE signal line 408.1 or CE signal line 408.2) for NAND device 404.1 and illustrates that the CE signal may be set (e.g., pulled down) in signals 548 (e.g., writing to a normal data bit order NAND target) and 550 (e.g., reading from a normal data bit order NAND target). Signal line 514 may represent a CE signal line for NAND device 404.2 (e.g., CE signal line 408.3 or CE signal line 408.4) and illustrates that the CE signal may be set (e.g., pulled down) in signals 552 (e.g., writing to a NAND target in a mirrored NAND device) and 554 (e.g., reading from a NAND target in a mirrored NAND device).

[0051] like Figure 5 As shown, during a write operation to NAND device 404.2 (e.g., a CE signal set on signal line 408.3 or signal line 408.4), NAND controller 402 can convert the data bit order from a normal data bit order (e.g., DQ[7:0]) to an inverted data bit order (e.g., DQ[0:7]) before sending the data to the data bus. Because the order can be inverted again by the data pins connected to the data bus, NAND device 404.2 can receive the data in the normal data bit order.

[0052] For a read operation from NAND device 404.2 (e.g., CE signal asserted on signal line 408.3 or signal line 408.4), controller 402 may receive data on the data bus in an inverted order (e.g., DQ[0:7]). By determining that electrical mirroring is enabled, controller 402 may perform another data bit order flip to restore the original data bit order DQ[7:0].

[0053] In read and write operations to a mirrored device (e.g., NAND device 404.2), the data on the NAND channel data bus can always have a data bit order that is reversed from the data bit order of the data inside the NAND controller 402. The NAND controller 402 can manage the data bit order by performing a round of data inversion on the electrically mirrored devices. NAND device 404.1 can be connected to the data bus in a matching order from DQ[7:0] to DQ[7:0], and electrical mirroring can be disabled for NAND device 404.1. Therefore, for NAND device 404.1, the data on the data bus can always have the same order as the data inside the controller 402.

[0054] Figure 6 FIG6 is a flow chart of an electrical mirroring configuration process 600 according to one embodiment of the present disclosure. In block 602, a system topology of the non-volatile storage system and which targets are located in the mirrored non-volatile storage devices may be determined. For example, in some embodiments, the NAND controller 102 may be configured to determine the system topology and which targets are located in the mirrored non-volatile storage devices of the non-volatile storage system 100 during the electrical mirroring configuration process. In one embodiment, the system topology may include: how many non-volatile storage devices are in the non-volatile storage system 100, how many channels the NVMs 104 are connected to the controller 102, how many targets are in each NVM 104, and which targets in the NVMs 104 belong to which channel.

[0055] In block 604, corresponding register bits may be set in the memory controller for all targets of all mirrored non-volatile memory devices. For example, in some embodiments, the NAND controller 102 may include multiple registers. In one embodiment, one register may be assigned to each channel, with each bit of the register corresponding to a target in the channel. Corresponding register bits may be set (e.g., to enable electronic mirroring) for the targets of the mirrored non-volatile memory devices.

[0056] Figure 77 is a flow chart of a process 700 for performing a write operation on a mirrored NAND device according to one embodiment of the present disclosure. In block 702, it can be determined that a non-volatile storage device of a non-volatile storage system is connected in reverse based on the corresponding register bits that are set. In one embodiment, a register bit corresponding to a target in the mirrored NVM can be set to indicate that the data pins of the target can be connected in reverse. In block 704, the data bit order of the data to be stored in the non-volatile storage device can be reversed on the storage controller. The data to be stored in the non-volatile storage device can be in the original data bit order in the storage controller before being reversed. In block 706, the data to be stored in the non-volatile storage device can be sent on the data bus in the reversed data bit order. In various embodiments, since the target is located in the mirrored storage device and the data pins are connected in reverse, the data can be received and stored in the mirrored storage device in its original data bit order.

[0057] Figure 8 FIG8 is a flow chart of a process 800 for reading from a mirrored NAND device according to one embodiment of the present disclosure. In block 802, data may be received from a non-volatile storage device of a non-volatile storage system at a storage controller. In block 804, the storage controller may determine that the non-volatile storage device is a mirrored non-volatile storage device based on a corresponding register bit being set. In block 806, the storage controller may reverse the data bit order of the received data.

[0058] Each of the processes 600, 700, and 800 can be implemented using software (e.g., executable by a computer processor (CPU, GPU, or both), hardware (e.g., a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC)), firmware, or any suitable combination of the three. In one embodiment, for example, the electric mirror configuration process 600 can be implemented in a hardware circuit (e.g., an FPGA or an ASIC). In another embodiment, the electric mirror configuration process 600 can be implemented in firmware and stored in a read-only memory (e.g., memory 108), and executed by the processor 106 executing the firmware. In addition, the processes 700 and 800 can be programmed in computer processor executable instructions, stored in a non-transitory machine-readable medium (e.g., NVM 104, a CD, a DVD, etc.), and executed by a computer processor (e.g., a microprocessor or microcontroller) executing the executable instructions.

[0059] In an exemplary embodiment, a method is provided that may include determining a system topology of a nonvolatile storage system and which targets are located in mirrored nonvolatile storage devices, and setting corresponding register bits in a storage controller for all targets in all mirrored nonvolatile storage devices.

[0060] In one embodiment, the system topology may include how many non-volatile storage devices are in the non-volatile storage system, how many channels the non-volatile storage devices are connected to the storage controller, how many targets are in each non-volatile storage device, and which targets in the non-volatile storage device belong to which channel.

[0061] In one embodiment, the memory controller may include a plurality of registers, each register corresponding to a channel.

[0062] In one embodiment, the method may further include determining, based on the corresponding register bits that are set, that the non-volatile storage device of the non-volatile storage system is a mirrored non-volatile storage device; for data to be stored in the non-volatile storage device in the original data bit order, reversing the data bit order of the data on the storage controller; and sending the data with the reversed data bit order to a data bus connected to the non-volatile storage device so that the data is stored in the non-volatile storage device in the original data bit order.

[0063] In one embodiment, the method may further include receiving data from a non-volatile storage device of the non-volatile storage system at the storage controller, determining that the non-volatile storage device is a mirrored non-volatile storage device based on the corresponding register bits set, and reversing a data bit order of the received data at the storage controller.

[0064] In one embodiment, each mirrored nonvolatile memory device is paired with a non-mirrored nonvolatile memory device in a mirrored configuration, wherein data pins of the mirrored nonvolatile memory device are connected to data pins of the non-mirrored nonvolatile memory device through vias in reverse order.

[0065] In another exemplary embodiment, a nonvolatile storage system is provided. The nonvolatile storage system may include a plurality of nonvolatile storage devices and a storage controller. The storage controller may be configured to perform an electronic mirroring configuration process, the electronic mirroring configuration process including determining a system topology of the nonvolatile storage system and which targets are located in mirrored nonvolatile storage devices, and setting corresponding register bits in the storage controller for all targets in all mirrored nonvolatile storage devices of the plurality of nonvolatile storage devices.

[0066] In one embodiment, the system topology may include how many non-volatile storage devices are in the non-volatile storage system, how many channels the non-volatile storage devices are connected to the storage controller, which non-volatile storage devices are mirrored non-volatile storage devices, and which targets in the non-volatile storage devices belong to which channel.

[0067] In one embodiment, the memory controller includes a plurality of registers, each register corresponding to a channel.

[0068] In one embodiment, the storage controller can also be configured to determine, based on the corresponding register bits that are set, that a non-volatile storage device among the multiple non-volatile storage devices is a mirrored non-volatile storage device, and for data to be stored in the non-volatile storage device in the original data bit order, reverse the data bit order of the data on the storage controller; and send the data with the reversed data bit order to a data bus connected to the non-volatile storage device so that the data is stored in the non-volatile storage device in the original data bit order.

[0069] In one embodiment, the storage controller may also be configured to receive data from a non-volatile storage device of the plurality of non-volatile storage devices on the storage controller, determine that the non-volatile storage device is a mirrored non-volatile storage device based on the corresponding register bits set, and reverse the data bit order of the received data on the storage controller.

[0070] In one embodiment, each mirrored nonvolatile memory device is paired with a non-mirrored nonvolatile memory device in a mirrored configuration, wherein data pins of the mirrored nonvolatile memory device are connected to data pins of the non-mirrored nonvolatile memory device through vias in reverse order.

[0071] In one embodiment, the storage controller may include a non-volatile computer-readable storage medium storing firmware and a processor configured to execute the firmware to perform the electronic mirroring configuration process.

[0072] In one embodiment, the storage controller may include a hardware circuit configured to perform the electronic mirror configuration process:

[0073] In yet another exemplary embodiment, a non-transitory machine-readable medium is provided. The non-transitory machine-readable medium may have computer instructions that, when executed by a hardware processor, cause the hardware processor to determine a system topology of a non-volatile storage system and which targets are located in mirrored non-volatile storage devices, and set corresponding register bits in a storage controller for all targets in all mirrored non-volatile storage devices.

[0074] In one embodiment, the system topology may include how many non-volatile storage devices are in the non-volatile storage system, how many channels the non-volatile storage devices are connected to the storage controller, how many targets are in each non-volatile storage device, and which targets in the non-volatile storage device belong to which channel.

[0075] In one embodiment, the memory controller may include a plurality of registers, each register corresponding to a channel.

[0076] In one embodiment, when the computer instructions are executed by the hardware processor, the computer instructions further cause the hardware processor to: determine, based on the corresponding register bits that are set, that the non-volatile storage device of the non-volatile storage system is a mirrored non-volatile storage device; and, for data to be stored in the non-volatile storage device in the original data bit order, reverse the data bit order of the data on the storage controller; and send the data with the reversed data bit order to a data bus connected to the non-volatile storage device so that the data is stored in the non-volatile storage device in the original data bit order.

[0077] In one embodiment, the computer instructions, when executed by the hardware processor, further cause the hardware processor to: receive, at the storage controller, data from a non-volatile storage device of the non-volatile storage system, determine, based on corresponding register bits being set, that the non-volatile storage device is a mirrored non-volatile storage device, and reverse, at the storage controller, a data bit order of the received data.

[0078] In one embodiment, each mirrored nonvolatile memory device is paired with a non-mirrored nonvolatile memory device in a mirrored configuration, wherein data pins of the mirrored nonvolatile memory device are connected to data pins of the non-mirrored nonvolatile memory device through vias in reverse order.

[0079] Any disclosed methods and operations may be implemented as computer-executable instructions (e.g., software code for the operations described herein) stored on one or more computer-readable storage media (e.g., non-transitory computer-readable media, such as one or more optical disk media, volatile storage components (e.g., DRAM or SRAM), or non-volatile storage components (e.g., hard drives) and executed on a device controller (e.g., firmware executed by an ASIC). Any computer-executable instructions for implementing the disclosed techniques, as well as any data created and used during implementation of the disclosed embodiments, may be stored on one or more computer-readable media (e.g., non-transitory computer-readable media).

[0080] Although various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for illustrative purposes only and are not intended to be limiting, with the true scope and spirit being indicated by the following claims.

Claims

1. A method comprising: enabling electrical mirroring of the non-volatile memory device by setting a corresponding register bit for the non-volatile memory device in the memory controller; receiving data to be stored in the non-volatile memory device, the data being received in original data bit order; Reversing a data bit sequence of the received data on the storage controller to generate data with reversed data bit sequence; The data with the reversed data bit order is transmitted to a data bus connected to the non-volatile memory device so that the received data is stored in the non-volatile memory device in the original data bit order.

2. The method according to claim 1, characterized in that The non-volatile memory device is a mirrored non-volatile memory device, and data pins of the mirrored non-volatile memory device are connected to the data bus in an inverted pin order.

3. The method according to claim 1, characterized in that The non-volatile memory device is part of a non-volatile memory system, and the method further comprises: determining a system topology of the non-volatile memory system, the system topology including which targets are located in the mirrored non-volatile memory devices, wherein a target is a memory cell controlled by a chip enable signal, respective data pins of all mirrored non-volatile memory devices are connected to the data bus in a reversed order, and each non-volatile memory device of the non-volatile memory system includes one or more targets; and Corresponding register bits are set in the memory controller for all targets in all mirrored non-volatile memory devices.

4. The method according to claim 3, characterized in that The system topology further includes: how many non-volatile storage devices are in the non-volatile storage system, how many channels the non-volatile storage devices are connected to the storage controller, how many targets are in each non-volatile storage device, and which targets in the non-volatile storage device belong to which channel.

5. The method according to claim 4, characterized in that Each mirrored non-volatile memory device is paired with a non-mirrored non-volatile memory device in a mirrored configuration, wherein data pins of the mirrored non-volatile memory device are connected to data pins of the non-mirrored non-volatile memory device in reverse order through vias.

6. The method according to claim 4, characterized in that The memory controller includes a plurality of registers, each register corresponding to a channel, and each register of the plurality of registers has a plurality of register bits, each register bit corresponding to a target.

7. The method according to claim 1, characterized in that Also includes: receiving, at the storage controller, storage data read from the non-volatile storage device; determining, based on the corresponding register bits being set, that the non-volatile storage device is a mirrored non-volatile storage device; and The data bit sequence of the storage data is reversed on the storage controller.

8. A non-volatile storage system, characterized in that: include: multiple non-volatile storage devices; and Storage controller, configured as: enabling electrical mirroring of the non-volatile memory device by setting a corresponding register bit for the non-volatile memory device in the memory controller; receiving data to be stored in the non-volatile memory device, the data being received in original data bit order; Reversing a data bit sequence of the received data on the storage controller to generate data with reversed data bit sequence; The data with the reversed data bit order is transmitted to a data bus connected to the non-volatile memory device so that the received data is stored in the non-volatile memory device in the original data bit order.

9. The non-volatile storage system according to claim 8, wherein: The non-volatile memory device is a mirrored non-volatile memory device, and data pins of the mirrored non-volatile memory device are connected to the data bus in an inverted pin order.

10. The non-volatile storage system according to claim 8, wherein: The storage controller is further configured to: determining a system topology of the non-volatile memory system, the system topology including which targets are located in the mirrored non-volatile memory devices, wherein a target is a memory cell controlled by a chip enable signal, respective data pins of all the mirrored non-volatile memory devices are connected to the data bus in a reversed order, and each non-volatile memory device of the non-volatile memory system includes one or more targets; and Corresponding register bits are set in the memory controller for all targets in all mirrored non-volatile memory devices.

11. The non-volatile storage system according to claim 10, wherein: The system topology further includes: how many non-volatile storage devices are in the non-volatile storage system, how many channels the non-volatile storage devices are connected to the storage controller, how many targets are in each non-volatile storage device, and which targets in the non-volatile storage device belong to which channel.

12. The non-volatile storage system according to claim 11, wherein: Each mirrored non-volatile memory device is paired with a non-mirrored non-volatile memory device in a mirrored configuration, wherein data pins of the mirrored non-volatile memory device are connected to data pins of the non-mirrored non-volatile memory device in reverse order through vias.

13. The non-volatile storage system according to claim 11, wherein: The memory controller includes a plurality of registers, each register corresponding to a channel, and each register of the plurality of registers has a plurality of register bits, each register bit corresponding to a target.

14. The non-volatile storage system according to claim 8, wherein: The storage controller is further configured to: receiving, at the storage controller, storage data read from the non-volatile storage device; determining, based on the corresponding register bits being set, that the non-volatile storage device is a mirrored non-volatile storage device; and The data bit sequence of the storage data is reversed on the storage controller.

15. A non-transitory machine-readable medium having computer instructions, characterized in that When the computer instructions are executed by a hardware processor, the computer instructions cause the hardware processor to perform the steps according to any one of claims 1 to 7.

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