Row mapping in memory controller

Abstract

The invention relates to row mapping in a memory controller. The rows may be mapped to spare rows in the memory. The mapping may include stopping the scheduler from issuing commands to the first group. In response to stopping the scheduler issuing commands to the first group, logic may map a particular row of the first group to the spare row. The mapping may include allowing the scheduler to schedule commands for a second group while mapping the particular row to the spare row.

Description

Technical Field

[0001] The present disclosure relates generally to memory and, more particularly, to apparatus and methods associated with mapping rows in a memory controller. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data, and includes random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered, and may include NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistance variable memory, such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), among others.

[0003] Memories are also used as volatile and non-volatile data storage devices for a wide range of electronic applications, including but not limited to personal computers, portable memory sticks, digital cameras, cellular phones, portable music players such as MP3 players, movie players, and other electronic devices. Memory cells can be arranged in an array, where the array is used in a memory device. When a row of an array fails, the memory can repair the row. Summary of the invention

[0004] In one aspect, the present disclosure provides an apparatus for mapping rows in a memory controller, comprising: a memory device, comprising: a first group of memory cells, comprising multiple rows of memory cells and a spare row of memory cells; a second group of memory cells; a controller, coupled to the memory device and comprising: a scheduler; and logic, coupled to the scheduler and configured to: stop the scheduler from issuing commands to the first group; in response to stopping the scheduler from issuing commands to the first group, map a specific row of the first group to the spare row; and allow the scheduler to schedule commands for the second group while mapping the specific row to the spare row.

[0005] In another aspect, the present disclosure further provides a method for mapping rows in a memory controller, comprising: receiving a command from a host at a controller of a memory subsystem to map a faulty row of a first group of a memory device of the memory subsystem to a spare row of the first group; in response to receiving the command, using logic of the controller to copy data from the faulty row to a memory of the controller; in response to copying the data to the memory of the controller, using the logic to stop a refresh circuit system of the controller from refreshing the first group; in response to stopping the refresh circuit system from refreshing the first group, using the logic to map the faulty row to the spare row; refreshing a second group of the memory device while mapping the faulty row to the spare row; and in response to mapping the faulty row to the spare row, copying the data from the memory to the spare row.

[0006] In yet another aspect, the present disclosure further provides an apparatus for mapping rows in a memory controller, comprising: a scheduler; a refresh circuit system; a memory; logic coupled to the scheduler, the refresh circuit system, and the memory, and configured to: monitor a plurality of registers, the plurality of registers storing bits identifying a first faulty row of a first group and a second faulty row of a second group; in response to monitoring the plurality of registers, copy first data from the first faulty row to the memory; in response to monitoring the plurality of registers, copy second data from the second faulty row to the memory; in response to copying the first data to the memory and copying the second data to the memory, stop the scheduler from issuing commands to the first group and the second group; in response to copying the first data to the memory and copying the second data to the memory , stop the refresh circuit system from refreshing the first group and the second group; in response to stopping the scheduler from issuing commands to the first group and stopping the refresh circuit system from refreshing the first group and the second group, map the first fault row to the first spare row of the first group, and map the second fault row to the second spare row of the second group; allow the scheduler to schedule commands for other groups while mapping the first fault row to the first spare row; allow the refresh circuit system to refresh the other groups while mapping the second fault row to the second spare row; in response to mapping the first fault row to the first spare row, copy the first data from the memory to the first spare row; and in response to mapping the second fault row to the second spare row, copy the second data from the memory to the second spare row. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1is a block diagram of a device in the form of a computing system that includes a memory subsystem according to several embodiments of the present disclosure.

[0008] Figure 2 is a block diagram of a group according to several embodiments of the present disclosure.

[0009] Figure 3 is a block diagram of a controller according to several embodiments of the present disclosure.

[0010] Figure 4 is a block diagram of an interface protocol according to several embodiments of the present disclosure.

[0011] Figure 5 is a block diagram of an interface protocol according to several embodiments of the present disclosure.

[0012] Figure 6 is a timing diagram for mapping rows to spare rows according to several embodiments of the present disclosure.

[0013] Figure 7 An example flow chart illustrating a method for mapping rows to spare rows according to several embodiments of the present disclosure.

[0014] Figure 8 An example machine of a computer system is illustrated within which a set of instructions for causing the machine to perform the various methodologies discussed herein may be executed. DETAILED DESCRIPTION

[0015] The present disclosure includes apparatus and methods related to mapping rows in a memory controller. The rows may be mapped by stopping a scheduler of a controller of a memory subsystem from issuing commands to a selected group of the memory subsystem. In response to stopping the scheduler from issuing commands to the selected group, logic of the controller may map a particular row of the group to a spare row. The scheduler may continue to schedule commands to other groups of the memory subsystem while mapping the particular row to the spare row. Logic may be coupled to the scheduler to allow the logic to provide a command to the scheduler to stop the scheduler from issuing commands to the selected group, thereby performing a row mapping change.

[0016] Soft post-pack repair (sPPR) is a quick but temporary way to repair one or more row addresses per bank or group of banks. Compared to hard post-pack repair (hPPR), which is a longer and permanent process, sPPR can be used during normal operation and can be used to dynamically change the rows being repaired as needed.

[0017] The complete sPPR sequence includes different operations and / or actions to be performed on the memory device. The different operations and / or actions include locking the running operation (read / write), issuing a mode register write (MRW) command, verifying additional security keys (if necessary), avoiding refresh conflicts, etc. The locking operation can be restored after the complete sPPR is performed. The locking operation can also include a refresh operation for all groups. Typically, performing a complete sPPR is complex and stops read / write commands for all groups. Stopping read / write commands for all groups increases the latency of executing commands received by the memory subsystem. In addition, data is lost when a row is mapped to a spare row using sPPR because the data is not copied before mapping to the spare row.

[0018] Aspects of the present disclosure address the above and other deficiencies by implementing logic in a controller that performs sPPR but is connected to a scheduler and / or refresh circuitry of the controller. The connection of the logic to the controller allows the scheduler to receive a command to stop scheduling and issuing commands to a group containing rows and spare rows while continuing to schedule and issue commands to other groups. The logic (e.g., mapping logic) is a hardware block added in a new or existing memory controller. The sPPR process can be performed by the logic in parallel with other commands, and the data of the row being repaired is preserved by moving the data to the spare row during the repair process.

[0019] As used herein, a failed row is any row in a memory device that experiences a number of errors greater than a threshold (e.g., a number of uncorrectable errors). A spare row is a row that is implemented in a group but is not accessible from outside the memory subsystem except by mapping the spare row to a different row that is accessible from outside the memory subsystem.

[0020] As used herein, "a number of" something may refer to one or more of such things. For example, a number of memory subsystems may refer to one or more memory subsystems. "A plurality of" something means two or more. Additionally, designators such as "M" as used herein, particularly with respect to reference numerals in the drawings, indicate that a number of particular features so designated may be included with several embodiments of the present disclosure.

[0021] Figures herein follow a numbering convention, wherein the first one or more digits correspond to the figure number, and the remaining digits identify the elements or components in the figure. Similar elements or components between different figures can be identified by using similar numbers. As should be understood, the elements shown in the various embodiments herein can be added, exchanged and / or removed to provide several additional embodiments of the present disclosure. In addition, the proportions and relative scales of the elements provided in the figure are intended to illustrate various embodiments of the present disclosure and are not used in a limiting sense.

[0022] Figure 1is a block diagram of a device in the form of a computing system 100 including a memory subsystem 103 according to several embodiments of the present disclosure. As used herein, for example, the memory subsystem 103, the memory array 108, and / or the host 102 may also be individually considered as a "device."

[0023] In this example, system 100 includes a host 102 coupled to a memory subsystem 103 via an interface 104. Computing system 100 may be a personal laptop computer, a desktop computer, a digital camera, a mobile phone, a memory card reader, or a device supporting the Internet of Things (IoT), as well as various other types of systems. Host 102 may include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of control circuitry) that are capable of accessing memory subsystem 103. System 100 may include separate integrated circuits, or both host 102 and memory subsystem 103 may be located on the same integrated circuit. For example, host 102 may be a system controller for multiple memory subsystems 103, where system controller 102 provides access to respective memory subsystems 103 through another processing resource, such as a central processing unit (CPU).

[0024] For clarity, system 100 has been simplified to focus on features that are particularly relevant to the present disclosure. For example, memory array 108 may be a DRAM array, a static random access memory (SRAM) array, a spin torque transfer (STT) RAM array, a PCRAM array, a thyristor RAM (TRAM) array, an RRAM array, a NAND flash array, and / or a NOR flash array. Array 108 may include memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as digit lines or data lines). Although in Figure 1 A single array 108 is shown in FIG. 1 , but embodiments are not so limited. For example, the memory subsystem 103 may include several arrays 108 (eg, several groups of DRAM cells).

[0025] The memory subsystem 103 includes an address circuit system 106 to latch address signals provided via the interface 104. The interface may include, for example, a physical interface that employs a suitable protocol (e.g., a data bus, an address bus, and a command bus, or a combined data / address / command bus). This protocol may be custom or proprietary, or the interface 104 may employ a standardized protocol, such as Peripheral Component Interconnect Express (PCIe), Gen-Z, CCIX, etc. The address signal is received and decoded by a row decoder 107 and a column decoder 110 to access the memory array 108. Data can be read from the memory array 108 by sensing voltage and / or current changes on the sense lines using a sense circuit system 109. The sense circuit system 109 may include, for example, a sense amplifier that can read and latch a page (e.g., a row) of data from the memory array 108. The I / O circuit system 112 may be used for bidirectional data communication with the host 102 via the interface 104. The read / write circuit system 111 is used to write data to the memory array 108 or read data from the memory array 108. As examples, circuitry 111 may include various drivers, latch circuitry, and the like.

[0026] The controller 105 decodes the signals provided by the host 102. These signals may include chip enable signals, write enable signals, and address latch signals used to control operations performed on the memory array 108, including data read, data write, and data erase operations. In various embodiments, the controller 105 is responsible for executing instructions from the host 102. The controller 105 may include a state machine, a sequencer, and / or some other type of control circuitry, which may be implemented in hardware, firmware, or software, or any combination of the three.

[0027] The controller 105 may include logic (e.g., mapping logic) configured to map a failed row to a spare row of the memory array 108. As used herein, the memory array 108, the row decoder 107, the column decoder 110, and the sensing circuit system 109 may also be referred to as a group. Multiple groups may be implemented in a memory device. A non-limiting example of a memory device is a memory die, which may also be referred to as a memory chip. The memory subsystem 103 may include a plurality of memory devices organized in a rank, such that a rank may include one or more memory devices, and each memory device includes one or more groups. Each rank is composed of memory devices coupled to the same chip select. Another non-limiting example of a memory device is a collection of memory dies bonded to a common circuit board, which may be referred to as a dual in-line memory module (DIMM).

[0028] The logic may be referred to as fast sPPR logic. Fast sPPR may implement sPPR without the limitations of conventional sPPR. Fast sPPR logic may be coupled to a command scheduler and / or refresh circuitry of controller 105. Fast sPPR logic may provide commands to the scheduler and / or refresh circuitry to cause the scheduler and / or refresh circuitry to avoid scheduling and / or issuing commands to a group containing a failed row and a spare row. The scheduler may continue to schedule and / or issue commands for a different group. The refresh circuitry may also continue to refresh a different group.

[0029] The logic may also store the data (or at least recoverable data) stored in the failed row in a memory of the controller before mapping the failed row to the spare row. Storing the data in the memory of the controller prevents data loss. If a failed row is mapped to a spare row without first storing the data elsewhere, the data (e.g., all the data in the failed row) may be lost.

[0030] The logic may map the failed row to the spare row based on the state of a register (not shown) of the controller. The register may be updated by the host 102. The logic may monitor the register to determine when to map the failed row to the spare row, and determine which row (e.g., the failed row) to map to the spare row. The address of the failed row may be saved in the register. The logic may also update the register when the mapping of the failed row to the spare row is completed. The register may be monitored by the host 102 to determine when the mapping of the failed row to the spare row is completed.

[0031] Figure 2 2 is a block diagram of a bank 208 according to several embodiments of the present disclosure. Bank 208 includes a row decoder 207 and a column decoder 210. Bank 208 also includes columns and rows of memory cells.

[0032] For example, group 208 includes row 221 and spare row 222. Group 208 may include multiple spare rows. The difference between row 221 and spare row 222 is that row 221 is accessible from outside the memory subsystem. Spare row 222 is not accessible from outside the memory subsystem. For example, the host may provide an access command addressed to row 221. However, the host may not know the address of spare row 222, and / or the controller of the memory subsystem may not schedule commands for the address of spare row 222. In any case, spare row 222 may not be directly accessed by the host. Spare row 222 may be implemented outside the main array area, while row 221 is implemented in the main array area.

[0033] A determination may be made as to whether row 221 has failed. One example of how row 221 may have failed is if the errors experienced when accessing row 221 are greater than a threshold over a period of time. The number of errors experienced when accessing row 221 may indicate that row 221 is unreliable.

[0034] To increase the reliability of group 208, row 221 can be mapped to spare row 222. Row 221 can be referred to as failed row 221. Mapping row 221 to spare row 222 can include configuring programmable elements of group 208.

[0035] The programmable elements of group 208 may store addresses of row 221 and / or spare row 222. The programmable elements may be hardware such as registers and associated logic. The programmable elements may compare the addresses with the stored addresses of row 221. If the address corresponding to the access command matches the stored address, the programmable element may provide the address of spare row 222. Even if the access command was originally associated with the address of row 221, the address of spare row 222 may be utilized to execute the access command on spare row 222 instead of row 221. The programmable elements may be configured to map the address of row 221 to spare row 222.

[0036] Figure 3 3 is a block diagram of a controller 305 according to several embodiments of the present disclosure. The controller 305 may include registers 331 (e.g., configuration registers), a write queue 332, a read queue 333, a scheduler 334, a refresh circuit system 335 (e.g., a refresh machine), command queues 336 (e.g., one command queue per group), logic 337 (e.g., fast sPPR logic), and memory 338 (e.g., sPPR data SRAM). The controller 305 may be coupled to a memory device 339. The memory device 339 may be in one or more ranks (e.g., rank 0, rank 1, rank 2, rank 3). The logic 337 and the memory 338 may be implemented as hardware and / or firmware.

[0037] In various cases, logic 337 may include registers separate from registers 331. The registers of logic 337 are Figure 4 441 in FIG. 4. The registers of logic 337 may be written by the host. For example, the host may provide a command to map a row to a spare row. The command (e.g., a mapping command) may be accompanied by the address of the row. The address of the row may be stored in a register of logic 337. For example, controller 305 may receive the address and may store the address in a register of logic 337. Although logic 337 is described as including registers (e.g., Figure 4 441), but the register may be external to logic 337 and separate from register 331.

[0038] The host may provide a command to map a row to a spare row in response to determining that a row has failed. The host may also provide a command to map a row to a spare row for other reasons. A row failure may be determined due to a row experiencing several errors within a period of time. Different types of errors on the memory array may produce column or row errors. A column error occurs when some memory cells along different rows coupled to the same column fail. A row error occurs when some memory cells along the same row fail and / or when an entire row fails due to, for example, a row decoder crack.

[0039] Logic 337 may monitor registers (e.g., Figure 4 Logic 337 may map a row to a spare row after noting the row address and / or register indicating that mapping is to occur.

[0040] For example, logic 337 may write to a register (e.g., store the start bit in Figure 4 Logic 337 may be triggered by register 441-2 of the group to perform mapping of the failed row to the spare row within the group. Logic 337 may map the failed row to the spare row using the address stored in registers 441-4, 441-5, 441-6. Logic 337 may update a register (e.g., register 441-1) to indicate that the mapping operation is being performed.

[0041] To map a row to a spare row, logic 337 may cause data stored in the failed row to be copied (e.g., moved) to memory 338. Memory 338 may be implemented as, but is not limited to, SRAM. Memory 338 may be implemented as different types of memory. Storing data in memory 338 is optional and may not be performed based on information stored in registers of logic 337. For example, a command provided by the host to cause a row to be mapped to a spare row may include an indication of whether to copy data stored in the row to memory 338 (e.g., as stored in registers). Figure 4 in register 441-3).

[0042] In response to copying data to memory 338 or in response to receiving a command from a host (e.g., by controller 305), logic 337 may continue to provide signals (e.g., commands) to scheduler 334 and / or refresh circuitry 335 to cause scheduler 334 and / or refresh circuitry 335 to stop providing commands to the group including rows and spare rows. Depending on the memory type, scheduler 334 may stop scheduling commands for one / multiple groups. Depending on the memory type, refresh circuitry 335 may stop refreshing one / multiple groups.

[0043] In response to copying data to memory 338 or in response to receiving a command from a host (e.g., by controller 305), logic 337 may monitor command queue 336 to determine whether command queue 336 lacks commands for the group with the row being remapped. In various cases, logic 337 may monitor a single queue from command queue 336 to determine whether the single queue lacks commands for the group. The single command queue may be a command queue associated with the group with the row being remapped. Logic 337 may monitor a specific queue instead of other queues because the other queues are associated with different groups and will not have commands corresponding to the specific group. In different embodiments, scheduler 334 may be required to monitor queues and other operations involving group commands. For example, scheduler 334 may monitor a specific queue.

[0044] In response to preventing scheduler 334 from scheduling commands to the group, preventing a refresh of the group, and / or waiting for one or more command queues 336 to be lacking commands for the group, logic 337 may map the row to a spare row.

[0045] Logic 337 may configure the programmable elements of a group by storing the address of the row in the programmable element. Logic 337 may configure the programmable elements of a group by reading a register (e.g., Figure 4 Register 441) to obtain the address of the row.

[0046] In response to mapping a row to a spare row, logic 337 may cause data stored in memory 338 to be copied to the spare row. Copying data from the row to memory 338 and from memory 338 to the spare row may preserve the data and may prevent data loss. Unless the data is stored elsewhere (e.g., memory 338), data stored in the row may be lost when the row is mapped to the spare row.

[0047] The coupling of logic 337 to scheduler 334, refresh circuitry 335, and / or command queue 336 allows logic 337 to prevent access to a particular group during a mapping operation (e.g., read, write, refresh, etc.). Depending on the memory type, scheduler 334, refresh circuitry 335, and command queue 336 may continue to perform actions related to other commands even if they are blocked from performing actions on a particular group including rows and spare rows. For example, scheduler 334 may continue to schedule commands for different groups even if logic 337 stops scheduler 334 from scheduling commands to a particular group. Scheduler 334 may continue to schedule commands for different groups while mapping rows to spare rows.

[0048] Even if logic 337 stops refresh circuitry 335 from refreshing a particular group of rows, refresh circuitry 335 may continue to refresh a different group. Refresh circuitry 335 may refresh a different group while mapping a row to a spare row. In various examples, based on the memory type, refresh circuitry may postpone the refresh operation until the mapping operation is complete.

[0049] The coupling of logic 337 to memory 338 allows logic 337 to coordinate the copying of data stored in the row to memory 338. Copying the data stored in the row to memory 338 allows the data to maintain the mapping of the row to the spare row. Data is lost in the process of mapping the row to the spare row because the row is no longer accessible. Data stored in the row is not accessible because commands to the row are mapped to the spare row.

[0050] Figure 4 is a block diagram of an interface protocol 442 according to several embodiments of the present disclosure. Registers 441-1, 441-2, 441-3, 441-4, 441-5 (referred to as registers 441) may serve as an interface between the host and the fast sPPR logic 437. Registers 441 are operable to store data indicating the address of a failing row.

[0051] The data stored in register 441 may include rank data stored in register 441-6, row data stored in register 441-5, and group data stored in register 441-4. The rank data, row data, and group data constitute the address of the faulty row. The rank data may be used to identify the rank of the group containing the faulty row. For example, the rank data may be the rank number corresponding to the rank containing the faulty row. The host may read and / or write to register 441-6. The rank data may depend on the configuration of the memory subsystem.

[0052] The row data may be used to identify the faulty row. The row data may be the row address of the faulty row. The host may read and / or write to register 441-5. The row data may depend on the configuration of the memory subsystem.

[0053] The group data may be used to identify the group containing the faulty row. The group data may be the group address of the group containing the faulty address. The host may read and / or write to register 441-4. The group data may depend on the configuration of the memory subsystem. Register 441 may store multiple rank addresses, row addresses, and / or group addresses.

[0054] Register 441 may also store a data save bit in register 441-3, a start bit in register 441-2, and status data in register 441-1. The data save bit may be used to indicate to logic 437 that the data stored in the faulty row will be saved in memory 438 before the faulty row is mapped to the spare row. The default value of register 441-3 may indicate that no data is copied from the faulty row to the spare row using memory 438. If the default value is stored in register 441-3, the data may be lost. The second value of register 441-3 may indicate that the data will be copied from the faulty row to the spare row using memory 438. The host may read and / or write to register 441-3.

[0055] The start bit may be used to indicate to logic 437 when to start mapping the faulty row to the spare row (eg, execution of the sPPR process). Once logic 437 starts mapping the faulty row to the spare row, the mapping of the faulty row to the spare row may not be interrupted. The host may read and / or write to register 441-2.

[0056] As used herein, mapping of a failed row may or may not include copying the data stored in the failed row to memory 438. For example, mapping of a failed row may be performed by logic without storing the data stored in the failed row in memory 438. Mapping of a failed row may include copying the data stored in the failed row to memory 438.

[0057] The host may provide data stored in register 441. The host may provide the data as part of a command to map a failed row to a spare row or as a separate signal (e.g., address information or data information associated with the command). The controller of the memory subsystem may store the data in register 441. Logic 437 may monitor register 441 to determine when to map a failed row to a spare row and determine whether to copy data stored in the failed row to the spare row. For example, logic 437 may monitor register 441-3 to monitor a data save bit to determine whether to save data stored in the failed row to memory 438. Logic 437 may monitor register 441-1 to monitor a start bit to determine when to start mapping a failed row to a spare row.

[0058] Logic 437 may update register 441-1 to indicate to the host when the mapping of the faulty row to the spare row is complete. For example, before starting to map the faulty row to the spare row, register 441-1 may store a first value that indicates to the host that the previous mapping command has been completed. After receiving the mapping command from the host, the controller may store a second value in register 441-1. The controller may save the second value in response to storing the address of the faulty row in registers 441-4, 441-5, 441-6. In various cases, logic 437 may store the second value in register 441-1 in response to determining that the address of the faulty row has been stored in registers 441-4, 441-5, 441-6.

[0059] After completing the mapping of the failed row to the spare row, logic 437 may update the status data by storing the first value in register 441-1. The host may monitor register 441-1 to determine when the mapping is complete. Knowing that the access command is mapped to the spare row, the host may continue to provide access commands to the failed row.

[0060] In various examples, the host may access data during the mapping of the failed row to the spare row. For example, if the data stored in the failed row is copied to the memory 438, the host may access the data while the data is stored in the memory 438. After the data is copied from the memory 438 to the spare row, the host may access the data from the spare row. When the data is not copied to the spare row or when the data is not copied to the memory 438, the host may access the data from the spare row. When the second value is stored in the register 441-3, the data may be accessed from the memory 438.

[0061] In various examples, the first value of the status data may be an idle state. The idle state may be used to indicate that mapping is not being performed or has not been previously performed. For example, the status data may have a first value after a predetermined amount of time has passed since the last time a faulty row was mapped to a spare row. The first value may be a default value. The second value of the status data may be an idle state after the mapping is complete. The address of the row stored in register 441 may be the address of the faulty row being mapped. The third value of the status data may indicate that mapping is in progress. The host may read the status data, but may not write to register 441-1 storing the status data.

[0062] The address of the previously mapped failed row may be maintained in registers 441-4, 441-5, 441-6 until the host requests the next mapping. Maintaining the address in registers 441-4, 441-5, 441-6 allows logic 437, the host and / or controller, and other devices to determine the last failed row mapped. Identifying the last mapped row may be useful, for example, to prevent multiple spare rows from being mapped to a failed row.

[0063] Figure 5 is a block diagram of an interface protocol 542 according to several embodiments of the present disclosure. Registers 541 - 1 , 541 - 16 (referred to as registers 541 ) store data and / or serve as an interface between the host and the fast sPPR logic 537 .

[0064] Each of the registers 541 is associated with a different mapping command. For example, the host may provide a first command to map the first fault row to the first spare row. The address of the first fault row may be stored in register 541-1. The host may also provide a data save bit and a start bit. The data save bit and the start bit are also stored in register 541-1.

[0065] The host may provide a second command to map the second fault row to the second spare row. The address of the second fault row may be stored in a next register (e.g., register 541-2 not shown). The host may also provide a data save bit and a start bit corresponding to the second command. The data save bit and the start bit corresponding to the second command may also be saved in the next register.

[0066] The host may provide a 16th command to map the 16th fault row to the 16th second spare row. The address of the 16th fault row may be stored in register 541-16. The host may also provide a data save bit and a start bit corresponding to the 16th command. The data save bit and the start bit may be saved in register 541-16. Although the examples provided herein indicate 16 registers, the number of registers may be reduced or increased depending on the memory type and / or controller internal resources.

[0067] If the map commands are directed to different groups, the map commands provided by the host may be executed simultaneously by the logic 537. For example, if a first command is directed to a first failed row in a first group and a second command is directed to a second failed row in a second group, the first command and the second command may be executed simultaneously by the logic 537. If the status data corresponding to the map commands is set to a run value (e.g., mapping in progress), the map commands may be executed simultaneously.

[0068] Even if some mapping commands are executed by copying data from the faulty row to the spare row using the memory 538, and other mapping commands are executed without copying data from the faulty row to the spare row, the mapping commands may be executed simultaneously by the logic 537. Even if portions of the mapping commands are executed serially, the mapping commands may be executed simultaneously. For example, the logic 537 may map the first faulty row to the first spare row while the memory 538 is storing data previously stored in the second faulty row in preparation for copying the data stored in the memory 538 to the second spare row. After the logic 537 completes mapping the first faulty row to the second faulty row, the logic 537 may map the second faulty row to the second spare row. Portions of the mapping commands may be executed simultaneously even if different portions of the mapping commands are not executed simultaneously.

[0069] Figure 6 6 is a timing diagram for mapping rows to spare rows according to several embodiments of the present disclosure. Host 602 may be implemented as hardware and / or firmware. The memory subsystem may include controller 605. Controller 605 may include logic, memory, a scheduler (e.g., a CMD scheduler), refresh circuitry (e.g., a refresh machine), and a queue (e.g., a CMD queue).

[0070] At 661, the host 602 may provide a command to the controller 605. The logic may receive the command. In response to receiving the command, the logic may write the address provided with the command to a register of the controller 605 to store the address of the failed row in the register. The logic may avoid performing other operations because the start bit has not been set to a value indicating that mapping of the failed row should begin.

[0071] At 662, the host 602 may provide one or more commands to the controller 605. The logic may receive the one or more commands. In response to receiving the commands, the logic may store a first value in a register associated with the start bit and a second value in a register associated with the data preservation bit. For example, the host 602 may provide data that, when stored in the register, causes the logic to copy data from the failed row to the spare row and causes the logic to initiate mapping of the failed row.

[0072] In response to storing the first value in the register associated with the data storage bit and storing the second value in the register associated with the start bit, the logic may provide a read command to the command queue at 663. The command queue may provide the read command to the corresponding memory device to cause the failed row to be read. The data returned from the failed row may be stored in a memory of the controller.

[0073] At 664-1 and 664-2, host 602 may provide commands to controller 605 to cause logic to read the status register and provide the read value to host 602. The host may avoid accessing the faulting row (eg, a map command has not completed execution) in response to reading the status register.

[0074] At 655, after copying the data of the failed row to the memory or while copying the data of the failed row to the memory, the logic may wait for the queue to lack commands for the specific group with the failed row. After verifying that there are no commands for the specific group in the queue, the logic may provide the command to the scheduler to cause the scheduler to avoid scheduling the command to the specific group. The scheduler may continue to schedule commands to other groups.

[0075] At 667, the logic may also provide a command to the refresh circuitry to prevent the refresh circuitry from refreshing the particular group. The logic may continue to schedule commands to different groups. The logic may lock the refresh circuitry and the scheduler simultaneously or sequentially. For example, the logic may cause the refresh circuitry to stop refreshing the particular group while locking the scheduler to prevent the scheduler from scheduling commands to the particular group. The logic may also cause the refresh circuitry to stop refreshing the particular group in response to the scheduler refraining from scheduling commands to the particular group.

[0076] In response to preventing the scheduler from scheduling commands to the particular group and / or in response to preventing the refresh circuitry from refreshing the particular group, logic may begin mapping the failing row at 668. For example, logic may provide a command to a queue to cause the failing row to be mapped to a spare row.

[0077] At 669, logic may cause data stored in the memory to be copied to the spare row. For example, logic may read data from the memory and may provide a write command to the command queue at 670 to cause the data to be written to the spare row. The command queue may provide the write command to the appropriate memory device. Even if the address of the failed row is provided, the memory device may write to the spare row because the failed row has been mapped to the spare row.

[0078] At 671, the logic may unlock the scheduler. At 672, the logic may unlock the refresh circuitry. The logic may update the status, but to reflect that the mapping of the failed row to the spare row is complete. At 664-3, the host 602 may read a register of the controller 605 to read the status data. The status data may indicate that the mapping is complete. In response to reading the status data, the host 602 may provide an access command to the failed row.

[0079] Figure 7 An example flow chart illustrating a method 780 for mapping a row to a spare row according to several embodiments of the present disclosure. The method may be performed by a memory subsystem of a computing system.

[0080] At 781, a command may be received at a controller of a memory subsystem from a host. The command may be provided to map a failed row of a first group of memory devices of the memory subsystem to a spare row of a first group. The command may be referred to as a mapping command. At 782, in response to receiving the command, logic of the controller may be utilized to copy data from the failed row to a memory of the controller. The data may be copied by providing a read command to a queue corresponding to the failed row.

[0081] In response to copying the data to the controller's memory, the logic may stop the controller's refresh circuitry from refreshing the first group at 783. For example, the logic may provide a command to the refresh circuitry that causes the refresh circuitry to stop refreshing the group that includes the failed row.

[0082] At 784, in response to stopping the refresh circuitry from refreshing the first group, mapping the failing row to a spare row using logic. The logic may provide a command to a memory device including the failing row to map the failing row to a spare row.

[0083] The second group of memory devices may be refreshed while mapping the failed row to the spare row at 785. For example, while a queue stores commands for a particular group to map the failed row to the spare row, new commands for the particular group may be stored in a different queue.

[0084] In response to mapping the failing row to the spare row, the logic may copy the data from the memory to the spare row at 786. Copying the data from the memory to the spare row makes the data available even if the failing row is mapped to the spare row.

[0085] The logic may also stop a scheduler of the controller from issuing commands to the first group in response to copying the data to the memory of the controller. The scheduler may schedule commands and issue the commands. Scheduling of commands occurs when the scheduler compiles an ordered list of commands. Commands are issued when the scheduler provides the commands to the corresponding queues or when the queues provide the commands to the corresponding memory devices. The failed row may be mapped to the spare row while issuing commands to the second group.

[0086] The host may provide a different command from the host to copy data from the failed row to the spare row and initiate mapping of the failed row. The different command may cause the controller and / or logic to store a copy bit in a copy register and a start bit in a start register of the controller. The logic may copy the data in response to receiving the different command.

[0087] The command may include an identifier of a rank, an identifier of a group, and an identifier of a row. The identifier of the rank, the identifier of the group, and the identifier of the row are addresses of faulty rows. The identifier of the group may correspond to the first group.

[0088] In several embodiments, a memory device of a memory subsystem may have a first group and a second group. The first group may include multiple rows of memory cells and spare rows of memory cells. A controller of the memory subsystem may be coupled to the memory device. The controller may include a scheduler and logic coupled to the scheduler.

[0089] The logic may stop the scheduler from issuing commands to the first group. In response to stopping the scheduler from issuing commands to the first group, the logic may map a specific row of the first group to a spare row. The logic may provide the command to the queue so that the queue provides the command to the specific memory device so that the memory device stores the address of the failed row in the programmable element, thereby mapping the failed row to the spare row. The logic may also allow the scheduler to schedule commands for the second group while mapping the specific row to the spare row.

[0090] The controller may include refresh circuitry. The logic may stop the refresh circuitry from refreshing the first group. For example, the logic may stop the refresh circuitry from refreshing the rows of the first group. The particular row may be mapped to a spare row while refreshing a third group of memory devices. The refresh circuitry and the scheduler may perform operations while mapping the particular row to the spare row. The operations may include refreshing and scheduling. The particular row may be mapped to the spare row while accessing a third group of different memory devices. For example, the scheduler may schedule commands to different groups of the same memory device and different groups of different memory devices while mapping a failed row of a particular group of the same memory device.

[0091] In various cases, the logic may provide a signal to the scheduler to stop the scheduler from issuing commands to the first group. The signal may be a command and / or a control signal. The signal may be received directly from the logic by the scheduler.

[0092] The scheduler may issue a command to access the second group. The command may be an access command. The access command may be issued while mapping a specific row to a spare row.

[0093] The logic may map the particular row to the spare row in response to the completion of commands issued to the first group after stopping the scheduler. For example, before mapping the particular row to the spare row, the logic may wait until commands for the first group in the particular queue are completed. Before the logic maps the particular row to the spare row, the logic may wait until the queue is free of commands for the first group.

[0094] In various examples, an apparatus includes a scheduler, a refresh circuit system, a memory, and logic. The logic can be connected to the scheduler, the refresh circuit system, and the memory.

[0095] The logic may monitor a plurality of registers storing bits identifying a first failed row of the first group and a second failed row of the second group. In response to monitoring the plurality of registers, the logic may copy first data from the first failed row to a memory. The first data may be copied to the memory in response to a host providing specific copy data bits. In response to monitoring the plurality of registers, the logic may copy second data from the second failed row to the memory.

[0096] In response to copying the first data to the memory and copying the second data to the memory, the logic may stop the scheduler from issuing commands to the first group and the second group. In response to copying the first data to the memory and copying the second data to the memory, the logic may stop the refresh circuitry from refreshing the first group and the second group. In response to stopping the scheduler from issuing commands to the first group and stopping the refresh circuitry from refreshing the first group and the second group, the logic may map the first failed row to a first spare row of the first group and map the second failed row to a second spare row of the second group.

[0097] The logic may allow the scheduler to schedule commands for other groups while mapping the first fault row to the first spare row. The logic may allow the refresh circuit system to refresh other groups while mapping the second fault row to the second spare row. In response to mapping the first fault row to the first spare row, the logic may copy first data from the memory to the first spare row. In response to mapping the second fault row to the second spare row, the logic may copy second data from the memory to the second spare row. In response to receiving a command to map the first fault row to the first spare row and the second fault row to the second spare row, a plurality of registers are set. The command may be received from a host. The command may cause a register of the controller to be set.

[0098] The logic is further configured to determine to stop the scheduler and refresh circuitry based on a register of the plurality of registers being set, wherein the register is set to provide an instruction to initiate mapping of the first failing row to the first spare row.The register may store a start bit.

[0099] The logic is further configured to avoid setting a different register (e.g., a status bit) of the plurality of registers in response to setting of the register, wherein the host has read access to the different register and the logic has write access to the different register. The logic does not set the different register until the mapping of the failed row to the spare row is complete. The logic may set the different register in response to copying the first data to the first spare row and copying the second data to the second spare row. The logic may set the different register to signal to the host that the first failed row is mapped to the first spare row and the second failed row is mapped to the second spare row.

[0100] Figure 8An example machine of a computer system 890 is illustrated in which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In various embodiments, the computer system 890 may correspond to a host system (e.g., Figure 1 102), wherein the host system includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 103) or may be used to execute a controller (e.g., Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0101] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be construed to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0102] The example computer system 890 includes a processing device 891, a main memory 893 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 897 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 898 that communicate with each other via a bus 896.

[0103] The processing device 891 represents one or more general processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 891 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 891 is configured to execute instructions 892 for performing the operations and steps discussed herein. The computer system 890 may further include a network interface device 508 for communicating via a network 895.

[0104] The data storage system 898 may include a machine-readable storage medium 899 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 892 or software embodying any one or more of the methods or functions described herein. The instructions 892 may also reside, completely or at least partially, within the main memory 893 and / or within the processing device 891 during execution thereof by the computer system 890, the main memory 893 and the processing device 891 also constituting machine-readable storage media.

[0105] In one embodiment, instructions 892 include instructions for implementing Figure 1 The machine-readable storage medium 899 is shown as a single medium in the example embodiment, but the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" should therefore be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0106] Although specific embodiments have been illustrated and described herein, it will be appreciated by those skilled in the art that arrangements calculated to achieve the same results may replace the specific embodiments shown. The present disclosure is intended to cover modifications or variations of the various embodiments of the present disclosure. It should be understood that the above description has been made in an illustrative and non-restrictive manner. After reviewing the above description, the combination of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art. The scope of the various embodiments of the present disclosure includes other applications using the above structures and methods. Therefore, the scope of the various embodiments of the present disclosure should be determined with reference to the attached claims and the full scope of equivalents granted by the claims.

[0107] In the foregoing detailed description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This approach to the disclosure should not be interpreted as reflecting an intent that the disclosed embodiments of the disclosure necessarily use more features than those explicitly recited in each claim. On the contrary, as reflected in the appended claims, the subject matter of the present invention lies in less than all of the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, with each claim existing on its own as a separate embodiment.

Claims

1. An apparatus for mapping a row in a memory controller, comprising: A memory device (339) comprising: a first group (208) of memory cells comprising a plurality of rows (221) of memory cells and a spare row (222) of memory cells; a second group (208) of memory cells; A controller (105, 305, 605) coupled to the memory device and comprising: Scheduler (334); and Logic (337, 437, 537) coupled to the scheduler and configured to: stopping the scheduler from issuing commands to the first group; In response to stopping the scheduler from issuing commands to the first group, mapping a specific row (221) of the first group to the spare row; and The scheduler is allowed to schedule commands for the second group while mapping the particular row to the spare row.

2. The apparatus of claim 1, wherein the controller further comprises refresh circuitry (335), and wherein the logic is further configured to stop the refresh circuitry of the controller from refreshing the first group.

3. The apparatus of claim 2, wherein the particular row is mapped to the spare row while refreshing a third group (208) of the memory device.

4. The apparatus of any one of claims 1-3, wherein the logic is further configured to map the particular row to the spare row while accessing a third group (208) of different memory devices (339).

5. The apparatus of any one of claims 1 to 3, wherein the logic provides a signal to the scheduler to stop the scheduler from issuing commands to the first group.

6. The apparatus of any one of claims 1-3, wherein the logic is further configured to map the particular row to the spare row while issuing a command to access the second group.

7. The apparatus of any one of claims 1 to 3, wherein the logic is further configured to map the particular row to the spare row in response to completion of commands issued to the first group after stopping the scheduler.

8. The apparatus of any one of claims 1 to 3, wherein the logic is coupled to a command queue (336) corresponding to the memory device, and wherein the logic maps the particular row to the spare row in response to the command queue having no commands for the first group before the logic maps the particular row to the spare row.

9. A method for mapping rows in a memory controller, comprising: Receiving a command from a host (102, 602) at a controller (105, 305, 605) of a memory subsystem (103) to map a failed row (221) of a first group (208) of memory devices (339) of the memory subsystem to a spare row (222) of the first group; In response to receiving the command, using logic (337, 437, 537) of the controller to copy data from the failed row to a memory (338, 438, 538) of the controller; In response to copying the data to the memory of the controller, stopping, using the logic, refresh circuitry (335) of the controller from refreshing the first group; responsive to stopping the refresh circuitry from refreshing the first group, mapping the failed row to the spare row using the logic; refreshing a second group of the memory devices while mapping the failed row to the spare row (208); and In response to mapping the failing row to the spare row, the data is copied from the memory to the spare row.

10. The method of claim 9, further comprising utilizing the logic to stop a scheduler (334) of the controller from issuing commands to the first group in response to copying the data to the memory of the controller.

11. The method of claim 10, further comprising mapping the failing row to the spare row while issuing commands to the second group.

12. The method of any one of claims 9 to 11, further comprising receiving a different command from the host to copy the data from the failing row to the spare row and to start the mapping of the failing row.

13. The method of claim 12, further comprising copying the data based on receiving the different command.

14. A method according to any one of claims 9 to 11, wherein the command comprises an identifier of a rank, an identifier of a group (208) and an identifier of a row, wherein the identifier of the rank, the identifier of the group and the identifier of the row comprise an address of the faulty row, wherein the identifier of the group corresponds to the first group.

15. An apparatus for mapping a row in a memory controller, comprising: Scheduler(334); Refresh circuit system (335); Memory (338, 438, 538); Logic (337, 437, 537) coupled to the scheduler, the refresh circuitry, and the memory, and configured to: monitoring a plurality of registers (441-5) storing bits identifying a first failed row (221) of the first group (208) and a second failed row (221) of the second group (208); responsive to monitoring the plurality of registers, copying first data from the first failing row to the memory; responsive to monitoring the plurality of registers, copying second data from the second failing row to the memory; in response to copying the first data to the memory and copying the second data to the memory, stopping the scheduler from issuing commands to the first group and the second group; in response to copying the first data to the memory and copying the second data to the memory, stopping the refresh circuitry from refreshing the first group and the second group; responsive to stopping the scheduler from issuing commands to the first group and stopping the refresh circuitry from refreshing the first group and the second group, mapping the first failing row to a first spare row (222) of the first group and mapping the second failing row to a second spare row (222) of the second group; allowing the scheduler to schedule commands for other groups (208) while mapping the first failed row to the first spare row; allowing the refresh circuitry to refresh the other groups while mapping the second failed row to the second spare row; In response to mapping the first failing row to the first spare row, copying the first data from the memory to the first spare row; and In response to mapping the second failing row to the second spare row, the second data is copied from the memory to the second spare row.

16. The apparatus of claim 15, configured to set the plurality of registers in response to receiving a command to map the first failing row to the first spare row and the second failing row to the second spare row.

17. The apparatus of claim 16, wherein the logic is further configured to read the plurality of registers to determine to copy the first data to the first spare row and to copy the second data to the second spare row.

18. The apparatus of claim 16, wherein the logic is further configured to determine to stop the scheduler and the refresh circuitry based on a register (441-2) of the plurality of registers being set, wherein the register is set to provide an instruction to initiate mapping of the first failing row to the first spare row.

19. The apparatus of claim 18, wherein the logic is further configured to avoid setting a different register (441-1) of the plurality of registers in response to setting the register, wherein the host has read access to the different register and the logic has write access to the different register.

20. The apparatus of claim 18, wherein the logic is further configured to set the different registers in response to copying the first data to the first spare row and copying the second data to the second spare row to send a signal to the host that the first failed row is mapped to the first spare row and the second failed row is mapped to the second spare row.

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