Hardware architecture performance test method and device

Abstract

The embodiment of the invention provides a performance test method and device for a hardware architecture, and the method comprises the steps: controlling a hard disk test unit to execute a performance test task in response to a test start signal from a central processing unit; in the execution process of the performance test task, test data of the performance test task is transmitted between the central processing unit and the hard disk test device through a configured PCIE link, and the PClE link is configured by the switching chip through a configuration command issued by the central processing unit; under the condition that execution of the performance test task is completed, the test data are transmitted back to the central processing unit through the configured PCIE link, a test result output by the central processing unit is obtained, and the test result is a hard disk performance test result of the hardware architecture. By means of the method and device, the problem that the performance testing efficiency of the hardware architecture is low is solved, and then the effect of improving the performance testing efficiency of the hardware architecture is achieved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computers, and more specifically, to a method and device for testing the performance of a hardware architecture. Background Art

[0002] In the specific scenario of hardware performance testing, existing technologies mainly focus on direct stress testing of hard disks mounted on the CPU through the PCIe interface. However, when faced with servers using hardware architecture, the situation becomes complicated. In such servers, data transmission needs to be mediated by switching chips, and it becomes impractical to implement dynamic switching tests, especially when the configuration scenario is more complex. The technical limitation is that the current methodology fails to effectively adapt to the high degree of integration and configuration diversity of devices under the hardware architecture, resulting in the inability to automatically perform hard disk performance tests on such complex devices.

[0003] Specifically, the complexity of the hardware architecture requires the test process to be able to flexibly respond to performance evaluations under different configuration states, but the existing technical framework lacks the ability to adapt to such dynamic environments. Therefore, it has to rely on manual intervention to make up for the technical deficiencies, which not only increases the manpower cost of the test, but also significantly reduces the overall efficiency of the performance test, which in turn leads to the problem of low performance test efficiency of the hardware architecture.

[0004] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention

[0005] The embodiments of the present application provide a method and device for performance testing of a hardware architecture, so as to at least solve the problem of low efficiency of performance testing of the hardware architecture in the related art.

[0006] According to one embodiment of the present application, a performance testing method for a hardware architecture is provided, comprising: in response to a test start signal from a central processing unit, controlling a hard disk test unit to execute a performance testing task, wherein the performance testing task is a task of performing a hard disk performance test on the hardware architecture, and the hardware architecture includes a switching chip; during the execution of the performance testing task, transmitting test data of the performance testing task between the central processing unit and the hard disk testing device through a configured PCIE link, wherein the PCIE link is configured by the switching chip through a configuration command issued by the central processing unit; when the performance testing task is completed, transmitting the test data back to the central processing unit through the configured PCIE link to obtain a test result output by the central processing unit, wherein the test result is a hard disk performance test result of the hardware architecture.

[0007] According to another embodiment of the present application, a performance testing device of a hardware architecture is provided, comprising: a first control unit, for controlling a hard disk testing unit to execute a performance testing task in response to a test start signal from a central processing unit, wherein the performance testing task is a task of performing a hard disk performance test on the hardware architecture, and the hardware architecture comprises a switching chip; a transmission unit, for transmitting test data of the performance testing task between the central processing unit and the hard disk testing device through a configured PCIE link during the execution of the performance testing task, wherein the PCIE link is configured by the switching chip through a configuration command issued by the central processing unit; an output unit, for transmitting the test data back to the central processing unit through the configured PCIE link when the performance testing task is completed, so as to obtain a test result output by the central processing unit.

[0008] Among them, the above test results are the hard disk performance test results of the above hardware architecture.

[0009] In an exemplary embodiment, the first control unit comprises: a first control module, for responding to the test start signal, controlling the hard disk test unit to perform a performance test task in a single-node scenario, wherein the single-node scenario is a test environment in which all test components are concentrated on one physical node or server, and all the test components include the central processing unit, the hard disk test unit, and the switching chip; or, a second control module, for responding to the test start signal, controlling the hard disk test unit to perform a performance test task in a multi-node scenario, wherein the test components in all the test components are distributed in a test environment on multiple physical nodes or servers.

[0010] In an exemplary embodiment, the central processor is connected to the MCIO connector of the hard disk test unit through the configured PCIE link, and is further connected to the system hard disk. The hard disk test unit is respectively connected to the central processor, the switch chip and the NVME hard disk through multiple interfaces. The device further includes: a first power-on unit, which is used to power on the switch chip, the NVME hard disk and the central processor in sequence before controlling the hard disk test unit to execute the performance test task in a single-node scenario in response to the test start signal, wherein the system hard disk is used to provide the test script for executing the performance test task, and the hard disk performance test result is the performance test result of the NVME hard disk; a first configuration unit, which is used to control the hard disk in response to the test start signal. Before the test unit executes the performance test task in the single-node scenario, the port connected to the central processor in the switching chip is configured as an uplink PCIE port, and the port connected to the NVME hard disk is configured as a downlink PCIE port, and the downlink PCIE port is bound to the uplink PCIE port to complete the configuration of the PCIE link and obtain the configured PCIE link; the first control module includes: a first test submodule, which is used to issue a test command through the operating system provided by the system hard disk to execute the test script; the device also includes: a second control unit, which is used to control the indicator light managed by the hard disk test unit to indicate the completion progress of the performance test task after controlling the hard disk test unit to execute the performance test task in the single-node scenario in response to the test start signal.

[0011] In an exemplary embodiment, the PCIE structure of the central processor is connected to the first signal enhancement device through a cable, connected to the switch chip through a CDFP interface at one end of the hard disk test unit, and connected to the system hard disk through a CDFP interface at the other end of the hard disk test unit. The device further includes: a second power-on unit, which is used to power on the switch chip, the NVME hard disk, and the central processor in sequence before controlling the hard disk test unit to perform a performance test task in a multi-node scenario in response to the test start signal, wherein the system hard disk is used to provide a test script for performing the performance test task, a connection is established between the switch chip and the NVME hard disk through the second signal enhancement device, and the hard disk performance test result is the performance test result of the NVME hard disk; a second configuration unit is used to control the hard disk test unit to perform a performance test task in a multi-node scenario in response to the test start signal, wherein the system hard disk is used to power on the switch chip, the NVME hard disk, and the central processor in sequence, wherein the system hard disk is used to provide a test script for performing the performance test task, a connection is established between the switch chip and the NVME hard disk through the second signal enhancement device, and the hard disk performance test result is the performance test result of the NVME hard disk; and a second configuration unit is used to control the hard disk test unit to perform a performance test task in response to the test start signal. The first control module comprises: a first test submodule, which is used to send a test command through the operating system provided by the system hard disk to execute the test script; the second control module comprises: a third control unit, which is used to control the indicator light managed by the hard disk test unit to indicate the completion progress of the performance test task after controlling the hard disk test unit to execute the performance test task in the multi-node scenario in response to the test start signal.

[0012] In an exemplary embodiment, the above-mentioned device also includes: a switching unit, which is used to control the above-mentioned switching chip to implement the switching of the above-mentioned PCIE link in response to a test configuration command from the above-mentioned central processing unit before the above-mentioned control of the hard disk test unit to perform a performance test task in response to a test start signal from the above-mentioned central processing unit, so as to obtain the above-mentioned configured PCIE link, wherein the number of the above-mentioned central processing units is set to allow expansion, the above-mentioned central processing unit is set in a server of a device cluster, the above-mentioned device cluster also includes a storage resource pool, the above-mentioned storage resource pool includes at least one hard disk module, and the above-mentioned hard disk performance test result is the performance test result of the above-mentioned at least one hard disk module.

[0013] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any one of the above method embodiments when running.

[0014] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0015] Through the embodiments of the present application, a series of technical means are used to realize the automation and efficient execution of hard disk performance testing under complex hardware architecture. Specifically, first, the solution responds to the test start signal from the central processing unit to start the hard disk test unit to perform the performance test task for the hardware architecture. This step ensures the accurate triggering of the test process, avoids the uncertainty caused by manual intervention, and thus improves the initial efficiency of the test. The key is that the solution can directly test the hardware architecture containing the switching chip, and is no longer limited to the traditional hard disk test mode directly mounted on the CPU.

[0016] Secondly, during the execution of the performance test task, the pre-configured PCIe link enables efficient transmission of test data between the CPU and the hard disk test device. This mechanism utilizes the configuration capability of the switch chip and dynamically sets the PCIe link through the configuration command issued by the CPU, effectively solving the complexity of data transmission in the hardware architecture through the switching chip intermediary. This dynamic configuration capability enables the test environment to adapt to different configuration states, enhances the flexibility and adaptability of the test, and reduces the manual adjustment time required due to configuration changes.

[0017] Finally, after the performance test task is completed, the test data is sent back to the central processor through the configured PCIe link to obtain the test results. This process not only ensures the accurate return of the test data, but also realizes the automatic output of the test results, further reducing the need for manual participation. The central processor directly processes and outputs the test results, which significantly improves the overall efficiency of the test and reduces labor costs.

[0018] The embodiments of the present application effectively solve the complexity problems faced by hard disk performance testing under hardware architecture through technical means such as responsive startup, dynamic configuration of PCIe links, and automated result output, and improve the degree of automation and overall efficiency of the test, thereby overcoming the limitations of the existing technical framework in adapting to the high integration and configuration diversity of hardware architecture devices, and can solve the problem of low performance testing efficiency of hardware architecture, thereby achieving the technical effect of improving the performance testing efficiency of hardware architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic diagram of an application environment of a performance testing method for a hardware architecture according to an embodiment of the present application;

[0020] Figure 2is a flowchart of a performance testing method for a hardware architecture according to an embodiment of the present application;

[0021] Figure 3 is a schematic diagram of a performance testing method for a hardware architecture according to an embodiment of the present application;

[0022] Figure 4 is a schematic diagram of a performance testing method for a hardware architecture according to an embodiment of the present application;

[0023] Figure 5 is a schematic diagram of a performance testing method for a hardware architecture according to an embodiment of the present application;

[0024] Figure 6 is a schematic diagram of a performance testing method for a hardware architecture according to an embodiment of the present application;

[0025] Figure 7 is a schematic diagram of a performance testing method for a hardware architecture according to an embodiment of the present application;

[0026] Figure 8 It is a structural block diagram of a performance testing device of the hardware architecture of an embodiment of the present application. DETAILED DESCRIPTION

[0027] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0028] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0029] The method embodiments provided in the embodiments of the present application can be executed in a server device or a similar computing device. Taking running on a server device as an example, Figure 1 1 is a hardware structure block diagram of a server device of a hardware architecture performance testing method of an embodiment of the present application. Figure 1 As shown, the server device may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the server device may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above server device. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.

[0030] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the performance test method of the hardware architecture in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the server device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0031] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the server device. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0032] In this embodiment, a performance testing method for a hardware architecture is provided. Figure 2 is a flowchart of a performance testing method for a hardware architecture according to an embodiment of the present application. Figure 2 As shown, the process includes the following steps:

[0033] Step S202, in response to a test start signal from the central processing unit, controlling the hard disk test unit to execute a performance test task, wherein the performance test task is a task of performing a hard disk performance test on a hardware architecture, and the hardware architecture includes a switching chip;

[0034] In an exemplary embodiment, the central processing unit (CPU) is the core component of a computer, responsible for executing program instructions, processing data, and controlling other parts of the computer.

[0035] In an exemplary embodiment, the test start signal is a specific instruction or signal sent by the CPU to trigger the hard disk test unit to start executing the performance test task.

[0036] In an exemplary embodiment, the hard disk test unit is a specially designed module or software for performing various performance tests on the hard disk, such as read and write speed, response time, data integrity, etc.

[0037] In an exemplary embodiment, the performance test task is a series of tests for hard disk performance, which is intended to evaluate the performance of the hard disk under specific conditions, especially when the hard disk is located in a hardware architecture including a switch chip.

[0038] In an exemplary embodiment, the hardware architecture is a server architecture that is a converged architecture obtained by interconnecting and integrating multiple hardware components (such as CPU, memory, hard disk, switch chip, etc.) to provide high performance, scalability and flexibility.

[0039] In an exemplary embodiment, a switch chip: In hardware architecture, a chip used to efficiently transfer data between different components. It may be responsible for routing data from one component to another, ensuring the speed and accuracy of data transmission.

[0040] Step S204, during the execution of the performance test task, the test data of the performance test task is transmitted between the central processing unit and the hard disk test device through the configured PCIE link, wherein the PCIE link is configured by the switch chip through the configuration command issued by the central processing unit;

[0041] In an exemplary embodiment, a PCIE link refers to a PCIe (PCI Express) link, which is a high-speed, serial, point-to-point data transmission channel used to connect a CPU and other devices (such as a hard disk, a graphics card, etc.).

[0042] In an exemplary embodiment, a configured PCIE link refers to a PCIe link that has been set and optimized according to specific requirements (such as the requirements of a performance test task).

[0043] In an exemplary embodiment, the hard disk testing device may be a part of the hard disk testing unit, or an independent device connected thereto, for performing actual hard disk performance testing.

[0044] In an exemplary embodiment, a configuration command is an instruction issued by a CPU and is used to tell the switch chip how to configure a PCIe link to meet the requirements of a performance test task.

[0045] Step S206, when the performance test task is completed, the test data is transmitted back to the central processing unit through the configured PCIE link to obtain the test result output by the central processing unit, wherein the test result is the hard disk performance test result of the hardware architecture.

[0046] In an exemplary embodiment, test data: data collected during a performance test, used to evaluate the performance of a hard disk.

[0047] In an exemplary embodiment, transmission back: the process of transferring data from the hard disk testing device or the hard disk itself back to the CPU.

[0048] In an exemplary embodiment, the test result is a conclusion obtained after the CPU processes the test data, which is used to indicate the performance of the hard disk in the performance test.

[0049] In an exemplary embodiment, the hard disk performance test result of the hardware architecture refers specifically to the result obtained after the hard disk is subjected to a performance test in the hardware architecture environment.

[0050] To further illustrate, optionally assume that there is a server with a hardware architecture that includes a switch chip, multiple hard disks, and a hard disk test unit. In order to test the performance of these hard disks, the CPU will send a test start signal to the hard disk test unit. After receiving the signal, the hard disk test unit will start to perform a series of performance tests, such as read and write speed tests, random access time tests, etc. During the test, the test data (such as read and write speed, response time, etc.) will be transmitted between the CPU and the hard disk test device through the configured PCIe link. This PCIe link is set by the switch chip according to the configuration command issued by the CPU, ensuring efficient and accurate data transmission. After the test is completed, the test data (such as the read and write speed, response time, etc. of each hard disk) will be transmitted back to the CPU through the same PCIe link. The CPU will process this data and output the test results, such as the performance score and ranking of each hard disk.

[0051] Through a series of technical means in the above steps, the implementation of this application realizes the automation and efficient execution of hard disk performance testing under complex hardware architecture. Specifically, first, the solution responds to the test start signal from the central processing unit to start the hard disk test unit to perform performance testing tasks for the hardware architecture. This step ensures the accurate triggering of the test process, avoids the uncertainty caused by manual intervention, and thus improves the initial efficiency of the test. The key is that the solution can directly test the hardware architecture containing the switching chip, and is no longer limited to the traditional hard disk test mode directly mounted on the CPU.

[0052] Secondly, during the execution of the performance test task, the pre-configured PCIe link enables efficient transmission of test data between the CPU and the hard disk test device. This mechanism utilizes the configuration capability of the switch chip and dynamically sets the PCIe link through the configuration command issued by the CPU, effectively solving the complexity of data transmission in the hardware architecture through the switching chip intermediary. This dynamic configuration capability enables the test environment to adapt to different configuration states, enhances the flexibility and adaptability of the test, and reduces the manual adjustment time required due to configuration changes.

[0053] Finally, after the performance test task is completed, the test data is sent back to the central processor through the configured PCIe link to obtain the test results. This process not only ensures the accurate return of the test data, but also realizes the automatic output of the test results, further reducing the need for manual participation. The central processor directly processes and outputs the test results, which significantly improves the overall efficiency of the test and reduces labor costs.

[0054] The embodiments of the present application effectively solve the complexity problems faced by hard disk performance testing under hardware architecture through technical means such as responsive startup, dynamic configuration of PCIe links, and automated result output, and improve the degree of automation and overall efficiency of the test, thereby overcoming the limitations of the existing technical framework in adapting to the high integration and configuration diversity of hardware architecture devices, and can solve the problem of low performance testing efficiency of hardware architecture, thereby achieving the technical effect of improving the performance testing efficiency of hardware architecture.

[0055] The execution subject of the above steps may be a server, a terminal, etc., but is not limited thereto.

[0056] The execution order of step S202, step S204 and step S206 is interchangeable, that is, step S204 may be executed first and then S202, or step S206 may be executed first and then S204.

[0057] As an optional solution, in response to a test start signal from a central processing unit, the hard disk test unit is controlled to perform a performance test task, including:

[0058] S1-1, in response to a test start signal, controlling the hard disk test unit to execute a performance test task in a single-node scenario, wherein the single-node scenario is a test environment in which all test components are concentrated on one physical node or server, and all test components include a central processing unit, a hard disk test unit, and a switch chip; or,

[0059] S1-2, in response to a test start signal, controls the hard disk test unit to execute a performance test task in a multi-node scenario, wherein the test components in all test components are distributed in a test environment on multiple physical nodes or servers.

[0060] In an optional embodiment, a single-node scenario refers to a test environment in which all components involved in the test (including a CPU, a hard disk test unit, a switch chip, etc.) are concentrated on one physical node or server.

[0061] In this scenario, since all components are in the same physical location, data transmission and processing can be faster and the testing environment is relatively simple.

[0062] To further illustrate, it is optional to assume that there is a server with a hardware architecture that includes a CPU, a hard disk test unit, and a switch chip. On this server, a single-node test environment can be built, all test components can be concentrated on this server, and then performance test tasks can be performed. For example, the read and write speed, response time, etc. of the hard disk can be tested.

[0063] In an optional embodiment, a multi-node scenario refers to a test environment in which components involved in the test are distributed on multiple physical nodes or servers.

[0064] In this scenario, since the components are distributed in different physical locations, it is necessary to consider the impact of factors such as network latency and data transmission bandwidth on the test results. At the same time, the multi-node scenario is also closer to the actual production environment, so the test results may be more valuable for reference.

[0065] To further illustrate, it is optional to assume that there are two servers with hardware architectures, each of which contains some test components. The two servers can be connected to build a multi-node test environment. In this environment, the data transmission speed and response time of the hard disk between different servers can be tested. For example, a distributed storage system can be simulated to test the performance of storing and reading data on different nodes.

[0066] By performing performance testing tasks in single-node and multi-node scenarios, you can have a more comprehensive understanding of the performance of the hard disk in the hardware architecture. Testing in a single-node scenario can help quickly discover the basic performance and potential problems of the hard disk; while testing in a multi-node scenario can more realistically simulate the actual production environment and help evaluate the performance and stability of the hard disk in a complex environment. This comprehensive testing method helps to improve the accuracy and reliability of the test results, and provides a strong basis for the optimization and selection of the hard disk. At the same time, through the automated testing process, the efficiency of the test can be significantly improved and the testing cost can be reduced.

[0067] As an optional solution, the central processing unit is connected to the MCIO connector of the hard disk test unit through a configured PCIE link, and is further connected to the system hard disk. The hard disk test unit is respectively connected to the central processing unit, the switch chip and the NVME hard disk through multiple interfaces. Before responding to the test start signal and controlling the hard disk test unit to perform the performance test task in the single-node scenario, the method also includes:

[0068] S2-1, power on the switch chip, NVME hard disk, and central processing unit in sequence, wherein the system hard disk is used to provide a test script for executing the performance test task, and the hard disk performance test result is the performance test result of the NVME hard disk;

[0069] S2-2, configure the port connected to the central processor in the switching chip as an uplink PCIE port, and configure the port connected to the NVME hard disk as a downlink PCIE port, and bind the downlink PCIE port to the uplink PCIE port to complete the configuration of the PCIE link and obtain the configured PCIE link;

[0070] In response to the test start signal, the hard disk test unit is controlled to execute the performance test task in the single-node scenario, including: issuing a test command through the operating system provided by the system hard disk to execute the test script;

[0071] In response to the test start signal, the hard disk test unit is controlled to execute the performance test task in the single-node scenario. The method also includes: controlling the indicator light managed by the hard disk test unit to indicate the completion progress of the performance test task.

[0072] In an optional embodiment, the MCIO connector may be an interface on the hard disk test unit, used to connect to the CPU via a PCIe link.

[0073] In an optional embodiment, multiple interfaces, including PCIe interface, SATA interface, SAS interface, etc., are used to connect different devices and components.

[0074] In an optional embodiment, NVME hard disk: a solid-state hard disk based on the NVMe (Non-Volatile Memory Express) protocol, with the characteristics of high performance and low latency.

[0075] In an optional embodiment, power on: powering a device or component to start working. The switch chip, NVME hard disk, and CPU need to be powered on in a specific order to ensure the stability and security of the test environment.

[0076] In an optional embodiment, the system hard disk is a hard disk on the server used to store an operating system and data.

[0077] In an optional embodiment, test script: a series of instructions and codes for executing performance testing.

[0078] In an optional embodiment, the uplink PCIE port refers to a PCIe port connected to the CPU and used to receive data and instructions from the CPU.

[0079] In an optional embodiment, the downstream PCIE port refers to a PCIe port connected to the NVME hard disk, which is used to send data and instructions to the NVME hard disk.

[0080] In an optional embodiment, the operating system is a program that manages computer hardware and software resources and provides an interface for users to interact with the computer. The operating system issues a test command to execute a test script stored on the system hard disk, thereby starting a performance test.

[0081] In an optional embodiment, the indicator light is an LED light or other type of indicator light on the hard disk test unit, which is used to display the test progress or status. By controlling the flashing frequency, color, etc. of the indicator light, the completion status of the performance test task can be intuitively understood.

[0082] For further example, it is optional to assume that there is a server with a hardware architecture that includes a CPU, a hard disk test unit, a switch chip, and an NVME hard disk. In order to test the performance of the NVME hard disk, you need to follow the following steps:

[0083] Power on the switch chip, NVME hard disk, and CPU in sequence to ensure that they are all in working order. Send test commands through the operating system and load the test script from the system hard disk. Configure the PCIe port of the switch chip, set the port connected to the CPU as the upstream PCIE port, set the port connected to the NVME hard disk as the downstream PCIE port, and bind them together.

[0084] Start the hard disk test unit and establish a PCIe link connection with the CPU through the MCIO connector. Execute the test script to start the performance test. During the test, the indicator light on the hard disk test unit can be controlled to indicate the test progress. After the test is completed, collect the test results, analyze and evaluate them.

[0085] Through the embodiment of the present application, the performance of the NVME hard disk in the hardware architecture can be effectively tested. By configuring the PCIe port and establishing a PCIe link connection, it is possible to ensure that data is efficiently and accurately transmitted between the CPU and the NVME hard disk. At the same time, by controlling the indicator light to indicate the test progress, the completion of the performance test can be intuitively understood. This method helps to improve the accuracy and reliability of the test results and provides a strong basis for the optimization and selection of the hard disk.

[0086] As an optional solution, the PCIE structure of the central processor is connected to the first signal enhancement device through a cable, connected to the above-mentioned switching chip through a CDFP interface at one end of the hard disk test unit, and connected to the system hard disk through the CDFP interface at the other end of the hard disk test unit. Before responding to the test start signal and controlling the hard disk test unit to perform the performance test task in the multi-node scenario, the method also includes:

[0087] S3-1, power on the switch chip, NVME hard disk, and central processing unit in sequence, wherein the system hard disk is used to provide a test script for executing a performance test task, a connection is established between the switch chip and the NVME hard disk through a second signal enhancement device, and the hard disk performance test result is a performance test result of the NVME hard disk;

[0088] S3-2, configure the port connected to the central processor in the switching chip as an upstream PCIE port, and configure the port connected to the NVME hard disk as a downstream PCIE port, and bind the downstream PCIE port to the upstream PCIE port to complete the configuration of the PCIE link and obtain the configured PCIE link;

[0089] In response to the test start signal, the hard disk test unit is controlled to execute the performance test task in the multi-node scenario, including: issuing a test command through the operating system provided by the system hard disk to execute the test script;

[0090] In response to the test start signal, the hard disk test unit is controlled to execute the performance test task in the multi-node scenario. The method also includes: controlling the indicator light managed by the hard disk test unit to indicate the completion progress of the performance test task.

[0091] In an optional embodiment, NVME hard disk: a solid-state hard disk based on the NVMe (Non-Volatile Memory Express) protocol, with the characteristics of high performance and low latency.

[0092] In an optional embodiment, power on: powering a device or component to start working. The switch chip, NVME hard disk, and CPU need to be powered on in a specific order to ensure the stability and security of the test environment.

[0093] In an optional embodiment, the system hard disk is a hard disk on the server used to store an operating system and data.

[0094] In an optional embodiment, test script: a series of instructions and codes for executing performance testing.

[0095] In an optional embodiment, the uplink PCIE port refers to a PCIe port connected to the CPU and used to receive data and instructions from the CPU.

[0096] In an optional embodiment, the downstream PCIE port refers to a PCIe port connected to the NVME hard disk, which is used to send data and instructions to the NVME hard disk.

[0097] In an optional embodiment, the operating system is a program that manages computer hardware and software resources and provides an interface for users to interact with the computer. The operating system issues a test command to execute a test script stored on the system hard disk, thereby starting a performance test.

[0098] In an optional embodiment, the indicator light is an LED light or other type of indicator light on the hard disk test unit, which is used to display the test progress or status. By controlling the flashing frequency, color, etc. of the indicator light, the completion status of the performance test task can be intuitively understood.

[0099] In an optional embodiment, the CDFP interface is a specific type of interface on the hard disk test unit, used to establish a connection with a switching chip.

[0100] In an optional embodiment, the PCIE structure of a central processing unit (CPU) refers to a structure or module on the CPU for supporting a PCI Express (PCIE) interface.

[0101] In an optional embodiment, the cable is a physical wire used to connect the PCIE structure of the CPU and the first signal enhancement device.

[0102] In an optional embodiment, the first signal enhancement device is a device for enhancing or amplifying the PCIE signal to ensure the stability and accuracy of the signal during transmission.

[0103] In an optional embodiment, the second signal enhancement device: similar to the first signal enhancement device, is used to enhance or amplify the signal between the switching chip and the NVME hard disk.

[0104] For further example, it is optional to assume that there is a hardware architecture system with multiple physical nodes, and each node contains some test components. In order to test the performance of NVME hard disk in a multi-node scenario, you can follow the steps below:

[0105] Power on the switch chip, NVME hard disk, and CPU in sequence. Send test commands through the operating system and load the test script from the system hard disk. Configure the PCIE port of the switch chip, set the port connected to the CPU as the upstream PCIE port, set the port connected to the NVME hard disk as the downstream PCIE port, and bind them together.

[0106] Use a cable to connect the CPU's PCIE structure to the first signal enhancement device to ensure signal stability and accuracy. Connect it to the switch chip and system hard disk through the CDFP interface of the hard disk test unit. Use the second signal enhancement device to enhance the signal connection between the switch chip and the NVME hard disk.

[0107] Start the hard disk test unit and start the performance test task in the multi-node scenario. During the test, you can control the indicator light on the hard disk test unit to indicate the test progress. After the test is completed, collect the test results, analyze and evaluate them.

[0108] Through the embodiment of the present application, the performance of NVME hard disks in multi-node scenarios can be effectively tested. By configuring PCIE ports, using signal enhancement equipment, and establishing stable connections, data can be ensured to be efficiently and accurately transmitted between multiple nodes. At the same time, by controlling the indicator light to indicate the progress of the test, the completion of the performance test can be intuitively understood. This method helps to improve the accuracy and reliability of the test results, provides a strong basis for the optimization and selection of hard disks, and helps to ensure the stability and performance of the hardware architecture system in actual operation.

[0109] As an optional solution, before controlling the hard disk test unit to execute the performance test task in response to the test start signal from the central processor, the method further includes:

[0110] In response to a test configuration command from a central processing unit, the switching chip is controlled to implement switching of a PCIE link to obtain a configured PCIE link, wherein the number of central processing units is set to allow expansion, the central processing unit is set in a server of a device cluster, the device cluster also includes a storage resource pool, the storage resource pool includes at least one hard disk module, and the hard disk performance test result is a performance test result of at least one hard disk module.

[0111] In an optional embodiment, the test configuration command is an instruction issued by the CPU for configuring the test environment or parameters.

[0112] In an optional embodiment, switching refers to changing the connection state or configuration of the PCIE link to adapt to test requirements.

[0113] In an optional embodiment, the number of central processing units is set to allow for scalability: this means that the system design allows for the addition of more CPUs to increase processing power and performance.

[0114] In an optional embodiment, a device cluster is a collection of multiple servers, storage devices, and other network devices, used to provide high-performance, high-availability, and scalable computing and data storage services.

[0115] In an optional embodiment, a server is a computer device that provides computing and data storage services.

[0116] In an optional embodiment, a storage resource pool is a collection of resources in a device cluster for storing data, and usually includes multiple hard disk modules.

[0117] In an optional embodiment, the hard disk module is a storage unit composed of one or more hard disks and is used to store and access data.

[0118] In an optional embodiment, the hard disk performance test result is a performance test result of at least one hard disk module: this means that the performance test will be performed on one or more hard disk modules in the storage resource pool and their performance test results will be obtained.

[0119] To further illustrate, let's assume that there is a device cluster that contains multiple servers and a storage resource pool. The storage resource pool consists of multiple hard disk modules that are used to store large amounts of data. To test the performance of these hard disk modules, follow these steps:

[0120] In response to the test configuration command from the CPU, the switch chip is controlled to implement the switching of the PCIE link to ensure that data can be correctly transmitted between the CPU and the hard disk module.

[0121] Configure the test environment, including setting the number of CPUs (allowing for expansion), selecting the hard disk module to be tested, etc.

[0122] Start the hard disk test unit and start the performance test task. During the test, the hard disk test unit will send read and write requests to the hard disk module and measure its response time, throughput and other performance indicators.

[0123] After the test is completed, the test results are collected and analyzed to obtain the performance test results of the hard disk module.

[0124] Through the embodiments of the present application, the performance of the hard disk module in the storage resource pool can be effectively tested. By responding to the test configuration command, controlling the switching chip to implement the switching of the PCIE link, and configuring the test environment, the smooth progress of the test process can be ensured. At the same time, by collecting and analyzing the test results, the performance test results of the hard disk module can be obtained, providing a strong basis for the optimization and selection of the hard disk. This method helps to improve the storage performance and resource utilization of the device cluster, and provides reliable support for practical applications.

[0125] As an optional solution, the hard disk module includes:

[0126] Hard disk backplane, NVME hard disk.

[0127] In an optional embodiment, the hard disk module is a storage unit that integrates a hard disk and related interfaces and control circuits to achieve data storage and access. The hard disk module can contain multiple hard disks (such as NVME hard disks) and connect and manage them through components such as backplanes to provide efficient and reliable data storage services.

[0128] In an optional embodiment, the hard disk backplane is an important component of the hard disk module, which provides a physical connection and electrical interface between the hard disk and the host system or other storage devices. The hard disk backplane may include multiple slots or interfaces for connecting hard disks and provide functions such as data transmission, power supply and signal conversion. It may also support advanced features such as hot plugging and fault indication to facilitate maintenance and management.

[0129] In an optional embodiment, the NVME (Non-Volatile Memory Express) hard disk is a solid-state drive (SSD) based on the NVME protocol, which uses a high-speed non-volatile memory (such as NAND flash memory) as a storage medium. The NVME hard disk has the characteristics of high performance, low latency, high concurrency, etc., and is suitable for application scenarios that require high-speed reading and writing and large-capacity storage. It is usually connected to the host system through a PCIE interface to provide high-speed data transmission services.

[0130] To further illustrate, it is optional to assume that there is a hard disk module, which includes a hard disk backplane and two NVME hard disks. The hard disk backplane provides two PCIE slots for connecting two NVME hard disks. When data needs to be written to the hard disk, the host system sends a write request to the hard disk backplane through the PCIE interface, and the hard disk backplane forwards the request to the corresponding NVME hard disk. Similarly, when data needs to be read, the hard disk backplane receives data from the NVME hard disk and forwards it to the host system.

[0131] By using hard disk modules, data storage and access can be effectively achieved. The hard disk backplane provides a reliable physical connection and electrical interface, allowing the hard disk to be stably connected to the host system or other storage devices. At the same time, the high performance characteristics of NVME hard disks make data read and write faster and with lower latency, thereby improving the overall performance of the system. In addition, the scalability and configurability of the hard disk module also enable it to adapt to different application requirements and system architectures, providing a flexible and efficient solution for data storage.

[0132] As an optional solution, the hard disk test device includes:

[0133] A power module, used to supply power to the hard disk test device;

[0134] In an optional embodiment, the power module is an important component of the hard disk test device, responsible for providing a stable and reliable power supply for the entire device. The power module converts external input electrical energy into various voltages and currents required by the device to ensure the normal operation of each module.

[0135] The single board management module is used to manage the status of the mainboard, the power supply management of the system hard disk, interact with the configuration information of the central processor, send the configuration information in the exchange chip, and provide HDMI, network port and USB interface. The HDMI interface can realize display control, and the network port can realize the parallel management of multiple test devices to realize large-scale simultaneous testing. The system hard disk is used to provide test scripts for executing performance test tasks;

[0136] In an optional embodiment, the single board management module is the core management component in the hard disk test device, responsible for the management of the mainboard status, the power supply management of the system hard disk, and the interaction with the central processing unit and other modules. Interact with the central processing unit configuration information, receive and process the test configuration commands from the CPU. Send configuration information to the switching chip to control the switching of the PCIE link. Provide HDMI, network port and USB interface for display control, parallel management and data transmission. Manage the system hard disk and provide test scripts for performing performance test tasks. Collect information such as temperature sensing and hard disk temperature on the hard disk test device for fan speed control.

[0137] The fan module is used to provide heat dissipation for the hard disk test device and is controlled by the single board management module. The single board management module collects information such as the temperature of the hard disk test device and the hard disk temperature, and controls the fan speed in real time according to the speed regulation strategy.

[0138] In an optional embodiment, the fan module is a heat dissipation component in the hard disk test device, which is responsible for providing heat dissipation for the device to prevent performance degradation or damage caused by overheating. The fan module is controlled by the single board management module, and adjusts the fan speed in real time according to the collected temperature sense and hard disk temperature information to keep the device within a suitable operating temperature range.

[0139] To further illustrate, it is optional to assume that there is a hard disk test device, which includes a power module, a single board management module and a fan module. When performing hard disk testing, the power module provides power supply for the entire device; the single board management module is responsible for managing the status of the motherboard, the power supply of the system hard disk, and exchanging configuration information with the central processor; at the same time, it also displays the test status through the HDMI interface, realizes parallel management of multiple test devices through the network port, and transmits data through the USB interface. The fan module adjusts the fan speed in real time according to the temperature information collected by the single board management module to ensure that the device runs at an appropriate working temperature.

[0140] By using the hard disk test device, the performance and stability of the hard disk can be tested efficiently and accurately. The power module ensures the stable power supply of the device; the single board management module provides comprehensive management and interaction functions, making the test process more convenient and efficient; the fan module ensures that the device operates at a suitable operating temperature to avoid performance degradation or damage caused by overheating. In addition, the configurability and scalability of the hard disk test device also enable it to adapt to different test requirements and hard disk types, providing strong support for the research and development, production and quality control of hard disks.

[0141] As an optional solution, for ease of understanding, the performance testing method of the hardware architecture is applied to the test scenario of the hard disk performance of the storage device, especially for this new application scenario where multiple hardware are integrated and associated with each other. The embodiment of the present application proposes an efficient hard disk performance testing solution. Specifically, by decoupling the functional modules of the server, the memory resources are pooled, and the flexible configuration of storage resources is realized, and the memory resource pooling is realized. Compared with the traditional server hard disk performance test, there are obvious differences in equipment control, test schemes, etc. The embodiment of the present application proposes a hard disk testing solution based on the server fusion structure.

[0142] In an optional embodiment, the location of the tested unit NVME POOL (storage resource pool) in the cabinet is as follows: Figure 3 As shown, Figure 3 The system architecture from onion routing to storage resource pool is shown in Figure 1. The tested unit NVME POOL (storage resource pool) is located at Figure 3 The bottom shows its bottom position in the whole system architecture. This layout clearly reflects the function of NVME POOL as the core of data storage, which directly bears the responsibility of data storage. From top to bottom, it is onion routing, memory pool, server, I / O switching module, and finally reaches the acceleration resource pool and storage resource pool, forming a complete system flow.

[0143] Further based on Figure 3 The scene shown, Figure 4 It is a functional block diagram related to the hardware architecture (device) and NVME (Non-Volatile Memory Host Controller Interface Specification) functions, consisting of three core parts: CPU layer, switch layer, and hard disk module layer.

[0144] The CPU layer is located at Figure 4 At the top of the diagram, multiple CPUs (CPU1 to CPUn) are shown, which are connected by bidirectional arrows, indicating that these CPUs can communicate and transfer data with each other to jointly process system tasks.

[0145] The switch layer is the key to connecting the CPU and the hard disk module. The switch (SW) is located in the middle, forming a complex network structure. These switches are not only responsible for data routing between CPUs, but also undertake the important task of data transmission between CPU and hard disk module, ensuring the efficient flow of data within the system.

[0146] The hard disk module layer is located at Figure 4 The bottom of the system consists of multiple hard disk modules, which are the physical basis for data storage in the system. The hard disk modules are connected to the switch through arrows, indicating that they can receive data requests from the CPU and return the required data, realizing fast data access.

[0147] also, Figure 4 The CPU part is located in Figure 3 The number of CPUs in a server chassis can be expanded. Figure 4 The SW (switch chip) in the device implements the switching of the PCIE link by receiving the configuration commands sent by the CPU. Figure 4 The hard disk module is located in the storage resource pool and is mainly composed of a hard disk backplane and NVME hard disk.

[0148] In an alternative embodiment, Figure 5 This is a block diagram of a hard disk test device (unit), which consists of a power module, a fan module, a main control module, a system hard disk, an MCIO connector, and a CDFP connector, as follows:

[0149] Power module: completes the power supply of the hard disk test device.

[0150] Fan module: provides heat dissipation for the test unit and is controlled by the single board management module. The single board management module collects information such as the temperature of the test unit and the hard disk temperature, and controls the fan speed in real time according to the speed regulation strategy.

[0151] Single board management module: management of the mainboard status, power supply management of the system hard disk, interaction with the CPU configuration information in the server, distribution of configuration information in the SW, and providing HDMI, network port and USB interface. The HDMI interface can realize display control. The network port can realize parallel management of multiple test devices and realize large-scale simultaneous testing.

[0152] System hard disk: As the test object, it is closely connected to the single board management module through MCIO and CDFP connectors to achieve fast data transmission and exchange.

[0153] MCIO connector and CDFP connector: Serving as a bridge, they ensure seamless connection between the system hard disk and the single-board management module, guaranteeing smooth and stable data transmission.

[0154] It should be noted that the existing technical solutions cannot carry out automated hard disk performance testing on servers with hardware architectures. Figure 5 The hard disk test unit shown can realize automated testing of the hard disk performance of the hardware architecture server according to different test requirement scenarios. In this embodiment, it mainly targets two test scenarios, namely a single-node scenario and a multi-node scenario.

[0155] To further illustrate, the optional Figure 5 The scene shown, continue as Figure 6 As shown in the figure, for a single-node scenario, the PCIE of the CPU in the server is connected to the MCIO connector of the test unit through a cable and connected to the system hard disk in the test device; the single-board management module is connected to the CPU in the server through IIC, connected to the SW through IIC2, and connected to the NVME hard disk module through IIC3. When a hard disk performance test task is started, a power-on command is issued on the control interface of the single-board management module, and each host unit of the hardware architecture device is powered on according to the predetermined power-on sequence, such as SW is powered on first, then the NVME hard disk module is powered on, and finally the server host is powered on. The correct power-on sequence ensures that the initial state of the device will not be abnormal. After power-on is completed, SW needs to be configured, and one of the CDFP ports of SW connected to the CPU in the server is configured as an upstream X16 PCIE port, and the port of the NVME hard disk module is configured as a downstream ×4 PCIE port, and the downstream port is bound to the upstream port, so that the PCIE link configuration is completed. Depending on the usage scenario, the number of configurations of the upstream and downstream ports is different. Configuration information can be sent from the test unit.

[0156] After the configuration is completed, the hard disk performance test begins. Enter the CPU operating system (provided by the system hard disk in the test unit), issue a test command to execute the test script in the system hard disk to start the test. When the test is completed, the indicator light in the test unit will turn green, indicating that this round of testing is completed.

[0157] Optional based on Figure 5 The scene shown, continue as Figure 7 As shown, for multi-node scenarios, its application is as follows Figure 7, the PCIE of the CPU in the server is connected to the retimer card through a cable, the retimer card outputs a CDFP interface, which is connected to the SW through a cable, and the SW outputs a CDFP interface and is connected to the CDFP connector of the test unit through a cable. When a hard disk performance test task is started, a power-on command is issued on the control interface of the single board management module, and each host unit of the hardware architecture device is powered on according to the predetermined power-on sequence, such as SW is powered on first, then the NVME hard disk module is powered on, and finally the server host is powered on. The correct power-on sequence ensures that the initial state of the device will not be abnormal. After power-on is completed, SW needs to be configured, and one of the CDFP ports of SW connected to the CPU in the server is configured as an upstream X16 PCIE port, and the port connected to the NVME hard disk module is configured as a downstream x4 PCIE port, and the downstream port is bound to the upstream port, so that the PCIE link configuration is completed. Depending on the usage scenario, the number of configurations of the upstream and downstream ports is different. Configuration information can be sent from the test unit.

[0158] After the configuration is completed, the hard disk performance test begins. Enter the CPU operating system (provided by the system hard disk in the test unit), issue a test command to execute the test script in the system hard disk to start the test. When the test is completed, the indicator light in the test unit will turn green, indicating that this round of testing is completed.

[0159] Through the embodiment of the present application, for the hardware architecture server, by decoupling each functional module and realizing the pooling of memory resources, the flexibility is improved. In view of the fact that different application scenarios require different information to be configured, resulting in increased complexity of hard disk testing, the embodiment of the present application proposes an automated solution to simplify the hard disk performance testing process in the hardware architecture server.

[0160] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods of each embodiment of the present application.

[0161] In the present embodiment, a performance test device of a hardware architecture is also provided, and the device is used to implement the above-mentioned embodiment and preferred implementation mode, and the descriptions that have been made are not repeated here. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the device described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware is also possible and conceivable.

[0162] Figure 8 is a structural block diagram of a performance testing device according to the hardware architecture of an embodiment of the present application, such as Figure 8 As shown, the device comprises:

[0163] A first control unit 802 is used to control the hard disk test unit to perform a performance test task in response to a test start signal from the central processing unit, wherein the performance test task is a task of performing a hard disk performance test on a hardware architecture, and the hardware architecture includes a switching chip;

[0164] The transmission unit 804 is used to transmit the test data of the performance test task between the central processing unit and the hard disk test device through the configured PCIE link during the execution of the performance test task, wherein the PCIE link is configured by the switch chip through the configuration command issued by the central processing unit;

[0165] The output unit 806 is used to transmit the test data back to the central processing unit through the configured PCIE link when the performance test task is completed, and obtain the test result output by the central processing unit, wherein the test result is the hard disk performance test result of the hardware architecture.

[0166] For specific embodiments, reference may be made to the examples shown in the performance testing method for the above-mentioned hardware architecture, which will not be described in detail in this example.

[0167] As an optional solution, the first control unit 802 includes:

[0168] A first control module is used to control the hard disk test unit to execute the performance test task in a single-node scenario in response to the test start signal, wherein the single-node scenario is a test environment in which all test components are concentrated on one physical node or server, and all test components include a central processing unit, a hard disk test unit, and a switch chip; or

[0169] The second control module is used to control the hard disk test unit to execute the performance test task in a multi-node scenario in response to the test start signal, wherein the test components in all the test components are distributed in the test environment on multiple physical nodes or servers.

[0170] For specific embodiments, reference may be made to the examples shown in the performance testing method for the above-mentioned hardware architecture, which will not be described in detail in this example.

[0171] As an optional solution, the central processing unit is connected to the MCIO connector of the hard disk test unit through a configured PCIE link, and is further connected to the system hard disk. The hard disk test unit is connected to the central processing unit, the switching chip and the NVME hard disk through multiple interfaces. The device also includes:

[0172] A first power-on unit is used to power on the switch chip, the NVME hard disk, and the central processing unit in sequence before controlling the hard disk test unit to perform the performance test task in a single-node scenario in response to a test start signal, wherein the system hard disk is used to provide a test script for performing the performance test task, and the hard disk performance test result is a performance test result of the NVME hard disk;

[0173] The first configuration unit is used to configure the port connected to the central processing unit in the switching chip as an upstream PCIE port, and the port connected to the NVME hard disk as a downstream PCIE port, and bind the downstream PCIE port to the upstream PCIE port to complete the configuration of the PCIE link before controlling the hard disk test unit to perform the performance test task in the single-node scenario in response to the test start signal, so as to obtain the configured PCIE link;

[0174] The first control module includes: a first test submodule, which is used to issue a test command through the operating system provided by the system hard disk to execute the test script;

[0175] The device also includes: a second control unit for controlling the hard disk test unit to execute the performance test task in a single-node scenario in response to a test start signal, and then controlling the indicator light managed by the hard disk test unit to indicate the completion progress of the performance test task.

[0176] For specific embodiments, reference may be made to the examples shown in the performance testing method for the above-mentioned hardware architecture, which will not be described in detail in this example.

[0177] As an optional solution, the PCIE structure of the central processor is connected to the first signal enhancement device through a cable, connected to the above-mentioned switching chip through a CDFP interface at one end of the hard disk test unit, and connected to the system hard disk through the CDFP interface at the other end of the hard disk test unit. The device also includes:

[0178] A second power-on unit is used to power on the switch chip, the NVME hard disk, and the central processing unit in sequence before controlling the hard disk test unit to perform the performance test task in the multi-node scenario in response to the test start signal, wherein the system hard disk is used to provide a test script for performing the performance test task, a connection is established between the switch chip and the NVME hard disk through the second signal enhancement device, and the hard disk performance test result is the performance test result of the NVME hard disk;

[0179] The second configuration unit is used to configure the port connected to the central processing unit in the switching chip as an upstream PCIE port, and the port connected to the NVME hard disk as a downstream PCIE port, and bind the downstream PCIE port to the upstream PCIE port to complete the configuration of the PCIE link, and obtain the configured PCIE link before controlling the hard disk test unit to perform the performance test task in the multi-node scenario in response to the test start signal;

[0180] The second control module includes: a second test submodule, which is used to issue a test command through the operating system provided by the system hard disk to execute the test script;

[0181] The device also includes: a third control unit, which is used to control the indicator light managed by the hard disk test unit to indicate the completion progress of the performance test task after controlling the hard disk test unit to execute the performance test task in a multi-node scenario in response to a test start signal.

[0182] For specific embodiments, reference may be made to the examples shown in the performance testing method for the above-mentioned hardware architecture, which will not be described in detail in this example.

[0183] As an optional solution, the device also includes:

[0184] The switching unit is used to control the switching chip to implement the switching of the PCIE link in response to the test configuration command from the central processing unit before controlling the hard disk test unit to execute the performance test task in response to the test start signal from the central processing unit, so as to obtain the configured PCIE link, wherein the number of central processing units is set to allow expansion, the central processing unit is set in a server of the device cluster, the device cluster also includes a storage resource pool, the storage resource pool includes at least one hard disk module, and the hard disk performance test result is the performance test result of at least one hard disk module.

[0185] For specific embodiments, reference may be made to the examples shown in the performance testing method for the above-mentioned hardware architecture, which will not be described in detail in this example.

[0186] It should be noted that the above-mentioned virtual devices (modules, units, sub-modules, sub-units, components, etc.) can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above-mentioned virtual devices are all located in the same processor; or, the above-mentioned virtual devices are located in different processors in any combination.

[0187] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0188] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0189] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0190] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0191] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0192] Obviously, those skilled in the art should understand that the above-mentioned virtual devices or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0193] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A performance testing method for a hardware architecture, characterized in that: include: In response to a test start signal from a central processing unit, controlling the hard disk test unit to execute a performance test task, wherein the performance test task is a task of performing a hard disk performance test on a hardware architecture, and the hardware architecture includes a switching chip; During the execution of the performance test task, the test data of the performance test task is transmitted between the central processing unit and the hard disk test device through a configured PCIE link, wherein the PCIE link is configured by the switching chip through a configuration command issued by the central processing unit; When the performance test task is completed, the test data is transmitted back to the central processing unit through the configured PCIE link to obtain a test result output by the central processing unit, wherein the test result is a hard disk performance test result of the hardware architecture.

2. The method according to claim 1, characterized in that The method of controlling the hard disk test unit to execute a performance test task in response to a test start signal from the central processing unit includes: In response to the test start signal, the hard disk test unit is controlled to execute a performance test task in a single-node scenario, wherein the single-node scenario is a test environment in which all test components are concentrated on one physical node or server, and all the test components include the central processing unit, the hard disk test unit, and the switching chip; or, in response to the test start signal, the hard disk test unit is controlled to execute a performance test task in a multi-node scenario, wherein the test components among all the test components are distributed in a test environment on multiple physical nodes or servers.

3. The method according to claim 2, characterized in that The central processor is connected to the MCIO connector of the hard disk test unit through the configured PCIE link, and is further connected to the system hard disk. The hard disk test unit is respectively connected to the central processor, the switch chip and the NVME hard disk through multiple interfaces. Before responding to the test start signal and controlling the hard disk test unit to perform the performance test task in the single-node scenario, the method also includes: The switching chip, the NVME hard disk, and the central processing unit are powered on in sequence, wherein the system hard disk is used to provide a test script for the execution performance test task, and the hard disk performance test result is the NVME Hard disk performance test results; The port connected to the central processing unit in the switching chip is configured as an uplink PCIE port, and the port connected to the NVME hard disk is configured as a downlink PCIE port, and the downlink PCIE port is bound to the uplink PCIE port to complete the configuration of the PCIE link and obtain the configured PCIE link; The step of controlling the hard disk test unit to execute the performance test task in a single-node scenario in response to the test start signal includes: issuing a test command through the operating system provided by the system hard disk to execute the test script; After controlling the hard disk test unit to execute the performance test task in a single-node scenario in response to the test start signal, the method further includes: controlling an indicator light managed by the hard disk test unit to indicate the completion progress of the performance test task.

4. The method according to claim 2, characterized in that: The PCIE structure of the central processor is connected to the first signal enhancement device through a cable, connected to the above-mentioned switching chip through a CDFP interface at one end of the hard disk test unit, and connected to the system hard disk through the CDFP interface at the other end of the hard disk test unit. Before responding to the test start signal and controlling the hard disk test unit to perform the performance test task in the multi-node scenario, the method also includes: Power on the switching chip, the NVME hard disk, and the central processing unit in sequence, wherein the system hard disk is used to provide a test script for executing the performance test task, a connection is established between the switching chip and the NVME hard disk via a second signal enhancement device, and the hard disk performance test result is a performance test result of the NVME hard disk; The port connected to the central processing unit in the switching chip is configured as an uplink PCIE port, and the port connected to the NVME hard disk is configured as a downlink PCIE port, and the downlink PCIE port is bound to the uplink PCIE port to complete the configuration of the PCIE link and obtain the configured PCIE link; In response to the test start signal, controlling the hard disk test unit to execute the performance test task in the multi-node scenario includes: issuing a test command through the operating system provided by the system hard disk to execute the test script; After controlling the hard disk test unit to execute the performance test task in a multi-node scenario in response to the test start signal, the method further includes: controlling an indicator light managed by the hard disk test unit to indicate the completion progress of the performance test task.

5. The method according to claim 1, characterized in that Before controlling the hard disk test unit to execute the performance test task in response to the test start signal from the central processor, the method further includes: In response to a test configuration command from the central processing unit, the switching chip is controlled to implement switching of the PCIE link to obtain the configured PCIE link, wherein the number of the central processing units is set to allow expansion, the central processing unit is set in a server of a device cluster, the device cluster also includes a storage resource pool, the storage resource pool includes at least one hard disk module, and the hard disk performance test result is a performance test result of the at least one hard disk module.

6. The method according to claim 5, characterized in that The hard disk module comprises: Hard disk backplane, NVME hard disk.

7. The method according to any one of claims 1 to 6, characterized in that The hard disk testing device comprises: A power supply module, used to supply power to the hard disk testing device; The single board management module is used for the management of the mainboard status, the power supply management of the system hard disk, the interaction with the configuration information of the central processor, the distribution of the configuration information in the switching chip, and provides HDMI, network port and USB interface. The HDMI interface can realize display control, and the network port can realize the parallel management of multiple test devices to realize large-scale simultaneous testing. The system hard disk is used to provide the test script for the execution performance test task; The fan module is used to provide heat dissipation function for the hard disk testing device and is controlled by the single board management module. The single board management module collects information such as temperature sensing and hard disk temperature on the hard disk testing device and controls the fan speed in real time according to the speed regulation strategy.

8. A performance testing device for a hardware architecture, characterized in that: include: A first control unit, configured to control the hard disk test unit to execute a performance test task in response to a test start signal from the central processing unit, wherein the performance test task is a task of performing a hard disk performance test on a hardware architecture, and the hardware architecture includes a switching chip; A transmission unit, used for transmitting the test data of the performance test task between the central processing unit and the hard disk test device through a configured PCIE link during the execution of the performance test task, wherein the PCIE link is configured by the switching chip through a configuration command issued by the central processing unit; The output unit is used to output the configured PCIE The link transmits the test data back to the central processing unit to obtain a test result output by the central processing unit, wherein the test result is a hard disk performance test result of the hardware architecture.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 1 to 7 when executed by a processor.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method described in any one of claims 1 to 7 are implemented.

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