Test Program Generation Method, Device, Computer Equipment, and Readable Storage Medium

Abstract

The present application provides a test program generation method, apparatus, computer device, and readable storage medium, belonging to the technical field of software development. The test program generation method includes: obtaining a test requirement document of a target chip; parsing the test requirement document to obtain keyword information corresponding to the test requirement document; obtaining test requirement development model information based on a preset test development model and the keyword information; calling at least one artificial intelligence interface in a preset large language model according to the test requirement development model information to generate multiple test codes; and generating a target test program corresponding to the target chip according to the multiple test codes. The present application can achieve the effects of shortening the development cycle of the test program and improving the development efficiency of the test program.

Description

Technical Field

[0001] This application relates to the field of software development technologies, and more specifically, to a method, device, computer device, and readable storage medium for generating test programs. Background Art

[0002] In the field of test program development, the traditional test program development method mainly relies on programmers to manually write code, which is inefficient and error-prone. Therefore, there is an urgent need for an efficient program development method.

[0003] In related technologies, generally, chip test programs mainly rely on manual development by test engineers. After understanding the chip test specification manual, test engineers need to manually write test programs according to the requirements of the chip test specification manual to complete the development of chip test programs.

[0004] However, when developing chip test programs based on related technologies, there are problems such as a long development cycle and low development efficiency of test programs. Summary of the Invention

[0005] The purpose of this application is to provide a method, device, computer device, and readable storage medium for generating test programs, which can achieve the effect of shortening the development cycle of test programs and improving the development efficiency of test programs.

[0006] The embodiments of this application are implemented as follows:

[0007] In the first aspect of the embodiments of this application, a method for generating a test program is provided. The method includes:

[0008] Obtain a test requirement document of a target chip;

[0009] Analyze the test requirement document to obtain keyword information corresponding to the test requirement document;

[0010] Based on a preset test development model and the keyword information, obtain test requirement development model information;

[0011] According to the test requirement development model information, call at least one artificial intelligence interface in a preset large language model to generate multiple test codes;

[0012] Generate a target test program corresponding to the target chip according to the multiple test codes.

[0013] As a possible implementation, obtaining a test requirement document of a target chip includes:

[0014] In response to a trigger action of the user in the graphical user interface, import and obtain the test requirement document of the target chip to be tested. The test requirement document includes: the functions to be tested of the target chip and the test conditions of the target chip.

[0015] As a possible implementation, parse the test requirement document to obtain the keyword information corresponding to the test requirement document, including:

[0016] Parse the test requirement document according to the document rules corresponding to the test requirement document, and extract the keyword information corresponding to the test requirement document.

[0017] As a possible implementation, based on a preset test development model and the keyword information, obtain the test requirement development model information, including:

[0018] Fill the keyword information corresponding to the test requirement document into the preset test development model to obtain the test requirement development model information corresponding to the test requirement document. The test requirement development model information includes: the model number of the target chip, the test items of the target chip, the type of the test machine for the target chip, the normal power supply voltage of the target chip, the package type of the target chip, the clock frequency of the target chip, the clock waveform of the target chip, the test vectors of the target chip, and the circuit characteristics of the target chip.

[0019] As a possible implementation, according to the test requirement development model information, call at least one artificial intelligence interface in the preset large language model to generate multiple test codes, including:

[0020] According to the model number of the target chip, the type of the test machine for the target chip, the normal power supply voltage of the target chip, the package type of the target chip, and the circuit characteristics in the test requirement development model information, call the first type of artificial intelligence interface of the large language model, and obtain the first interface return information of the large language model;

[0021] Generate the first test code according to the first interface return information. The first test code includes: test configuration items, and the test configuration items include: basic configuration items, pin resource configuration items, pin configuration items, and binning result configuration items;

[0022] According to the test items of the target chip in the test requirement development model information, call the second type of artificial intelligence interface in the preset large language model, and obtain the second interface return information of the large language model;

[0023] Generate the second test code according to the second interface return information. The second test code includes: multiple functional test code segments, and each functional test code segment is used to test one or more chip functions;

[0024] Develop the clock frequency and clock waveform of the target chip in the model information according to the test requirements, call the third type of artificial intelligence interface in the preset large language model, and obtain the return information of the third interface of the large language model;

[0025] Generate the third test code according to the return information of the third interface. The third test code is used to test the clock frequency and waveform of the target chip;

[0026] Develop the test vector of the target chip in the model information according to the test requirements, call the fourth type of artificial intelligence interface in the preset large language model, and obtain the return information of the fourth interface of the large language model;

[0027] Generate the fourth test code according to the return information of the fourth interface. The fourth test code is used to run the test vector corresponding to the target chip.

[0028] As a possible implementation, generate the first test code according to the return information of the first interface, including:

[0029] Fill the first node information in the return information of the first interface into the first target node;

[0030] Fill the second node information in the return information of the first interface into the second target node;

[0031] Fill the third node information in the return information of the first interface into the third target node;

[0032] Fill the fourth node information in the return information of the first interface into the fourth target node;

[0033] Combine the first target node, the second target node, the third target node, and the fourth target node into the first test code.

[0034] As a possible implementation, generate the target test program corresponding to the target chip according to multiple test codes, including:

[0035] According to the test rules of the target chip, splice the first test code, the second test code, the third test code, and the fourth test code to obtain the target test program corresponding to the target chip.

[0036] In the second aspect of the embodiments of the present application, a test program generation device is provided. The test program generation device includes:

[0037] An acquisition module, configured to acquire a test requirement document of the target chip;

[0038] An analysis module, configured to analyze the test requirement document to obtain keyword information corresponding to the test requirement document;

[0039] A development module, configured to obtain test requirement development model information based on a preset test development model and keyword information;

[0040] A first generation module, configured to call at least one artificial intelligence interface in a preset large language model according to the test requirement development model information to generate multiple test codes;

[0041] A second generation module, configured to generate a target test program corresponding to a target chip according to the multiple test codes.

[0042] In a third aspect of the embodiments of the present application, a computer device is provided. The computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, the test program generation method described in the first aspect above is implemented.

[0043] In a fourth aspect of the embodiments of the present application, a computer-readable storage medium is provided. The computer-readable storage medium stores a computer program, and when the computer program is executed by the processor, the test program generation described in the first aspect above is implemented.

[0044] The beneficial effects of the embodiments of the present application include:

[0045] A test program generation method provided by the embodiments of the present application imports a test requirement document of a target chip edited by a user to obtain the test requirement document of the target chip; parses the test requirement document of the target chip, and extracts keyword information from the parsing result of the test requirement document; fills the keyword information corresponding to the test requirement document into a preset test development model to obtain test requirement development model information corresponding to the test requirement document; calls at least one artificial intelligence interface of a preset large language model according to the test requirement development model information, and the preset large language model generates corresponding multiple test codes based on the test requirement development model information received by each artificial intelligence interface; splices and arranges each test code according to the test rules of the target chip to obtain the test program of the target chip. In this way, it is not necessary for a test engineer to study the test specification of the target chip, nor is it necessary for the test engineer to manually code, which can achieve the effect of shortening the development cycle of the test program and improving the development efficiency of the test program. Description of the Drawings

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0047] Figure 1 Flow chart of the first test program generation method provided by the embodiment of the present application;

[0048] Figure 2 System block diagram of an analysis model provided by the embodiment of the present application;

[0049] Figure 3 Interface schematic diagram of a requirements development model provided by the embodiment of the present application;

[0050] Figure 4 Flow chart of the second test program generation method provided by the embodiment of the present application;

[0051] Figure 5 Flow chart of the third test program generation method provided by the embodiment of the present application;

[0052] Figure 6 Complete flow chart of the test program generation method provided by the embodiment of the present application;

[0053] Figure 7 Structural schematic diagram of a test program generation device provided by the embodiment of the present application;

[0054] Figure 8 Structural schematic diagram of a computer device provided by the embodiment of the present application. Detailed implementation manners

[0055] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Usually, the components of the embodiments of the present application described and illustrated herein can be arranged and designed in various different configurations.

[0056] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but merely represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0057] Currently, chip test programs mainly rely on manual development by test engineers. After studying the chip test specification manual, test engineers need to manually write test programs according to the requirements of the chip test specification manual to complete the development of chip test programs. However, this solution requires test engineers to spend a lot of effort studying the chip test specification manual and also requires a large number of engineers to manually code, resulting in a long development cycle for chip test programs and low development efficiency of chip test programs.

[0058] For this reason, the embodiments of the present application provide a test program generation method. The user edits a test requirement document for the target chip to be tested and imports the test requirement document of the target chip into the test program generation system through a graphical user interface. The parsing program in the test program generation system parses the test requirement document for the target chip and extracts keyword information from the parsing result of the test requirement document. The keyword information corresponding to the test requirement document is filled into the test requirement development model to obtain the test requirement development model information corresponding to the test requirement document. At least one artificial intelligence interface of a preset large language model is called based on the test requirement development model information. The preset large language model generates corresponding multiple test codes based on the test requirement development model information received by each artificial intelligence interface. Each test code is spliced according to the test rules of the target chip to be tested to obtain the test program of the target chip. In this way, it is not necessary for test engineers to study the chip test specification manual of the target chip, nor is it necessary for test engineers to manually code, which can greatly reduce the development cycle of the test program and improve the development efficiency of the test program.

[0059] The following will explain in detail the test program generation method provided by the embodiments of the present application with reference to the accompanying drawings.

[0060] Figure 1 The flowchart of a test program generation method provided by the present application, which can be applied to a computer device. See Figure 1 The embodiments of the present application provide a test program generation method, including:

[0061] S101. Obtain a test requirement document for the target chip.

[0062] Optionally, the target chip is used to indicate the chip that the user wants to test. The test requirement document for the target chip is a document edited by the tester according to the test requirements. The test requirement document is used to indicate the test case description of the target chip. According to the test requirement document for the target chip, the functions that the tester wants to test the target chip and the test basic information of the target chip can be determined.

[0063] S102. Parse the test requirement document to obtain the keyword information corresponding to the test requirement document.

[0064] Optionally, parse the test requirement document of the target chip, and extract the keyword information included in the parsing result of the test requirement document. The keyword information refers to the keywords related to the target chip test in the test requirement document, and the keyword information includes: the name of the target chip, the model of the target chip, the type of the test machine for testing the target chip, the pin resources of the target chip, the communication protocol of the target chip, the package type of the target chip, the clock frequency of the target chip, the clock waveform of the target chip, the test conditions of the target chip, etc. This application does not make specific limitations on this.

[0065] S103. Obtain the test requirement development model information based on the preset test development model and the keyword information.

[0066] Optionally, the preset test development model is a test development model pre-constructed by testers through multiple iterative trainings based on the test programs of a large number of test chips. Filling the keyword information corresponding to the test requirement document of the target chip into the preset test development model can obtain the test requirement development model information of the target chip. The test requirement development model information is used to indicate the basic information required for the development of the test program of the target chip. The preset test development model can be regarded as providing a test program development template for the test program development, and filling the keywords corresponding to the test requirement document into the corresponding positions in the preset test development model.

[0067] S104. According to the test requirement development model information, call at least one artificial intelligence interface in the preset large language model to generate multiple test codes.

[0068] Optionally, the preset large language model is implemented by the Chat GPT model. The preset large language model includes multiple AI interfaces, that is, multiple artificial intelligence interfaces. Call at least one AI interface in the Chat GPT model according to the type of each keyword information in the test requirement development model information. Each AI interface in the Chat GPT model is used to receive the test requirement development model information of the target chip. After the Chat GPT model receives the test requirement development model information, it generates multiple test codes. The test codes are used to indicate the program codes corresponding to the functions to be tested of the target chip.

[0069] It should be noted that the multiple test codes generated by the preset large language model are not related to each other. The preset large language model only outputs the corresponding program codes from each AI interface according to the test requirement development model information received by each AI interface.

[0070] S105. Generate the target test program corresponding to the target chip according to the multiple test codes.

[0071] Optionally, there are many types of test rules for IC chips. By combining multiple test codes according to the test rules of the target chip, the target test program applicable to the target chip can be obtained.

[0072] Optionally, the target test program is used to indicate a program that meets the test requirements specified by the tester, and the target test program can be applicable to the target chip specified by the tester.

[0073] In the embodiment of the present application, the test requirement document of the target chip edited by the user is imported to obtain the test requirement document of the target chip; the test requirement document of the target chip is parsed, and keyword information is extracted from the parsing result of the test requirement document; the keyword information corresponding to the test requirement document is filled into a preset test development model to obtain the test requirement development model information corresponding to the test requirement document; at least one artificial intelligence interface of a preset large language model is called according to the test requirement development model information, and the preset large language model generates corresponding multiple test codes based on the test requirement development model information received by each artificial intelligence interface; each test code is spliced and sorted according to the test rules of the target chip to obtain the test program of the target chip. In this way, it is not necessary for the test engineer to study the test specification of the target chip, nor is it necessary for the test engineer to manually code, which can achieve the effect of shortening the development cycle of the test program and improving the development efficiency of the test program.

[0074] In an optional implementation manner, the specific operation of the above step S101 may be:

[0075] In response to the triggering action of the user on the graphical user interface, import and obtain the test requirement document of the target chip to be tested. The test requirement document includes: the function to be tested of the target chip and the test conditions of the target chip.

[0076] Optionally, the target chip to be tested is used to indicate an IC chip that the user wants to test but has not yet tested. The test requirement document includes: the function to be tested of the target chip and the test conditions of the target chip. The function to be tested is used to indicate the performance of the target chip that the user wants to test. The function to be tested may be the circuit characteristics, pin resources, etc. of the target chip; the test conditions of the target chip correspond one-to-one with the function to be tested, and the test conditions are used to indicate the prerequisite conditions for the test operation of the function to be tested, such as the pin voltage of the target chip under high level, the pin voltage of the target chip under low level, etc. The present application does not make specific limitations on this.

[0077] Optionally, the graphical user interface is a development user interface developed based on winform. When the user clicks the "spec selection" button on the graphical user interface, the computer device starts to import the test requirement document of the target chip.

[0078] In an alternative embodiment, the specific operation of the above step S102 may be as follows:

[0079] Parse the test requirement document according to the document rules corresponding to the test requirement document, and extract the keyword information corresponding to the test requirement document.

[0080] Optionally, the document rules corresponding to the test requirement document are used to indicate the document editing format of the test requirement document. The document rules of the test requirement document may be in pdf format, word document, picture, etc., and the present application does not make specific limitations thereto.

[0081] Optionally, according to the document rules corresponding to the test requirement document, different parsing models are called. When the document rules corresponding to the test requirement document select an adapted parsing model to parse the test requirement document, keyword information is extracted from the test document.

[0082] Figure 2 For the system block diagram of a parsing model provided by the present application, see Figure 2 , and the parsing model can parse the test requirement document of the target chip from multiple perspectives. Figure 2 As an example, it mainly parses from five perspectives: test items, pins, package types, communication protocols, and clock waveforms, that is, the parsing model divides the test requirement document of the target chip into five parts.

[0083] In an alternative embodiment, the specific operation of the above step S103 may be as follows:

[0084] Fill the keyword information corresponding to the test requirement document into a preset test development model to obtain the test requirement development model information corresponding to the test requirement document. The test requirement development model information includes: the model of the target chip, the test items of the target chip, the type of the test machine for the target chip, the normal power voltage of the target chip, the package type of the target chip, the clock frequency of the target chip, the clock waveform of the target chip, the test vector of the target chip, and the circuit characteristics of the target chip.

[0085] Optionally, by filling the keyword information corresponding to the test requirement document into a preset test development model, the test requirement development model information corresponding to the test requirement document can be obtained. Among them, the model of the target chip is used to indicate the production specifications of the target chip, the test items of the target chip are used to indicate the functions to be tested of the target chip, the type of test machine for the target chip is used to indicate the type of the test machine for testing the target chip, the normal power supply voltage of the target chip is used to indicate the pin voltage of the target chip, the package type of the target chip is used to indicate the pin package type of the target chip, the clock frequency of the target chip is used to indicate the clock frequency to be tested of the target chip, the clock waveform of the target chip is used to indicate the rising edge, falling edge and period of the clock frequency of the target chip, the test vector of the target chip is used to indicate the pin level of the target chip, and the circuit characteristics of the target chip are used to indicate the open circuit characteristics, short circuit characteristics, open circuit characteristics, leakage characteristics and normal operating range, etc. of the target chip.

[0086] Figure 3 The following is a schematic diagram of the interface of a requirement development model provided by this application. Refer to Figure 3 The interface of a requirement development model information provided by an embodiment of this application mainly includes: product model, FT / CP, machine type, normal power supply voltage, clk clock frequency, waveform, circuit characteristics OS (force voltage, clamping current, maximum effective current and minimum effective current), test vector scan pattern and multiple test items. Among them, the product model is used to indicate the model of the target chip, FT is used to indicate the package test of the target chip, CP is used to indicate the wafer test of the target chip, the machine type is used to indicate the type of the machine for executing the test program to test the target chip, the normal power supply voltage is used to indicate the voltage for testing each pin when the target chip is running normally, the clock frequency is used to indicate the clock frequency of the target chip, the waveform is used to indicate the rising edge, falling edge and clock period of the clock waveform of the target chip, the circuit characteristics are used to indicate the open circuit, short circuit, leakage, etc. of the test target chip, and the test item is used to indicate the test function of the target chip.

[0087] In an optional implementation manner, refer to Figure 4 The specific operation of the above step S104 can be:

[0088] S401. According to the model of the target chip, the type of test machine for the target chip, the normal power supply voltage of the target chip, the package type of the target chip and the circuit characteristics in the test requirement development model information, call the first type of artificial intelligence interface of the large language model and obtain the first interface return information of the large language model.

[0089] Optionally, the first type of artificial intelligence interface is used to indicate the set of AI interfaces called by the Chat GPT model to receive the model information of the target chip's model, the type of test machine for the target chip, the normal power voltage of the target chip, the package type of the target chip, and the circuit characteristics of the target chip in the test requirement development model information. The first interface feedback information is composed of a large number of strings. After the first type of artificial intelligence interface of the Chat GPT model receives the test requirement development model information, it generates the first interface feedback information, which is used to characterize the test basic configuration information of the target chip.

[0090] S402. Generate the first test code according to the first interface feedback information. The first test code includes: test configuration items, and the test configuration items include: basic configuration items, pin resource configuration items, pin configuration items, and binning result configuration items.

[0091] Optionally, the basic configuration item is used to indicate the test summary information of the target chip. The test summary information includes the pin definition of the target chip, the clock definition of the target chip, the name of the target chip, etc. The pin resource configuration item is used to indicate the connection relationship between each pin of the target chip and the pins of the test machine. The pin configuration is used to indicate the set of pins included in the target chip; the binning result configuration item is used to indicate the binning of the test results of the target chip.

[0092] Optionally, extract the test summary information of the target chip, the pin resource information of the target chip, the set of pins of the target chip, and the test result binning information of the target chip from the first interface feedback information, and generate the basic configuration item, the pin resource configuration item, the pin configuration item, and the binning result configuration item respectively according to these information. The test configuration item is used to indicate the definition of the basic configuration information of the target chip.

[0093] S403. According to the test items of the target chip in the test requirement development model information, call the second type of artificial intelligence interface in the preset large language model, and obtain the second interface feedback information of the large language model.

[0094] Optionally, the second type of artificial intelligence interface is used to indicate the set of AI interfaces called by the Chat GPT model to receive the test items of the target chip in the test requirement development model information. The second interface feedback information is composed of a large number of strings. After the second type of artificial intelligence interface of the Chat GPT model receives the test requirement development model information, it generates the second interface feedback information, which is used to characterize the functions to be tested of the target chip.

[0095] S404. Generate the second test code according to the second interface feedback information. The second test code includes: multiple functional test code segments, and each functional test code segment is used to test one or more chip functions.

[0096] Optionally, extract the test code related to the function to be tested of the target chip from the information returned from the second interface to obtain the second test code, where the second test code can be implemented by a.prg file.

[0097] S405. Develop the clock frequency and clock waveform of the target chip in the model information according to the test requirements, call the third type of artificial intelligence interface in the preset large language model, and obtain the information returned by the third interface of the large language model.

[0098] Optionally, the third type of artificial intelligence interface is used to indicate the set of AI interfaces called by the Chat GPT model to receive the clock frequency and clock waveform of the target chip in the test requirement development model information. The information returned by the third interface consists of a large number of strings. After the third type of artificial intelligence interface of the Chat GPT model receives the test requirement development model information, it generates the information returned by the third interface, and the information returned by the third interface is used to characterize the clock signal to be tested of the target chip.

[0099] S406. Generate the third test code according to the information returned by the third interface, and the third test code is used to test the clock frequency and waveform of the target chip.

[0100] Optionally, extract the test code related to the clock frequency and clock waveform of the target chip from the information returned by the third interface to obtain the third test code, where the third test code can be implemented by a.tim file.

[0101] Exemplarily, a third test code is as follows:

[0102] @@TIMING_DEFINE

[0103] @@GROUP_1

[0104] @@AC_SET_1

[0105] [NAME=TIM_138]

[0106] [TS]

[0107] PERIOD=200T

[0108] ALLPINS:{DRV_RS=50T}

[0109] {DRV_FL=150T}

[0110] {STB_RS=180T}

[0111] [END_TS]

[0112] [FMT]

[0113] ALLPINS: {DRV_FMT = NRZ}

[0114] [END_FMT]

[0115] @@END_AC_SET_1

[0116] @@END_GROUNP_1

[0117] @@END_TIMING_DEFINE

[0118] S407. Develop test vectors for the target chip in the model information according to the test requirements, call the fourth type of artificial intelligence interface in the preset large language model, and obtain the fourth interface return information of the large language model.

[0119] Optionally, the fourth type of artificial intelligence interface is used to indicate the set of AI interfaces called by the Chat GPT model to receive the test vectors of the target chip in the test requirement development model information. The fourth interface return information is composed of a large number of strings. After the fourth type of artificial intelligence interface of the Chat GPT model receives the test requirement development model information, it generates the fourth interface return information, and the fourth interface return information is used to characterize the test level of the target chip.

[0120] S408. Generate the fourth test code according to the fourth interface return information, and the fourth test code is used to run the test vectors corresponding to the target chip.

[0121] Optionally, extract the test code related to the test vectors of the target chip from the fourth interface return information to obtain the fourth test code, where the fourth test code can be implemented by a.sd file.

[0122] Exemplarily, a fourth test code containing only one test vector is as follows:

[0123]

[0124] In an alternative implementation, referring to Figure 5 , the specific operation of the above step S402 can be:

[0125] S501. Fill the first node information in the first interface return information into the first target node.

[0126] Optionally, the first target node can be implemented by the @@START_UP_TABLE node, and the first node information is used to indicate the summary information of the test program.

[0127] Exemplarily, the first node information may be as follows: TEST_DIE = 1 indicates the number of Sites for combined testing, and the numbers 1, 2, 3... correspond to the number of Sites; Program_Name = Plan.prg indicates that the test item execution file is Plan.prg, PATTERN_HEAD = PIN_HEAD.hed indicates in which file the Patten pin definition is located, TIMING_NAME = DIE_TIM.tim indicates in which file the pin clock definition is located, SYTEM_CLK = 200MHz indicates that the tester clock is 200MHz, DEV_NAME = SN73S138 indicates the product name of the IC, DVC_PINCOUNT = 768 indicates the maximum number of pins supported by the tester, and CSV_FILE_OUTPUT = ON indicates that the switch for outputting test data to the CSV file is turned on.

[0128] S502. Fill the second node information in the first interface feedback information into the second target node.

[0129] Optionally, the second target node may be implemented by the @@PIN_DEFINE_TABLE node, and the second node information is used to indicate the pin resource information of the target chip.

[0130] Exemplarily, A, io, 1, 1 defines the IC pin A as an input / output pin, with a logic number of 1, connected to the physical pin 1 of the tester; VCC_DPS PWR 1001LOGIC_DPS1: The IC pin VCC_DPS, with a logic number of 1001, is connected to the LOGIC_DPS1 power pin of the tester.

[0131] S503. Fill the third node information in the first interface feedback information into the third target node.

[0132] Optionally, the third target node may be implemented by the @@PIN_GROUP_TABLE node, and the third node information is used to indicate the pin set of the target chip.

[0133] Exemplarily, INPINS, ["1-6"] is used to represent the pin set with logic numbers from 1 to 6.

[0134] S504. Fill the fourth node information in the first interface feedback information into the fourth target node.

[0135] Optionally, the fourth target node may be implemented by the @@BIN_MAP node, and the fourth node information is used to indicate the binning result information of the target chip.

[0136] Exemplarily, for the test result of 1, i.e., 1, 0x00000001, 1, 0, it is binned into bin 1; for the test result of 2, i.e., 2, 0x00000002, 0, 1, it is binned into bin 2.

[0137] S505. Combine the first target node, the second target node, the third target node, and the fourth target node into the first test code.

[0138] In an alternative implementation, the operation of the above step S105 can specifically be:

[0139] According to the test rules of the target chip, splice the first test code, the second test code, the third test code, and the fourth test code to obtain the target test program corresponding to the target chip.

[0140] Optionally, the test rules of the target chip are used to indicate the inertia of the target chip to run the test program. After sorting and splicing the first test code, the second test code, the third test code, and the fourth test code according to the test rules of the target chip, the target test program that can run on the target chip is obtained.

[0141] Figure 6 For the complete flowchart of the test program generation method provided by this application, see Figure 6 , the specific implementation process of the test program generation method provided by the embodiments of this application is as follows: S1. The user edits the test requirement document of the target chip to be tested and imports the test requirement document of the target chip into the test program generation system through the graphical user interface; S2. The test program generation system calls the corresponding mechanical program according to the document rules corresponding to the test requirement document of the target chip to parse the test requirement document of the target chip, and extracts keyword information from the parsing result of the test requirement document;

[0142] S3. Fill the keyword information corresponding to the test requirement document into the test requirement development model to obtain the test requirement development model information corresponding to the test requirement document; S4. Call multiple artificial intelligence interfaces of the preset large language model based on the test requirement development model information; S5. The preset large language model generates corresponding multiple test codes based on the test requirement development model information received by each artificial intelligence interface; S6. Sort and splice each test code according to the test rules of the target chip to be tested to obtain the test program of the target chip.

[0143] The following describes the device, equipment, computer-readable storage medium, etc. for executing the test program generation method provided by this application. For the specific implementation process and technical effects, see the above, and details will not be repeated below.

[0144] Figure 7It is a schematic structural diagram of a test program generation device provided by this application. Refer to Figure 7 , the device includes:

[0145] An acquisition module 701, configured to acquire a test requirement document of a target chip;

[0146] An analysis module 702, configured to analyze the test requirement document to obtain keyword information corresponding to the test requirement document;

[0147] A development module 703, configured to obtain test requirement development model information based on a preset test development model and the keyword information;

[0148] A first generation module 704, configured to call at least one artificial intelligence interface in a preset large language model according to the test requirement development model information to generate multiple test codes;

[0149] A second generation module 705, configured to generate a target test program corresponding to the target chip according to the multiple test codes.

[0150] In a possible implementation manner, the above-mentioned acquisition module 701 is specifically configured to:

[0151] Respond to a triggering action of a user on a graphical user interface, import and acquire a test requirement document of a target chip to be tested, where the test requirement document includes: the function to be tested of the target chip and the test conditions of the target chip.

[0152] In a possible implementation manner, the above-mentioned analysis module 702 is specifically configured to:

[0153] Analyze the test requirement document according to the document rules corresponding to the test requirement document, and extract the keyword information corresponding to the test requirement document.

[0154] In a possible implementation manner, the above-mentioned development module 703 is specifically configured to:

[0155] Fill the keyword information corresponding to the test requirement document into a preset test development model to obtain test requirement development model information corresponding to the test requirement document. The test requirement development model information includes: the model of the target chip, the test items of the target chip, the type of the test machine platform of the target chip, the normal power voltage of the target chip, the package type of the target chip, the clock frequency of the target chip, the clock waveform of the target chip, the test vector of the target chip, and the circuit characteristics of the target chip.

[0156] In a possible implementation manner, the above-mentioned first generation module 704 is specifically configured to:

[0157] According to the model information developed based on the test requirements, including the model number of the target chip, the type of test machine for the target chip, the normal power supply voltage of the target chip, the package type of the target chip, and the circuit characteristics of the target chip, call the first type of artificial intelligence interface of the large language model and obtain the information returned by the first interface of the large language model;

[0158] Generate the first test code based on the information returned by the first interface. The first test code includes test configuration items, and the test configuration items include: chip model configuration item, machine type configuration item, voltage configuration item, package type configuration item, and circuit characteristic configuration item;

[0159] According to the test items of the target chip in the model information developed based on the test requirements, call the second type of artificial intelligence interface in the preset large language model and obtain the information returned by the second interface of the large language model;

[0160] Generate the second test code based on the information returned by the second interface. The second test code includes multiple functional test code segments, and each functional test code segment is used to test one or more chip functions;

[0161] According to the clock frequency and clock waveform of the target chip in the model information developed based on the test requirements, call the third type of artificial intelligence interface in the preset large language model and obtain the information returned by the third interface of the large language model;

[0162] Generate the third test code based on the information returned by the third interface. The third test code is used to test the clock frequency and waveform of the target chip;

[0163] According to the test vector of the target chip in the model information developed based on the test requirements, call the fourth type of artificial intelligence interface in the preset large language model and obtain the information returned by the fourth interface of the large language model;

[0164] Generate the fourth test code based on the information returned by the fourth interface. The fourth test code is used to run the test vector corresponding to the target chip.

[0165] In a possible implementation manner, the above-mentioned first generation module 704 is specifically further configured to:

[0166] Fill the first node information in the information returned by the first interface into the first target node;

[0167] Fill the second node information in the information returned by the first interface into the second target node;

[0168] Fill the third node information in the information returned by the first interface into the third target node;

[0169] Fill the fourth node information in the information returned by the first interface into the fourth target node;

[0170] Combine the first target node, the second target node, the third target node, and the fourth target node into a first test code.

[0171] In a possible implementation manner, the second generation module 705 is specifically configured to:

[0172] According to the test rules of the target chip, splice the first test code, the second test code, the third test code, and the fourth test code to obtain a target test program corresponding to the target chip.

[0173] The above device is used to execute the method provided in the foregoing embodiment, and its implementation principle and technical effects are similar, which will not be elaborated here.

[0174] The above modules may be one or more integrated circuits configured to implement the above method. For example: one or more application specific integrated circuits (ASICs), or, one or more microprocessors, or, one or more field programmable gate arrays (FPGAs), etc. Again, when a certain module above is implemented in the form of a processing element scheduling program code, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processors that can call program code. Again, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0175] Figure 8 It is a schematic structural diagram of a computer device provided by the present application. Refer to Figure 8 , the computer device includes: a memory 801 and a processor 802. A computer program that can run on the processor 802 is stored in the memory 801. When the processor 802 executes the computer program, the steps in any of the above method embodiments are implemented.

[0176] The embodiment of the present application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments can be implemented.

[0177] Optionally, the present application also provides a program product, such as a computer-readable storage medium, including a program, which is used to execute any of the above test program generation method embodiments when executed by a processor.

[0178] In several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections between each other can be through some interfaces. The indirect couplings or communication connections of devices or units can be in electrical, mechanical or other forms.

[0179] The units described as separate components may or may not be physically separated. The components shown as units may or may not be physical units, that is, they can be located in one place, or they can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0180] In addition, each functional unit in various embodiments of the present invention can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above-mentioned integrated units can be implemented in the form of hardware, or in the form of hardware plus software functional units.

[0181] The above-mentioned integrated units implemented in the form of software functional units can be stored in a computer-readable storage medium. The above-mentioned software functional units stored in a storage medium include several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor (English: processor) to execute some steps of the methods in various embodiments of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (English: Read-Only Memory, abbreviated as: ROM), random access memories (English: Random Access Memory, abbreviated as: RAM), magnetic disks or optical discs that can store program codes.

[0182] The above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in this application, and all should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

[0183] The above are only the preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A test program generation method, characterized in that, The method includes: Obtain the test requirement document of the target chip; Parse the test requirement document to obtain the keyword information corresponding to the test requirement document; Based on a preset test development model and the keyword information, obtain test requirement development model information, where the test requirement development model information includes: the model of the target chip, the test items of the target chip, the type of test machine for the target chip, the normal power supply voltage of the target chip, the package type of the target chip, the clock frequency of the target chip, the clock waveform of the target chip, the test vectors of the target chip, and the circuit characteristics of the target chip; According to the test requirement development model information, call at least one artificial intelligence interface in a preset large language model to generate multiple test codes; Generate a target test program corresponding to the target chip according to the multiple test codes; The step of, according to the test requirement development model information, calling at least one artificial intelligence interface in a preset large language model to generate multiple test codes includes: According to the model of the target chip, the type of test machine for the target chip, the normal power supply voltage of the target chip, the package type of the target chip, and the circuit characteristics in the test requirement development model information, call the first type of artificial intelligence interface of the large language model and obtain the first interface return information of the large language model; Generate a first test code according to the first interface return information, where the first test code includes: test configuration items, and the test configuration items include: basic configuration items, pin resource configuration items, pin configuration items, and binning result configuration items; According to the test items of the target chip in the test requirement development model information, call the second type of artificial intelligence interface in the preset large language model and obtain the second interface return information of the large language model; Generate a second test code according to the second interface return information, where the second test code includes: multiple functional test code segments, and each functional test code segment is used to test one or more chip functions; According to the clock frequency and the clock waveform of the target chip in the test requirement development model information, call the third type of artificial intelligence interface in the preset large language model and obtain the third interface return information of the large language model; Generate a third test code according to the third interface return information, and the third test code is used to test the clock frequency and waveform of the target chip; According to the test vectors of the target chip in the test requirement development model information, call the fourth type of artificial intelligence interface in the preset large language model and obtain the fourth interface return information of the large language model; Generate a fourth test code according to the fourth interface return information, and the fourth test code is used to run the test vectors corresponding to the target chip.

2. The method for generating a test program according to claim 1, wherein The step of obtaining the test requirement document of the target chip includes: In response to a trigger action of the user in the graphical user interface, import and obtain the test requirement document of the target chip to be tested, where the test requirement document includes: the functions to be tested of the target chip and the test conditions of the target chip.

3. The method for generating a test program according to claim 1, wherein Parsing the test requirement document to obtain keyword information corresponding to the test requirement document, including: Parsing the test requirement document according to the document rules corresponding to the test requirement document, and extracting keyword information corresponding to the test requirement document.

4. The test program generation method according to claim 1, wherein Based on a preset test development model and the keyword information, obtaining test requirement development model information, including: Filling the keyword information corresponding to the test requirement document into a preset test development model to obtain test requirement development model information corresponding to the test requirement document.

5. The method for generating a test program according to claim 1, wherein Generating a first test code according to the first interface return information, including: Filling the first node information in the first interface return information into a first target node; Filling the second node information in the first interface return information into a second target node; Filling the third node information in the first interface return information into a third target node; Filling the fourth node information in the first interface return information into a fourth target node; Combining the first target node, the second target node, the third target node, and the fourth target node into the first test code.

6. The method for generating a test program according to claim 1, wherein Generating a target test program corresponding to the target chip according to the multiple test codes, including: According to the test rules of the target chip, splicing the first test code, the second test code, the third test code, and the fourth test code to obtain a target test program corresponding to the target chip.

7. A test program generation device, characterized in that The device includes: An acquisition module, configured to acquire a test requirement document of a target chip; An analysis module, configured to analyze the test requirement document to obtain keyword information corresponding to the test requirement document; A development module, configured to obtain test requirement development model information based on a preset test development model and the keyword information, where the test requirement development model information includes: the model of the target chip, the test items of the target chip, the type of the test machine for the target chip, the normal power supply voltage of the target chip, the package type of the target chip, the clock frequency of the target chip, the clock waveform of the target chip, the test vector of the target chip, and the circuit characteristics of the target chip; A first generation module, configured to call at least one artificial intelligence interface in a preset large language model to generate multiple test codes according to the test requirement development model information; A second generation module, configured to generate a target test program corresponding to the target chip according to the multiple test codes; The first generation module is specifically configured to: according to the model number of the target chip, the type of the test machine for the target chip, the normal power supply voltage of the target chip, the package type of the target chip, and the circuit characteristics of the target chip in the test requirement development model information, call the first type of artificial intelligence interface of the large language model, and obtain the first interface return information of the large language model; according to the first interface return information, generate the first test code, and the first test code includes: test configuration items, and the test configuration items include: basic configuration items, pin resource configuration items, pin configuration items, and binning result configuration items; according to the test items of the target chip in the test requirement development model information, call the second type of artificial intelligence interface in the preset large language model, and obtain the second interface return information of the large language model; according to the second interface return information, generate the second test code, and the second test code includes: a plurality of functional test code segments, and each functional test code segment is respectively used to test one or more chip functions; according to the clock frequency and the clock waveform of the target chip in the test requirement development model information, call the third type of artificial intelligence interface in the preset large language model, and obtain the third interface return information of the large language model; according to the third interface return information, generate the third test code, and the third test code is used to test the clock frequency and waveform of the target chip; according to the test vector of the target chip in the test requirement development model information, call the fourth type of artificial intelligence interface in the preset large language model, and obtain the fourth interface return information of the large language model; according to the fourth interface return information, generate the fourth test code, and the fourth test code is used to run the test vector corresponding to the target chip.

8. A computer device, characterized in that, Comprising: A memory and a processor, wherein the memory stores a computer program that can be run on the processor, and when the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 above are implemented.

9. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is executed by the processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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