Method, device and program product for determining logical block address access sequence

Abstract

The embodiment of the present application provides a method and device and program product for determining a logical block address access sequence, wherein the method comprises: collecting an access sequence set of a logical block address from the solid-state storage device; determining M target logical block areas from N logical block areas using the access sequence set; constructing a logical block adjacency matrix of the M target logical block areas, wherein the logical block adjacency matrix is ​​used to represent the transfer frequency between the M target logical block areas; and determining H target logical block access sequences based on the logical block adjacency matrix. Through the present application, the problem of sparse distribution and poor regularity of LBA sequence data in the related art, which leads to an increase in the training complexity of the pre-reading model, is solved, so as to effectively improve the reading performance of the solid-state storage device and enable the pre-reading model to more accurately predict and pre-fetch data.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of computers, and in particular, to a method and device for determining a logical block address access sequence, and a program product. Background Art

[0002] In order to improve the read and write speed of storage devices, solid-state storage devices have developed rapidly in recent years. For example, solid-state drives (SSDs) are non-volatile storage devices based on NAND. Currently, SSDs are mainly used in mobile devices and servers.

[0003] When using SSDs in mobile devices, a pre-read operation is generally adopted. That is, after accessing a certain logical block address (LogicBlock Address, referred to as LBA), the system reads the LBA adjacent to the LBA to meet subsequent read and write operations. However, the LBA sequence data in related technologies is sparsely distributed and has poor regularity, which brings about the problems of high resource usage and high complexity in the establishment and training of pre-read models. Summary of the invention

[0004] The embodiments of the present application provide a method, device, and program product for determining a logical block address access sequence, so as to at least solve the problem in the related art that LBA sequence data is sparsely distributed and has poor regularity, which increases the training complexity of the pre-reading model.

[0005] According to one embodiment of the present application, a method for determining a logical block address access sequence is provided, which is applied to a data processing device, wherein the data processing device is deployed in a solid-state storage device and connected to a pre-reading device in the solid-state storage device, and the method comprises: collecting an access sequence set of a logical block address from the solid-state storage device, wherein the access sequence set comprises a plurality of access sequences, and the access sequence is a time sequence of performing access operations in the order of N logical block areas included in the solid-state storage device, wherein N is a natural number greater than 1; using the access sequence set to determine M target logical block areas from the N logical block areas, wherein the M target logical block areas The target logic block areas are all areas where the data access frequency is greater than the preset access frequency, and M is a natural number less than or equal to N; constructing a logic block adjacency matrix of the M target logic block areas, wherein the logic block adjacency matrix is ​​used to represent the transfer frequency between the M target logic block areas; determining H target logic block access sequences based on the logic block adjacency matrix, wherein the H target logic block access sequences are used to train a pre-reading model, and the pre-reading model is used to output the logic block area to be accessed during the process of performing the access operation on the solid-state storage device, and H is a natural number greater than or equal to M, and the pre-reading model is set in the pre-reading device.

[0006] In an exemplary embodiment, the access sequence set is used to determine M target logical block areas from a plurality of the logical block areas, including: dividing the logical block space in the solid-state storage device into N logical block areas according to a preset length; determining the frequency of each logical block access sequence from the access sequence set to obtain N access frequencies; sorting the N logical block areas according to the N access frequencies; and selecting M target logical block areas from the sorted N logical block areas, wherein the sum of the M frequencies of the M target logical block areas is greater than a first preset threshold.

[0007] In an exemplary embodiment, the frequency of each of the logical block access sequences is determined from the access sequence set to obtain N access frequencies, including: traversing the access sequence set to calculate the number of times the access data corresponding to each of the access sequences falls into each of the logical block areas within a preset time period; using the number of times the access data corresponding to each of the access sequences falls into each of the logical block areas and the preset time period, calculating the frequency of each of the logical block access sequences to obtain N access frequencies.

[0008] In an exemplary embodiment, a logical block adjacency matrix of M target logical block areas is constructed, including: determining the logical block addresses of the M target logical block areas to obtain L1 logical block addresses; determining the logical block address increments between the M target logical block areas to obtain L2 logical block address increments, wherein the logical block address increments are used to represent the increased values ​​between the M target logical block areas; using the L1 logical block addresses and the L2 logical block address increments to construct the logical block adjacency matrix, wherein the element values ​​in the logical block adjacency matrix are used to represent the transfer frequency between adjacent access sequences.

[0009] In an exemplary embodiment, determining the logical block address increments between M target logical block areas to obtain L2 logical block address increments includes: determining the access sequences in the M target logical block areas from the access sequence set to obtain P access sequences, wherein P is a natural number greater than 1; performing interval differential operations on the P access sequences respectively to capture the sequence characteristics of the P access sequences in the M target logical block areas to obtain differential access sequences; performing incremental statistics on the differential access sequences to calculate the frequency of each incremental value in the differential access sequences; determining an incremental value having a frequency greater than a preset frequency from the frequency of each incremental value to obtain a target incremental value; and determining the logical block address increment corresponding to the target incremental value as L2 logical block address increments.

[0010] In an exemplary embodiment, determining the logical block addresses of the M target logical block areas to obtain L1 logical block addresses includes: calculating the number of logical block addresses of each target logical block area by the following formula to obtain L1 logical block addresses: , wherein the The number of logical block addresses used to represent the target logical block area, A value used to represent the logical block address of the current row in the target logical block area, A numerical value used to represent the logical block increment of the current column in the target logical block area.

[0011] In an exemplary embodiment, the logic block adjacency matrix is ​​constructed using L1 logic block addresses and L2 logic block address increments, including: initializing an original adjacency matrix, wherein the original adjacency matrix is ​​an L1×L2 matrix; determining the next logic block address pointed to by each logic block address based on the L1 logic block addresses and L2 logic block address increments, wherein the rows in the original adjacency matrix are used to represent the current logic block address, and the columns in the original adjacency matrix are used to represent the next logic block address; transferring each logic block address to the frequency of each logic block address increment, and determining the frequency as the element value in the original adjacency matrix, to obtain the logic block adjacency matrix, wherein the rows in the logic block adjacency matrix are used to represent the logic block address, and the columns in the logic block adjacency matrix are used to represent the logic block address increment.

[0012] In an exemplary embodiment, after constructing the logic block adjacency matrix using L1 logic block addresses and L2 logic block address increments, the method further includes: determining the logic block addresses where transfer occurs in the M target logic block areas from the access sequence set to obtain M groups of transfer logic block addresses; counting the frequencies in the M groups of transfer logic block addresses, wherein the frequencies are used to represent the number of times the state transfer occurs in the transfer logic block address; sorting the multiple frequencies in a preset order, and calculating the ratio between two adjacent maximum frequencies from the sorted frequencies to obtain a frequency ratio; when the frequency ratio is greater than a preset threshold, determining the logic block address corresponding to the frequency ratio as the target transfer logic block address, wherein the target transfer logic block address is the logic block address to be transferred in the M groups of transfer logic block addresses.

[0013] In an exemplary embodiment, H target logic block access sequences are determined based on the logic block adjacency matrix, including: storing the current access sequence and the corresponding target access sequence in a table to obtain M tables, wherein one access sequence corresponds to one table, and the table includes the logic block address of the current access sequence and the logic block address of the target access sequence; constructing a logic block path dictionary using the M tables; and determining H target logic block access sequences based on the logic block path dictionary.

[0014] In an exemplary embodiment, constructing a logic block path dictionary using M tables includes: creating M instances of the table to obtain M instances; and constructing path relationships between the M instances to obtain the logic block path dictionary.

[0015] In an exemplary embodiment, H target logical block access sequences are determined based on the logical block path dictionary, including: determining a starting logical block address from the logical block path dictionary, wherein the starting logical block address is a target access sequence in a valid state in the logical block path dictionary; querying a first logical block address from the logical block path dictionary according to a first query direction, wherein the first query direction is a direction at a time before the starting logical block address; querying a second logical block address from the logical block path dictionary according to a second query direction, wherein the second query direction is a direction at a time after the starting logical block address; and determining H target logical block access sequences using the first logical block address, the starting logical block address, and the second logical block address.

[0016] In an exemplary embodiment, the first logical block address, the starting logical block address and the second logical block address are used to determine H target logical block access sequences, including: when the logical block address before the first logical block address is an invalid logical block address, and the logical block address after the second logical block address is the invalid logical block address, a logical block address path is constructed according to the time sequence between the first logical block address, the starting logical block address and the second logical block address; and the access path included in the logical block address path is determined as the H target logical block access paths.

[0017] In an exemplary embodiment, after determining H target logical block access sequences using the first logical block address, the starting logical block address and the second logical block address, the method further includes: deleting the logical block addresses corresponding to the H target logical block access sequences in the logical block path dictionary; or, setting the logical block addresses corresponding to the H target logical block access sequences to an invalid state in the logical block path dictionary.

[0018] In an exemplary embodiment, after determining H target logic block access sequences based on the logic block adjacency matrix, the method further includes: using the H target logic block access sequences to train an initial pre-reading model to obtain the pre-reading model, wherein the initial pre-reading model includes a fusion subnetwork and a classification subnetwork, and for each group of the H target logic block access sequences, the fusion subnetwork is used to fuse sequence features in the H target logic block access sequences, and the classification subnetwork is used to classify and identify logic block areas based on the fused sequence features.

[0019] According to another embodiment of the present application, a data processing device is provided, comprising: a data port, a processing chip and a storage device port connected in sequence, wherein the data port is connected to the solid-state storage device for transmitting an access sequence set of logical block addresses collected from the solid-state storage device; the processing chip is deployed with the method described in any one of the above items; the storage device port is connected to a pre-reading device in the solid-state storage device for storing H target logical block access sequences, and transmitting the H target logical block access sequences to the pre-reading device.

[0020] In an exemplary embodiment, a hot spot area screening device, a matrix building device and a path field processing device are deployed in the processing chip, wherein the hot spot area screening device is used to screen out M target logic block areas from N logic block areas when an access sequence set is received, wherein the hot spot area screening device includes an adder and a first comparator; the matrix building device is used to construct a logic block adjacency matrix of the M target logic block areas, wherein the matrix building device includes a first storage device, an adder and a second comparator; the path field processing device is used to process the logic block adjacency matrix to obtain a logic block path dictionary.

[0021] According to another embodiment of the present application, a device for determining a logical block address access sequence is provided, comprising: a first acquisition module, for acquiring an access sequence set of a logical block address from a solid-state storage device, wherein the access sequence set includes a plurality of access sequences, and the access sequence is a time sequence of performing access operations in the order of N logical block areas included in the solid-state storage device, wherein N is a natural number greater than 1; a first determination module, for determining M target logical block areas from the N logical block areas using the access sequence set, wherein the M target logical block areas are all areas where the data access frequency is greater than a preset An area of ​​access frequency, wherein M is a natural number less than or equal to N; a first construction module, used to construct a logic block adjacency matrix of the M target logic block areas, wherein the logic block adjacency matrix is ​​used to represent the transfer frequency between the M target logic block areas; a second determination module, used to determine H target logic block access sequences based on the logic block adjacency matrix, wherein the H target logic block access sequences are used to train a pre-read model, and the pre-read model is used to output the logic block area to be accessed during the process of performing the access operation on the solid-state storage device, and H is a natural number greater than or equal to M.

[0022] According to another embodiment of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0023] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when run.

[0024] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0025] By the present application, since the access sequence set is first used to determine the M target logic block areas with relatively high acquisition access frequency from N logic block areas, then the logic block adjacency matrix of the M target logic block areas is constructed, and finally H target logic block access sequences are determined based on the logic block adjacency matrix, and the pre-reading model is trained using the H target logic block access sequences. It can be seen from this that the H target logic block access sequences screened out have stronger regularity and less noise data volume, which reduces the complexity and resource occupation of establishing or training the pre-reading model, and improves the feasibility and applicability of the pre-reading algorithm. Therefore, the problem of sparse distribution and poor regularity of LBA sequence data in the related art, which leads to an increase in the training complexity of the pre-reading model, reaches an effective improvement in the reading performance of the solid-state storage device, and enables the pre-reading model to more accurately predict and pre-fetch data. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a hardware structure block diagram of a server device of a method for determining a logical block address access sequence according to an embodiment of the present application;

[0027] Figure 2 is a flowchart of a method for determining a logical block address access sequence according to an embodiment of the present application;

[0028] Figure 3 is a structural diagram of an SSD that allows deployment of a data processing device according to an embodiment of the present application;

[0029] Figure 4 is a schematic diagram of screening hot spot LBA areas according to an embodiment of the present application;

[0030] Figure 5 is a schematic diagram of an LBA adjacency matrix according to an embodiment of the present application;

[0031] Figure 6 is a flow chart for selecting an adjacency matrix address increment according to an embodiment of the present application;

[0032] Figure 7 is a schematic diagram of a method for selecting a transfer LBA according to an embodiment of the present application;

[0033] Figure 8 is a schematic diagram of a hotspot area LBA path dictionary according to an embodiment of the present application;

[0034] Fig. 9 is a flow chart of a method for outputting a pre-processed LBA sequence according to an embodiment of the present application;

[0035] Fig.10 is a schematic diagram of outputting a pre-processed LBA sequence according to an embodiment of the present application;

[0036] Fig.11is a flow chart according to a specific embodiment of the present application;

[0037] Fig.12 It is a schematic diagram of an instantiation of a specific embodiment of the present application;

[0038] Fig.13 is a structural block diagram of a data processing device according to an embodiment of the present application;

[0039] Fig.14 This is a structural diagram of an SSD hard disk supporting LBA sequence preprocessing technology according to an embodiment of the present application;

[0040] Fig.15 It is a structural block diagram of an apparatus for determining a logical block address access sequence according to an embodiment of the present application. DETAILED DESCRIPTION

[0041] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0042] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0043] The method embodiments provided in the embodiments of the present application can be executed in a server device or a similar computing device. Taking running on a server device as an example, Figure 1 1 is a hardware structure block diagram of a server device of a method for determining a logical block address access sequence according to an embodiment of the present application. Figure 1 As shown, the server device may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the above-mentioned server device may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above server device. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.

[0044] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for determining the logical block address access sequence in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the server device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0045] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the server device. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0046] In this embodiment, a method for determining a logical block address access sequence is provided, which is applied to a data processing device. The data processing device is deployed in a solid-state storage device and connected to a pre-reading device in the solid-state storage device. Figure 2 is a flowchart of a method for determining a logical block address access sequence according to an embodiment of the present application. Figure 2 As shown, the process includes the following steps:

[0047] Step S202, collecting an access sequence set of a logical block address from a solid-state storage device, wherein the access sequence set includes a plurality of access sequences, and the access sequence is a time sequence of performing access operations in the order of N logical block areas included in the solid-state storage device, where N is a natural number greater than 1;

[0048] Optionally, the solid-state storage device in this embodiment refers to a storage device that uses solid-state electronic storage technology rather than traditional magnetic or optical storage media. These devices generally provide higher data access speeds, durability, and energy efficiency. Solid-state storage devices include, but are not limited to, solid-state hard drives (SSDs), USB flash drives, solid-state U disks, memory cards, and memory storage. The following embodiments are all described using SSDs as examples. For example, Figure 3, which is a structural diagram of an SSD that allows deployment of a data processing device in this embodiment, including a pre-reading function of an FTL layer.

[0049] Solid State Drive (SSD) is a data storage device that uses non-volatile storage technology. Its main features are no moving parts, fast read and write speed, strong durability, small size, and low power consumption. The structure of SSD mainly includes the following parts:

[0050] NAND flash memory chip: It is the core storage component of SSD and is used to store data. NAND flash memory is a non-volatile storage technology that can keep data from being lost even in the event of a power outage.

[0051] Controller: Responsible for managing and coordinating data read and write operations. It controls the operation of the flash memory chip, performs data erase, read, and encryption operations, and manages tasks such as garbage collection and wear leveling.

[0052] Cache: Some SSDs include a small DRAM cache for temporarily storing data to increase read and write speeds. The cache reduces the number of data transfers between the controller and the NAND flash memory, thereby improving performance.

[0053] Interface: SSD is connected to the computer through an interface. Common interface types include SATA, PCIe (NVMe), M.2, etc.

[0054] Main control board: The main control board is the physical carrier of the SSD, on which are installed the controller, NAND flash memory chip, interface and other components. The file system and underlying driver are both set on the main control board.

[0055] This embodiment also adds a pre-reading function of the FTL layer in the SSD, wherein the pre-reading function is used to read data in advance to reduce access delay. Figure 3 As shown in Figure 1, in SSDs, pre-reading can be achieved through the FTL layer. The FTL layer can predict the data that may need to be accessed next by analyzing the access pattern, and then read the data into the cache in advance. If the data access shows obvious sequentiality, the FTL can pre-read a series of continuous data blocks.

[0056] The pre-reading function in this embodiment can also be implemented by pre-reading by the controller. The controller can monitor the data access mode and automatically pre-read subsequent data blocks when a continuous read request is detected.

[0057] The pre-reading function in this embodiment can also be implemented by pre-reading at the operating system level. Pre-reading at the operating system level is usually implemented by reading larger data blocks, which can reduce the number of I / O requests to the SSD.

[0058] The pre-reading function in this embodiment can also be implemented through hybrid pre-reading, which can combine the pre-reading strategies of the FTL layer and the controller, and the pre-reading mechanism of the operating system to achieve more efficient data pre-reading.

[0059] It should be noted that the pre-reading function in this embodiment needs to balance the amount of pre-read data and the possible additional writing (because the pre-read data may not be used in the end) to avoid negative impact on the life of the SSD. In addition, the design of the pre-reading strategy also needs to take into account different types of workloads, because different application scenarios may require different pre-reading strategies.

[0060] Optionally, the access sequence set of the SSD refers to a time sequence of access operations performed in the order of N logical block areas contained in the SSD. These sequences may include read or write operations and are usually executed according to commands sent by the operating system or the host. For example, if an application needs to read data blocks 1, 2, 3, and 4, the SSD will access these logical blocks in this order. Logical Block Addressing (LBA for short) is an addressing mode that locates blocks starting from 0, for example, the first block LBA=0, the second block LBA=1, and so on. This addressing mode simplifies the interaction between the operating system and the storage device hardware. For example, in an SSD, the LBA sequence set of a read command is composed of a series of registers and commands for reading data from the SSD. The following are the steps of the LBA sequence set of the SSD read command in this embodiment:

[0061] S1, select hard disk: select master disk or slave disk by setting device register. For example, outb(0x1F6, 0x40 |(slavebit << 4));

[0062] S2, set the number of sectors: specify the number of sectors to be read or written through the sector count register. For example, outb(0x1F2, sectorcount high byte) and outb(0x1F2, sectorcount low byte);

[0063] S3, set the LBA address: first set the high 32 bits of LBA: outb(0x1F3, LBA4), outb(0x1F4, LBA5), outb(0x1F5, LBA6); then set the low 32 bits of LBA: outb(0x1F3, LBA1), outb(0x1F4, LBA2), outb(0x1F5, LBA3);

[0064] S4, send read command: Send the "READ SECTORS EXT" command (0x24) to start the read operation.

[0065] S5, read data: read data from the data register (0x1F0) until all sectors have been read.

[0066] S6, Check Status: Check the disk status through the command register (0x1F7) to ensure that the read operation is completed.

[0067] The registers and commands involved in these steps are part of the ATA / ATAPI command set, which is used to communicate with the hard drive. In actual operation, the settings of these commands and registers may vary, depending on the model and firmware of the SSD. In addition, the SSD's FTL (Flash Translation Layer) layer handles LBA to PBA (physical block address) mapping, as well as tasks such as wear leveling and garbage collection to optimize the performance and life of the SSD.

[0068] Step S204, using the access sequence set to determine M target logical block areas from the N logical block areas, wherein the M target logical block areas are all areas where the data access frequency is greater than the preset access frequency, and M is a natural number less than or equal to N;

[0069] Optionally, this embodiment targets a large range of LBAs in large-capacity storage systems in related technologies. Limited by the storage space of a computer or SSD, collecting all LBA sequences as the data source of the pre-read model is not targeted. Therefore, this embodiment collects LBA sequences of high-frequency access LBA areas, thereby focusing the pre-read algorithm on hot spot LBA areas. The M target logical block areas are the selected hot spot LBA areas.

[0070] In this embodiment, the values ​​of M and N can be set based on specific application scenarios. It should be noted that the frequency of the accumulation of the M target logic block areas needs to meet a predetermined percentage r%.

[0071] Step S206, constructing a logic block adjacency matrix of the M target logic block regions, wherein the logic block adjacency matrix is ​​used to represent the transfer frequency between the M target logic block regions;

[0072] Optionally, the logic block adjacency matrix in this embodiment is used to count the frequency of the row-direction LBA being transferred to the column-direction LBA. Therefore, the rows of the adjacency matrix represent the LBA values ​​of the hotspot area. For example, the adjacency matrix rows of the hotspot LBA area numbered n represent the logic block addresses nL to nL+L-1.

[0073] Step S208, determining H target logic block access sequences based on the logic block adjacency matrix, wherein the H target logic block access sequences are used to train a pre-reading model, and the pre-reading model is used to output the logic block area to be accessed during the access operation on the solid-state storage device, and the H is a natural number greater than or equal to the M, and the pre-reading model is set in the pre-reading device.

[0074] Optionally, the H target logical block access sequences are the sequences finally selected in this embodiment for training the pre-reading model. The sequences in the hotspot LBA area have a reduced amount of noise data, which can reduce the complexity and resource usage of establishing the pre-reading model, and improve the feasibility and applicability of the pre-reading model.

[0075] Through the above steps, since the access sequence set is first used to determine the M target logic block areas with relatively high access frequencies from the N logic block areas, and then the logic block adjacency matrix of the M target logic block areas is constructed, and finally the H target logic block access sequences are determined based on the logic block adjacency matrix, the pre-reading model is trained using the H target logic block access sequences. It can be seen that the H target logic block access sequences selected have stronger regularity and less noise data volume, which reduces the complexity and resource occupation of establishing or training the pre-reading model, and improves the feasibility and applicability of the pre-reading algorithm. Therefore, the problem of sparse distribution and poor regularity of LBA sequence data in the related art, which leads to an increase in the training complexity of the pre-reading model, can be solved, and the reading performance of the solid-state storage device is effectively improved, and the pre-reading model can be made to more accurately predict and pre-fetch data.

[0076] In an exemplary embodiment, the access sequence set is used to determine M target logical block areas from a plurality of the logical block areas, including: dividing the logical block space in the solid-state storage device into N logical block areas according to a preset length; determining the frequency of each logical block access sequence from the access sequence set to obtain N access frequencies; sorting the N logical block areas according to the N access frequencies; and selecting M target logical block areas from the sorted N logical block areas, wherein the sum of the M frequencies of the M target logical block areas is greater than a first preset threshold.

[0077] Optionally, the purpose of dividing the preset length in this embodiment is to reduce the amount of calculation, because if the access amount of each LBA is counted, a large amount of memory will be occupied. Fixed division can solve this problem, and the preset length of the division can be as long as it can reach less memory occupation, for example, the preset length L=1024.

[0078] Optionally, the frequency of each of the logical block access sequences is determined from the access sequence set to obtain N access frequencies, including: traversing the access sequence set to calculate the number of times the access data corresponding to each of the access sequences falls into each of the logical block areas within a preset time period; using the number of times the access data corresponding to each of the access sequences falls into each of the logical block areas and the preset time period to calculate the frequency of each of the logical block access sequences to obtain N access frequencies.

[0079] In this embodiment, for each logic block area, the access frequency in the access sequence set is calculated, that is, the number of times each logic block area appears in the access sequence set is counted. Figure 4 The figure is a schematic diagram of the screening of hot spot LBA areas in this embodiment. The specific process includes: dividing all LBA areas of the SSD into N areas according to a fixed length L; then, calculating the access frequency F of each LBA area, that is, the number of times the LBA sequence falls in a certain area; finally, sorting the access frequency F, and screening out several groups of areas with the highest access frequency as the execution objects of the pre-reading algorithm. In this embodiment, the access frequency of each LBA area is actually the frequency of all LBA sequences falling in each area. For any sequence , the numbers need to be The frequency of the area is accumulated by 1. Here, the symbol Represents the largest integer not exceeding x.

[0080] Optionally, the sorting in this embodiment may be in ascending order or descending order, depending on the target to be optimized (for example, this embodiment gives priority to the area with the highest visit frequency).

[0081] In this embodiment, M target logic block areas are selected from the sorted logic block areas, and the selection is based on the fact that the sum of the access frequencies of these areas is greater than a preset threshold. This threshold is to ensure that the selected logic block areas are frequently accessed, that is, they are "hot spots".

[0082] This embodiment can help identify frequently accessed data blocks in the storage device through the above steps, so that these areas can be optimized, especially when certain data needs to be frequently accessed, and hot target logic block areas can be quickly screened out.

[0083] In an exemplary embodiment, constructing a logical block adjacency matrix of M target logical block areas includes: determining the logical block addresses of the M target logical block areas to obtain L1 logical block addresses, wherein the number of the logical block addresses included in each target logical block area is the ratio of all the logical block addresses included in the N logical block areas to N; determining the logical block address increments between the M target logical block areas to obtain L2 logical block address increments, wherein the logical block address increments are used to represent the increased values ​​between the M target logical block areas; constructing the logical block adjacency matrix using the L1 logical block addresses and the L2 logical block address increments, wherein the element values ​​in the logical block adjacency matrix are used to represent the transfer frequency between adjacent access sequences.

[0084] Optionally, after determining the M target logical block areas, the next step of this embodiment is to determine the logical block addresses of these areas. The step of determining the logical block addresses includes: determining the number of the logical block area. Since the logical block space has been divided into N logical block areas, each area has a unique number. These numbers usually start from 0 and increase in sequence. Perform frequency statistics. For each logical block area, count its frequency of occurrence in the access sequence set. Sorting is performed. All logical block areas are sorted according to the access frequency. Select logical block areas: select the first M logical block areas whose sum of frequencies exceeds the first preset threshold as target logical block areas. Determine the logical block address. For each selected target logical block area, determine its logical block address. In a simplified model, the logical block address can be the address of the first logical block of the area. If the logical block area is equally divided, the logical block address can be calculated by multiplying the area number by the length of each logical block area (in blocks). Record the logical block addresses. The logical block addresses of the M target logical block areas are recorded. These addresses represent frequently accessed areas. Output logical block addresses and finally output L1 logical block addresses, which can be used for further operations such as data migration, optimized read path, garbage collection strategy adjustment, etc.

[0085] For example, if the logical block space of a solid-state storage device is divided into 1024 logical blocks, each logical block size is 4KB, then the entire logical block space size is 4MB. If this 4MB space is divided into 4 logical block areas with a length of 1MB, then the logical block address range of each area is as follows:

[0086] Area 0: logical block addresses range from 0 to 1023 (i.e. 0x00000000 to 0x000003FF);

[0087] Area 1: logical block address range from 1024 to 2047 (i.e. 0x00000400 to 0x00000FFF);

[0088] Area 2: logical block address range from 2048 to 3071 (i.e. 0x00001000 to 0x000017FF);

[0089] Area 3: logical block address range from 3072 to 4095 (i.e. 0x00001800 to 0x00001FFF);

[0090] If areas 0, 1, and 2 are selected as target logical block areas, the corresponding logical block addresses are the address ranges calculated above.

[0091] Optionally, the value of the logic block increment in each column of the logic block adjacency matrix is ​​determined by the following formula: , wherein the A value used to represent the logical block increment of each column in the logical block adjacency matrix, A value used to represent the logical block address of the current row in the logical block adjacency matrix, Numeric value representing the logical block increment for the current column.

[0092] like Figure 5 , which is a schematic diagram of the LBA adjacency matrix in this embodiment, wherein the adjacency matrix row of the hot spot LBA area numbered n represents the logical block address nL to nL+L-1. The columns of the adjacency matrix represent the LBA increment, and the LBA value corresponding to each column is the current row LBA value plus the LBA increment, and the rows of the adjacency matrix represent the LBA values ​​of the hot spot area.

[0093] In addition, the values ​​stored in the adjacency matrix represent the frequency of transfer from row LBA to column LBA. For example, if a certain LBA time series is LBA(n) = (1, 3, 8, 10, 1, 3, 1), then the frequency of LBA value transfer from 1 to 3 is 2. Therefore, the adjacency matrix needs to store the LBA number pairs. 2 is accumulated at each location; the frequency of LBA value transferring from 3 to 1 is 1, so the number of LBA pairs in the adjacency matrix needs to be 1 is accumulated at each LBA, and so on. It should be noted that, considering issues such as user concurrency, some LBAs at adjacent moments do not belong to the same user. Therefore, when accumulating the frequency of the adjacency matrix, a slack variable S needs to be preset so that the S LBAs adjacent to the current LBA in the LBA sequence are all treated as adjacent LBAs. For example, if the slack variable S=2 is set, and a certain LBA sequence is LBA(n)=(1, 3, 8, 10, 1, 3, 1), then the frequency of LBA values ​​transferring from 1 to 8 needs to be increased by 1, while the frequency of 1 transferring to 10 does not need to be increased.

[0094] Optionally, determining the logical block address increments between the M target logical block areas to obtain L2 logical block address increments includes: determining the access sequences in the M target logical block areas from the access sequence set to obtain P access sequences, wherein P is a natural number greater than 1; performing interval differential operations on the P access sequences respectively to capture the sequence characteristics of the P access sequences in the M target logical block areas to obtain differential access sequences; performing incremental statistics on the differential access sequences to calculate the frequency of each incremental value in the differential access sequences; determining an incremental value whose frequency is greater than a preset frequency from the frequency of each incremental value to obtain a target incremental value; and determining the logical block address increment corresponding to the target incremental value as L2 logical block address increments.

[0095] In this embodiment, the determination of the address increment of the adjacency matrix refers to the selection of the column-wise value. The selection method is to calculate the distribution frequency of each increment value, and select several address increments with higher frequencies as the values ​​represented in the column direction of the adjacency matrix. For example, Figure 6 , which is a flow chart for selecting the address increment of the adjacency matrix in this embodiment, specifically includes the following steps:

[0096] S601, considering the concurrency of SSD reading and writing, adjacent LBAs in a LBA sequence may not belong to the same user or the same data, so it is necessary to perform interval differentiation on the LBA sequence to capture the characteristics of the LBA sequence over a long distance. Initialize the differential interval k=0. The "differential interval" in this embodiment is the first-order difference of the number of intervals in a sequence. Suppose a sequence is x(n) and the sequence length is N, then its k-interval differential can be expressed as: .

[0097] S602, the upper limit of the differential interval can be set to K, which can be determined according to the number of concurrent users of the SSD, the physical parameters of the SSD (for example, the number of data frames contained in a unit wordline, etc.), etc. For example, it is set to 48, and the differential interval is increased by 1 in each step.

[0098] S603, determine whether the current differential interval exceeds the preset maximum differential interval. If yes, end the differential calculation of the LBA sequence and execute S606; otherwise, execute S604.

[0099] S604, solving the k-interval differential value of the LBA sequence.

[0100] S605, statistically filter the address increment sequence to filter the several increment values ​​with the highest frequency in the k interval differential values. The specific number of filters can be determined according to the physical parameters of the SSD and the probability distribution of user concurrency. For example, 32 1-interval differential values, 16 2-interval differential values, 8 3-interval differential values, etc. are selected.

[0101] S606, performing a union operation to use the union of the obtained 1 to K interval difference increments as the column direction value of the adjacency matrix, the formula is as follows: .

[0102] For example, suppose there are the following access sequences: sequence 1: [10, 15, 20, 30, 40], sequence 2: [5, 10, 18, 25, 35], sequence 3: [3, 8, 16, 24, 33], after performing the interval difference operation, we get: difference sequence 1: [5, 5, 10, 10], difference sequence 2: [5, 8, 7, 10], difference sequence 3: [5, 8, 8, 9], and perform incremental statistics on the differenced sequences, and we may get the following frequencies: increment 5: 3 times, increment 7: 2 times, increment 8: 2 times, increment 9: 1 time, increment 10: 2 times. If the preset frequency is 2, then the target increment values ​​will be 5 and 10. Therefore, the increments of the L2 logical block addresses will be 5 and 10. This embodiment can help understand typical changes in access patterns in a target logical block area, thereby optimizing data layout and improving the performance of a storage device.

[0103] Optionally, the logical block adjacency matrix is ​​constructed using L1 logical block addresses and L2 logical block address increments, including: initializing an original adjacency matrix, wherein the original adjacency matrix is ​​an L1×L2 matrix; determining the next logical block address pointed to by each logical block address based on the L1 logical block addresses and L2 logical block address increments; transferring each logical block address to the frequency of each logical block address increment, and determining the frequency as the element value in the original adjacency matrix to obtain the logical block adjacency matrix, wherein the rows in the logical block adjacency matrix are used to represent the logical block addresses, and the columns in the logical block adjacency matrix are used to represent the logical block address increments.

[0104] In this embodiment, M is the number of target logical block regions, and each element in the matrix represents a direct access relationship from one logical block to another. For each logical block address, the logical block address increment is used to determine the next logical block address. For example, if the logical block address is A and the increment is X, then the next logical block address is A + X.

[0105] Optionally, filling the adjacency matrix specifically includes: traversing each logical block address and the corresponding logical block address increment. For each logical block address, find its row in the adjacency matrix. According to the logical block address increment, determine the next logical block address and find its column in the adjacency matrix. Fill the value of the logical block address increment at the intersection of the current row of the adjacency matrix and the column of the next logical block address. The resulting matrix is ​​the logical block adjacency matrix, which reflects the access relationship between logical blocks.

[0106] For example, assuming we have 3 logical block addresses (A1, A2, A3) and corresponding logical block address increments (Increment 1, Increment 2, Increment 3), we can construct the following adjacency matrix:

[0107] The next logical block address of A1 is A1 + increment 1;

[0108] The next logical block address of A2 is A2 + increment 2;

[0109] The next logical block address of A3 is A3 + increment 3;

[0110] The adjacency matrix might look like Table 1:

[0111] Table 1:

[0112]

[0113] In this matrix, the row represents the current logical block address, the column represents the next logical block address, and the value in the matrix represents the frequency of transfer. If a logical block does not directly point to another logical block, the corresponding matrix element can be 0 or a special mark, such as NaN (Not a Number), indicating that there is no direct access relationship. This adjacency matrix can be used to analyze the access pattern between logical blocks, optimize the data prefetching strategy, or make decisions in garbage collection and wear leveling algorithms.

[0114] In an exemplary embodiment, after constructing the logic block adjacency matrix using L1 logic block addresses and L2 logic block address increments, the method further includes: determining the logic block addresses where transfer occurs in the M target logic block areas from the access sequence set to obtain M groups of transfer logic block addresses; counting the frequencies of the M groups of transfer logic block addresses, wherein the frequencies are used to represent the number of times the state transfer occurs at the transfer logic block address; sorting the multiple frequencies in a preset order, and calculating the ratio between two adjacent maximum frequencies from the sorted frequencies to obtain a frequency ratio; when the frequency ratio is greater than a preset threshold, determining the logic block address corresponding to the frequency ratio as the target transfer logic block address, wherein the target transfer logic block address is the logic block address to be transferred in the M groups of transfer logic block addresses.

[0115] Optionally, when all LBA access frequencies in the adjacency matrix have been updated, the transfer frequencies of each row need to be sorted to determine the transfer LBA of the LBA in the row. Figure 7 As shown, it is a schematic diagram of the selection method of the transfer LBA in this embodiment. It should be noted that due to the possible concurrency of read requests, there may be interference between LBAs. For example, when selecting the transfer LBA, for some LBAs with a small number of statistical times, the set transfer LBA frequencies are almost equal, which means that the LBA values ​​determined by the adjacency matrix cannot be used as the transfer LBA of the current LBA. Therefore, the LBA with the largest access frequency cannot be directly selected as the transfer LBA. For this reason, this embodiment proposes a screening criterion based on frequency ratio, and its basic idea is to solve the ratio of two adjacent maximum values. The formula is as follows: , where if there is a certain r value greater than the set threshold (for example, 1.414), the LBA corresponding to the maximum frequency is selected as the transfer LBA, otherwise it is considered that there is no transfer LBA in the row LBA. For example, the LBA represented by a row of the adjacency matrix is ​​1, and the transfer LBAs represented by its column direction are 2, 3, 4, and 5, respectively, and the corresponding frequencies are 10, 11, 9, and 13, then each column cannot be used as a transfer LBA; if the corresponding frequencies are 11, 1, 3, and 1, then LBA=2 can be used as a transfer LBA.

[0116] Optionally, determining H target logical block access sequences based on the logical block adjacency matrix includes: storing the logical block addresses and the corresponding target transfer logical block addresses in a table to obtain M tables, wherein one target transfer logical block address corresponds to one table, and the table includes the logical block address and the corresponding target transfer logical block address; constructing a logical block path dictionary using the M tables; and determining H target logical block access sequences based on the logical block path dictionary.

[0117] In this embodiment, the process of determining the H target logic block access sequences based on the logic block adjacency matrix is ​​a data-driven analysis process, which aims to discover and utilize access patterns to optimize the performance of the storage device. The following are the detailed steps:

[0118] Store current and target access sequences: For each access sequence, store its current logical block address and target logical block address in a table. Each access sequence corresponds to a table that records the current logical block address and target logical block address for each step in the sequence.

[0119] Build tables: Create P tables, each corresponding to an access sequence. In the table, list each logical block access in the access sequence, including the current logical block address and the next logical block address (determined by the adjacency matrix).

[0120] Construct a logical block path dictionary: Use P tables to construct a logical block path dictionary. The key of the logical block path dictionary is the current logical block address, and the value is a list containing all possible next logical block addresses (i.e., the logical block addresses of the target access sequence). Figure 8 As shown in the figure, a schematic diagram of the hotspot LBA path dictionary is shown. The size of the table is equal to the number of LBAs in the hotspot area; the depth is 2, which represents the current LBA value and the transfer LBA value respectively. For LBAs that do not have transfer addresses, their corresponding transfer LBAs can be assigned invalid values; they can also be deleted from the transfer table to save storage space for the LBA path dictionary.

[0121] Determine the target logical block access sequence: Based on the logical block path dictionary, determine H target logical block access sequences. For each target sequence, find the next logical block address of the current logical block address from the dictionary until the sequence is completed or reaches a predetermined length.

[0122] Analyze and select sequences: Analyze the paths in the logical block path dictionary and select the H most frequent or important access sequences as target sequences. These sequences may be selected based on access frequency, access pattern, or other optimization criteria.

[0123] Output target access sequence: Output H target logic block access sequences, which can be used for performance optimization, predicting future data access patterns, or performing other related analysis.

[0124] For example, suppose we have the following logical block adjacency matrix as shown in Table 2:

[0125] Table 2:

[0126]

[0127] The following table can be constructed:

[0128] Table 3:

[0129]

[0130] Table 4:

[0131]

[0132] Building a logical block path dictionary might look like this:

[0133] A1: [A2, A3];

[0134] A2: [A1, A3];

[0135] A3: [A1, A2];

[0136] Based on the logical block path dictionary, we can determine the target logical block access sequence, for example:

[0137] Sequence 1: A1 -> A2 -> A3;

[0138] Sequence 2: A3 -> A1 -> A2;

[0139] Finally, H such sequences are selected as target logical block access sequences. These sequences reflect common access patterns and can be used to optimize the performance and response time of storage devices.

[0140] Optionally, constructing a logic block path dictionary using the M tables includes: creating M instances of the table to obtain M instances; and constructing path relationships between the M instances to obtain the logic block path dictionary.

[0141] The purpose of using M tables to construct a logical block path dictionary in this embodiment is to create a mapping that can describe the access path relationship between logical blocks. The following are the detailed steps for constructing a logical block path dictionary:

[0142] Create table instance: For each access sequence, create a table instance. This instance will contain the current address and next address of all logic blocks in the sequence. Each table instance corresponds to an access sequence and contains access information of all logic blocks in the sequence.

[0143] Construct path relationships between instances: Analyze the logical block access sequence in each table instance and determine the path relationship between logical blocks. For each logical block address, record the next logical block address that it can access.

[0144] Build a logical block path dictionary: Create a dictionary where the key is the current logical block address and the value is a list containing all possible next logical block addresses. This dictionary will contain the path information in all P table instances.

[0145] Populate the dictionary: Iterate over each table instance, and for each pair of current logical block address and target logical block address in each instance, update the dictionary. If the current logical block address is a key in the dictionary, add the target logical block address to the corresponding list. If the current logical block address is not a key in the dictionary, create a new key, initialize the list, and add the target logical block address to the list.

[0146] Handling duplicates: When filling the dictionary, make sure that the list does not contain duplicate logical block addresses. If the same logical block address is accessed multiple times, you may need to decide whether to keep one entry or multiple entries based on the actual situation.

[0147] Optimizing dictionary structure: The dictionary can be optimized as needed, for example, if some paths are very frequent, they can be marked as high priority paths.

[0148] Output logical block path dictionary: Finally, the constructed logical block path dictionary is output, which can be used to analyze access patterns, optimize data access strategies, or for other purposes.

[0149] For example, consider the following two access sequences:

[0150] Access sequence 1: A1 -> A2 -> A3;

[0151] Access sequence 2: A3 -> A1 -> A2;

[0152] You can create two table instances and build the logical block path dictionary as follows:

[0153] Example 1 (accessing table of sequence 1):

[0154] Current logical block address: A1, next logical block address: A2;

[0155] Current logical block address: A2, next logical block address: A3;

[0156] Example 2 (accessing the table of sequence 2);

[0157] Current logical block address: A3, next logical block address: A1;

[0158] Current logical block address: A1, next logical block address: A2;

[0159] A logical block path dictionary might be:

[0160] A1: [A2];

[0161] A2: [A3];

[0162] A3: [A1];

[0163] This dictionary reflects the access path relationship between logical blocks and can be used to determine how to transfer from one logical block to another.

[0164] Optionally, determining H target logical block access sequences based on the logical block path dictionary includes: determining a starting logical block address from the logical block path dictionary, wherein the starting logical block address is a target access sequence in a valid state in the logical block path dictionary; querying a first logical block address from the logical block path dictionary according to a first query direction, wherein the first query direction is a direction at a time before the starting logical block address; querying a second logical block address from the logical block path dictionary according to a second query direction, wherein the second query direction is a direction at a time after the starting logical block address; and determining H target logical block access sequences using the first logical block address, the starting logical block address, and the second logical block address.

[0165] In this embodiment, the process of determining H target logical block access sequences based on the logical block path dictionary involves extracting and constructing access sequences from the dictionary. For example, assuming that the logical block path dictionary is as follows:

[0166] A -> B -> C -> D; the starting logical block address can be B, because B is an active node with a predecessor A and a successor C. First query direction: query from B forward, the first logical block address is A. Second query direction: query from B backward, the second logical block address is C. The constructed access sequence may be: A -> B -> C; B -> C -> D; if K=2 sequences are required, these two sequences can be selected as the target logical block access sequence.

[0167] Optionally, the first logical block address, the starting logical block address and the second logical block address are used to determine H target logical block access sequences, including: when the logical block address before the first logical block address is an invalid logical block address, and the logical block address after the second logical block address is the invalid logical block address, constructing a logical block address path according to the time sequence between the first logical block address, the starting logical block address and the second logical block address; and determining the access path included in the logical block address path as H target logical block access paths.

[0168] In this embodiment, to determine H target logical block access sequences, it is necessary to construct a logical block address path based on the time sequence between the first logical block address, the starting logical block address, and the second logical block address, and determine the access path therefrom. For example, assuming the following logical block address sequence: first logical block address: A; starting logical block address: B; second logical block address: C; logical block addresses before A and after C are considered invalid. Then, the following logical block address path may be constructed: A -> B -> C; based on this path, the following access sequence can be determined: A -> B; B -> C. If K=2 sequences are required, these two sequences can be selected as the target logical block access sequence.

[0169] Optionally, after determining H target logical block access sequences using the first logical block address, the starting logical block address and the second logical block address, the method further includes: deleting the logical block addresses corresponding to the H target logical block access sequences in the logical block path dictionary; or, setting the logical block addresses corresponding to the H target logical block access sequences to an invalid state in the logical block path dictionary.

[0170] In this embodiment, after the hot spot area LBA transfer table is established, the LBA at the next moment can be queried according to the LBA value at the current moment, until the LBA at the next moment is an invalid value. Fig. 9 FIG. 1 is a flow chart of a method for outputting a pre-processed LBA sequence in this embodiment, comprising the following steps:

[0171] S901, select a starting LBA, that is, select any valid LBA in the path dictionary as the starting search LBA.

[0172] S902, forward query and backward query, respectively query the LBA of the previous moment and the next moment of the current LBA.

[0173] S903, judging whether the LBA of the previous moment or the next moment is invalid, as the termination judgment condition of the forward or backward query. If yes, executing step S904, terminating the query in the corresponding direction; otherwise, continuing to execute the query in the direction.

[0174] S905, judging whether the bidirectional query is completely finished, as the termination condition of an LBA path. If so, executing step S906, outputting an LBA path; otherwise, continuing to execute the query.

[0175] S907, delete the LBA in the path to facilitate searching for the next LBA path.

[0176] Alternatively, if Fig.10As shown, it is a schematic diagram of outputting the pre-processed LBA sequence of this embodiment. For example, initially, there are 5 current logical block addresses in the LBA path dictionary, and their values ​​are 1, 2, 3, 4, and 5, respectively, and the corresponding transfer addresses are invalid, 3, 4, 5, and invalid, respectively. First, the starting LBA is selected as 3; then, a bidirectional query is performed, the forward query stops at 2, and the backward query stops at 5, and then an LBA path of 2->3->4->5 is output; finally, the LBA passed by the path is deleted from the path dictionary. At this time, there is only one logical block address in the transfer table, and its value is 1, and the corresponding transfer address is invalid.

[0177] In an exemplary embodiment, after determining H target logic block access sequences based on the logic block adjacency matrix, the method further includes: using the H target logic block access sequences to train an initial pre-reading model to obtain the pre-reading model, wherein the initial pre-reading model includes a fusion subnetwork and a classification subnetwork, and for each group of the H target logic block access sequences, the fusion subnetwork is used to fuse sequence features in the H target logic block access sequences, and the classification subnetwork is used to classify and identify logic block areas based on the fused sequence features.

[0178] Optionally, in this embodiment, after determining H target logic block access sequences based on the logic block adjacency matrix, the process of training the pre-reading model involves using these sequences to optimize the pre-reading performance of the storage device. The pre-reading model usually includes two main parts: a fusion sub-network and a classification sub-network.

[0179] Fusion sub-network: This part is used to fuse the sequence features in the H target logic block access sequences. The fusion process can be implemented in many ways, such as through weighted averaging, attention mechanism, or fusion layer in deep learning. The purpose of the fusion sub-network is to extract common features in the sequence and provide rich feature representation for the classification sub-network.

[0180] Classification subnetwork: After the fusion subnetwork extracts and fuses features, the classification subnetwork classifies and identifies logical block areas based on these fused sequence features. The classification subnetwork can use traditional machine learning algorithms, such as support vector machines (SVMs), random forests, etc., or deep learning models, such as convolutional neural networks (CNNs), recurrent neural networks (RNNs), or Transformers.

[0181] The training process includes the following steps:

[0182] Data preparation: H target logic block access sequences are input into the pre-reading model as training data.

[0183] Model training: The fusion subnetwork and the classification subnetwork are trained using the target logic block access sequence. This process involves adjusting the model parameters to minimize the difference between the predicted output and the actual label.

[0184] Model evaluation: During the training process, the performance of the model needs to be evaluated regularly, which can be achieved through cross-validation, independent test sets, etc.

[0185] Hyperparameter tuning: Based on the results of model evaluation, adjust the model’s hyperparameters, such as learning rate, number of layers, number of hidden units, etc., to further improve the performance of the model.

[0186] The resulting read-ahead model is able to predict future access sequences based on the access patterns of logical blocks, thereby improving the data read-ahead efficiency of storage devices. Such models are particularly important in storage devices such as solid-state drives (SSDs), as they can significantly reduce data access latency and improve overall system performance.

[0187] The present application is described below in conjunction with specific embodiments:

[0188] This specific embodiment proposes an LBA sequence preprocessing method for an SSD pre-reading algorithm, such as Fig.11 FIG. 1 is a flowchart of this specific embodiment, which specifically includes the following steps:

[0189] S1101, collect LBA access sequences, that is, collect LBA sequences corresponding to all read requests initiated by the host; the specific LBA access sequence process is the same as the above-mentioned method of collecting the access sequence set of the logical block address from the solid-state storage device, and will not be repeated here.

[0190] S1102, filter the hot spot LBA area. This step can be simply divided into three steps. First, divide the entire LBA space into multiple blocks according to fixed lengths, such as Figure 4 As shown; then, the frequency of the LBA sequence collected in step S1101 falling into each interval is counted; finally, the first M areas with the highest access frequency (ie, the target logical block area) are selected as the target interval of the pre-reading algorithm.

[0191] S1103, establish an LBA adjacency matrix. This step can be divided into two steps. First, the size of the address increment set is determined, and an adjacency matrix is ​​established based on the set size and the LBA area length, such as Figure 4 As shown; then, the values ​​of the adjacency matrix are updated according to the statistical data of step S1101.

[0192] S1104: Create a path dictionary. According to the formula , calculate the frequency ratio of each row of LBA in the LBA adjacency matrix, and then filter out the transfer LBA and establish Figure 8 The LBA path dictionary shown;

[0193] S1105, outputting the pre-processed LBA sequence. According to the path dictionary obtained in step S1104, all LBA sequences are output in a query manner as the pre-processed LBA sequence. The pre-processed LBA sequence can be used as an input data set for pre-reading model training or establishment.

[0194] The instantiation form of the LBA sequence data preprocessing algorithm in this specific embodiment is as follows: Fig.12 As shown,

[0195] like Fig.12 As shown, it is an instantiation of this specific embodiment, which includes the step of hot spot area screening, which is the same as the above-mentioned embodiment and will not be repeated here. As well as the effect of the LBA sequence data preprocessing algorithm, this specific embodiment screens the frequently accessed LBA area as the execution area of ​​the preprocessing algorithm, ensuring the number of samples of the LBA sequence in the hot spot LBA area, and improving the reliability of the LBA sequence while compressing the data volume. On the other hand, the method of this specific embodiment draws on the idea of ​​the adjacency matrix in graph theory, and outputs the preprocessed LBA sequence through operations such as address increment selection and path dictionary establishment, thereby improving the regularity of the LBA sequence and reducing the resource occupancy rate of establishing or training the pre-reading model.

[0196] In addition, the present application also provides a data processing device, such as Fig.13 As shown, it includes: a data port, a processing chip and a storage device port connected in sequence, wherein,

[0197] The data port is connected to the solid-state storage device and is used to transmit an access sequence set for collecting logical block addresses from the solid-state storage device;

[0198] Any of the methods described in item 1 is deployed on the processing chip;

[0199] The storage device port is connected to the pre-reading device in the solid-state storage device, and is used to store H target logic block access sequences and transmit the H target logic block access sequences to the pre-reading device.

[0200] Optionally, a hotspot area screening device, a matrix building device and a path field processing device are deployed in the processing chip, wherein:

[0201] The hotspot area screening device is used to screen out M target logic block areas from the N logic block areas when receiving the access sequence set, wherein the hotspot area screening device includes an adder and a first comparator;

[0202] The matrix building device is used to build the logic block adjacency matrix of the M target logic block areas, wherein the matrix building device includes a first storage device, an adder, and a second comparator;

[0203] The path field processing device is used to process the logic block adjacency matrix to obtain a logic block path dictionary.

[0204] The data processing device in this embodiment can be a solid state drive (SSD) architecture, which supports logical block address (LBA) sequence preprocessing technology and adds a flash translation layer (FTL) pre-reading function. Among them, the key hardware in the LBA sequence collection module includes a storage unit. It is mainly used to collect and store logical block address sequences, which reflect the order of data access.

[0205] The key hardware in the hotspot area screening module includes adders and comparators, which are used to count the access frequency of each LBA area and sort the frequency to identify the frequently accessed hotspot areas.

[0206] The key hardware in the adjacency matrix building module includes storage units, subtractors, and comparators, which are mainly used to store the adjacency matrix, perform interval difference operations to capture the sequence characteristics of the access sequence, and filter out the frequently occurring LBA increments.

[0207] The key hardware in the path dictionary storage module includes a storage unit, which is mainly used to store a logical block path dictionary, which contains a mapping relationship from a logical block address to the next logical block address.

[0208] The key hardware in the pre-processing output module includes a search unit and a storage unit, which are used to search for LBA paths and store these paths for use in training or establishing a pre-reading model.

[0209] The key hardware in the pre-read model training / building module includes a computing unit and a storage unit, which are used to train or build pre-read models and store these models for future data access pre-reading.

[0210] The purpose of this architecture is to optimize the performance of SSDs, especially in data access read-ahead. By analyzing access sequences and building an adjacency matrix, the system can predict future access patterns and read data that may be needed in advance, thereby reducing access latency and improving overall performance.

[0211] The following is a possible implementation flow of this architecture: Data collection: The LBA sequence collection module collects data access sequences. Hot spot identification: The hot spot area screening module identifies frequently accessed areas. Adjacency matrix construction: The adjacency matrix establishment module builds the access relationship between logical blocks. Path dictionary construction: The path dictionary storage module stores the access path of the logical blocks. Preprocessing output: The preprocessing output module outputs the preprocessed data for pre-reading model training. Model training / establishment: The pre-reading model training / establishment module trains or establishes the pre-reading model and stores it for subsequent use. This architecture can be integrated into the firmware of the SSD, allowing the SSD to manage data access more intelligently and improve performance.

[0212] For example, Fig.14 As shown, it is the SSD hard disk structure diagram supporting LBA sequence preprocessing technology in this embodiment, and this architecture adds the pre-reading function of FTL layer. It is mainly composed of six modules, including sequence collection module, hot spot area screening module, adjacency matrix establishment module, path dictionary storage module, preprocessing output module and pre-reading model training / establishment module. Among them, the key hardware constituting the LBA sequence collection module and the path dictionary storage module is the storage unit. The hot spot area screening module is composed of an adder and a comparator, which are respectively used to count the access frequency of each LBA area and sort the frequency. The adjacency matrix establishment module is composed of a storage unit, a subtractor and a comparator, which are respectively used to store the adjacency matrix, interval difference and screen LBA increment. The preprocessing output module is composed of a search unit and a storage unit, which are respectively used to search and store LBA paths. The pre-reading model training / establishment module is composed of a computing unit and a storage unit, which are respectively used to train or establish a pre-reading model and store a pre-reading model.

[0213] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0214] In the present embodiment, a device for determining a logical block address access sequence is also provided, and the device is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made are not repeated here. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0215] Fig.15 is a structural block diagram of an apparatus for determining a logical block address access sequence according to an embodiment of the present application, such as Fig.15 As shown, the device comprises:

[0216] A first acquisition module 1502 is used to acquire an access sequence set of a logic block address from a solid-state storage device, wherein the access sequence set includes a plurality of access sequences, and the access sequence is a time sequence of performing access operations in the order of N logic block areas included in the solid-state storage device, where N is a natural number greater than 1;

[0217] A first determining module 1504 is configured to determine M target logical block areas from the N logical block areas by using the access sequence set, wherein the M target logical block areas are all areas whose data access frequency is greater than a preset access frequency, and M is a natural number less than or equal to N;

[0218] A first constructing module 1506 is used to construct a logic block adjacency matrix of the M target logic block regions, wherein the logic block adjacency matrix is ​​used to represent the transfer frequency between the M target logic block regions;

[0219] The second determination module 1508 is used to determine H target logic block access sequences based on the logic block adjacency matrix, wherein the H target logic block access sequences are used to train a pre-read model, and the pre-read model is used to output the logic block area to be accessed during the access operation on the solid-state storage device, and H is a natural number greater than or equal to M.

[0220] Through the above-mentioned device, since the access sequence set is first used to determine the M target logic block areas with relatively high acquisition access frequencies from the N logic block areas, then the logic block adjacency matrix of the M target logic block areas is constructed, and finally H target logic block access sequences are determined based on the logic block adjacency matrix, and the pre-reading model is trained using the H target logic block access sequences. It can be seen that the H target logic block access sequences screened out have stronger regularity and less noise data volume, which reduces the complexity and resource occupation of establishing or training the pre-reading model, and improves the feasibility and applicability of the pre-reading algorithm. Therefore, the problem of sparse distribution and poor regularity of LBA sequence data in the related art, which leads to an increase in the training complexity of the pre-reading model, can be solved, and the reading performance of the solid-state storage device is effectively improved, and the effect of enabling the pre-reading model to more accurately predict and pre-fetch data can be achieved.

[0221] In an exemplary embodiment, the above-mentioned first determination module 1504 includes: a first division unit, used to divide the logical block space in the solid-state storage device into N logical block areas according to a preset length; a first determination unit, used to determine the frequency of each logical block access sequence from the access sequence set to obtain N access frequencies; a first sorting unit, used to sort the N logical block areas according to the N access frequencies; a first selection unit, used to select M target logical block areas from the sorted N logical block areas, wherein the sum of the M frequencies of the M target logical block areas is greater than a first preset threshold.

[0222] In an exemplary embodiment, the above-mentioned first determination unit includes: a first traversal submodule, used to traverse the access sequence set and calculate the number of times the access data corresponding to each access sequence falls into each logical block area within a preset time period; a first calculation submodule, used to calculate the frequency of each logical block access sequence using the number of times the access data corresponding to each access sequence falls into each logical block area and the preset time period, to obtain N access frequencies.

[0223] In an exemplary embodiment, the first construction module 1506 includes: a second determination unit, used to determine the logical block addresses of the M target logical block areas, and obtain L1 logical block addresses, wherein the number of the logical block addresses included in each of the target logical block areas is the ratio of all the logical block addresses included in the N logical block areas to N; a third determination unit, used to determine the logical block address increments between the M target logical block areas, and obtain L2 logical block address increments, wherein the logical block address increments are used to represent the increased values ​​between the M target logical block areas; a first construction unit, used to construct the logical block adjacency matrix using the L1 logical block addresses and the L2 logical block address increments, wherein the element values ​​in the logical block adjacency matrix are used to represent the transfer frequency between adjacent access sequences.

[0224] In an exemplary embodiment, the third determination unit includes: a first determination submodule, used to determine the access sequence in the M target logical block areas from the access sequence set to obtain P access sequences, wherein P is a natural number greater than 1; a first operation submodule, used to perform interval differential operations on the P access sequences respectively to capture the sequence characteristics of the P access sequences in the M target logical block areas to obtain the differential access sequence; a first statistical submodule, used to perform incremental statistics on the differential access sequence to calculate the frequency of each incremental value in the differential access sequence; a second determination submodule, used to determine the incremental value whose frequency is greater than the preset frequency from the frequency of each incremental value to obtain the target incremental value; and a third determination submodule, used to determine the logical block address increment corresponding to the target incremental value as L2 logical block address increments.

[0225] In an exemplary embodiment, determining the logical block addresses of the M target logical block areas to obtain L1 logical block addresses is to calculate the number of logical block addresses of each target logical block area by the following formula to obtain L1 logical block addresses: , wherein the The number of logical block addresses used to represent the target logical block area, A value used to represent the logical block address of the current row in the target logical block area, A numerical value used to represent the logical block increment of the current column in the target logical block area.

[0226] In an exemplary embodiment, the above-mentioned first construction unit includes: a first initialization submodule, used to initialize the original adjacency matrix, wherein the original adjacency matrix is ​​an L1×L2 matrix; a second determination submodule, used to determine the next logical block address pointed to by each logical block address based on L1 logical block addresses and L2 logical block address increments; a first filling submodule, used to transfer each logical block address to the frequency of each logical block address increment, and determine the frequency as the element value in the original adjacency matrix to obtain the logical block adjacency matrix, wherein the rows in the logical block adjacency matrix are used to represent the logical block addresses, and the columns in the logical block adjacency matrix are used to represent the logical block address increments.

[0227] In an exemplary embodiment, the above-mentioned device also includes: a second determination module, which is used to use L1 logical block addresses and L2 logical block address increments to construct the logical block adjacency matrix, and then determine the M logical block addresses in the target logical block area where the transfer occurs from the access sequence set to obtain M groups of transfer logical block addresses; a first statistical module, which is used to count the frequencies of the M groups of transfer logical block addresses, wherein the frequencies are used to represent the number of times the state of the transfer logical block address undergoes a state transfer; a first calculation module, which is used to sort the multiple frequencies in a preset order, and calculate the ratio between two adjacent maximum frequencies from the sorted frequencies to obtain a frequency ratio; a third determination module, which is used to determine the logical block address corresponding to the frequency ratio as the target transfer logical block address when the frequency ratio is greater than a preset threshold, wherein the target transfer logical block address is the logical block address to be transferred in the M groups of transfer logical block addresses.

[0228] In an exemplary embodiment, the second determination module includes: a first storage unit, used to store the logical block address and the corresponding target transfer logical block address in a table to obtain M tables, wherein one target transfer logical block address corresponds to one table, and the table includes the logical block address and the corresponding target transfer logical block address; a second construction unit, used to construct a logical block path dictionary using the M tables; and a fourth determination unit, used to determine H target logical block access sequences based on the logical block path dictionary.

[0229] In an exemplary embodiment, the second construction unit includes: a first creation submodule, used to create M instances of the table to obtain M instances; a second construction submodule, used to construct the path relationship between the M instances to obtain the logic block path dictionary.

[0230] In an exemplary embodiment, the fourth determination unit includes: a fourth determination submodule, used to determine the starting logical block address from the logical block path dictionary, wherein the starting logical block address is a target access sequence in a valid state in the logical block path dictionary; a first query submodule, used to query the first logical block address from the logical block path dictionary according to a first query direction, wherein the first query direction is the direction at a time before the starting logical block address; a second query submodule, used to query the second logical block address from the logical block path dictionary according to a second query direction, wherein the second query direction is the direction at a time after the starting logical block address; a fifth determination submodule, used to determine H target logical block access sequences using the first logical block address, the starting logical block address and the second logical block address.

[0231] In an exemplary embodiment, the fifth determination submodule is used to determine H target logical block access sequences using the first logical block address, the starting logical block address and the second logical block address in the following manner: when the logical block address before the first logical block address is an invalid logical block address, and the logical block address after the second logical block address is the invalid logical block address, a logical block address path is constructed according to the time sequence between the first logical block address, the starting logical block address and the second logical block address; and the access path included in the logical block address path is determined as H target logical block access paths.

[0232] In an exemplary embodiment, the above-mentioned device also includes: a first deletion module, which is used to use the first logical block address, the starting logical block address and the second logical block address to determine H target logical block access sequences, and then delete the logical block addresses corresponding to the H target logical block access sequences in the logical block path dictionary; or, a first setting module, which is used to set the logical block addresses corresponding to the H target logical block access sequences in the logical block path dictionary to an invalid state.

[0233] In an exemplary embodiment, the above-mentioned device also includes: a training module, which is used to train an initial pre-reading model using the H target logic block access sequences after determining H target logic block access sequences based on the logic block adjacency matrix to obtain the pre-reading model, wherein the initial pre-reading model includes a fusion subnetwork and a classification subnetwork, and for each group of the H target logic block access sequences, the fusion subnetwork is used to fuse the sequence features in the H target logic block access sequences, and the classification subnetwork is used to classify and identify the logic block area based on the fused sequence features.

[0234] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0235] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0236] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0237] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0238] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0239] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above method embodiments are implemented.

[0240] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0241] The embodiments of the present application also provide a computer program, which includes computer instructions, which are stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps of any one of the above method embodiments.

[0242] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0243] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0244] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for determining a logical block address access sequence, characterized in that: Applied to a data processing device, the data processing device is deployed in a solid-state storage device and connected to a pre-reading device in the solid-state storage device, the method comprises: Collecting an access sequence set of a logical block address from the solid-state storage device, wherein the access sequence set includes a plurality of access sequences, and the access sequence is a time sequence of performing access operations in the order of N logical block areas included in the solid-state storage device, where N is a natural number greater than 1; Determine M target logic block areas from the N logic block areas by using the access sequence set, wherein the M target logic block areas are all areas with data access frequencies greater than a preset access frequency, and M is a natural number less than or equal to N; Constructing a logic block adjacency matrix of the M target logic block regions, wherein the logic block adjacency matrix is ​​used to represent the transfer frequency between the M target logic block regions; Determine H target logic block access sequences based on the logic block adjacency matrix, wherein the H target logic block access sequences are used to train a pre-reading model, the pre-reading model is used to output a logic block area to be accessed during the process of performing the access operation on the solid-state storage device, the H is a natural number greater than or equal to the M, and the pre-reading model is set in the pre-reading device; Determine H target logic block access sequences based on the logic block adjacency matrix, including: store the logic block address and the corresponding target transfer logic block address in a table to obtain M tables, wherein one target transfer logic block address corresponds to one table, and the table includes the logic block address and the corresponding target transfer logic block address; use the M tables to construct a logic block path dictionary; determine the H target logic block access sequences based on the logic block path dictionary.

2. The method according to claim 1, characterized in that: Determining M target logical block areas from the plurality of logical block areas by using the access sequence set includes: Dividing the logic block space in the solid-state storage device into N logic block areas according to a preset length; Determine the frequency of each of the logic block access sequences from the access sequence set to obtain N access frequencies; Sorting the N logical block areas according to the N access frequencies; M target logic block areas are selected from the sorted N logic block areas, wherein a sum of the M frequencies of the M target logic block areas is greater than a first preset threshold.

3. The method according to claim 2, characterized in that Determining the frequency of each of the logic block access sequences from the access sequence set to obtain N access frequencies includes: Traversing the access sequence set, and calculating the number of times the access data corresponding to each access sequence falls into each logic block area within a preset time period; The frequency of each of the logic block access sequences is calculated by using the number of times the access data corresponding to each of the access sequences falls into each of the logic block regions and the preset time period to obtain N access frequencies.

4. The method according to claim 1, characterized in that: Constructing a logic block adjacency matrix of the M target logic block areas, comprising: Determine the logical block addresses of the M target logical block areas to obtain L1 logical block addresses, wherein the number of the logical block addresses included in each of the target logical block areas is the ratio of all the logical block addresses included in the N logical block areas to N; Determine a logical block address increment between the M target logical block areas to obtain L2 logical block address increments, wherein the logical block address increment is used to represent an increased value between the M target logical block areas; The logic block adjacency matrix is ​​constructed by using L1 logic block addresses and L2 logic block address increments, wherein the element values ​​in the logic block adjacency matrix are used to represent the transfer frequency between adjacent access sequences.

5. The method according to claim 4, characterized in that Determining the logical block address increments between the M target logical block areas to obtain L2 logical block address increments includes: Determine access sequences in the M target logic block areas from the access sequence set to obtain P access sequences, where P is a natural number greater than 1; Performing interval differential operations on the P access sequences respectively to capture sequence characteristics of the P access sequences in the M target logic block regions to obtain differential access sequences; Performing incremental statistics on the access sequence after differentiation, and calculating the frequency of each incremental value in the access sequence after differentiation; Determine, from the frequency of each of the incremental values, an incremental value whose frequency is greater than a preset frequency, and obtain a target incremental value; The logical block address increment corresponding to the target increment value is determined to be L2 logical block address increments.

6. The method according to claim 4, characterized in that Determining the logical block addresses of the M target logical block areas to obtain L1 logical block addresses includes: The number of logical block addresses of each target logical block area is calculated by the following formula to obtain L1 logical block addresses: , wherein the The number of logical block addresses used to represent the target logical block area, A value used to represent the logical block address of the current row in the target logical block area, A numerical value used to represent the logical block increment of the current column in the target logical block area.

7. The method according to claim 4, characterized in that Using L1 logical block addresses and L2 logical block address increments to construct the logical block adjacency matrix includes: Initialize an original adjacency matrix, wherein the original adjacency matrix is ​​an L1×L2 matrix; Determine the next logical block address pointed to by each of the logical block addresses based on the L1 logical block addresses and the L2 logical block address increments; The frequency of transferring each of the logical block addresses to each of the logical block address increments is calculated, and the frequency is determined as the element value in the original adjacency matrix to obtain the logical block adjacency matrix, wherein the rows in the logical block adjacency matrix are used to represent the logical block addresses, and the columns in the logical block adjacency matrix are used to represent the logical block address increments.

8. The method according to claim 4, characterized in that After constructing the logic block adjacency matrix using L1 logic block addresses and L2 logic block address increments, the method further includes: Determine the logical block addresses where the transfer occurs in M ​​target logical block areas from the access sequence set, and obtain M groups of transfer logical block addresses; Counting the frequencies of the M groups of transfer logic block addresses, wherein the frequencies are used to indicate the number of times the transfer logic block addresses undergo state transfers; Sorting the plurality of frequencies according to a preset order, and calculating the ratio between two adjacent maximum frequencies from the sorted frequencies to obtain a frequency ratio; When the frequency ratio is greater than a preset threshold, the logic block address corresponding to the frequency ratio is determined as the target transfer logic block address, wherein the target transfer logic block address is the logic block address to be transferred in the M groups of transfer logic block addresses.

9. The method according to claim 1, characterized in that: The logical block path dictionary is constructed using the M tables, including: Creating M instances of the table to obtain M instances; Construct the path relationship between the M instances to obtain the logic block path dictionary.

10. The method according to claim 1, characterized in that Determining H target logical block access sequences based on the logical block path dictionary includes: Determine a starting logical block address from the logical block path dictionary, wherein the starting logical block address is a target access sequence in a valid state in the logical block path dictionary; Querying a first logic block address from the logic block path dictionary according to a first query direction, wherein the first query direction is a direction at a time before the starting logic block address; Querying a second logical block address from the logical block path dictionary according to a second query direction, wherein the second query direction is a direction at a time after the starting logical block address; H target logical block access sequences are determined using the first logical block address, the starting logical block address, and the second logical block address.

11. The method according to claim 10, characterized in that Determining H target logical block access sequences by using the first logical block address, the starting logical block address, and the second logical block address, comprises: In a case where a logical block address before the first logical block address is an invalid logical block address, and a logical block address after the second logical block address is the invalid logical block address, constructing a logical block address path according to a time sequence between the first logical block address, the starting logical block address, and the second logical block address; The access paths included in the logical block address path are determined as H target logical block access paths.

12. The method according to claim 10, characterized in that After determining H target logical block access sequences using the first logical block address, the starting logical block address, and the second logical block address, the method further includes: Deleting the logical block addresses corresponding to the H target logical block access sequences in the logical block path dictionary; or, The logical block addresses corresponding to the H target logical block access sequences are set to an invalid state in the logical block path dictionary.

13. The method according to claim 1, characterized in that After determining H target logic block access sequences based on the logic block adjacency matrix, the method further includes: The initial pre-reading model is trained using the H target logic block access sequences to obtain the pre-reading model, wherein the initial pre-reading model includes a fusion subnetwork and a classification subnetwork, and for each group of the H target logic block access sequences, the fusion subnetwork is used to fuse sequence features in the H target logic block access sequences, and the classification subnetwork is used to classify and identify logic block areas based on the fused sequence features.

14. A data processing device, characterized in that: include: The data port, processing chip and storage device port are connected in sequence, where: The data port is connected to the solid-state storage device and is used to transmit an access sequence set for collecting logical block addresses from the solid-state storage device; The processing chip is provided with the method described in any one of claims 1 to 13; The storage device port is connected to the pre-reading device in the solid-state storage device, and is used to store H target logic block access sequences and transmit the H target logic block access sequences to the pre-reading device.

15. The device according to claim 14, characterized in that The processing chip is equipped with a hotspot area screening device, a matrix building device and a path field processing device, wherein: The hotspot area screening device is used to screen out M target logic block areas from the N logic block areas when receiving the access sequence set, wherein the hotspot area screening device includes an adder and a first comparator; The matrix building device is used to build the logic block adjacency matrix of the M target logic block areas, wherein the matrix building device includes a first storage device, an adder, and a second comparator; The path field processing device is used to process the logic block adjacency matrix to obtain a logic block path dictionary.

16. A device for determining a logical block address access sequence, characterized in that: include: A first acquisition module is used to acquire an access sequence set of a logic block address from a solid-state storage device, wherein the access sequence set includes a plurality of access sequences, and the access sequence is a time sequence of performing access operations in the order of N logic block areas included in the solid-state storage device, where N is a natural number greater than 1; A first determination module is used to determine M target logic block areas from the N logic block areas by using the access sequence set, wherein the M target logic block areas are all areas whose data access frequency is greater than a preset access frequency, and M is a natural number less than or equal to N; A first construction module is used to construct a logic block adjacency matrix of the M target logic block regions, wherein the logic block adjacency matrix is ​​used to represent the transfer frequency between the M target logic block regions; A second determination module is used to determine H target logic block access sequences based on the logic block adjacency matrix, wherein the H target logic block access sequences are used to train a pre-reading model, and the pre-reading model is used to output a logic block area to be accessed during the process of performing the access operation on the solid-state storage device, and H is a natural number greater than or equal to M; The second determination module is also used to store the logical block address and the corresponding target transfer logical block address in a table to obtain M tables, wherein one target transfer logical block address corresponds to one table, and the table includes the logical block address and the corresponding target transfer logical block address; use the M tables to build a logical block path dictionary; and determine H target logical block access sequences based on the logical block path dictionary.

17. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 13 are implemented.

18. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 1 to 13 when executed by a processor.

19. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method described in any one of claims 1 to 13 are implemented.

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