Cache operation method and device, computer readable storage medium and electronic equipment

Abstract

The invention discloses a cache operation method and device, a computer readable storage medium and electronic equipment. The cache operation method comprises the steps that a data reading request for object data is received in response to a first cache, a target cache line is allocated for the object data in the first cache, target position information of the object data in the target cache line is determined, and the target position information is independent of storage address information of the object data; and after the first cache receives the object data, writing the object data into the target cache line according to the target position information. According to the cache operation method, the cache utilization rate and the data access efficiency can be improved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a cache operation method and cache operation device, a computer-readable storage medium, and an electronic device. Background Art

[0002] In computer architecture, data interaction between processors and memory is affected by physical distance and data granularity mismatch, which will lead to access delay and bandwidth waste. Adding cache between processors and memory can improve data transmission efficiency. However, the alignment of the data address corresponding to the data read request issued by the processor is inconsistent with the cache line requirement in the cache, which may lead to cache space waste. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a cache operation method, comprising: in response to a first cache receiving a data read request for object data, allocating a target cache line for the object data in the first cache, and determining target location information of the object data in the target cache line, wherein the target location information is independent of storage address information of the object data; and after the first cache receives the object data, writing the object data into the target cache line according to the target location information.

[0004] For example, in the cache operation method provided in an embodiment of the present disclosure, it also includes: after sending the object data from the first cache in response to the data read request, marking the target cache line as free.

[0005] For example, in the cache operation method provided in an embodiment of the present disclosure, before allocating the target cache line for the object data in the first cache, it also includes: receiving a cache operation mode signal, instructing the first cache to operate in a buffer mode for the data read request, wherein in the buffer mode the target location information is independent of the storage address information of the object data.

[0006] For example, in the cache operation method provided in one embodiment of the present disclosure, it also includes: in response to the cache operation mode signal and in response to the object data not being cached in the first cache, the first cache operates in a buffering mode for the data read request to indicate that the target cache line is allocated for the object data in the first cache.

[0007] For example, in a cache operation method provided in an embodiment of the present disclosure, allocating the target cache line for the object data in the first cache includes: selecting a target cache group; and selecting the target cache line in the target cache group.

[0008] For example, in the cache operation method provided in an embodiment of the present disclosure, selecting the target cache line in the target cache group includes: in response to the number of free cache lines in the target cache group being greater than or equal to the required number of target cache lines, selecting a free cache line in the target cache group for the target cache line, or in response to the number of free cache lines in the target cache group being less than the required number of target cache lines, evicting at least part of the non-free cache lines in the target cache group so that the number of free cache lines in the target cache group is greater than or equal to the required number of target cache lines, and then selecting a free cache line in the target cache group for the target cache line.

[0009] For example, in the cache operation method provided in an embodiment of the present disclosure, it also includes: storing the target location information in a first storage unit; wherein, writing the object data into the target cache line according to the target location information includes: reading the target location information from the first storage unit; and writing the object data into the target cache line according to the read target location information.

[0010] For example, in the cache operation method provided in one embodiment of the present disclosure, it also includes: adding the target location information to the data read request to obtain a collaborative data read request, and sending the collaborative data read request to read the object data; wherein, writing the object data to the target cache line according to the target location information includes: obtaining the object data and the target location information from the information returned according to the collaborative data read request; and writing the object data to the target cache line according to the obtained target location information.

[0011] For example, in the cache operation method provided in an embodiment of the present disclosure, it also includes: sending the data read request to a downstream cache or memory of the first cache to receive the object data from the downstream cache or memory.

[0012] For example, in a cache operation method provided in an embodiment of the present disclosure, the size of the object data is an integer multiple of the size of a single cache line in the first cache.

[0013] For example, in a cache operation method provided in an embodiment of the present disclosure, the object data includes multiple sub-data parts, and the target location information includes multiple sub-location information corresponding to the multiple sub-data parts in the target cache line.

[0014] At least one embodiment of the present disclosure provides a cache operation device for a first cache, comprising: a determination device and a writing device.

[0015] The determining device is configured to, in response to the first cache receiving a data read request for object data, allocate a target cache line for the object data in the first cache and determine target location information of the object data in the target cache line, wherein the target location information is independent of storage address information of the object data; and the writing device is configured to write the object data into the target cache line according to the target location information after the first cache receives the object data.

[0016] At least one embodiment of the present disclosure provides a non-transitory computer-readable storage medium for non-transitory storage of computer-readable instructions, which, when executed by a computer, implements the cache operation method provided by any embodiment of the present disclosure.

[0017] At least one embodiment of the present disclosure provides a cache operation device for a first cache, comprising: a processing unit; and a storage unit, comprising at least one computer program module; wherein the at least one computer program module is stored in the storage unit and is configured to be executed by the processing unit, and the at least one computer program module includes instructions for implementing the cache operation method provided by any embodiment of the present disclosure.

[0018] At least one embodiment of the present disclosure provides an electronic device, including the cache operation device provided by any embodiment of the present disclosure.

[0019] For example, in an electronic device provided in an embodiment of the present disclosure, the electronic device includes a processor core, and the processor core includes the first cache and is configured to send the data read request.

[0020] For example, in an electronic device provided by an embodiment of the present disclosure, the first cache includes the cache operation device provided by any embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0022] Figure 1 The schematic diagram of the mapping relationship between memory and cache is shown;

[0023] Figure 2 A schematic diagram showing a cache set associative organization and addressing mode;

[0024] Figure 3 A flowchart of a cache operation method provided by at least one embodiment of the present disclosure is shown;

[0025] Figure 4 A flowchart showing an application example of a cache operation method provided by at least one embodiment of the present disclosure;

[0026] Figure 5 A schematic block diagram of a cache operation device provided by at least one embodiment of the present disclosure is shown;

[0027] Figure 6 A schematic diagram showing a computer-readable storage medium provided by at least one embodiment of the present disclosure is shown;

[0028] Figure 7 A schematic block diagram of another cache operation device provided by at least one embodiment of the present disclosure is shown;

[0029] Figure 8 A schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown; and

[0030] Fig. 9 A schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0032] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0033] Data interaction between the processor and the memory (abbreviated as "memory") is the core link for computers to perform tasks. However, due to the physical distance between the computing unit in the processor and the memory, and the mismatch in data granularity, direct access to the memory may cause significant delays and bandwidth waste. In order to alleviate this problem, for example, a strategy of adding a cache between the computing unit of the processor and the memory can be adopted; the cache can include multiple levels of cache, such as the first level cache (L1), the second level cache (L2), etc.

[0034] The capacity of the cache is very small, and the data stored in the cache is only a subset of the data in the memory, and the data exchange between the cache and the memory is in units of data blocks. In order to cache the data in the memory into the cache, it is necessary to apply a certain function to locate the memory address to the cache, which is called address mapping. After the data in the memory is stored in the cache according to this mapping relationship, when the CPU executes the program, it will transform the memory address in the program into the cache address. The address mapping method of the cache can be, for example, direct mapping, fully associative or set associative mapping.

[0035] Although the capacity of the cache is smaller than that of the memory, the speed is much faster than that of the memory. Therefore, the main function of the cache is to store data that the processor may need to access frequently in the near future. In this way, the processor can directly read data from the cache without frequently accessing the slower memory, thereby increasing the processor's access speed to the memory. The basic unit of the cache is a cache block or cache line. Similar to the division of the cache into multiple cache blocks, the data stored in the memory is also similarly divided. The divided data blocks in the memory are called data blocks or memory blocks. For example, the size of a memory block can be 4KB (kilobyte). For example, the size of a cache block can be 32B, 64B, 128B or 256B, etc. It is understandable that in actual applications, the size of the memory block and cache line can also be set to other values.

[0036] The mapping relationship between memory and cache in direct associative, fully associative and set associative is as follows: Figure 1 As shown in Figure 1. Divide both the memory and cache into blocks of equal size. Assume that the memory has 32 items and the cache has 8 items. In the direct associative mode, each memory block can only be placed in one location in the cache. Figure 1 As shown in (a), suppose you want to put the 12th block of memory into the cache. Since the cache has only 8 items, it can only be placed on the (13mod 8=5)th item (i.e., the 4th item), and cannot be placed anywhere else. Therefore, it can be seen that the 4th, 12th, 20th, and 28th memory blocks all correspond to the 4th item of the cache. If there is a conflict, they can only be replaced. The hardware required for the direct connection method is simple but inefficient. Figure 1As shown in (b) in the full associative mode, each memory block can be placed in any position of the cache, so that the 4th, 12th, 20th, and 28th memory blocks can be placed in the cache at the same time. The hardware required for the full associative mode is complex but efficient. Set associativity is a compromise between direct associativity and full associativity. Figure 1 As shown in (c) in the figure, taking two-way set associative as an example, the cache positions 0, 2, 4, and 6 are one way (here called way 0), and positions 1, 3, 5, and 7 are another way (here called way 1), with 4 blocks in each way. For the 12th block of the memory, since the remainder of 13 divided by 4 is 1, the 12th block can be placed in the 0th position of the 0th way of the cache (i.e., the 0th position of the cache), or in the 0th position of the 1st way (i.e., the 1st position of the cache).

[0037] Figure 2 FIG. 1 shows a schematic diagram of a cache set associative organization and addressing method. Figure 2 As shown in the figure, the cache is organized in the form of an array of cache lines. A column of cache lines constitutes a way, and multiple cache lines at the same position in multiple columns of cache lines constitute a set. The location of the data or instruction in the cache is obtained by the physical address of the data or instruction to be read (set, way, byte). Each physical address is divided into three parts:

[0038] Index, which is used to select a set in the cache. All cache lines in the same set are selected by the index.

[0039] Tag, used to select a specific cache line in a set. The tag of the physical address is compared with the tag of each cache line. If they match, it is a cache hit, thus selecting this cache line. Otherwise, it is a cache miss.

[0040] The offset is used to select the corresponding address in the cache line. It indicates the first byte of the physical address in the cache line. The corresponding data or instruction is read from the position of this byte.

[0041] The inventors of the present disclosure have noticed that the efficiency of memory access is improved because the cache makes full use of the time and space limitations of memory access. The time limitation can be used to indicate that the data currently being accessed is likely to be accessed repeatedly in a short period of time. Therefore, temporarily storing the currently accessed data in a cache closer to the processor's computing unit can significantly speed up subsequent access to these data. The space limitation can be used to indicate that the data adjacent to the currently accessed data is also highly likely to be accessed. Therefore, when reading the requested data from the memory, the adjacent data of the requested data can be retrieved in blocks and temporarily stored in the cache for subsequent quick access. In order to accurately search for data in the cache, the cache usually adopts a strict address mapping mechanism so that each access to the same address can follow the same mapping logic, so that the same position in the cache can be located and the data can be correctly obtained.

[0042] However, for example, in a processor (such as a processor that supports vector operations), when an instruction processes multiple data at the same time, if the address alignment of these multiple data is inconsistent with the requirements of the cache line, then the data that could originally be accommodated in one cache line may be scattered across multiple different cache lines, thereby causing a waste of cache space and affecting cache efficiency.

[0043] For example, for data that will not be repeatedly accessed in the short term (i.e., in the current task process), the cache actually only serves as a buffer. In this case, if the cache still performs a strict address mapping mechanism during work, it may cause a waste of cache space resources.

[0044] At least one embodiment of the present disclosure provides a cache operation method and cache operation device, an electronic device, and a computer-readable storage medium.

[0045] The cache operation method of at least one embodiment of the present disclosure includes: in response to a first cache receiving a data read request for object data, allocating a target cache line for the object data in the first cache, and determining target location information of the object data in the target cache line, wherein the target location information is independent of the storage address information of the object data; and after the first cache receives the object data, writing the object data into the target cache line according to the target location information. The embodiments of the present disclosure can optimize the use of cache space, reduce resource waste of cache space, and improve cache utilization and data access efficiency by decoupling object data storage address information from target location information in a cache line, allocating a cache set, and processing target location information.

[0046] Figure 3 A flowchart of a cache operation method provided by at least one embodiment of the present disclosure is shown.

[0047] like Figure 3 As shown, the method may include steps S100 to S110.

[0048] Step S100: in response to a first cache receiving a data read request for object data, allocating a target cache line for the object data in the first cache, and determining target location information of the object data in the target cache line.

[0049] Step S110: after the first cache receives the object data, the object data is written into the target cache line according to the target location information.

[0050] For the above step S100, for example, the cache may include multiple levels of cache, and the first cache may include a first level cache (L1 Cache) or a second level cache (L2 Cache), etc., which is not limited in the embodiments of the present disclosure.

[0051] For example, a data read request for object data sent by a processor may be received by the first cache. Here, the processor may include, for example, a CPU (or a CPU core), a graphics processing unit (GPU), a coprocessor (such as an AI accelerator), etc., and the embodiments of the present disclosure are not limited to this.

[0052] For example, one or more cache lines may be allocated in the first cache as target cache lines for the object data to be received. For example, any one or more cache lines that are currently in an idle state (e.g., cache lines marked as invalid) may be determined as target cache lines. For example, a cache line in which other data is already stored may be replaced as a target cache line according to a specific replacement strategy (e.g., Least Recently Used (LRU) or First In First Out (FIFO) strategy).

[0053] After the target cache line is determined, for example, the specific storage location of the object data in the target cache line, that is, the target location information, can be determined. For example, the target location information can be an offset to indicate the starting position of the object data in the target cache line; for another example, the target location information can also be an index to identify the specific location of the object data in the target cache line, and the embodiments of the present disclosure are not limited to this. Here, "object data" is used to refer to any data that is a processing object, and the present disclosure does not limit the data type, etc.

[0054] It should be noted that the target location information in the embodiment of the present disclosure is independent of the storage address information of the object data in the memory, that is, the target location information and the address information of the object data are decoupled, and the target location information is not obtained by the storage address information of the object data in the memory through a mapping relationship. In the embodiment of the present disclosure, the target location information is decoupled from the address information, so that the first cache can store the object data more flexibly without being restricted by the storage address information of the object data.

[0055] Through step S100, the first cache can prepare corresponding storage space for the object data to be received, so that the object data can be accurately written to the corresponding position of the target cache line, thereby improving the access efficiency of the cache, reducing data access latency and maintaining data consistency. At the same time, by decoupling the storage address information of the object data and the target location information in the cache, the cache has higher flexibility and scalability.

[0056] For example, in some embodiments of the present disclosure, after step S100, the cache operation method further includes: sending a data read request to a downstream cache or memory of the first cache to receive object data from the downstream cache or memory.

[0057] For example, when the first cache receives a data read request for object data, it can confirm whether the object data is stored in the first cache. If the object data is not cached in the first cache, the object data can be obtained from a downstream cache or memory of the first cache, that is, the data read request is sent to a downstream cache of the first cache or to the memory. For example, the downstream cache of the first cache is a second cache or a third cache, or the downstream cache of the second cache is a third cache or a last level cache (LLC).

[0058] For example, if the object data exists in the downstream cache of the first cache, the downstream cache of the first cache can provide the object data to the first cache; if the object data does not exist in the downstream cache of the first cache, the data read request can continue to be sent to a lower-level cache or to the memory, so that when the first cache does not store the object data, the object data can be obtained from the downstream cache or the memory to meet the data read request and maintain the validity of the cache.

[0059] In addition, for the above step S110, after the first cache receives the object data provided by the next-level cache or the memory, the object data may be written into the target cache line according to the above-determined target location information.

[0060] Through step S110, after receiving the object data provided by the next level cache or memory, the first cache can accurately write the object data to the previously allocated target cache line for storage according to the target location information, which helps to improve the access efficiency of the first cache and reduce access latency, and also helps to maintain data synchronization between multiple cache levels or processors and caches.

[0061] In some embodiments of the present disclosure, the cache operation method may further include the following steps:

[0062] Step S120: after sending the object data from the first cache in response to the data read request, marking the target cache line as free.

[0063] For step S120, for example, after the first cache receives a data read request from the processor for object data and writes the object data into the target cache line through the operation of the aforementioned step S110, the first cache provides the object data to the processor as a response to the data read request from the processor for the object data.

[0064] After the object data is provided to the processor, for example, if the object data will not be repeatedly accessed in the short term, the target cache line in the first cache may no longer store the object data. For example, marking the target cache line as free may mark the target cache line as invalid to indicate that the target cache line can be used to store new data.

[0065] It should be noted that marking the target cache line as free does not affect other subsequent operations on the first cache. For example, the processor can still send data read or write requests to the first cache, and the first cache can process these data read requests according to the current status of each cache line and the corresponding replacement strategy.

[0066] For example, after marking the target cache line as free, for a subsequent new data read request or data write request, the first cache system may reallocate and use the target cache line.

[0067] Through step S120 , the first cache can effectively manage the state of the target cache line, which helps to improve the space utilization and overall performance of the cache.

[0068] In some embodiments of the present disclosure, before allocating a target cache line for the object data in the first cache, the cache operation method may further include: receiving a cache operation mode signal to instruct the first cache to operate in a buffering mode for a data read request.

[0069] Among them, in the buffer mode, the target location information is independent of the storage address information of the object data. Further, for example, in the buffer mode, the method of determining the target location information is different from that in the usual cache mode, that is, the target location information is no longer determined by the storage address information of the object data through a strict mapping relationship. Here, the method of determining the target location information can, for example, refer to the relevant descriptions of other embodiments of the present disclosure, which will not be repeated here; and, in the buffer mode, when a data read request for the object data is sent to the downstream cache or memory of the first cache, the method of processing the target location information (described below) is also different from that in the usual cache mode. This means that the current cache can work in both the usual cache mode and the buffer mode according to the control.

[0070] For example, in response to receiving a cache operation mode signal, the first cache operates in a buffer mode for a data read request, that is, the first cache acts as a buffer and can use a target cache line of the first cache to cache and store the object data.

[0071] For example, the cache operation mode signal may come from the upper system (such as an operating system or a memory manager), a processor or a compiler of the first cache, and the embodiments of the present disclosure are not limited to this. Exemplarily, when compiling a program, the compiler may analyze the instructions and the object data corresponding to the instructions, and determine which data data reading operations can be applied to the buffer mode operation. For example, the compiler may embed the cache operation mode signal indication information in the data reading instruction (such as a Load instruction) of the object data to instruct the first cache to switch to the buffer mode operation when executing the data reading instruction.

[0072] It should be noted that, in the buffer mode, the storage location of the object data in the first cache (i.e., the target location information) is independent of the storage address information of the object data in the memory, that is, the target location information and the storage address information of the object data are decoupled. For a specific description, for example, please refer to the relevant description of the aforementioned embodiment, which will not be repeated here.

[0073] In some embodiments of the present disclosure, the cache operation method also includes: in response to a cache operation mode signal and in response to the object data not being cached in the first cache, the first cache operates in a buffering mode for a data read request to indicate that a target cache line is allocated for the object data in the first cache.

[0074] For example, when the first cache does not cache the object data, the first cache switches to the buffering mode in response to receiving the cache operation mode signal.

[0075] For example, before sending the cache operation mode signal to the first cache, the cache operation method may further include checking whether the object data is cached in the first cache. For example, in addition to checking whether the object data is cached in the first cache, the usage frequency of the object data in a short period of time may be further confirmed. For example, it may be confirmed whether the usage frequency of the object data in a short period of time is 1 time, that is, the object data may only be used once in the current task process.

[0076] For example, after receiving a data read request for object data, if the object data is not cached in the first cache and the object data is used once in a short period of time, a cache operation mode signal is sent to the first cache, so that the first cache switches to buffer mode.

[0077] The operation of the first cache operating in a buffer mode for a data read request to indicate allocating a target cache line for the object data in the first cache may also refer to the related description of the aforementioned embodiment, which will not be repeated here.

[0078] In at least one embodiment of the present disclosure, when the first cache receives a cache operation mode signal and determines that the required object data has not been cached within the first cache, the first cache can operate in a buffering mode, thereby allocating corresponding target cache lines for the object data, so that the cache can efficiently process data read requests.

[0079] In some embodiments of the present disclosure, allocating a target cache line for object data in a first cache includes: selecting a target cache group and selecting a target cache line in the target cache group.

[0080] In the cache operation method, allocating a target cache line for object data may, for example, involve selecting a corresponding target cache set and selecting one or more target cache lines in the target cache set.

[0081] For example, when the first cache receives a data read request for object data, a corresponding target cache group may be selected according to the current cache data status in each cache group.

[0082] For example, a cache group in which all cache lines in the cache group are in an idle state can be determined as the target cache group; for example, a cache group in which a large number of cache lines in an idle state are determined as the target cache group; for example, a cache group in which data stored in the cache group is less frequently used can be determined as the target cache group; for example, a cache group in which any cache line in an idle state is determined as the target cache group, and the embodiments of the present disclosure are not limited thereto.

[0083] For example, after the target cache group is determined, one or more cache lines may be determined as the target cache line according to the conditions of each cache line in the target cache group.

[0084] For example, the target cache line in the target cache group may be determined according to the data width and quantity of the object data.

[0085] For example, the target cache line in the target cache group may also be determined according to the data width and quantity of the object data and the status of each cache line in the target cache group.

[0086] In at least one embodiment of the present disclosure, the process of allocating a target cache line for object data in a first cache includes selecting a target cache group, and selecting one or more free or replaceable cache lines in the target cache group as target cache lines, and determining the target location information of the object data in the cache line. This process enables the cache to effectively manage its storage space and provide efficient responses to data access requests.

[0087] In some embodiments of the present disclosure, selecting a target cache line in a target cache group may further include: in response to the number of free cache lines in the target cache group being greater than or equal to the required number of target cache lines, selecting a free cache line in the target cache group for the target cache line.

[0088] For example, after the target cache group is determined, the number of cache lines in the target cache group that are in an idle state may be confirmed.

[0089] Here, an idle cache line (eg, a cache line in an idle state) refers to a cache line that currently does not store valid data and can be used to store new data.

[0090] For example, the number of free cache lines in the target cache group can be compared with the required number of target cache lines. If the number of free cache lines in the target cache group is greater than or equal to the required number of target cache lines, the required number of cache lines can be selected from the free cache lines as target cache lines to store object data.

[0091] For example, the selection process of selecting a target cache line from free cache lines may be based on a corresponding selection strategy, such as a sequential selection strategy, a random selection strategy, or a selection strategy based on other optimization considerations, etc., which is not limited in the embodiments of the present disclosure.

[0092] In some embodiments of the present disclosure, selecting a target cache line in a target cache group may also include: in response to the number of free cache lines in the target cache group being less than the required number of target cache lines, evicting at least some non-free cache lines in the target cache group so that the number of free cache lines in the target cache group is greater than or equal to the required number of target cache lines, and then selecting a free cache line in the target cache group for the target cache line.

[0093] When the first cache receives a data read request for the object data and determines the target cache group, the number of free cache lines in the target cache group can be confirmed. If the number of free cache lines in the target cache group is less than the required number of target cache lines, a corresponding operation can be performed to increase the number of free cache lines in the target cache group.

[0094] For example, the data stored in which non-free cache lines can be evicted can be determined according to the eviction policy. Here, the eviction policy may include, for example, an LRU (Least Recently Used) policy, an LFU (Least Frequently Used) policy, or a random eviction policy, etc., which is not limited in the embodiments of the present disclosure.

[0095] For example, the data of the evicted cache line may be written back to the downstream cache of the first cache, the memory or other storage medium. For example, if it is determined that the evicted data is clean, the data may be directly discarded. The embodiments of the present disclosure are not limited to this.

[0096] For example, after a non-free cache line is evicted, the state of each cache line in the target cache group may be updated to reflect the increase in the number of free cache lines.

[0097] For example, after the non-free cache lines are evicted, the number of free cache lines reaches or exceeds the required number of target cache lines, and the required number of cache lines may be selected from the free cache lines of the target cache group as target cache lines.

[0098] In at least one embodiment of the present disclosure, when there are insufficient free cache lines in the target cache group, the number of free cache lines can be increased by evicting some non-free cache lines, thereby meeting the demand for storing object data, helping to optimize cache usage and increase data access speed.

[0099] In some embodiments of the present disclosure, the cache operation method further includes: storing target location information in the first storage unit. Writing the object data into the target cache line according to the target location information includes: reading the target location information from the first storage unit; and writing the object data into the target cache line according to the read target location information.

[0100] For example, after the target position information of the object data in the target cache line is determined, the target position information may be stored in the first storage unit for use in a subsequent object data writing process.

[0101] For example, when the first cache receives a data read request for object data, it allocates a target cache line for the object data and determines target location information of the object data in the target cache line.

[0102] Here, the first storage unit may include, for example, a buffer zone in the first cache (ie, a storage device used as a buffer in addition to a storage array for cache lines in the first cache itself) or other storage media, etc., and the embodiments of the present disclosure are not limited to this.

[0103] For example, when the first cache receives object data provided by its next level cache or memory, the target location information stored in the first storage unit can be read from the first storage unit. Exemplarily, when the first cache receives object data provided by the next level cache or memory, the target location information corresponding to the object data can be obtained from the first storage unit by query. After reading the target location information corresponding to the object data, the object data can be written to the target cache line of the first cache according to the target location information.

[0104] In at least one embodiment of the present disclosure, by separating the target location information from the data read request and storing the target location information in the first storage unit, the object data can be accurately written to the target cache line in the first cache, the cache storage space can be effectively managed, and an efficient response can be provided for data access requests.

[0105] In some embodiments of the present disclosure, the cache operation method further includes: adding the target location information to the data read request to obtain a coordinated data read request, and sending the coordinated data read request to read the object data. According to the target location information, writing the object data into the target cache line includes: acquiring the object data and the target location information from the information returned according to the coordinated data read request; and writing the object data into the target cache line according to the acquired target location information.

[0106] For example, after determining the target location information of the object data in the target cache line, the target location information may be added to a data read request to obtain a coordinated data read request, and the coordinated data read request may be sent to a next level cache or memory of the first cache.

[0107] Here, the collaborative data reading request may include, for example, an identifier of the required object data and target location information corresponding to the object data.

[0108] For example, after receiving the collaborative data read request, the next-level cache or memory of the first cache may retrieve the object data according to the data read request information for the object data carried in the collaborative data read request.

[0109] For example, the retrieved object data and the target location information carried in the collaborative data read request may be packaged together to form returned information and provided to the first cache.

[0110] For example, after receiving the returned information, the first cache may parse or extract the object data and target location information contained therein from the returned information.

[0111] For example, the object data may be written into a target cache line of the first cache according to the extracted target location information.

[0112] In at least one embodiment of the present disclosure, by forming a collaborative data read request including target location information, object data can be accurately written to the target cache line of the first cache, thereby improving cache utilization, reducing data access latency, and improving the overall performance of the cache.

[0113] In some embodiments of the present disclosure, the size of the object data is an integer multiple of the size of a single cache line in the first cache.

[0114] For example, the size of the cache line may be configured to be 64 bytes, 128 bytes, etc., which is not limited in the embodiments of the present disclosure.

[0115] For example, the size of the object data may be an integer multiple of the cache line size.

[0116] For example, if the size of each cache line in the first cache is configured to be 64 bytes, then the size of the object data may be 64 bytes, 128 bytes, 192 bytes, or 256 bytes, etc., which is not limited in the embodiments of the present disclosure.

[0117] For example, when the size of the object data is an integer multiple of the cache line size, the object data can be fully aligned to the cache line boundary, which helps reduce the performance loss caused by data alignment issues. In addition, the object data can fill several cache lines, so it will not cause partial free space or "fragmentation" of the cache line, thereby improving the utilization of the cache. In addition, the size of the object data is an integer multiple of the cache line size, which makes it easier to manage the storage and access of the object data in the cache.

[0118] In some embodiments of the present disclosure, the object data includes multiple parts, which may be referred to as sub-data parts, and the target location information includes multiple sub-location information corresponding to the multiple sub-data parts in the target cache line.

[0119] For example, the target location information may not only indicate the storage location of the object data as a whole in the target cache line, but may also further indicate the specific storage location of each sub-data portion in the object data in the target cache line. Thus, for each sub-data portion in the object data, there is corresponding sub-location information to indicate the storage location of each sub-data portion in the target cache line.

[0120] Exemplarily, in an object data consisting of three integer fields, each integer field occupies 4 bytes, for example. If the size of the target cache line is configured as 64 bytes, and the target cache line has been allocated for storing the object data, then the target location information may include three sub-location information, wherein the first sub-location information may be used to indicate the starting position of the first integer field in the target cache line (such as a 0-byte offset), the second sub-location information may be used to indicate the starting position of the second integer field in the target cache line (such as a 4-byte offset), and the third sub-location information may be used to indicate the starting position of the third integer field in the target cache line (such as an 8-byte offset).

[0121] The above configuration of object data size and cache line size can enable cache operations to more finely control the storage and access of object data, and can also enable the cache to independently access or modify each sub-data portion in the object data without moving or copying the entire object data, thereby improving data organization and access efficiency, and helping to reduce unnecessary cache line conflicts and replacements.

[0122] Figure 4 A flowchart showing an application example of a cache operation method provided by at least one embodiment of the present disclosure is shown.

[0123] The following is an exemplary description of a cache operation method provided by at least one embodiment of the present disclosure. Figure 4 As shown, the cache operation method includes steps S200-S290.

[0124] Step S200: The first cache receives a data read request for object data.

[0125] For example, the first cache may receive a data read request for object data sent by a processor (eg, a CPU or a GPU).

[0126] Step S210: allocating a target cache line for the object data in the first cache according to the order in which the data read request is received, and determining target position information of the object data in the target cache line.

[0127] For example, the processor may send one or more data read requests for the object data to the first cache. When the first cache receives the one or more data read requests, it may allocate a corresponding target cache line for the object data in the cache according to the order in which the data read requests are received, and determine the target location information of the object data in the target cache line. The method of allocating a target cache line for the object data in the first cache and determining the target location information of the object data in the target cache line may also refer to the relevant description in the aforementioned embodiment, and will not be repeated here.

[0128] Step S220: Record target location information.

[0129] For example, after the target location information is confirmed, the target location information may be recorded for use in subsequent operations.

[0130] Step S230: Processing the target location information when sending a data read request.

[0131] For example, before sending a data read request for the object data to a cache at a next level of the first cache (eg, a second cache), the target location information may be processed.

[0132] For example, processing the target location information includes at least two processing methods (method 1 and method 2 described below).

[0133] For example, in method 1, the target location information may be added to the data read request to obtain a coordinated data read request, which is then sent to a downstream cache or memory of the first cache (ie, step S240).

[0134] For example, in the second method, the target location information may be temporarily stored, for example, the target location information may be stored in a first storage unit (ie, step S260 ).

[0135] For example, the processing method for the target location information may be preconfigured. For example, the method of the above-mentioned "method 1" may be preconfigured to process the target location information, and then after step S220, step S240 may be directly entered without executing steps S230 and S260.

[0136] For another example, the method of "method 2" described above may be pre-configured to process the target location information. Then, after step S220, the process may directly proceed to step S260 without executing steps S230 and S240.

[0137] Step S240: adding the target location information to the data read request to obtain a coordinated data read request, and sending the coordinated data read request to a downstream cache or memory of the first cache.

[0138] For example, the target location information may be added to the data read request to form a coordinated data read request, which may include, for example, the original data read request and the additional target location information.

[0139] For example, after the coordinated data read request is formed, the coordinated data read request may be sent to a next-level cache or a memory of the first cache.

[0140] Step S250: The first cache receives the returned information.

[0141] For example, after receiving a collaborative data read request, the next-level cache or memory of the first cache can retrieve object data based on the data read request information carried in the collaborative data read request, and provide the retrieved object data and target location information as return information to the first cache, that is, the first cache receives the return information.

[0142] Step S260: storing the target location information in the first storage unit, and sending a data read request to a downstream cache or memory of the first cache.

[0143] For example, the target location information may be stored in a first storage unit, and the data read request may be sent to a next-level cache or a memory of the first cache. Here, the first storage unit may include a buffer of the first cache or other storage media.

[0144] Step S270: The first cache receives the returned information.

[0145] For example, after receiving the data read request, the next level cache or memory of the first cache can retrieve and return the object data. Here, the returned information includes the object data.

[0146] Step S280: Acquire target location information.

[0147] For step S280, if the previous step of step S280 is step S250, the target location information carried therein can be extracted from the returned information. If the previous step of step S280 is step S270, the target location information can be obtained from the first storage unit, for example, by querying the target location information from the first storage unit. After the target location information is obtained in step S280, step S290 is entered.

[0148] Step S290: writing the object data into the target cache line according to the target location information.

[0149] For example, the object data may be written into the target cache line of the first cache according to the target location information acquired in the aforementioned step S280 .

[0150] In at least one embodiment of the present disclosure, the cache operation method can efficiently process data read requests and target location information, so that object data can be accurately stored in the target cache line of the first cache, thereby improving cache utilization and data access efficiency.

[0151] Figure 5 A schematic block diagram of a cache operation device 300 provided by at least one embodiment of the present disclosure is shown.

[0152] For example, Figure 5 As shown, the cache operation device 300 includes a determination device 310 and a writing device 320 .

[0153] The determining device 310 is configured to, in response to the first cache receiving a data read request for the object data, allocate a target cache line for the object data in the first cache, and determine target location information of the object data in the target cache line. The target location information is independent of the storage address information of the object data. The determining device 310 may, for example, execute Figure 3 Step S100 described.

[0154] The writing device 320 is configured to write the object data into the target cache line according to the target location information after the first cache receives the object data. The writing device 320 may, for example, execute Figure 3 Step S110 described.

[0155] For example, in the cache operation device 300 provided in an embodiment of the present disclosure, the determination device 310 may also be configured to mark the target cache line as free after sending the object data from the first cache in response to the data read request.

[0156] For example, in the cache operation device 300 provided in an embodiment of the present disclosure, before allocating a target cache line for the object data in the first cache, the determination device 310 may also be configured to receive a cache operation mode signal, indicating that the first cache operates in a buffer mode for a data read request, wherein the target location information is independent of the storage address information of the object data in the buffer mode.

[0157] For example, in the cache operation device 300 provided in an embodiment of the present disclosure, the determination device 310 can also be configured to, in response to a cache operation mode signal and in response to the object data not being cached in the first cache, operate the first cache in a buffering mode for a data read request to indicate that a target cache line is allocated for the object data in the first cache.

[0158] For example, in the cache operation device 300 provided in an embodiment of the present disclosure, a target cache line is allocated to the object data in the first cache, and the determination device 310 can also be configured to select a target cache group; and select a target cache line in the target cache group.

[0159] For example, in the cache operation device 300 provided in an embodiment of the present disclosure, a target cache line is selected in a target cache group, and the determination device 310 can also be configured to select a free cache line in the target cache group for the target cache line in response to the number of free cache lines in the target cache group being greater than or equal to the required number of target cache lines, or to evict at least part of the non-free cache lines in the target cache group in response to the number of free cache lines in the target cache group being less than the required number of target cache lines, so that the number of free cache lines in the target cache group is greater than or equal to the required number of target cache lines, and then select a free cache line in the target cache group for the target cache line.

[0160] For example, in the cache operation device 300 provided in an embodiment of the present disclosure, the determining device 310 may also be configured to store the target location information in the first storage unit. The writing device 320 may also be configured to read the target location information from the first storage unit; and write the object data into the target cache line according to the read target location information.

[0161] For example, in the cache operation device 300 provided in an embodiment of the present disclosure, the determining device 310 may also be configured to add the target location information to the data read request to obtain the coordinated data read request, and send the coordinated data read request to read the object data. The writing device 320 may also be configured to obtain the object data and the target location information from the information returned according to the coordinated data read request; and write the object data into the target cache line according to the obtained target location information.

[0162] For example, in the cache operation device 300 provided in an embodiment of the present disclosure, the determination device 310 may also be configured to send a data read request to a downstream cache or memory of the first cache to receive object data from the downstream cache or memory.

[0163] For example, in the cache operation device 300 provided in an embodiment of the present disclosure, the size of the object data is an integer multiple of the size of a single cache line in the first cache.

[0164] For example, in the cache operation device 300 provided in an embodiment of the present disclosure, the object data includes multiple sub-data parts, and the target location information includes multiple sub-location information corresponding to the multiple sub-data parts in the target cache line.

[0165] For example, the determining device 310 and the writing device 320 may be hardware, software, firmware, or any feasible combination thereof. For example, the determining device 310 and the writing device 320 may be a dedicated or general circuit, chip, or device, or may be a combination of a processor and a memory. The embodiments of the present disclosure do not limit the specific implementation forms of the above-mentioned units.

[0166] It should be noted that in the embodiment of the present disclosure, each unit of the cache operation device 300 corresponds to each step of the aforementioned cache operation method. For the specific functions of the cache operation device 300, reference may be made to the relevant description of the cache operation method, which will not be repeated here. Figure 5 The components and structures of the cache operation device 300 shown are merely exemplary and non-limiting. The cache operation device 300 may further include other components and structures as required.

[0167] At least one embodiment of the present disclosure further provides a computer-readable storage medium, which is used to non-temporarily store computer-readable instructions, and when the computer-readable instructions are executed by a computer, the cache operation method provided by any of the above embodiments is implemented. By using the computer-readable storage medium, the utilization rate of the cache and the efficiency of data access can be improved.

[0168] Figure 6 A schematic diagram of a computer-readable storage medium provided by at least one embodiment of the present disclosure is shown. Figure 6 As shown, the computer-readable storage medium 400 is used to store computer-readable instructions 410. For example, when the computer-readable instructions 410 are executed by a computer, one or more steps in the cache operation method described above can be executed.

[0169] For example, the computer-readable storage medium 400 may be applied to an electronic device 600 (described below). For example, the relevant description of the computer-readable storage medium 400 may refer to the corresponding description of the cache operation method above, which will not be repeated here.

[0170] Figure 7 FIG. 2 is a schematic block diagram of another cache operation device provided by at least one embodiment of the present disclosure. Figure 7 As shown, the cache operation device 500 includes a processing unit 510 and a storage unit 520. Among them, one or more computer program modules are stored in the storage unit 520. The processing unit 510 is configured to run the one or more computer program modules, and the one or more computer program modules can perform one or more steps in the cache operation method described above when the processing unit 510 runs. The cache operation device 500 can improve the utilization rate of the cache and the efficiency of data access.

[0171] The storage unit 520 and the processing unit 510 may be interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0172] For example, the processing unit 510 may be a central processing unit (CPU), a graphics processing unit (GPU), or other forms of processing units with data processing capabilities and / or program execution capabilities, etc., and the embodiments of the present disclosure are not limited thereto. The processing unit 510 may also be a general-purpose processor or a dedicated processor, and may control other components in the cache operation device 500 to perform desired functions.

[0173] It should be noted that, in the embodiments of the present disclosure, the specific functions and technical effects of the cache operation device 500 may also refer to the above description of the cache operation method, and will not be repeated here.

[0174] At least one embodiment of the present disclosure provides an electronic device, which may include the cache operation device provided by any embodiment of the present disclosure. The cache operation device may include, for example, the cache operation device 300 or the cache operation device 500 provided by the aforementioned embodiment.

[0175] Figure 8 A schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0176] like Figure 8 As shown, the electronic device 600 includes a processor core 610 and a cache operation device 620. The cache operation device 620 may include, for example, a cache operation device provided by any of the aforementioned embodiments (e.g., the cache operation device 300 or the cache operation device 500). The processor core 610 may include, for example, a first cache, and the processor core 610 may also be configured to send a data read request to the first cache.

[0177] For example, the first cache may include a cache operation device 620 to perform cache operations to implement a cache operation method according to at least one embodiment of the present disclosure.

[0178] For example, when the processor core 610 needs to access data, the processor core 610 may send a data read request to the first cache. If the object data corresponding to the data read request is already in the first cache (cache hit), the data is directly read from the first cache. If the object data corresponding to the data read request is not in the cache (cache miss), and the object data corresponding to the data read request is used less frequently (for example, once), the cache operation device 620 may execute the cache operation method provided in any embodiment of the present disclosure to read the object data from the downstream cache or memory of the first cache, store it in the first cache, and provide the object data to the processor core 610.

[0179] Fig. 9 A schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0180] For example, Fig. 9 As shown, in some examples, the electronic device 700 includes a processor 701 and a random access memory (cache) 703.

[0181] For example, the processor 701 may include a processor provided by any embodiment of the present disclosure (eg, a central processing unit, a graphics processing unit, etc.).

[0182] For example, the processor 701 may include a cache (not shown in the figure, for example, it may be a first-level cache (L1Cache), etc.), and the cache may include the cache operation device provided by any embodiment of the present disclosure to perform a buffering operation, thereby realizing the cache operation method of at least one embodiment of the present disclosure. Alternatively, for example, the cache 703 may be a first-level cache (L1 Cache), etc.), and the cache 703 may include the cache operation device provided by any embodiment of the present disclosure to perform a buffering operation, thereby realizing the cache operation method of at least one embodiment of the present disclosure.

[0183] The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Fig. 9 The electronic device 700 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0184] For example, the processor 701 can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 702 or a program loaded from a storage device 708 into a cache 703. Various programs and data required for the operation of the computer system are also stored in the cache 703. The processor 701, the ROM 702, and the cache 703 are connected to each other via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0185] For example, the following components may be connected to the I / O interface 705: an input device 706 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 707 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 708 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 709 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 709 may allow the electronic device 700 to communicate with other devices wirelessly or by wire to exchange data, and perform communication processing via a network such as the Internet. The drive 710 is also connected to the I / O interface 705 as needed. Removable media 711, such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive 710 as needed, so that the computer programs read therefrom are installed into the storage device 708 as needed. Although Fig. 9 The electronic device 700 is shown to include various devices, but it should be understood that it is not required to implement or include all the devices shown. More or fewer devices may be implemented or included instead.

[0186] For example, the electronic device 700 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 709 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN) and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and techniques, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging and / or Short Message Service (SMS), or any other suitable communication protocol.

[0187] For example, the electronic device 700 can be any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, a server, etc., or it can be any combination of data processing devices and hardware, and the embodiments of the present disclosure are not limited to this.

[0188] There are a few points to note:

[0189] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0190] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0191] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A cache operation method, comprising: In response to the first cache receiving a data read request for object data, allocating a target cache line for the object data in the first cache, and determining target location information of the object data in the target cache line, wherein the target location information is independent of storage address information of the object data; and After the first cache receives the object data, the first cache writes the object data into the target cache line according to the target location information.

2. The method of claim 1, further comprising: After sending the object data from the first cache in response to the data read request, marking the target cache line as free.

3. The method according to claim 1 or 2, before allocating the target cache line for the object data in the first cache, further comprising: receiving a cache operation mode signal, indicating that the first cache operates in a buffer mode for the data read request, Wherein, in the buffer mode, the target location information is independent of the storage address information of the object data.

4. The method of claim 3, further comprising: In response to the cache operation mode signal and in response to the object data not being cached in the first cache, the first cache operates in a buffering mode for the data read request to indicate that the target cache line is allocated for the object data in the first cache.

5. The method according to any one of claims 1 to 4, wherein: Allocating the target cache line for the object data in the first cache includes: Selecting a target cache group; and The target cache line is selected in the target cache group.

6. The method of claim 5, wherein: Selecting the target cache line in the target cache group includes: In response to the number of free cache lines in the target cache group being greater than or equal to the required number of target cache lines, selecting a free cache line in the target cache group for the target cache line, or In response to the number of free cache lines in the target cache group being less than the required number of target cache lines, at least some of the non-free cache lines in the target cache group are evicted so that the number of free cache lines in the target cache group is greater than or equal to the required number of target cache lines, and then a free cache line is selected in the target cache group for the target cache line.

7. The method according to any one of claims 1 to 6, further comprising: Storing the target location information in a first storage unit; Wherein, writing the object data into the target cache line according to the target location information includes: Reading the target location information from the first storage unit; and The object data is written into the target cache line according to the read target location information.

8. The method according to any one of claims 1 to 6, further comprising: adding the target location information to the data read request to obtain a coordinated data read request, and sending the coordinated data read request to read the object data; Wherein, writing the object data into the target cache line according to the target location information includes: acquiring the object data and the target location information from the information returned according to the collaborative data read request; and The object data is written into the target cache line according to the acquired target location information.

9. The method according to any one of claims 1 to 8, further comprising: The data read request is sent to a downstream cache or memory of the first cache to receive the object data from the downstream cache or memory.

10. The method according to any one of claims 1 to 9, wherein: The size of the object data is an integer multiple of the size of a single cache line in the first cache.

11. The method according to any one of claims 1 to 10, wherein: The object data includes a plurality of sub-data parts, and the target location information includes a plurality of sub-location information corresponding to the plurality of sub-data parts in the target cache line.

12. A cache operation device, used for a first cache, comprising: a determining device configured to, in response to the first cache receiving a data read request for object data, allocate a target cache line for the object data in the first cache, and determine target location information of the object data in the target cache line, wherein the target location information is independent of storage address information of the object data; and The writing device is configured to write the object data into the target cache line according to the target location information after the first cache receives the object data.

13. A non-transitory computer-readable storage medium, used for non-transitory storage of computer-readable instructions, which, when executed by a computer, implements the cache operation method according to any one of claims 1 to 11.

14. A cache operation device, used for a first cache, comprising: Processing unit; as well as a storage unit comprising at least one computer program module; The at least one computer program module is stored in the storage unit and is configured to be executed by the processing unit, and the at least one computer program module includes instructions for implementing the cache operation method according to any one of claims 1-11.

15. An electronic device comprising the cache operation device according to claim 12 or 14.

16. The electronic device according to claim 15, wherein: The electronic device includes a processor core, which includes the first cache and is configured to send the data read request.

17. The electronic device according to claim 16, wherein: The first cache includes the cache operating device.

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