PCIe interface and direct connection interface multiplexing communication method and system based on CXL protocol

Abstract

The invention discloses a PCIe interface and direct connection interface multiplexing communication method and system based on a CXL protocol. The method comprises the steps that the value of a working mode selection register is read; in response to a PCIe interface mode indicated by the value of the working mode selection register, entering the PCIe interface mode after exiting the reset state, and performing communication through an external PCIe device; and in response to the value indication of the working mode selection register as a CXL direct connection interface mode, respectively configuring the coupling mode of the system, a reference clock, receiving end detection and low delay characteristics of a controller based on a physical layer PHY, and carrying out Die-to-Die communication through a user-defined direct connection packet. The PCIe interface and the CXL direct connection interface are combined into one, so that the hardware resource utilization rate of the system is greatly improved, and the system can be freely switched between the two modes according to actual requirements.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design and interconnection technology, and in particular to a PCIe interface and direct connection interface multiplexing communication method and system based on a CXL protocol. Background Art

[0002] In the prior art, PCIe interfaces and direct-connect interfaces in chips are usually implemented through independent hardware designs. In traditional system architectures, PCIe interfaces are mainly used for communication with external devices, such as hard disks, network cards and other peripherals. In order to achieve high-speed Die-to-Die communication in chips, it is usually necessary to design additional dedicated direct-connect interfaces, which complicates the system hardware design and requires more hardware resources and circuit wiring to be reserved for different interfaces, increasing development costs and space occupancy. In addition, independent PCIe and direct-connect interfaces make it difficult for the system to flexibly switch under different communication requirements, and the interface utilization rate is low, which cannot fully meet the diverse needs in different scenarios.

[0003] At the same time, the traditional chip direct connection interface lacks an effective processing mechanism for data cache consistency. When performing high-speed data transmission, data asynchrony or conflict problems are prone to occur, which in turn leads to unstable communication. Especially in high-performance computing and data-intensive applications, transmission efficiency and stability are limited. In addition, in existing interface designs, the physical layers for different protocols often need to be configured and managed independently, and system switching and debugging are complicated, which cannot flexibly respond to different application requirements. These problems have affected the communication performance and resource utilization efficiency of the overall system. Summary of the invention

[0004] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a method and system for multiplexing communication between a PCIe interface and a direct-connect interface based on the CXL protocol. By multiplexing the same hardware interface, both external PCIe device communication and Die-to-Die communication in the chip can be supported, thereby simplifying hardware design, improving interface utilization, and realizing flexible switching of the system under different communication requirements.

[0005] To achieve the above object, the present invention is implemented by adopting the following technical solutions: In a first aspect, the present invention provides a method for multiplexing communication between a PCIe interface and a direct-connect interface based on a CXL protocol, comprising: Read the value of the working mode selection register; In response to the value of the working mode selection register indicating the PCIe interface mode, entering the PCIe interface mode after exiting the reset state, and communicating through an external PCIe device; In response to the value of the working mode selection register indicating the CXL direct connection interface mode, the system coupling mode, reference clock, receiving end detection and low latency characteristics of the controller are configured based on the physical layer PHY, and Die-to-Die communication is performed through a custom direct connection packet.

[0006] Further, the coupling mode includes DC coupling and AC coupling; The coupling mode based on the physical layer PHY configuration system includes: The termination mode of the receiving end is set to DC coupling or AC coupling by configuring the control signal of the receiving end.

[0007] Furthermore, the method further comprises: Before setting the termination mode of the receiving end to DC coupling by configuring the control signal of the receiving end, the system is put into a reset state and the reference clock is set to an invalid state; After the termination mode of the receiving end is set to DC coupling by configuring the control signal of the receiving end, the system is exited from the reset state and the reference clock is set to the valid state.

[0008] Furthermore, the receiving end detection based on the physical layer PHY configuration system includes: Configure the PHY register to simulate returning a fake RX detection result to the controller, thereby skipping the actual PHY receive end detection stage.

[0009] Furthermore, the reference clock of the system is configured based on the physical layer PHY, including: The physical layers PHY at both ends of the Die-to-Die are configured to use the reference clock of the same source and disable the spread spectrum clock.

[0010] Furthermore, the low latency characteristics of the controller based on the physical layer PHY configuration include: Enable the CXL.cache interface; when the data link rate exceeds 8GT / s, enable the Header bypass and Driftbuffer functions.

[0011] Furthermore, before communicating through an external PCIe device and before performing Die-to-Die communication through a custom direct connection packet, the link between the physical layer PHY and the controller is initialized, and link training is started according to different working modes; wherein the link training includes calibrating the clock synchronization and data transmission of the transmitter and receiver.

[0012] In a second aspect, the present invention provides a system for multiplexing communication between a PCIe interface and a direct connection interface based on a CXL protocol, comprising: An operating mode selection register, used to store information determining the operating mode of the system; PHY, connected to the controller, capable of switching between the PCIe interface mode and the CXL direct connection interface mode according to the value of the working mode selection register, and used for transmitting data in the PCIe interface mode and the CXL direct connection interface mode; The controller is connected to the PHY and can select the value of the register according to the working mode, configure the coupling mode, reference clock, receiving end detection and low latency characteristics of the controller based on the PHY configuration system shared by the two working modes; switch between the PCIe interface mode and the CXL direct connection interface mode, communicate through an external PCIe device in the PCIe interface mode, and perform Die-to-Die communication through a custom direct connection packet in the CXL direct connection interface mode.

[0013] Furthermore, the PHY supports multiple physical Lanes and can select DC coupling or AC coupling according to the value of the working mode selection register; The controller includes a MUX module and a register configuration unit; A MUX module is used to select the working mode of the controller according to the control signal of the working mode selection register; An APB bus, connected to the working mode selection register via APB_MUX, is used to access the PHY register and the controller register, and dynamically configures the receiving end detection of the PHY register and the reference clock and low latency characteristics of the controller register according to the value of the working mode selection register; APB_MUX, used to switch the access path of the APB bus in different working modes according to the value of the working mode selection register, including: In response to the value of the working mode selection register indicating the PCIe interface mode, the APB_MUX connects the APB bus to the PCIe processing unit, and configures the PHY register and the controller register based on the PCIe protocol for communication with the PCIe device; In response to the value of the working mode selection register indicating the CXL direct connection mode, the APB_MUX connects the APB bus to the custom direct connection processing unit, and configures the PHY register and the controller register based on the CXL protocol for Die-to-Die direct communication.

[0014] Furthermore, the system further comprises: The adaptive configuration unit is used to perform link training after completing link initialization, read the value of the working mode selection register, determine whether the system is in PCIe interface mode or CXL direct connection interface mode, and start link training according to different working modes.

[0015] Compared with the prior art, the present invention has at least the following beneficial effects: The present invention realizes the function of supporting both external PCIe device communication and Die-to-Die communication through the CXL direct connection interface mode by reusing the same hardware interface. First, the multiplexing communication method provided by the embodiment of the present invention greatly improves the hardware resource utilization of the system and reduces the hardware overhead and complexity of setting up multiple interfaces separately for different communication requirements in the design. By combining the PCIe interface and the CXL direct connection interface into one, the system can switch freely between the two modes according to actual needs, which not only saves physical space but also reduces production costs.

[0016] Secondly, the design flexibility of the multiplexing communication method provided by the embodiment of the present invention allows for meeting diverse communication needs in different application scenarios. For external PCIe devices, the PCIe interface mode ensures compatibility with standard PCIe devices and maintains high-speed and stable data transmission. In the die-to-die communication scenario in the chip, the custom direct connection package and cache consistency mechanism of the CXL protocol can provide more efficient die-to-die communication in the chip in low-latency, high-bandwidth demand scenarios, meeting the performance requirements of high-performance computing scenarios such as modern data centers and cloud computing.

[0017] In addition, based on the PHY configuration mechanism, the system can flexibly adjust the coupling mode, reference clock, receiver detection and low latency characteristics of the controller, ensuring the stability of the link and the reliability of data transmission in different communication modes, further improving the system's work efficiency and communication performance. This design enables the system to adapt to the needs of different communication rates and application scenarios, providing a more efficient and flexible solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a flowchart of a method for multiplexing communication between a PCIe interface and a direct-connect interface based on the CXL protocol provided in the first embodiment of the present invention; Figure 2 It is a schematic diagram of the architecture of a PCIe interface and direct-connect interface multiplexing communication system based on the CXL protocol provided in the second embodiment of the present invention. DETAILED DESCRIPTION

[0019] The technical solution of the present invention is described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present application and the specific features in the embodiments are detailed descriptions of the technical solution of the present application, rather than limitations on the technical solution of the present application. In the absence of conflict, the embodiments of the present application and the technical features in the embodiments can be combined with each other.

[0020] Embodiment 1:

[0021] This embodiment provides a PCIe interface and a direct connection interface multiplexing communication method based on the CXL protocol, including: Read the value of the working mode selection register; In response to the value of the working mode selection register indicating the PCIe interface mode, entering the PCIe interface mode after exiting the reset state, and communicating through an external PCIe device; In response to the value of the working mode selection register indicating the CXL direct connection interface mode, the system coupling mode, reference clock, receiving end detection and low latency characteristics of the controller are configured based on the physical layer PHY, and Die-to-Die communication is performed through a custom direct connection packet.

[0022] This embodiment provides a PCIe (Peripheral Component Interconnect Express) interface and direct connection interface multiplexing communication method based on the CXL (Compute Express Link) protocol, so that a single hardware interface can simultaneously support the communication of an external PCIe device and the Die-to-Die direct connection function in a chip.

[0023] With the development of semiconductor technology, more and more high-performance chips are broken down into multiple independent Dies (chips), each Die is responsible for different functional modules. This multi-Die structure breaks the traditional single chip overall design and provides more possibilities for improving computing performance, reducing power consumption and optimizing spatial layout. However, when the chip is divided into multiple Dies, in order to ensure efficient collaboration between the Dies, a high-speed, low-latency communication method must be established. Die-to-Die technology is designed for this purpose, allowing high-speed data transmission between these Dies, so that different modules inside the chip can exchange data efficiently without relying on traditional external interfaces. This not only greatly reduces latency, but also optimizes overall system performance and meets the high-performance requirements of modern chips.

[0024] Figure 1 This is a flowchart of a method for multiplexing communication between a PCIe interface and a direct-connection interface based on the CXL protocol in this embodiment. First, the value of the working mode selection register is read to determine whether the system enters the working mode of an external PCIe device or the CXL direct-connection interface mode. In the PCIe interface mode, since the physical layer itself already has the ability to communicate with the PCIe device, the system can directly communicate with the PCIe device after exiting the reset state without additional configuration of the PHY. In this case, the system communicates directly with the external device through the physical layer, and the link setting in the PCIe interface mode is relatively simple, and data transmission can be performed after entering the working state.

[0025] When the value of the operating mode selection register indicates that the system enters the CXL direct interface mode, more configuration adjustments are required. Since the CXL direct interface mode involves direct Die-to-Die communication in the chip, the system needs to set parameters such as coupling mode, reference clock, and receiving end detection based on PHY to ensure the stability and performance of Die-to-Die communication. These configurations are the core steps to ensure that the CXL direct mode can operate normally.

[0026] This embodiment takes advantage of the compatibility of CXL and PCIe at the physical transport layer, and both share the same PHY layer. By introducing a new protocol layer, CXL can handle cache consistency and memory sharing, which is particularly suitable for low-latency, high-bandwidth communication scenarios. In the CXL direct interface mode, this embodiment implements Die-to-Die communication of custom direct packets through the CXL.Cache subprotocol. The CXL.Cache subprotocol ensures data consistency between devices, avoids transmission errors, and ensures the integrity and reliability of Die-to-Die data transmission through an embedded error detection and correction mechanism.

[0027] Through the above steps, the system realizes flexible interface multiplexing in two working modes. It can communicate with external devices as a standard PCIe interface, and can also realize efficient Die-to-Die direct communication based on the CXL protocol. This communication method not only improves the utilization rate of the interface, but also enhances the flexibility and compatibility of hardware design.

[0028] As an embodiment of the present invention, a coupling method of a physical layer PHY configuration system includes: The termination mode of the receiving end is set to DC coupling or AC coupling by configuring the control signal of the receiving end.

[0029] Before setting the termination mode of the receiving end to DC coupling by configuring the control signal of the receiving end, the system is put into a reset state and the reference clock is set to an invalid state; After the termination mode of the receiving end is set to DC coupling by configuring the control signal of the receiving end, the system is exited from the reset state and the reference clock is set to the valid state.

[0030] When implementing Die-to-Die communication, you first need to switch the PHY coupling mode to DC coupling. This is because in Die-to-Die direct communication, DC coupling (Direct Current Coupling) can directly transmit signals, and does not need to isolate the DC component of the signal through capacitors like AC coupling (Alternating Current Coupling). By setting PHY to DC coupling, the signal transmission path can be simplified and the complex design of the signal at the packaging layer can be reduced, which is particularly suitable for the design requirements of Die-to-Die direct connection.

[0031] In order to set the DC coupling mode, the system needs to enter the reset state first to ensure that all related modules are in the initial state. At this time, the reference clock is set to an invalid state to prevent the clock signal from interfering with the PHY configuration process. Only after the system is completely reset can the PHY coupling mode be smoothly switched to DC coupling.

[0032] When the PHY coupling mode is switched to DC coupling, the system exits the reset state and resets the reference clock to a valid state to ensure that the system can normally enter the subsequent link training and communication phases. This reset and clock management mechanism ensures the accuracy and stability of the PHY coupling mode switching, providing reliable physical layer support for subsequent Die-to-Die communications based on the CXL protocol.

[0033] As an embodiment of the present invention, the receiving end detection based on the PHY configuration system includes: configuring the PHY register to simulate returning a false RX detection result to the controller, thereby skipping the actual PHY receiving end detection stage.

[0034] Normally, the PCIe interface uses AC coupling mode, and AC coupling capacitors are required between TX (Transmitter) and RX (Receiver) to isolate the DC voltage, and use different reference voltages for signal detection. In CXL direct interface mode, the DC voltage between TX and RX is the same, so such a detection mechanism is no longer needed, so this detection stage is skipped.

[0035] In the specific implementation, first access the PHY register to find the register used to report the RX detection result. Then, manually write a "success" status through register operation to deceive the controller into thinking that RX detect has been completed, so as to continue the configuration of data transmission.

[0036] As an embodiment of the present invention, configuring a reference clock of a system based on PHY includes: configuring the physical layer PHYs at both ends of a Die-to-Die to use the reference clock of the same source and turning off the spread spectrum clock.

[0037] In actual operation, die-to-die communication requires extremely high timing accuracy, so the PHYs at both ends must share the same reference clock source. Using the same reference clock can ensure strict clock consistency during signal transmission and avoid data errors or communication delays caused by clock asynchrony.

[0038] In order to further optimize the stability of the clock, this embodiment also turns off the spread spectrum clock when configuring the reference clock. The spread spectrum clock will cause a slight jitter in the clock frequency, which is unacceptable in Die-to-Die communication. By turning off the spread spectrum clock, the frequency stability and consistency of the reference clock are ensured, further reducing the risk of delay in data transmission.

[0039] As an embodiment of the present invention, the low latency characteristic of the controller is configured based on the PHY, including: enabling the CXL.cache interface; and enabling the Header bypass and Drift buffer functions when the data link rate exceeds 8GT / s.

[0040] In this embodiment, when the system enables the CXL.cache interface, it can support low-latency Die-to-Die communication. The CXL.cache interface is mainly used to handle cache consistency issues between multiple devices to ensure data synchronization and efficient transmission during Die-to-Die direct communication. This interface optimizes the cache consistency mechanism to achieve higher transmission rates and lower communication delays while ensuring data transmission security.

[0041] In addition, when the data link rate exceeds 8GT / s, the system will further enable the low-latency features in the controller to improve data transmission efficiency. Among them, the Header bypass and Drift buffer functions are two low-latency optimization mechanisms specially designed in the CXL protocol. The Header bypass function can bypass the processing steps of some data packet headers, reduce the additional processing delay of data packets during transmission, and thus speed up the overall data transmission speed. This function is particularly critical in high-frequency and large-data volume transmission scenarios, and can effectively improve data processing efficiency. The Drift buffer function is used to buffer and adjust timing drift in data transmission. When the data link rate is extremely high, tiny timing errors may accumulate and affect the transmission quality. The Drift buffer function dynamically adjusts these errors to ensure that data can be transmitted continuously and accurately, further improving the stability and performance of communications.

[0042] As an embodiment of the present invention, the PCIe interface and direct-connect interface multiplexing communication method based on the CXL protocol also includes: before communicating through an external PCIe device and before performing Die-to-Die communication through a custom direct-connect packet, initializing the link between the physical layer PHY and the controller, and starting link training according to different working modes; wherein the link training includes calibrating the clock synchronization and data transmission of the transmitting and receiving ends.

[0043] This embodiment aims to achieve clock synchronization between the transmitter and receiver and accurate calibration of data transmission through a link training process, thereby ensuring that data can be transmitted in an efficient and stable environment and avoiding errors or delays during the communication process.

[0044] In practice, the first step of link training is clock synchronization. At this stage, the clock frequency and phase between the transmitter and receiver must be consistent to ensure that devices in different physical locations can transmit data under the same time reference. To achieve this synchronization, the transmitter continuously sends training signals through the physical link, and the receiver adjusts its internal clock based on these signals until it matches the transmitter. When clock synchronization is complete, the receiver returns a confirmation signal to the transmitter, indicating that the clocks have been aligned.

[0045] The next step is data transmission calibration. Data calibration is the most critical step in the link training process, which ensures that the data between the sender and the receiver can be sent and received at the correct timing. To achieve this goal, link training will test the link's delay, noise interference, signal integrity and other factors by sending special calibration data packets. Based on the feedback results of these data packets, the system will dynamically adjust the timing of data transmission, signal level and other parameters to optimize link performance and ensure that no data errors or signal loss will occur during actual communication.

[0046] The entire link training process not only optimizes the communication of the physical layer, but also provides the necessary foundation for the collaborative work between the controller layer and the PHY layer. Whether in PCIe interface mode or CXL direct interface mode, successful link training can ensure that the PHY layer and the controller layer can communicate with the optimal parameters, providing guarantee for subsequent stable data transmission.

[0047] Embodiment 2:

[0048] This embodiment provides a system for multiplexing communication between a PCIe interface and a direct connection interface based on a CXL protocol, including: An operating mode selection register, used to store information determining the operating mode of the system; PHY, connected to the controller, capable of switching between the PCIe interface mode and the CXL direct connection interface mode according to the value of the working mode selection register, and used for transmitting data in the PCIe interface mode and the CXL direct connection interface mode; The controller is connected to the PHY and can select the value of the register according to the working mode, configure the coupling mode, reference clock, receiving end detection and low latency characteristics of the controller based on the PHY configuration system shared by the two working modes; switch between the PCIe interface mode and the CXL direct connection interface mode, communicate through an external PCIe device in the PCIe interface mode, and perform Die-to-Die communication through a custom direct connection packet in the CXL direct connection interface mode.

[0049] The system provided in this embodiment realizes dynamic switching between PCIe interface mode and CXL direct connection interface mode by reading the value of the working mode selection register. Figure 2As shown in the figure, a maintenance register (i.e., working mode selection register) for maintaining two working modes is defined, and the register stores the control signal CXL_MODE. This signal determines the working mode of the controller: when the value of the CXL_MODE signal is 0, the controller Work in PCIe works in the PCIe interface mode, which is used for communication with external PCIe devices; when the value of the CXL_MODE signal is 1, the controller Work in CXL works in the CXL direct connection interface mode, which is used for Die-to-Die communication in the chip.

[0050] As an embodiment of the present invention, the PHY supports multiple physical Lanes and can select DC coupling or AC coupling according to the value of the working mode selection register; The controller includes a MUX module and an APB bus; A MUX module is used to select the working mode of the controller according to the control signal of the working mode selection register; An APB bus, connected to the working mode selection register via APB_MUX, is used to access the PHY register and the controller register, and dynamically configures the receiving end detection of the PHY register and the reference clock and low latency characteristics of the controller register according to the value of the working mode selection register; APB_MUX, used to switch the access path of the APB bus in different working modes according to the value of the working mode selection register, including: In response to the value of the working mode selection register indicating the PCIe interface mode, the APB_MUX connects the APB bus to the PCIe processing unit, and configures the PHY register and the controller register based on the PCIe protocol for communication with the PCIe device; In response to the value of the working mode selection register indicating the CXL direct connection mode, the APB_MUX connects the APB bus to the custom direct connection processing unit, and configures the PHY register and the controller register based on the CXL protocol for Die-to-Die direct communication.

[0051] The specific system architecture and the process of interaction of control signals of maintenance registers are as follows: Figure 2 As shown in the figure, PHY selects the physical coupling mode according to the value of the CXL_MODE signal. When CXL_MODE=0, PHY communicates with PCIe devices through AC coupling; when CXL_MODE=1, PHY switches to DC coupling to meet the low latency requirements of Die-to-Die direct connection, and configures the control signal term_acdc=0 at the receiving end, setting the termination mode of the receiving end to DC coupling.

[0052] The MUX determines the data flow path of the controller according to the value of the CXL_MODE signal. When CXL_MODE=0, the MUX connects the controller to the PCIe processing unit, and the data packet follows the PCIe protocol to communicate with external devices; when CXL_MODE=1, the MUX switches the controller to CXL mode, and the data packet is interconnected between the dies in the chip through the direct-connect processing unit via the Cache sub-protocol in the CXL protocol.

[0053] The controller is connected to the MUX and PHY to process data packets according to different modes. When CXL_MODE=0, the controller processes PCIe protocol data and communicates with peripherals; when CXL_MODE=1, the controller switches to CXL mode and uses a custom data packet format for Die-to-Die high-speed direct communication.

[0054] The APB bus accesses the PHY registers and controller registers, performs read and write operations on them, and configures the parameters of the PHY and controller related to the two modes. When CXL_MODE=0, the controller first sends the RX detection request signal txX_detrx_req to request the PHY to detect the receiving end. When the PHY detects the existence of the receiving end, it will confirm the detection result to the controller by returning the txX_detrx_result signal.

[0055] When CXL_MODE=1, APB configures the PHY register to skip the actual PHY receiver detection phase; configures the controller register to adjust the low latency characteristics of the controller and ensure low latency clock transmission, such as enabling the Headerbypass and Drift buffer functions, setting the same source reference clock, and disabling the spread spectrum clock. Figure 2 As shown, the controller sends an RX detection request signal txX_detrx_req, configures the PHY register, finds the register for reporting the RX detection result in the PHY register, and manually writes a "success" status through register operation to overwrite the receiving end detection result txX_detrx_result to deceive the controller into thinking that the receiving end detection has been completed, thereby continuing the data transmission configuration.

[0056] Configure the controller register, set cache_en to 1 to enable the CXL.cache interface, and the controller reads the link rate field in the PHY status register. If the current link rate exceeds 8GT / s, enable the Headerbypass and Drift buffer functions in the low latency feature; configure cmn_refclk_mode=1 in the controller register to use the same reference clock; configure sris_mode=0 to turn off the spread spectrum clock to ensure the stability and consistency of the reference clock frequency.

[0057] During the system reset process, the PHY reset signal phy_reset is set to 1 through upper-layer software control, and the reference clock enable signal refa / b_clk_en is set to 0 to temporarily shut down the reference clock; after the PHY coupling mode is switched to DC coupling, the clock control unit restores the reference clock, that is, turns on the reference clock enable signal refa / b_clk_en and sets it to 1, and exits the reset state, that is, sets the PHY reset signal phy_reset to 0.

[0058] Through the above system configuration, the CXL_MODE control signal is used as the core driver to determine the system switching between PCIe interface mode and CXL direct interface mode. The behavior of each component is adjusted accordingly based on the state of CXL_MODE, so that the system can flexibly support external PCIe device communication and Die-to-Die communication. This architecture not only improves the reuse efficiency of the hardware interface, but also ensures the best performance in different communication modes.

[0059] As an embodiment of the present invention, the system further includes: The adaptive configuration unit is used to perform link training after completing link initialization, read the value of the working mode selection register, determine whether the system is in PCIe interface mode or CXL direct connection interface mode, and start link training according to different working modes.

[0060] Specifically, the system first configures the PHY register through link initialization. When the phy_sram_init_done register value is detected to be 1, it indicates that the PHY initialization process has been successfully completed. At this point, the system enters the next link training process.

[0061] Before link training begins, the adaptive configuration unit reads the operating mode selection register, obtains the control signal of the current mode, and determines whether the system is in PCIe interface mode or CXL direct connection interface mode. When the operating mode is determined, the adaptive configuration unit starts link training according to the corresponding mode. In PCIe interface mode, the system will perform standard link establishment and communication processes according to the PCIe protocol to ensure that external PCIe devices can connect and communicate stably; in CXL direct connection interface mode, the system will perform Die-to-Die high-speed interconnection through the sub-protocol of the CXL protocol, and optimize the configuration in terms of low latency and efficient data transmission.

[0062] In specific operations, when the control signal selects to enter the link training phase, the system activates the link enable signal app_ltssm_en to start formal link training. This process includes clock synchronization, calibration of the signal transmission path, and interaction between the PHY layer and the controller layer, ultimately ensuring that data packets can be stably transmitted along the optimal path in different modes. Through this series of operations, the system can maintain efficient communication performance in multiple modes.

[0063] As an embodiment of the present invention, the controller uses a CXL 2.0 controller, and the controller is connected to the PHY through a PIPE 5.1 ​​Serdes interface. The PHY can use PCIe 5.0 x8 or two independent PCIe 5.0 x4 physical Lanes, and the data bit width of each Lane is 80 bits.

[0064] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A PCIe interface and direct connection interface multiplexing communication method based on CXL protocol, characterized in that: include: Read the value of the working mode selection register; In response to the value of the working mode selection register indicating the PCIe interface mode, entering the PCIe interface mode after exiting the reset state, and communicating through an external PCIe device; In response to the value of the working mode selection register indicating the CXL direct connection interface mode, the system coupling mode, reference clock, receiving end detection and low latency characteristics of the controller are configured based on the physical layer PHY, and Die-to-Die communication is performed through a custom direct connection packet.

2. The PCIe interface and direct connection interface multiplexing communication method based on the CXL protocol according to claim 1, characterized in that: The coupling mode includes DC coupling and AC coupling; The coupling mode based on the physical layer PHY configuration system includes: The termination mode of the receiving end is set to DC coupling or AC coupling by configuring the control signal of the receiving end.

3. The PCIe interface and direct connection interface multiplexing communication method based on the CXL protocol according to claim 2, characterized in that: The method further comprises: Before setting the termination mode of the receiving end to DC coupling by configuring the control signal of the receiving end, the system is put into a reset state and the reference clock is set to an invalid state; After the termination mode of the receiving end is set to DC coupling by configuring the control signal of the receiving end, the system is exited from the reset state and the reference clock is set to the valid state.

4. The PCIe interface and direct connection interface multiplexing communication method based on the CXL protocol according to claim 1, characterized in that: Receiver detection based on the physical layer PHY configuration system, including: Configure the PHY register to simulate returning a fake RX detection result to the controller, thereby skipping the actual PHY receive end detection stage.

5. The PCIe interface and direct connection interface multiplexing communication method based on the CXL protocol according to claim 3, characterized in that: The reference clock of the system based on the physical layer PHY configuration includes: The physical layers PHY at both ends of the Die-to-Die are configured to use the reference clock of the same source and disable the spread spectrum clock.

6. The PCIe interface and direct connection interface multiplexing communication method based on the CXL protocol according to claim 1, characterized in that: The low latency features of the physical layer PHY configuration controller include: Enable the CXL.cache interface; when the data link rate exceeds 8GT / s, enable the Header bypass and Driftbuffer functions.

7. The PCIe interface and direct connection interface multiplexing communication method based on the CXL protocol according to claim 1, characterized in that: Before communicating through an external PCIe device, and before Die-to-Die communication through a custom direct-connect packet, Initialize the link between the physical layer PHY and the controller, and start link training according to different working modes; The link training includes calibrating clock synchronization and data transmission between the transmitting end and the receiving end.

8. A system for multiplexing communication between a PCIe interface and a direct-connect interface based on a CXL protocol, characterized in that: include: An operating mode selection register, used to store information determining the operating mode of the system; PHY, connected to the controller, capable of switching between the PCIe interface mode and the CXL direct connection interface mode according to the value of the working mode selection register, and used for transmitting data in the PCIe interface mode and the CXL direct connection interface mode; A controller, connected to the PHY, capable of selecting register values ​​according to the operating mode, and configuring the coupling mode, reference clock, receiving end detection and low latency characteristics of the controller based on the PHY configuration system common to the two operating modes; Switch between PCIe interface mode and CXL direct connection interface mode. In PCIe interface mode, communication is performed through an external PCIe device. In CXL direct connection interface mode, Die-to-Die communication is performed through a custom direct connection packet.

9. The system for multiplexing communication between PCIe interface and direct connection interface based on CXL protocol according to claim 8, characterized in that: The PHY supports multiple physical lanes and can select DC coupling or AC coupling according to the value of the working mode selection register; The controller includes a MUX module and an APB bus; A MUX module is used to select the working mode of the controller according to the control signal of the working mode selection register; An APB bus, connected to the working mode selection register via APB_MUX, is used to access the PHY register and the controller register, and dynamically configures the receiving end detection of the PHY register and the reference clock and low latency characteristics of the controller register according to the value of the working mode selection register; APB_MUX, used to switch the access path of the APB bus in different working modes according to the value of the working mode selection register, including: In response to the value of the working mode selection register indicating the PCIe interface mode, the APB_MUX connects the APB bus to the PCIe processing unit, and configures the PHY register and the controller register based on the PCIe protocol for communication with the PCIe device; In response to the value of the working mode selection register indicating the CXL direct connection mode, the APB_MUX connects the APB bus to the custom direct connection processing unit, and configures the PHY register and the controller register based on the CXL protocol for Die-to-Die direct communication.

10. The system for multiplexing communication between PCIe interface and direct connection interface based on CXL protocol according to claim 9, characterized in that: Also includes: The adaptive configuration unit is used to perform link training after completing link initialization, read the value of the working mode selection register, determine whether the system is in PCIe interface mode or CXL direct connection interface mode, and start link training according to different working modes.

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