Data access method and DPU

Abstract

A data access method and a DPU (Data Processing Unit) relate to the field of computers and are used for reducing the time delay of accessing a storage system by a host. In the application, the method is applicable to a host, the host comprises a CPU, a DPU, a memory and a bus, and the CPU, the DPU and the memory are connected to the bus. The method is executed by a DPU, and comprises the steps that the DPU receives an NVMe access request from a CPU through a bus, and the NVMe access request is used for indicating a data structure; the DPU performs a splicing operation on the data structure to obtain a data structure after the splicing operation, and the number of substructures included in the data structure after the splicing operation is less than the number of substructures included in the data structure before the splicing operation. The DPU generates an RoCE access request according to the NVMe access request and an index field used for searching the data structure after the splicing operation, the RoCE access request is sent to a storage system, and the DPU and the storage system communicate through a network.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computers, and in particular to a data access method and a data processing unit (DPU). Background Art

[0002] The non-volatile memory express (NVMe) protocol is a controller interface specification developed for solid state disk (SSD) systems that use the high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIe) specification. It is used to standardize the communication between the host and the SSD. When the NVMe protocol is adapted in different types of networks, different technical routes are formed, such as NVMe over RDMA based on remote direct memory access (RDMA) technology. As for NVMe over RoCE transmitted on the RDMA over converged Ethernet (RoCE) network, it is a type of NVMe over RDMA.

[0003] The host includes a DPU and a central processing unit (CPU), and the DPU can be an NVMe device for the host. The host can access the storage system through the DPU. Specifically, the DPU can receive an NVMe access request from the CPU, perform protocol conversion on the NVMe access request to obtain an NVMe over RoCE access request (which can be referred to as a RoCE access request), and send the RoCE access request to the storage system. In the above process, the DPU needs to convert the physical address in the NVMe access request into a virtual address, carry the virtual address and the remote key (key) together in the RoCE access request, and apply to the DPU memory for the memory region (memory region, MR) required for the RoCE access request, store the mapping relationship between the remote key, the physical address and the virtual address in the MR, so that when responding to the subsequent read and write operations of the storage system, the MR is searched according to the remote key, and the physical address is obtained from the MR.

[0004] As a result, the processing delay inside the DPU is long, resulting in a long delay for the host to access the storage system. Summary of the invention

[0005] The present application provides a data access method and a DPU for reducing the latency of a host accessing a storage system.

[0006] In a first aspect, the present application provides a data access method, applicable to a host, the host includes a CPU, a DPU, a memory and a bus, and the CPU, the DPU and the memory are connected to the bus. The method is executed by the DPU, and the method includes: the DPU receives an NVMe access request from the CPU through the bus, and the NVMe access request is used to indicate a data structure, wherein the data structure is, for example, a scatter / gather list (SGL) or a physical region page (PRP) list, and the data structure includes multiple substructures. The DPU performs a splicing operation on the data structure to obtain a data structure after the splicing operation, wherein the number of substructures included in the data structure after the splicing operation is less than the number of substructures included in the data structure before the splicing operation. The DPU then generates a RoCE access request based on the NVMe access request and an index field for finding the data structure after the splicing operation. It can be understood that the RoCE access request is obtained after the DPU performs protocol conversion on the NVMe access request, and the RoCE access request includes an index field. The DPU sends a RoCE access request to the storage system, wherein the DPU and the storage system communicate through a network (such as a RoCE network). The NVMe access request is specifically an access request that complies with the NVMe protocol, and the RoCE access request is specifically an access request that complies with the RoCE protocol.

[0007] In the above technical solution, the DPU does not need to convert the physical address indicated by the data structure into a virtual address, and does not need to apply to the DPU memory for the MR required for the RoCE access request, which helps to reduce the processing delay inside the DPU. Further, the DPU performs a splicing operation on the data structure, wherein the number of substructures included in the spliced ​​data structure is less than the number of substructures included in the data structure before the splicing operation, reducing the number of times the DPU searches for a subsequent substructure based on a previous substructure, that is, reducing the delay of the DPU determining the physical address in the host memory based on multiple substructures, which helps to shorten the delay of the host accessing the storage system.

[0008] In a possible implementation, the DPU stores the data structure after the splicing operation in a preset space of the DPU memory, and the DPU can allocate one or more complete memory pages in the preset space to the data structure after the splicing operation. Compared with the host CPU which can only allocate part of the memory page in the host memory (i.e., an incomplete memory page) to the data structure before the splicing operation, this solution can achieve: the number of substructures smaller than the memory page size in the data structure after the splicing operation is less than the number of substructures smaller than the memory page size in the data structure before the splicing operation; and / or the number of substructures equal to the memory page size in the data structure after the splicing operation is more than the number of substructures equal to the memory page size in the data structure before the splicing operation. The above technical solution helps to reduce the delay of the DPU determining the physical address in the host memory based on multiple substructures, and helps to shorten the delay of the host accessing the storage system.

[0009] In a possible implementation, after the DPU sends a RoCE access request to the storage system, it also receives an RDMA operation from the storage system, wherein the RDMA operation is initiated when the storage system responds to the RoCE access request and needs to write user data in the storage system to the host memory, or when it needs to read user data from the host memory to the storage system. The DPU searches for the data structure after the splicing operation based on the index field included in the RDMA operation, and then determines the physical address (i.e., DMA address) corresponding to the RDMA operation in the host memory based on the data structure after the splicing operation, and initiates the DMA operation to the memory through the bus based on the DMA address. In the above technical solution, the DPU directly determines the physical address (i.e., DMA address) corresponding to the RDMA operation in the host memory based on the data structure after the splicing operation, and then initiates the DMA operation to the host memory based on the DMA address, without converting the virtual address in the RDMA operation into a physical address in the host memory, which helps to realize the storage system to quickly respond to the host's access request.

[0010] In a possible implementation, when the DPU receives an RDMA operation from the storage system, it may specifically be that when the amount of data that can be carried in the RDMA operation is less than the amount of user data, multiple RDMA operations from the storage system are received in sequence, and the first RDMA operation of the multiple RDMA operations carries an index field. When the DPU determines the physical address corresponding to the RDMA operation in the host memory according to the data structure after the splicing operation, it may specifically be that the physical address corresponding to each RDMA operation in the host memory is determined for the amount of data of the data slice carried in each RDMA operation and the data structure after the splicing operation, and the data slice is a part of the user data. In the above technical solution, the DPU receives multiple RDMA operations from the storage system, processes each RDMA operation, and solves the problem that the amount of data to be accessed exceeds the amount of data that can be carried by a single RDMA operation. And the DPU only needs to obtain the index field from the first RDMA operation, and search the data structure after the splicing operation from the preset space according to the index field, which helps to reduce the length of the RDMA operation.

[0011] In one possible implementation, the DPU performs a splicing operation on the data structure, and after obtaining the data structure after the splicing operation, it can also generate an index field, and store the data structure after the splicing operation and the index field in the preset space of the DPU accordingly. Furthermore, the RDMA operation includes an index field, and after receiving the RDMA operation, the DPU can also determine the data structure after the splicing operation based on the mapping relationship between the index field, the index field in the preset space of the DPU, and the data structure after the splicing operation. In the above technical solution, the DPU only needs to find the data structure after the splicing operation from the preset space of the DPU according to the index field, without converting the virtual address in the RDMA operation into a physical address in the host memory, which helps to realize the storage system to quickly respond to the host's access request.

[0012] In a possible implementation, the preset space of the DPU is generated when the DPU is started. In this way, the DPU does not need to apply for an MR from the DPU memory every time it receives an NVMe access request from the host CPU, which helps to further reduce the processing delay inside the DPU, that is, reduce the delay of the host accessing the storage system.

[0013] In a second aspect, the present application provides a DPU, which is applicable to a host, wherein the host includes a CPU, a DPU, a memory and a bus, wherein the CPU, the DPU and the memory are connected to the bus. The DPU includes: a first protocol processing module, which is used to receive an NVMe access request from the CPU through the bus, wherein the NVMe access request is used to indicate a data structure; a programming module, which is used to perform a splicing operation on the data structure to obtain a data structure after the splicing operation, wherein the number of substructures included in the data structure after the splicing operation is less than the number of substructures included in the data structure before the splicing operation; a RoCE access request is generated according to the NVMe access request and an index field for searching the data structure after the splicing operation; a second protocol processing module, which sends a RoCE access request to a storage system, and the DPU and the storage system communicate through a network.

[0014] In one possible implementation, the number of substructures smaller than the memory page size in the data structure after the splicing operation is less than the number of substructures smaller than the memory page size in the data structure before the splicing operation; and / or the number of substructures equal to the memory page size in the data structure after the splicing operation is more than the number of substructures equal to the memory page size in the data structure before the splicing operation.

[0015] In a possible implementation, after the second protocol processing module sends the RoCE access request to the storage system, the second protocol processing module is further used to: receive an RDMA operation from the storage system. The programming module is further used to: search for a data structure after the splicing operation according to an index field in the RDMA operation, and, according to the data structure after the splicing operation, initiate a DMA operation to the memory through the bus.

[0016] In one possible implementation, after the programming module performs a concatenation operation on the data structure to obtain the concatenated data structure, it is also used to: generate an index field; and store the concatenated data structure and the index field correspondingly in a preset space of the DPU.

[0017] In a possible implementation manner, the preset space of the DPU is generated when the DPU is started.

[0018] In a third aspect, the present application provides a host, comprising a CPU in any possible implementation of the first aspect, and a DPU in any possible implementation of the first aspect, wherein the CPU and the DPU communicate via a bus, and the DPU is used to execute a method in any possible implementation of the first aspect.

[0019] In a fourth aspect, the present application provides a DPU interface card, comprising a processor and an interface, the interface supporting a bus protocol, the interface being used to communicate with a host CPU via a bus, and the processor being used to execute a method in any possible implementation of the first aspect above.

[0020] In a fifth aspect, the present application provides a processor, the processor comprising a logic circuit and a power supply circuit, the power supply circuit is used to supply power to the logic circuit, and the logic circuit is used to execute the method in any possible implementation manner of the above-mentioned first aspect.

[0021] The technical effects that can be achieved in any of the second to fifth aspects mentioned above can refer to the description of the beneficial effects in the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a queue pair implementation method;

[0023] Figure 2 It is a schematic diagram of the structure of a NoF storage system;

[0024] Figure 3 The schematic diagram of the structure of a host;

[0025] Figure 4 A schematic diagram of a process of a host accessing a storage system;

[0026] Figure 5 A flowchart of a data access method provided for this application;

[0027] Figure 6 A schematic diagram of the format of SGL provided for this application;

[0028] Figure 7 A schematic diagram of the format of a PRP list provided for this application;

[0029] Figure 8 A schematic diagram of the format of an SGL descriptor provided in this application;

[0030] Fig. 9 A schematic diagram of splicing multiple substructures provided in this application;

[0031] Fig.10 A schematic diagram of an update data structure provided for this application;

[0032] Fig.11 A flowchart of a data access method in a specific scenario provided by this application;

[0033] Fig.12 A schematic diagram of the structure of a DPU provided in this application. DETAILED DESCRIPTION

[0034] The following first explains the relevant technical features involved in the embodiments of the present application. It should be noted that these explanations are intended to make the embodiments of the present application easier to understand and should not be regarded as limiting the scope of protection claimed by the present application.

[0035] 1. Non-volatile memory express (NVME) protocol

[0036] In the NVME protocol, communication between the host and the SSD can be achieved through a series of paired submission queues (SQ) and completion queues (CQ). Specifically, these queues are created by the driver running on the host and shared between the driver and the SSD. The queue itself can be located in the shared memory of the host or in the memory provided by the SSD. Figure 1 It is an implementation of a queue pair. In step 1, the host places a new submission queue entry (SQE) at the tail of the SQ. Step 2, the driver notifies the SSD that there is a new SQE to be executed by writing the new tail pointer in the SQ to the doorbell register (DB register). Step 3, the SSD obtains the SQE from the head of the SQ. Step 4, the SSD processes the SQE. Step 5, the SSD puts a completion queue entry (CQE) at the tail of the CQ. Step 6, the SSD generates an interrupt. Step 7, the driver obtains the CQE from the head of the CQ and processes the CQE. Step 8, writes the head pointer of the CQ to the doorbell register to notify the SSD that it has read the CQE.

[0037] 2. Non-volatile memory express over fabric (NoF)

[0038] When NVMe is adapted to different types of networks, different technical routes are formed, which may include: NVMe over FC transmitted on fiber channel (FC), NVMe over TCP transmitted on Internet protocol (IP) network based on transmission control protocol (TCP), and NVMe over RDMA based on RDMA technology. These technical routes are collectively referred to as NoF protocols. NVMe over RDMA includes NVMe over RoCE transmitted on RDMA over converged ethernet (RoCE) network.

[0039] 3. Memory Access Technology

[0040] Memory access technologies may include direct memory access (DMA) and remote direct memory access (RDMA). Specifically, DMA is to send data on a device in the host to the memory without the involvement of the CPU. Specifically, RDMA is to use RDMA technology to directly access the memory of one host from the memory of another host when two or more hosts are communicating, without the involvement of the CPUs of the two hosts.

[0041] Based on the above explanations of terms, the embodiments of the present application are described as follows.

[0042] Figure 2 A schematic diagram of the structure of a NoF storage system provided as an example for the present application. The NoF storage system includes: a host 100 and a storage system 200. The host 100 and the storage system 200 can communicate through a network 300, and the network 300 can specifically be a Fibre Channel network, an IP network, a converged Ethernet, etc. The host 100 can be one or more. When there are multiple hosts 100, the multiple hosts 100 can belong to the same user or to different users. In different embodiments, the host 100 can be a business server, a network host, a computing node, etc. There can be hosts of different types among the multiple hosts 100. This embodiment does not limit the specific type of the host 100, and only requires the host 100 to support the NVMe protocol. The storage system 200 can specifically be a storage array, a hard disk frame, a distributed storage system, a storage server, etc. Exemplarily, the storage system 200 includes multiple storage units, such as SSDs.

[0043] like Figure 3 An exemplary structural diagram of a host 100 is provided, where the host 100 includes at least a CPU, a DPU, a memory, and a hard disk, wherein the CPU, the DPU, the memory, and the hard disk are connected via a bus, and the memory and the hard disk can be collectively referred to as a storage device.

[0044] Exemplarily, the DPU communicates with the CPU via a bus protocol, or the DPU communicates with the memory via a bus protocol. The bus protocol is, for example, the PCIe protocol. Exemplarily, the DPU can communicate with the storage system via the network 300.

[0045] Exemplarily, when the CPU receives a write data request, it temporarily stores the data in the write data request in the memory. When the total amount of data in the memory reaches a certain threshold, the CPU sends the data stored in the memory to the hard disk for persistent storage. In addition, the CPU is also used to calculate or process data, such as metadata management, data compression, data verification, virtualized storage space, and address conversion. Figure 3 Only one CPU is shown in the figure, but in actual applications, there are often multiple CPUs, wherein one CPU has one or more CPU cores. This application does not limit the number of CPUs and the number of CPU cores.

[0046] Memory refers to the internal memory that directly exchanges data with the CPU. It can read and write data at any time and at a very fast speed. It serves as a temporary data storage for the operating system or other running programs. Memory includes at least two types of memory. For example, memory can be either random access memory or read-only memory (ROM). For example, random access memory is dynamic random access memory (DRAM) or storage class memory (SCM). Read-only memory is programmable read only memory (PROM), erasable programmable read only memory (EPROM), etc. In addition, memory can also be a dual in-line memory module or a dual-line memory module (DIMM), that is, a module composed of DRAM, or a solid state disk (SSD).

[0047] The DPU can be installed on the host 100 as a network card of the host 100. The DPU can be an NVMe device for the host 100. The host 100 can access the storage system through the DPU. Specifically, the DPU can receive an NVMe access request from the CPU, perform protocol conversion on the NVMe access request to obtain a RoCE access request, and send the RoCE access request to the storage system. Based on the RoCE access request, the storage system 200 initiates an RDMA operation to the DPU, and the DPU initiates a DMA operation to the memory. The storage system 200 sends a RoCE access completion to the DPU, and the DPU performs protocol conversion on the received RoCE access completion to obtain an NVMe access completion, and sends the NVMe access completion to the CPU.

[0048] The DPU may further include a computing power module and a memory, wherein the computing power module may be a CPU, that is, the DPU further includes one or more CPUs. For the convenience of description, the present application may refer to the CPU and memory in the host as the host CPU and host memory, respectively, and the memory inside the DPU as the DPU memory.

[0049] When the DPU converts the NVMe access request into the RoCE access request, or when the DPU converts the RoCE access completion into the NVMe access completion, specifically, the computing power module inside the DPU is executed according to the NoF application software. For details, see Figure 4 A schematic diagram of an exemplary process of a host accessing a storage system.

[0050] In this process, the host accesses the storage system specifically means that the host reads user data from the storage system.

[0051] Process 1: The host sends a read request to the storage system.

[0052] Step 1: The host CPU places the NVMe SQE at the tail of the SQ, and writes the new tail pointer in the SQ into the doorbell register to notify the NVMe protocol processing module inside the DPU that there is a new SQE to be executed. Correspondingly, the NVMe protocol processing module obtains the NVMe SQE from the head of the SQ. Subsequently, the NVMe protocol processing module sends the NVMe SQE to the computing power module.

[0053] Among them, NVMe SQE can also be called NVMe access request. NVMe SQE includes data structure and operation type. Data structure is, for example, scatter / gather list (SGL) or physical region page (PRP) list. The operation type is used to indicate whether the NVMe access request is a write request or a read request, and the operation type is, for example, an operation code (opcode). In this scenario, the operation type is used to indicate that the NVMe access request is a read request.

[0054] Step 2: The computing power module converts the format of the NVMe SQE to obtain the NoF SQE.

[0055] Exemplarily, the computing module is installed with NoF application software, and each action in step 2 can be obtained by the computing module based on the NoF application software. Specifically, the computing module first applies for a memory region (MR) from the DPU memory, converts the physical address indicated by the data structure into a virtual address, writes the mapping relationship between the physical address and the virtual address into the page table of the DPU memory, and then stores the page table address and key of the page table in the MR, and generates a NoF SQE according to the virtual address and key.

[0056] Step 3: The computing module sends the NoF SQE to the RoCE protocol processing module inside the DPU.

[0057] Step 4: The RoCE protocol processing module encapsulates the NoF SQE into a RoCE message (ie, a RoCE access request), and sends the RoCE access request to the storage system. The operation indicated by the RoCE access request may be an RDMA send operation.

[0058] Process 2: The storage system sends a read response to the host.

[0059] Step 1: The storage system parses the RoCE access request to obtain the NoF SQE.

[0060] Step 2: The storage system determines that the NoF SQE is a read request based on the operation type in the NoF SQE, and then reads the user data from the storage system based on the logical block address (LBA) and data size in the NoFSQE. The storage system initiates an RDMA write operation to the DPU based on the read user data, key, and virtual address.

[0061] Step 3: The RoCE protocol processing module receives the RDMA write operation from the storage system, parses the RDMA write operation into user data, key, and virtual address, and sends the user data, key, and virtual address to the computing power module.

[0062] Exemplarily, the key and the virtual address may be located in an RDMA extended transport header (RDMA extended transport header, Reth) of an RDMA write operation, and the user data may be located in a payload of the RDMA write operation.

[0063] Step 4: The computing module indexes the MR from the DPU memory according to the key, and then reads the page table address from the MR, obtains the page table according to the page table address, and then determines the physical address (i.e., DMA address) corresponding to the virtual address according to the page table and the virtual address, and initiates a DMA write operation to the host memory according to the DMA address and user data.

[0064] Process 3: The storage system sends a completion response to the host.

[0065] Step 1: After determining that the RDMA write operation is completed, the storage system forms a RoCE access completion and sends the RoCE access completion to the DPU, where the RoCE access completion includes a NoF CQE.

[0066] Step 2: After receiving the RoCE access completion, the DPU obtains the NoF CQE from the RoCE access completion, converts the NoF CQE to NVMe CQE, and sends the NVMe CQE to the host CPU. NVMe CQE is also called NVMe access completion, and NVMe CQE is used to notify the host CPU that "the storage system has completed the read request initiated by the host."

[0067] In the above scheme, the computing power module inside the DPU is based on the NoF application software, which not only needs to perform protocol conversion, but also needs to register MR in the DPU memory, perform conversion between physical addresses and virtual addresses, etc., resulting in a long processing delay inside the DPU, which in turn causes a long delay in the host accessing the storage system. To this end, the present application provides a data access method, which, compared with the previous scheme, does not require registration of MR, nor does it require conversion between physical addresses and virtual addresses, etc., thereby reducing the delay in the host accessing the storage system.

[0068] For details, please refer to Figure 5 A flowchart of a data access method is shown as an example:

[0069] Step 501: The host CPU sends an NVMe access request to the DPU via a bus. Correspondingly, the DPU receives the NVMe access request from the host CPU via the bus.

[0070] The NVMe access request is used to indicate a first data structure, and the first data structure includes multiple substructures. In one possible manner, the NVMe access request includes a physical address, which is specifically the physical address of the first substructure in the host memory among the multiple substructures. The first substructure may include the physical address of the second substructure in the host memory, and the second substructure may include the physical address of the third substructure in the host memory. By analogy, the DPU can obtain the first data structure from the host memory according to the physical address of the first substructure in the host memory in the NVMe access request.

[0071] Exemplarily, each substructure includes one or more description information. The description information may include one or more of the following: physical address, description information type. Among them, the physical address may specifically include a starting address and a length, or the physical address is specifically a starting address. The physical address indicates a space in the host memory (which may be referred to as a physical memory space), which is used to store user data or the next substructure connected to the substructure. The description information type is used to identify whether the physical memory space is used to store user data or the next substructure.

[0072] Exemplarily, when the description information type is the first type, it indicates that the physical memory space is used to store the next substructure, and when the description information type is the second type, it indicates that the physical memory space is used to store user data. In any two adjacent substructures, the description information type in the last description information of the previous substructure is the first type, and the physical address is used to indicate the location of the next substructure in the host memory. The description information type of the description information other than the last description information in the previous substructure is the second type.

[0073] Furthermore, the length of each description information is fixed, for example, the length of each description information is 16 bytes. When the description information type is the first type, the length in the description information can also be used to indicate the number of description information included in the next substructure.

[0074] When the description information type is used to identify that the physical memory space is used to store the next substructure, it can also be further used to describe whether the next substructure is the last substructure in the first data structure. Exemplarily, when the description information type is the first type 1, it indicates that the next substructure is not the last substructure in the first data structure; when the description information type is the first type 2, it indicates that the next substructure is the last substructure in the first data structure.

[0075] The first data structure may be a SGL or a PRP list.

[0076] When the first data structure is SGL:

[0077] When the SGL includes one or more SGL segments (i.e., substructures), each SGL segment includes one or more SGL descriptors (or scatter / gather elements (SGE), i.e., description information). Figure 6 The format diagram of an SGL is shown in FIG. 1 , wherein the SGL includes SGL segments 1 to SGL segments 3, wherein each SGL descriptor occupies 16 bytes. The SGL segment 1 includes SGL descriptors 11 and 12, wherein the SGL descriptor 11 includes a starting address 11, a length of 3KB, and a second type, and is used to indicate the physical memory space where the user data A is located, and the length of the user data A is 3KB; the SGL descriptor 12 includes a starting address 12, a length of 32 bytes, and a first type 1, and is used to indicate the physical memory space where the SGL segment 2 is located, and the SGL segment 2 includes 2 SGL descriptors, and the SGL segment 2 is not the last substructure in the SGL. SGL segment 2 includes SGL descriptor 21 and SGL descriptor 22. SGL descriptor 21 includes starting address 21, length 4KB and second type, which is used to indicate the physical memory space where user data B is located, and the length of user data B is 4KB. SGL descriptor 22 includes starting address 22, length 16 bytes and first type 2, which is used to indicate the physical memory space where SGL segment 3 is located, and SGL segment 3 includes 1 SGL descriptor, and SGL segment 3 is the last substructure in SGL. SGL segment 3 includes SGL descriptor 31, SGL descriptor 31 includes starting address 31, length 4KB and second type, which is used to indicate the physical memory space where user data C is located, and the length of user data C is 4KB.

[0078] When the first data structure is a PRP list:

[0079] When the first data structure includes one or more PRP list pages (PRP list page) (i.e., substructures), each PRP list page includes one or more PRP entries (i.e., description information). Each PRP entry includes a starting address, and the PRP entry is used to describe a continuous physical memory space of a fixed length, and the fixed length can be one of 4KB, 8KB, 16KB, ..., 128KB. Taking the fixed length of 4KB as an example, a memory page can store a maximum of 512 PRP entries, and the 512 PRP entries can describe user data of 512×4K=2MB in size. When the first data structure includes multiple PRP list pages, the last PRP entry in the previous PRP list page of any two adjacent PRP list pages is used to represent the physical address of the next PRP list page in the host memory. For example Figure 7 The format diagram of a PRP list is shown in FIG. 1 , where the PRP list includes PRP list page 1 and PRP list page 2, wherein PRP list page 1 includes PRP entries 11 to 15, and PRP list page 2 includes PRP entries 21 to 25. Further, PRP entries 11 to 14 and PRP entries 21 to 25 include respective starting addresses, and respective starting addresses and fixed lengths of 4K are used to indicate respective physical memory spaces, each of which is used to store user data. The starting address and fixed length 4K in PRP entry 15 are used to indicate the physical memory space in which PRP list page 2 is stored.

[0080] Optionally, the NVMe access request also includes LBA, the total data size of the user data to be accessed, and an operation type, wherein the operation type is used to indicate whether the NVMe access request is a write request or a read request, and the operation type is, for example, an operation code (opcode).

[0081] For example, an NVMe access request is Figure 4 In the NVMe SQE of the related embodiment, the host CPU sends the NVMe SQE to the DPU through the bus, which can be seen in the above Figure 4 as described in Scheme 1.

[0082] Step 502: The DPU performs a splicing operation on the first data structure to obtain a second data structure. The number of substructures included in the second data structure is less than the number of substructures included in the first data structure. It can be considered that the first data structure is the data structure before the DPU performs splicing, that is, the data structure indicated by the NVMe access request, and the second data structure is the data structure after the DPU performs splicing.

[0083] Before step 502, the DPU may first obtain the first data structure from the host memory according to the physical address of the first substructure in the NVMe access request in the host memory. In a specific implementation, the DPU obtains the first substructure from the host memory according to the physical address of the first substructure in the host memory in the NVMe access request; then obtains the second substructure from the host memory according to the physical address in the host memory indicated in the last description information of the first substructure; then obtains the third substructure from the host memory according to the physical address in the host memory indicated in the last description information of the second substructure, and so on, until the DPU obtains the first data structure.

[0084] When the DPU splices multiple substructures in the first data structure, specifically, the DPU performs the following operations for every two adjacent substructures: delete the last description information in the previous substructure; splice the next substructure to the second-to-last description information in the previous substructure. In this way, the DPU can splice multiple substructures to obtain a spliced ​​structure. Since a memory page can store a limited amount of description information, for example, a memory page can only store 512 description information, the DPU can divide the structure obtained after splicing into multiple memory pages again, and set the last description information of the previous memory page in any two adjacent memory pages to describe the physical address of the next memory page in the preset space to obtain a second data structure. Among them, all memory pages except the last memory page in the multiple memory pages are full. For example, the structure obtained after splicing includes 1000 description information, and one memory page can only store 512 description information. Then the DPU can store the first 511 description information in the first memory page, and set the last description information in the first memory page to describe the physical address of the second memory page in the preset space, and store the remaining 489 description information (that is, the 512th description information to the 1000th description information) in the second memory page.

[0085] It is understandable that the DPU memory includes a preset space, which is used to store the second data structure. Further, the DPU can allocate one or more complete memory pages in the preset space to the second data structure. Compared with the host CPU being able to only allocate part of the memory page in the host memory (i.e., an incomplete memory page) to the first data structure, this solution can achieve: the number of substructures smaller than the memory page size in the second data structure is less than the number of substructures smaller than the memory page size in the first data structure; and / or the number of substructures equal to the memory page size in the second data structure is more than the number of substructures equal to the memory page size in the first data structure.

[0086] Furthermore, the second data structure may be a new type of SGL, each memory page corresponds to a new type of SGL segment in the second data structure, and each new type of SGL segment includes multiple SGL descriptors. An SGL descriptor includes a physical address (i.e., starting address, length) and a description information type. Furthermore, when the SGL descriptor is the last SGL descriptor in a memory page, the description information type in the SGL descriptor may be of the first type or the third type. Specifically, when the description information type in the SGL descriptor is of the first type, it is used to characterize that the physical memory space indicated by the SGL descriptor is used to store the next memory page; when the description information type in the SGL descriptor is of the third type, it is used to characterize that the SGL descriptor is the last SGL descriptor of the current second data structure. Optionally, when the SGL descriptor is not the last SGL descriptor in the memory page, the description information type is of the second type, i.e., it is used to indicate that the physical memory space indicated by the SGL descriptor is used to store user data. The format of the SGL descriptor can be found in Figure 8 As shown, the SGL descriptor may occupy 16 bytes, the start address may occupy 8 bytes, the length may occupy 4 bytes, and the description information type may occupy 4 bytes. In addition, when the SGL descriptor is not the last SGL descriptor in the memory page, the description information type may not be included in the SGL descriptor to reduce the overall length of the SGL descriptor.

[0087] like Fig. 9The schematic diagram of a substructure splicing is shown in the figure. The first data structure includes SGL segments 1 to SGL segments 3. SGL segment 1 includes SGL descriptors 1-1 to SGL descriptors 1-n. SGL segment 2 includes SGL descriptors 2-1 to SGL descriptors 2-m. SGL segment 3 includes SGL descriptors 3-1 and SGL descriptors 3-2. The values ​​of m and n can be the same or different. SGL segment 2 is stored in the physical memory space indicated by the starting address 1-n and the length 16×m bytes in SGL descriptors 1-n. SGL segment 3 is stored in the physical memory space indicated by the starting address 2-m and the length 32 bytes in SGL descriptors 2-m. Furthermore, when the DPU splices the SGL segment 1 and the SGL segment 2, it may specifically delete the SGL descriptors 1-n and then splice the SGL segment 2 after the SGL descriptor 1-(n-1); when the DPU splices the SGL segment 2 and the SGL segment 3, it may specifically delete the SGL descriptor 2-m and then splice the SGL segment 3 after the SGL descriptor 2-(m-1). In this way, the DPU obtains the structure after splicing. Furthermore, the DPU divides the SGL descriptors 1-1 to SGL descriptors 2-(m-2) in the spliced ​​structure into memory page 1 according to the memory page size, and divides the descriptors 2-(m-1) to SGL descriptors 3-2 into memory page 2. It can be understood that memory page 1, under the premise of including SGL descriptors 1-1 to SGL descriptors 2-(m-2), also includes the last SGL descriptor x, the description information type in the SGL descriptor x is the first type, and the starting address x is the starting address of memory page 2 in the preset space; the DPU also sets the description information type in the SGL descriptor 3-2 in memory page 2 to the third type, indicating that the SGL descriptor 3-2 is the last SGL descriptor in the second data structure.

[0088] It can be understood that in the second data structure, the length of each substructure (i.e., each memory page) except the last substructure is fixed, so the number of description information contained in each substructure is the same, and the DPU does not need to calculate the number of description information in the next substructure according to the "length" field in the description information every time it reads the last description information of the substructure, which helps to reduce the amount of calculation of the DPU. Furthermore, when the DPU generates the second data structure, in any two adjacent memory pages, the last description information in the previous memory page may no longer need to include the "length" field, which helps to reduce the length of the last description information. In addition, when the DPU splices the first data structure to obtain the second data structure, the function of the first type 2 in the first data structure is removed, and the function of the first type 1 is retained, that is, the first type in the second data structure is no longer used to indicate whether the next description information is the last description information in the first data structure, but by setting the description information type of the last description information in the second data structure to the third type, it indicates that the description information is the last description information in the second data structure. In this way, when the DPU reads the third type during the process of reading the second data structure, it can directly determine that the description information corresponding to the third type is the last description information in the second data structure. There is also no need to carry the "length" field in the last description information of the previous substructure to calculate the number of description information in the next substructure.

[0089] In one possible way, when the DPU is started, it applies for the preset space from the DPU memory. Optionally, the DPU can create a context corresponding to the access operation in the preset space and store the second data structure in the context. Optionally, the DPU can also store the total data size to be accessed in the context. The context can specifically be an input / output (IO) context. The DPU memory is, for example, a double data rate synchronous dynamic random access memory (DDR SDRAM) of the DPU. Optionally, the DPU also generates an index field for the second data structure and stores the index field of the second data structure and the second data structure in the preset space of the DPU accordingly. The index field is used by the DPU to index the second data structure from the preset space. In a specific implementation, the DPU stores the index field and the physical address of the first substructure of the second data structure in the preset space of the DPU accordingly, and accordingly, the index field is used to index the first substructure of the second data structure from the preset space (see the description in step 506 below for details).

[0090] Step 503: The DPU generates a RoCE access request based on the NVMe access request and the index field.

[0091] Exemplarily, the DPU may first perform protocol conversion on the NVMe access request to obtain a RoCE access request, and then add an index field to the RoCE access request; further exemplary, the DPU may first add an index field to the NVMe access request, and then perform protocol conversion on the NVMe access request with the newly added index field to obtain a RoCE access request. It can be understood that the RoCE access request includes not only the index field of the second data structure, but also the LBA, the total data size of the user data to be accessed, the operation type, etc.

[0092] Step 504: The DPU sends a RoCE access request to the storage system. Correspondingly, the storage system receives the RoCE access request from the DPU. The storage system and the DPU (or host) communicate via the RoCE network.

[0093] Step 505: The storage system initiates an RDMA operation to the DPU, and the RDMA operation includes an index field.

[0094] Among them, the RDMA operation can be considered as a response sent by the storage system to the DPU based on the RoCE access request, and the RDMA operation can also be called an RDMA request.

[0095] Specifically, after receiving the RoCE access request from the DPU, the storage system can parse the RoCE access request and obtain one or more of the following parameters from the RoCE access request: LBA, the total data size of the user data to be accessed, the index field, and the operation type. Then, the storage system initiates an RDMA operation to the DPU according to the RoCE access request.

[0096] When the storage system determines that the RoCE access request is a read request based on the operation type, the storage system reads the user data from the storage system based on the LBA and the total data size of the user data to be accessed, and then initiates an RDMA write operation to the DPU based on the read user data and index field. The RDMA write operation is used by the storage system to write the read user data to the host memory.

[0097] When the storage system determines that the RoCE access request is a write request based on the operation type, the storage system initiates an RDMA read operation to the DPU based on the LBA, the total data size of the user data to be accessed, and the index field. The RDMA read operation is used by the storage system to read user data from the host memory and write the read user data to the location indicated by the LBA in the storage system.

[0098] Step 506: The DPU searches for a second data structure from the DPU memory according to the index field in the RDMA operation.

[0099] The DPU searches the preset space for the physical address of the first substructure in the second data structure corresponding to the index field in the RDMA operation, and searches the preset space for the physical address of the second substructure in the second data structure according to the physical address of the first substructure in the second data structure, and so on, to obtain the second data structure.

[0100] When the DPU searches for the physical address of the first substructure from the preset space according to the index field in the RDMA operation, specifically, the DPU searches for the context containing the index field from the preset space according to the index field in the RDMA operation, and then obtains the physical address of the first substructure from the context. Exemplarily, the index field includes multiple bits, the first k bits of the multiple bits are used to index the context, and the remaining bits of the multiple bits except the first k bits are used for enhanced verification. Exemplarily, the index field includes 32 bits, k is equal to 24, that is, the first 24 bits in the index field are used to index the context, and the 25th to 32nd bits are used for enhanced verification.

[0101] It can be understood that, since the amount of data that can be carried by an RDMA operation is limited, when the total data size of the user data to be accessed by the NVMe access request (or RoCE access request) exceeds the maximum amount of data that can be carried by an RDMA operation, the storage system needs to send multiple RDMA operations to the DPU in sequence, and the amount of data carried in each RDMA operation is part of the total user data, and then the data carried in the multiple RDMA operations constitute the total user data. In this application, the user data carried in an RDMA operation can be referred to as a data shard. In this case, the storage system can carry an index field only in the first RDMA operation, which is used for the DPU to search for the second data structure from the preset space, and the index field does not need to be carried in subsequent RDMA operations, which helps to reduce the length of the RDMA operation.

[0102] Step 507: The DPU initiates a DMA operation to the host memory according to the second data structure.

[0103] Among them, the DMA operation can be considered as a response sent by the DPU to the host memory based on the NVMe access request, and the DMA operation can also be called a DMA request. Specifically, it can be divided into the following two cases: Case 1, the RDMA operation is an RDMA write operation, and the DMA operation is a DMA write operation. The DPU can write the data slice to the physical address of the host memory through a DMA write operation according to the physical address (i.e., DMA address) corresponding to the RDMA operation in the host memory. Case 2, the RDMA operation is an RDMA read operation, and the DMA operation is a DMA read operation. The DPU initiates a DMA read operation to the host memory according to the physical address corresponding to the RDMA read operation in the host memory. Correspondingly, the host memory can send a DMA write response to the DPU based on the physical address in the DMA read operation, and the DMA write response includes the data slice at the physical address of the host memory. The DPU then sends an RDMA write response to the storage system, and the RDMA write response includes the data slice. The storage system receives the RDMA write response and stores the data slice in the RDMA write response in the storage system.

[0104] In one possible implementation, the DPU determines the physical address corresponding to the RDMA operation in the host memory based on the second data structure, and then initiates a DMA operation to the host memory based on the physical address. In the case where the storage system needs to send multiple RDMA operations to the DPU in sequence, when the DPU determines the physical address corresponding to the RDMA operation in the host memory based on the second data structure, specifically, the DPU determines the physical address corresponding to each RDMA operation in the host memory based on the data size of the data slice indicated by each RDMA operation and the description information that has not been used in the second data structure. Among them, when the RoCE access request is a read request, the description information has not been used means that the storage system has not written user data into the physical memory space indicated by the description information; when the RoCE access request is a write request, the description information has not been used means that the storage system has not read user data from the physical memory space indicated by the description information into the storage system.

[0105] In one possible implementation, the DPU obtains the first j description information that has not been used in the second data structure, where j is a positive integer, and the physical memory space indicated by the j description information is greater than or equal to the size of the data shard. Furthermore, when j is greater than 1, the physical memory space indicated by the first j-1 description information is smaller than the size of the data shard. The DPU determines the physical address corresponding to the RDMA operation in the host memory based on the physical memory space indicated by the first j description information and the data size of the data shard. If the DPU determines that the physical memory space indicated by the j description information is greater than the data size of the data shard, it can also update the jth description information based on the remaining physical memory space. It can be understood that the physical memory space indicated by the jth description information after the update is the remaining physical memory space.

[0106] For example, if the total size of the user data to be accessed is 20KB, and the amount of data that can be carried by the RDMA operation is 5KB, then the storage system needs to send 4 RDMA operations to the DPU in sequence, and each RDMA operation can be used to indicate a 5KB data slice. Furthermore, for each 5KB of data, the DPU needs to determine which physical address in the host memory the 5KB of data corresponds to. Fig.10 In the second data structure shown, when the storage system sends the first RDMA operation to the DPU, the DPU obtains the SGL descriptor 1-1, and the physical memory space indicated by the starting address and length in the SGL descriptor 1-1 is 4KB, which is smaller than the size of a data slice. Then, the DPU can further obtain the SGL descriptor 1-2, and the physical memory space indicated by the starting address and length in the SGL descriptor 1-2 is 4KB. The DPU determines the starting address and length 4KB in the SGL descriptor 1-1 and the starting address and length 1KB in the SGL descriptor 1-2 as the physical address, where j=2. Further, the DPU updates the second data structure in the context, and the updated second data structure is as follows: Fig.10 In the updated second data structure, the SGL descriptors in the dashed-line frame are the SGL descriptors that have been used, and the SGL descriptors in the solid-line frame are the SGL descriptors that have not been used.

[0107] In the above technical solution, the DPU can receive multiple RDMA operations from the storage system and process each RDMA operation to solve the problem that the amount of data to be accessed by the NVMe access request (or RoCE access request) exceeds the amount of data that can be carried by a single RDMA operation. In addition, the storage system can carry an index field only in the first RDMA operation for the DPU to search for the second data structure from the preset space, and the index field does not need to be carried in subsequent RDMA operations, which helps to reduce the length of the RDMA operation.

[0108] Optionally, the method further includes:

[0109] Step 508: The storage system sends a RoCE access completion to the DPU, wherein the RoCE access completion includes a NoF CQE.

[0110] Step 509, the DPU obtains the NoF CQE from the RoCE response, performs protocol conversion on the NoF CQE to obtain the NVMe CQE, and sends the NVMe CQE to the host CPU. The NVMe CQE can also be called the NVMe access completion.

[0111] It should be added that in the above Figure 5 In a related embodiment, the DPU may include a computing power module, a programming module, an NVMe protocol processing module, a RoCE protocol processing module and a memory. Among them, the programming module can be implemented in whole or in part by software, hardware, firmware or any other combination. The programming module can be used to perform the actions of steps 502 to 507 above, that is, the present application can implement protocol conversion through the programming module, perform splicing operations on the first data structure to obtain the second data structure, generate the index field of the second data structure, index the second data structure from the preset space of the DPU, determine the physical address corresponding to the RDMA operation in the host memory, etc., without the participation of the computing power module, that is, there is no need to register MR, and there is no need to perform conversion between physical addresses and virtual addresses.

[0112] Combined with DPU architecture, such as Fig.11 This is a data access method in a specific scenario. The data access method is that the host reads user data from the storage system:

[0113] Process 1: The host sends a read request to the storage system.

[0114] Step 1: The host CPU places the NVMe SQE in the tail of the SQ, and notifies the NVMe protocol processing module that there is a new SQE to be executed by writing the new tail pointer in the SQ into the doorbell register. Correspondingly, the NVMe protocol processing module obtains the NVMe SQE from the head of the SQ. Subsequently, the NVMe protocol processing module sends the NVMe SQE to the programming module.

[0115] Among them, NVMe SQE is equivalent to Figure 5 NVMe SQE is used to indicate a first data structure. Exemplarily, the NVMe SQE includes a physical address of a first substructure in the first data structure in the host memory. The first data structure is, for example, an SGL or PRP list. For specific implementation, see the description in step 501 above.

[0116] Step 2: The programming module concatenates the first data structure to obtain a second data structure, generates an index field of the second data structure, and stores the second data structure and the index field in a preset space of the DPU. For specific implementation, please refer to the description in the above step 502.

[0117] Step 3: The programming module generates a NoF SQE according to the NVMe SQE and the index field, and sends the NoF SQE to the RoCE protocol processing module. For specific implementation, please refer to the description in the above step 503.

[0118] Step 4: The RoCE protocol processing module encapsulates the NoF SQE into a RoCE message (ie, a RoCE access request) and sends the RoCE access request to the storage system. For specific implementation, please refer to the description in the above steps 503 and 504.

[0119] Process 2: The storage system sends a read response to the host.

[0120] Step 1: The storage system parses the RoCE access request to obtain the NoF SQE.

[0121] Step 2: The storage system determines that the NoF SQE is a read request based on the operation type in the NoF SQE, and then reads data (i.e., data slices) from the storage system based on the LBA and data size in the NoFSQE. The storage system initiates an RDMA write operation to the DPU based on the read data slices, data slice size, and index fields. For specific implementation, please refer to the description in the above step 505.

[0122] Step 3: The RoCE protocol processing module receives the RDMA write operation from the storage system, parses the RDMA write operation into index fields, data slices, and data slice sizes, and sends the index fields, data slices, and data slice sizes to the programming module.

[0123] Step 4: The programming module indexes the second data structure from the DPU memory according to the index field. For specific implementation, please refer to the description in the above step 506.

[0124] Step 5: The programming module determines the DMA address according to the second data structure and the size of the data slice, and then initiates a DMA write operation to the host memory according to the DMA address and the data slice. That is, the programming module writes the user data to the DMA address of the host memory. For specific implementation, please refer to the description in the above step 507.

[0125] Process 3: The storage system sends a completion response to the host.

[0126] Step 1: After determining that the RDMA write operation is completed, the storage system forms a RoCE access completion and sends the RoCE access completion to the DPU, where the RoCE access completion includes a NoF CQE.

[0127] Step 2: After receiving the RoCE access completion, the DPU obtains the NoF CQE from the RoCE access completion, converts the NoF CQE to NVMe CQE, and sends the NVMe CQE to the host CPU. Among them, NVMe CQE can also be called NVMe access completion, and NVMe CQE is used to notify the host CPU that "the storage system has completed the read request initiated by the host."

[0128] In a specific implementation, after receiving the RoCE access completion, the RoCE protocol processing module obtains the NoF CQE from the RoCE access completion and sends the NoF CQE to the programming module. The programming module performs protocol conversion on the NoF CQE to obtain the NVMeCQE and sends the NVMe CQE to the NVMe protocol processing module. The NVMe protocol processing module puts the NVMe CQE at the end of the CQ and generates an interrupt to the host CPU. The host CPU obtains the CQE from the head of the CQ, processes the CQE, and writes the head pointer of the CQ to the doorbell register to notify the NVMe protocol processing module that it has read the CQE.

[0129] In the above technical solution, the DPU does not need to convert the physical address indicated by the data structure into a virtual address, and does not need to apply to the DPU memory for the MR required for the RoCE access request, which helps to reduce the processing delay inside the DPU. Further, the DPU performs a splicing operation on the first data structure to obtain a second data structure, wherein the number of substructures included in the second data structure is less than the number of substructures included in the first data structure, reducing the number of times the DPU searches for a subsequent substructure based on a previous substructure, that is, reducing the delay of the DPU determining the physical address in the host memory based on multiple substructures, which helps to shorten the delay of the host accessing the storage system.

[0130] It should be added that the above scheme is described by taking the deployment of the DPU inside the host 100 as an example. In another possible way, the DPU can also be used as an external device of the host 100. At this time, it can also be considered that the DPU receives an NVMe access request from the host CPU through the bus, and the NVMe access request is used to indicate the first data structure; the DPU performs a splicing operation on the first data structure to obtain a second data structure, and generates a RoCE access request based on the NVMe access request and the index field of the second data structure, and sends the RoCE access request to the storage system. In addition, the DPU receives an RDMA operation from the storage system, searches for the second data structure based on the index field included in the RDMA operation, and initiates a DMA operation to the memory through the bus based on the second data structure. For specific implementation, please refer to the description in the above embodiments.

[0131] Based on the above content and the same idea, Fig.12 The schematic diagram of the structure of the possible DPU provided by way of example in this application. These DPUs can be used to implement the functions of the DPU in the above method embodiments, and thus can also achieve the beneficial effects possessed by the above method embodiments.

[0132] like Fig.12 As shown, the DPU 1200 includes:

[0133] The first protocol processing module 1201, the programming module 1202, and the second protocol processing module 1203. Among them, the first protocol processing module 1201 is used to receive an NVMe access request from the CPU through the bus, and the NVMe access request is used to indicate a data structure; the programming module 1202 is used to perform a splicing operation on the data structure to obtain a data structure after the splicing operation, wherein the number of substructures included in the data structure after the splicing operation is less than the number of substructures included in the data structure before the splicing operation; a RoCE access request is generated according to the NVMe access request and an index field for searching the data structure after the splicing operation; the second protocol processing module 1203 is used to send a RoCE access request to the storage system, and the DPU and the storage system communicate through the network. A more detailed description of the above-mentioned first protocol processing module 1201, programming module 1202, and second protocol processing module 1203 can be directly obtained by referring to the relevant description in the above-mentioned method embodiment, and will not be repeated here. Exemplarily, the first protocol processing module 1201 and the second protocol processing module 1203 can be respectively Figure 4 or Fig.11 NVMe protocol processing module and RoCE protocol processing module in. Exemplarily, programming module 1202 is Figure 4 or Fig.11 The programming module in .

[0134] Based on the above content and the same concept, the present application provides a host, including the CPU in the above method embodiment, and the DPU in the above method embodiment, wherein the CPU and the DPU communicate through a bus, and the DPU is used to execute the method in the above method embodiment.

[0135] Based on the above content and the same concept, the present application provides a DPU interface card, including a processor and an interface, the interface supports a bus protocol, the interface is used to communicate with the host's CPU through the bus, and the processor is used to execute the method in the above method embodiment.

[0136] Based on the above content and the same concept, the present application provides a processor, which includes a logic circuit and a power supply circuit. The power supply circuit is used to supply power to the logic circuit, and the logic circuit is used to execute the method in the above method embodiment.

[0137] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function according to the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage system such as a server, data center, etc. that contains one or more available media sets. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium. The semiconductor medium can be a solid state drive (SSD).

[0138] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0139] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0140] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0141] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0142] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A data access method, characterized in that: Applicable to a host, the host comprises a central processing unit CPU, a data processing unit DPU, a memory and a bus, the CPU, the DPU and the memory are connected to the bus; The method is performed by the DPU, and the method includes: Receiving a non-volatile storage fast NVMe access request from the CPU through the bus, wherein the NVMe access request is used to indicate a data structure; Performing a concatenation operation on the data structure to obtain a data structure after the concatenation operation, wherein the number of substructures included in the data structure after the concatenation operation is less than the number of substructures included in the data structure before the concatenation operation; Generate a remote direct memory access RoCE access request based on converged Ethernet according to the NVMe access request and an index field for searching the data structure after the splicing operation; The RoCE access request is sent to a storage system, and the DPU and the storage system communicate through a network.

2. The method according to claim 1, characterized in that The number of substructures smaller than the memory page size in the data structure after the splicing operation is less than the number of substructures smaller than the memory page size in the data structure before the splicing operation; and / or, The number of substructures equal to the memory page size in the data structure after the splicing operation is greater than the number of substructures equal to the memory page size in the data structure before the splicing operation.

3. The method according to claim 1, characterized in that After sending the RoCE access request to the storage system, the method further includes: Receiving a remote direct memory access (RDMA) operation from the storage system; According to the index field included in the RDMA operation, searching for the data structure after the splicing operation; According to the data structure after the splicing operation, a direct memory access (DMA) operation is initiated to the memory through the bus.

4. The method according to any one of claims 1 to 3, characterized in that After the data structure is spliced ​​to obtain the data structure after the splicing operation, the method further includes: Generate the index field; The data structure after the splicing operation and the index field are stored correspondingly in the preset space of the DPU.

5. The method according to claim 4, characterized in that The preset space of the DPU is generated when the DPU is started.

6. A data processing unit DPU, characterized in that: Applicable to a host, the host comprises a central processing unit CPU, the DPU, a memory and a bus, the CPU, the DPU and the memory are connected to the bus; The DPU includes: A first protocol processing module, configured to receive a non-volatile storage fast NVMe access request from the CPU through the bus, wherein the NVMe access request is used to indicate a data structure; A programming module, configured to perform a splicing operation on the data structure to obtain a data structure after the splicing operation, wherein the number of substructures included in the data structure after the splicing operation is less than the number of substructures included in the data structure before the splicing operation; and generating a remote direct memory access RoCE access request based on converged Ethernet according to the NVMe access request and an index field for searching the data structure after the splicing operation; The second protocol processing module sends the RoCE access request to the storage system, and the DPU and the storage system communicate through the network.

7. The DPU according to claim 6, characterized in that The number of substructures smaller than the memory page size in the data structure after the splicing operation is less than the number of substructures smaller than the memory page size in the data structure before the splicing operation; and / or, The number of substructures equal to the memory page size in the data structure after the splicing operation is greater than the number of substructures equal to the memory page size in the data structure before the splicing operation.

8. The DPU according to claim 6, characterized in that After the second protocol processing module sends the RoCE access request to the storage system, the second protocol processing module is further used to: receive a remote direct memory access RDMA operation from the storage system; The programming module is also used to: search for the data structure after the splicing operation according to the index field included in the RDMA operation, and initiate a direct memory access DMA operation to the memory through the bus according to the data structure after the splicing operation.

9. The DPU according to any one of claims 6 to 8, characterized in that: After performing a splicing operation on the data structure to obtain the data structure after the splicing operation, the programming module is also used to: generate the index field; and store the data structure after the splicing operation and the index field correspondingly in the preset space of the DPU.

10. The DPU according to claim 9, characterized in that The preset space of the DPU is generated when the DPU is started.

11. A host, characterized in that: It comprises a central processing unit CPU as described in any one of claims 1 to 5 and a data processing unit DPU as described in any one of claims 1 to 5, the CPU and the DPU communicate via a bus, and the DPU is used to execute the method as described in any one of claims 1 to 5.

12. A data processing unit DPU interface card, characterized in that: The method comprises a processor and an interface, wherein the interface supports a bus protocol and is used to communicate with a central processing unit (CPU) of a host through a bus. The processor is used to execute a method as claimed in any one of claims 1 to 5.

13. A processor, characterized in that: The processor comprises a logic circuit and a power supply circuit, wherein the power supply circuit is used to supply power to the logic circuit, and the logic circuit is used to execute the method according to any one of claims 1 to 5.

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