In-memory calculation method, system and device based on 1T and storage medium

Abstract

The invention discloses a 1T-based in-memory calculation method, system and device and a storage medium, and the method comprises the steps: firstly, designing the width-to-length ratio of a transistor to complete different weight mapping and storage; the digital-to-analog converter receives an input signal and converts the input signal into an input voltage; further, the input voltage is input to grid electrodes of a plurality of transistors in an in-memory calculation unit, and leakage current is determined based on the width-to-length ratio of each transistor and the input voltage; and finally, the in-memory calculation unit determines a final matrix addition and multiplication result according to the leakage current output by each transistor. According to the invention, the width-to-length ratio of the transistor is used for representing the stored data, the 1T transistor is used for forming the analog in-memory calculation array, and finally the integration of storage and calculation is realized.

Description

Technical Field

[0001] The present invention relates to the field of in-memory computing technology, and in particular to an 1T-based in-memory computing method, system, device and storage medium. Background Art

[0002] In-Memory Computing is a computing mode that integrates data storage and processing in the same memory space to improve the speed and efficiency of data processing. With the advent of the era of big data and artificial intelligence, the amount of data is growing exponentially, and traditional data processing methods have been unable to meet the rapidly growing computing needs. In this context, in-memory computing came into being. It greatly reduces the latency of data access by storing data directly in memory instead of traditional hard disk storage.

[0003] Digital in-memory computing and analog in-memory computing are the two main forms of in-memory computing technology, each with different principles, advantages and application scenarios. Digital in-memory computing uses all-digital circuits to perform calculations, and directly integrates bit-by-bit digital multiplication and accumulation operations into the memory array. This computing method has great application potential in neural network computing scenarios. Data in-memory computing has the advantages of high precision and high robustness, but digital in-memory computing has large area (due to the limited density of SRAM process) and power consumption overhead, and digital in-memory computing is designed based on volatile memory, and data transfer is still required. Analog in-memory computing is mainly based on physical laws (such as Ohm's law and Kirchhoff's law) to implement multiplication and accumulation operations on in-memory computing arrays. This computing method usually uses RRAM (resistive random access memory) and Flash (flash memory) as storage media. Analog in-memory computing has a small overhead in terms of area, power consumption, etc., and is energy efficient, but may lack accuracy. Using non-volatile memory devices (such as RRAM, PCM) for in-memory computing is a promising method to reduce data transmission. In the prior art, storage media based on non-volatile analog in-memory computing, such as RRAM and PCM, have more complex processes and low yields. In addition, the data stored in RRAM and PCM will undergo slight changes during each calculation, resulting in the need to rewrite after a certain number of calculations.

[0004] Therefore, the prior art needs to be improved. Summary of the invention

[0005] The technical problem to be solved by the present invention is that, in view of the above-mentioned defects of the prior art, an in-memory computing method, system, device and storage medium based on 1T are provided, aiming to solve the problems of low area efficiency of digital in-memory computing and immature analog in-memory computing technology in the prior art.

[0006] The technical solution adopted by the present invention to solve the problem is as follows:

[0007] In a first aspect, an embodiment of the present invention provides an in-memory computing method based on 1T, wherein the method comprises:

[0008] Design the width-to-length ratio of transistors to achieve different weight mapping and storage;

[0009] The digital-to-analog converter receives an input signal and converts the input signal into an input voltage;

[0010] Inputting the input voltage to the gates of a plurality of transistors in an in-memory computing unit, and determining a leakage current based on a width-to-length ratio of each transistor and the input voltage;

[0011] The in-memory computing unit determines the final matrix multiplication result based on the leakage current output by each transistor.

[0012] In one implementation, the input voltage includes a saturation region input voltage, a linear region input voltage, and a subthreshold region input voltage, and converting the input signal into the input voltage includes:

[0013] Inputting the input signal into a digital-to-analog converter, the digital-to-analog converter converts the input signal so that the input signal is in a saturation region of the transistor, and obtaining a saturation region input voltage;

[0014] Or, inputting the input signal into a digital-to-analog converter, the digital-to-analog converter adjusts the input signal so that the input signal is in the linear region of the transistor, and obtaining a linear region input voltage;

[0015] Alternatively, the input signal is input into a digital-to-analog converter, and the digital-to-analog converter adjusts the input signal so that the input signal is in a subthreshold region of the transistor, thereby obtaining a subthreshold region input voltage.

[0016] In one implementation, determining the leakage current based on the width-to-length ratio of each transistor and the input voltage includes:

[0017] When the input voltage is a saturation region input voltage, the calculation formula of the leakage current is:

[0018]

[0019] Among them, I D Represents leakage current, μ n represents the electron mobility, C ox represents the gate oxide capacitance, W represents the width of the transistor, L represents the length of the transistor, V GS Indicates the saturation region input voltage, V thRepresents the threshold voltage.

[0020] In one implementation, determining the leakage current based on the width-to-length ratio of each transistor and the input voltage includes:

[0021] When the input voltage is a linear region input voltage, the calculation formula of the leakage current is:

[0022]

[0023] Among them, I D Represents leakage current, μ n represents the electron mobility, C ox represents the gate oxide capacitance, W represents the width of the transistor, L represents the length of the transistor, V GS Represents the linear region input voltage, V th represents the threshold voltage, the V DS represents the drain-source voltage.

[0024] In one implementation, determining the leakage current based on the width-to-length ratio of each transistor and the input voltage includes:

[0025] When the input voltage is a subthreshold region input voltage, the calculation formula of the leakage current is:

[0026]

[0027] Among them, I D represents the leakage current, I0 represents the empirical current, V GS represents the subthreshold region adjustment voltage, n represents the process parameter, represents the thermal voltage, k represents the Boltzmann constant, T represents the absolute temperature, q represents the electron charge, μ n represents the electron mobility, C ox represents gate oxide capacitance, W represents the width of the transistor, and L represents the length of the transistor.

[0028] In one implementation, the method further includes:

[0029] Several transistors in the in-memory computing unit are connected in series or in parallel.

[0030] In a second aspect, an embodiment of the present invention further provides an in-memory computing system based on 1T, wherein the system includes:

[0031] Transistor design module, used to design the width-to-length ratio of transistors to complete different weight mapping and storage;

[0032] A regulating module, used for a digital-to-analog converter to receive an input signal and convert the input signal into an input voltage;

[0033] An input module, used for inputting the input voltage to the gates of a plurality of transistors in the in-memory computing unit, and determining a leakage current based on the width-to-length ratio of each transistor and the input voltage;

[0034] The calculation module is used to determine the final matrix multiplication and addition result according to the leakage current output by each transistor in the internal calculation unit.

[0035] In one implementation, the calculation module is further used for:

[0036] Use the width-to-length ratio of each transistor to store the parameters of the neural network;

[0037] Alternatively, the number of transistors connected in series or in parallel is used to represent the stored neural network parameter value.

[0038] In a third aspect, an embodiment of the present invention further provides a terminal device, wherein the terminal device is a commercial display terminal, the terminal device includes a memory, a processor, and a program based on an in-memory computing method based on 1T stored in the memory and executable on the processor, and when the processor executes the program based on the in-memory computing method based on 1T, the steps of the in-memory computing method based on 1T of any one of the above-mentioned schemes are implemented.

[0039] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, wherein a program of an in-memory computing method based on 1T is stored on the computer-readable storage medium, and when the program of the in-memory computing method based on 1T is executed by a processor, the steps of the in-memory computing method based on 1T described in any one of the above schemes are implemented.

[0040] Beneficial effects of the present invention: Compared with the prior art, the present invention provides an in-memory computing method, system, device and storage medium based on 1T. First, the present invention designs the aspect ratio of transistors to complete different weight mapping and storage; then the digital-to-analog converter receives the input signal and converts the input signal into an input voltage; further, the input voltage is input to the gates of several transistors in the in-memory computing unit, and the leakage current is determined based on the aspect ratio of each transistor and the input voltage; finally, the in-memory computing unit determines the result of the final matrix multiplication according to the leakage current output by each transistor. This application uses the aspect ratio of transistors to represent the stored data, and uses 1T transistors to form an analog in-memory computing array, and finally realizes the integration of storage and computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0042] Figure 1 It is a flowchart of an in-memory computing method based on 1T provided in an embodiment of the present invention.

[0043] Figure 2 It is a schematic diagram of in-memory computing based on non-volatile memory provided by an embodiment of the present invention.

[0044] Figure 3 It is a schematic diagram of transistor parallel connection based on the 1T in-memory computing method provided by an embodiment of the present invention.

[0045] Figure 4 It is a schematic diagram of transistor series connection of an in-memory computing method based on 1T provided in an embodiment of the present invention.

[0046] Figure 5 It is a principle block diagram of an 1T-based in-memory computing system provided by an embodiment of the present invention.

[0047] Figure 6 It is a block diagram of the internal structure principle of an 1T-based in-memory computing device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0048] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present invention. However, it should be clear to those skilled in the art that the present invention may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present invention.

[0049] It should be understood that when used in this specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0050] It should also be understood that the terms used in the present specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0051] It should be further understood that the term "and / or" used in the present description and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0052] As used in this specification and the appended claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0053] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0054] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0055] In the prior art, there is a problem of low in-memory computing efficiency.

[0056] In order to solve the problems in the prior art, this embodiment provides an in-memory computing method based on 1T, by which efficient and fast in-memory computing can be achieved. In specific implementation, first, the width-to-length ratio of the transistor is designed to complete different weight mapping and storage; then the digital-to-analog converter receives the input signal and converts the input signal into an input voltage; further, the input voltage is input to the gates of several transistors in the in-memory computing unit, and the leakage current is determined based on the width-to-length ratio of each transistor and the input voltage; finally, the in-memory computing unit determines the final matrix multiplication result according to the leakage current output by each transistor. This application uses the width-to-length ratio of transistors to represent the stored data, and uses 1T transistors to form an analog in-memory computing array, ultimately realizing the integration of storage and computing.

[0057] For example, first, the aspect ratio of the transistor is designed to complete different weight mapping and storage; then the digital-to-analog converter receives the input signal and converts the input signal into an input voltage; further, the input voltage is input to the gates of several transistors in the in-memory computing unit, and the leakage current is determined based on the aspect ratio of each transistor and the input voltage; finally, the in-memory computing unit determines the final matrix multiplication result based on the leakage current output by each transistor. This application uses the aspect ratio of transistors to represent the stored data, and uses 1T transistors to form an analog in-memory computing array, ultimately realizing the integration of storage and computing.

[0058] Exemplary Methods

[0059] This embodiment provides an in-memory computing method based on 1T, which can be applied to a terminal device for in-memory storage and computing. Figure 1 As shown, the method includes:

[0060] Step S100, designing the width-to-length ratio of transistors to complete different weight mapping and storage.

[0061] In this embodiment, first, the aspect ratio of the transistor is designed to complete the mapping and storage of different weights.

[0062] Step S200: The digital-to-analog converter receives an input signal and converts the input signal into an input voltage.

[0063] In this embodiment, the input signal is converted by a digital-to-analog converter (DAC) so that the transistor works in a specific working area. In a specific implementation, the input voltage includes a saturation region input voltage, a linear region input voltage and a subthreshold region input voltage, and the input signal is converted into an input voltage, including: inputting the input signal into a digital-to-analog converter, the digital-to-analog converter converts the input signal so that the input signal is in the saturation region of the transistor, and obtains a saturation region input voltage; or, inputting the input signal into a digital-to-analog converter, the digital-to-analog converter adjusts the input signal so that the input signal is in the linear region of the transistor, and obtains a linear region input voltage; or, inputting the input signal into a digital-to-analog converter, the digital-to-analog converter adjusts the input signal so that the input signal is in the subthreshold region of the transistor, and obtains a subthreshold region input voltage.

[0064] Step S300: input the input voltage to the gates of several transistors in the in-memory computing unit, and determine the leakage current based on the width-to-length ratio of each transistor and the input voltage.

[0065] In this embodiment, the input signal has been adjusted to the target working area in step S200, that is, it has been converted into the input voltage of a specific working area, and then the converted input voltage is directly applied to the gates of several transistors in the in-memory computing unit, and the leakage current is calculated based on the width-to-length ratio of each transistor and the input voltage.

[0066] In this embodiment, the aspect ratio of each transistor is used to represent the stored information, and the output current of the transistor is proportional to the aspect ratio of the transistor. Therefore, the output leakage current can be determined by the aspect ratio of the transistor. In a specific implementation, the leakage current is determined based on the aspect ratio of each transistor and the input voltage, including: when the input voltage is a saturation region input voltage, the calculation formula of the leakage current is: Among them, I D Represents leakage current, μ n represents the electron mobility, C ox represents the gate oxide capacitance, W represents the width of the transistor, L represents the length of the transistor, V GS Indicates the saturation region input voltage, V th Represents the threshold voltage. If the adjusted input voltage can ensure that the transistor operates in the saturation region, the leakage current output by each transistor can be calculated according to the formula.

[0067] In one implementation, the determining of the leakage current based on the width-to-length ratio of each transistor and the input voltage includes: when the input voltage is a linear region input voltage, the calculation formula of the leakage current is: Among them, I D Represents leakage current, μ n represents the electron mobility, C ox represents the gate oxide capacitance, W represents the width of the transistor, L represents the length of the transistor, V GS Represents the linear region input voltage, V th represents the threshold voltage, the V Ds Represents the drain-source voltage. If the regulated input voltage can ensure that the transistor operates in the linear region, the leakage current output by each transistor is calculated according to the formula.

[0068] In one implementation, the determining of the leakage current based on the width-to-length ratio of each transistor and the input voltage includes: when the input voltage is a subthreshold region input voltage, the calculation formula of the leakage current is: Among them, I D represents the leakage current, and I0 represents the empirical current, which is usually used to describe the current level of the transistor in the subthreshold region. It is related to the geometric size, process parameters and working conditions of the transistor. In practical applications, it can be regarded as an empirical parameter obtained through experimental measurement. V GSrepresents the subthreshold region input voltage, n represents the process parameter, represents the thermal voltage, k represents the Boltzmann constant, T represents the absolute temperature, q represents the electron charge, μ n represents the electron mobility, C ox represents the gate oxide capacitance, W represents the width of the transistor, and L represents the length of the transistor. If the adjusted input voltage can ensure that the transistor operates in the subthreshold region, the leakage current output by each transistor is calculated according to the formula.

[0069] Step S400: The in-memory computing unit determines the final matrix multiplication result according to the leakage current output by each transistor.

[0070] In this embodiment, the leakage current output by each transistor has been obtained in step S300. In specific implementation, the matrix multiplication and addition result is calculated for the leakage current output by each transistor.

[0071] In one implementation, the method further includes: a plurality of transistors in the in-memory computing unit are connected in series or in parallel. Figure 2 This is a schematic diagram of in-memory computing in a common non-volatile memory. Figure 3 The figure shows the parallel connection of transistors. Figure 4 Shown is a series arrangement of transistors, created by connecting two standard aspect ratio transistors in series to represent a transistor of twice the length.

[0072] Beneficial effects of the present application: The present application realizes a non-volatile storage, small area (only one transistor is needed for the storage and calculation of each weight), low power consumption analog in-memory calculation that does not require special processes (no need for RRAM, PCM, etc.), can be made with the current mature CMOS process, and compared with other in-memory calculations based on non-volatile memory, such as RRAM, this method only uses mature CMOS processes, and has the advantages of low cost, high yield, and short manufacturing cycle. By using the width-to-length ratio of transistors as storage media, it will not change with calculations. Reduce power consumption and area overhead. Compared with digital in-memory calculations, this method greatly reduces data handling, improves storage density, and uses the inherent characteristics of transistors for calculations without the need to use huge addition numbers. Multiple modes: Transistors can choose to work in the saturation region or actively choose to work in the subthreshold region. Working in the subthreshold region can achieve extreme low energy consumption, but will bring delays and a certain degree of precision reduction. Suitable for scenarios that are not sensitive to delays and precision but have high requirements for low power consumption.

[0073] Exemplary Systems

[0074] Based on the above embodiments, the present invention also provides an in-memory computing system based on 1T, such as Figure 5As shown, the system in this embodiment includes a transistor design module 10, an adjustment module 20, an input module 30 and a calculation module 40. Specifically, the transistor design module 10 is used to design the width-to-length ratio of the transistor to complete different weight mappings and storage; the adjustment module 20 is used for the digital-to-analog converter to receive the input signal and convert the input signal into an input voltage; the input module 30 is used to input the input voltage to the gates of several transistors in the in-memory calculation unit, and determine the leakage current based on the width-to-length ratio of each transistor and the input voltage; the calculation module 40 is used for the in-memory calculation unit to determine the final matrix multiplication result according to the leakage current output by each transistor.

[0075] In one implementation, the calculation module is further used for:

[0076] Use the width-to-length ratio of each transistor to store the parameters of the neural network;

[0077] Alternatively, the number of transistors connected in series or in parallel is used to represent the stored neural network parameter value.

[0078] The working principles of each module in the 1T in-memory computing system in this embodiment are the same as the principles of each step in the above method embodiment, and will not be repeated here.

[0079] Based on the above embodiments, the present invention further provides a terminal device, the principle block diagram of the terminal device can be as follows: Figure 6 The terminal device may include one or more processors 100 ( Figure 6 Only one is shown), a memory 101 and a computer program 102 stored in the memory 101 and executable on one or more processors 100, for example, a program based on an in-memory computing method of 1T. When one or more processors 100 execute the computer program 102, the various steps in the method embodiment based on the in-memory computing method of 1T can be implemented. Alternatively, when one or more processors 100 execute the computer program 102, the functions of the various modules / units in the device embodiment based on the in-memory computing method of 1T can be implemented, which is not limited here.

[0080] In one embodiment, the processor 100 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0081] In one embodiment, the memory 101 may be an internal storage unit of an electronic device, such as a hard disk or memory of the electronic device. The memory 101 may also be an external storage device of the electronic device, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the electronic device. Further, the memory 101 may also include both an internal storage unit of the electronic device and an external storage device. The memory 101 is used to store computer programs and other programs and data required by the terminal device. The memory 101 may also be used to temporarily store data that has been output or is to be output.

[0082] Those skilled in the art will understand that Figure 3 The principle block diagram shown in the figure is only a block diagram of a part of the structure related to the solution of the present invention, and does not constitute a limitation on the terminal device to which the solution of the present invention is applied. The specific terminal device includes Figure 3 More or fewer components may be shown, or certain components may be combined, or may have a different arrangement of components.

[0083] An embodiment of the present invention further provides a computer-readable storage medium, on which a super device model generation method program is stored. When the super device model generation method program is executed by a processor, the steps of any super device model generation method provided by the embodiment of the present invention are implemented.

[0084] It should be understood that the serial numbers of the steps in the above embodiments do not imply a sequence of execution, and the execution sequence of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0085] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the above-mentioned device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present invention. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0086] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0087] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0088] In the embodiments provided by the present invention, it should be understood that the disclosed apparatus / terminal equipment and method can be implemented in other ways. For example, the apparatus / terminal equipment embodiments described above are only illustrative, for example, the division of the above modules or units is only a logical function division, and in actual implementation, other division methods can be used, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0089] If the above-mentioned integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The above-mentioned computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the above-mentioned computer program includes computer program code, and the above-mentioned computer program code can be in source code form, object code form, executable file or some intermediate form. The above-mentioned computer-readable medium may include: any entity or device capable of carrying the above-mentioned computer program code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium. It should be noted that the content contained in the above-mentioned computer-readable storage medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction.

[0090] In summary, the present invention discloses an in-memory computing method, system, device and storage medium based on 1T, the method comprising: first, designing the width-to-length ratio of transistors to complete different weight mapping and storage; then the digital-to-analog converter receives the input signal and converts the input signal into an input voltage; further, the input voltage is input to the gates of several transistors in the in-memory computing unit, and the leakage current is determined based on the width-to-length ratio of each transistor and the input voltage; finally, the in-memory computing unit determines the result of the final matrix multiplication according to the leakage current output by each transistor. This application uses the width-to-length ratio of transistors to represent the stored data, and uses 1T transistors to form an analog in-memory computing array, and finally realizes the integration of storage and computing.

[0091] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A 1T-based in-memory computing method, characterized in that: The method comprises: Design the width-to-length ratio of transistors to achieve different weight mapping and storage; The digital-to-analog converter receives an input signal and converts the input signal into an input voltage; Inputting the input voltage to the gates of a plurality of transistors in an in-memory computing unit, and determining a leakage current based on a width-to-length ratio of each transistor and the input voltage; The in-memory computing unit determines the final matrix multiplication result based on the leakage current output by each transistor.

2. The 1T-based in-memory computing method according to claim 1, characterized in that: The input voltage includes a saturation region input voltage, a linear region input voltage and a subthreshold region input voltage, and the step of converting the input signal into the input voltage includes: Inputting the input signal into a digital-to-analog converter, the digital-to-analog converter converts the input signal so that the input signal is in a saturation region of the transistor, and obtaining a saturation region input voltage; Or, inputting the input signal into a digital-to-analog converter, the digital-to-analog converter adjusts the input signal so that the input signal is in the linear region of the transistor, and obtaining a linear region input voltage; Alternatively, the input signal is input into a digital-to-analog converter, and the digital-to-analog converter adjusts the input signal so that the input signal is in a subthreshold region of the transistor, thereby obtaining a subthreshold region input voltage.

3. The 1T-based in-memory computing method according to claim 2, characterized in that: The determining of the leakage current based on the width-to-length ratio of each transistor and the input voltage comprises: When the input voltage is a saturation region input voltage, the calculation formula of the leakage current is: Among them, I D Represents leakage current, μ n represents the electron mobility, C ox represents the gate oxide capacitance, W represents the width of the transistor, L represents the length of the transistor, V GS Indicates the saturation region input voltage, V th Represents the threshold voltage.

4. The 1T-based in-memory computing method according to claim 2, characterized in that: The determining of the leakage current based on the width-to-length ratio of each transistor and the input voltage comprises: When the input voltage is a linear region input voltage, the calculation formula of the leakage current is: Among them, I D Represents leakage current, μ n represents the electron mobility, C ox represents the gate oxide capacitance, W represents the width of the transistor, L represents the length of the transistor, V GS Represents the linear region input voltage, V th represents the threshold voltage, the V DS represents the drain-source voltage.

5. The 1T-based in-memory computing method according to claim 2, characterized in that: The determining of the leakage current based on the width-to-length ratio of each transistor and the input voltage comprises: When the input voltage is a subthreshold region input voltage, the calculation formula of the leakage current is: Among them, I D represents the leakage current, I0 represents the empirical current, V GS represents the subthreshold region adjustment voltage, n represents the process parameter, represents the thermal voltage, k represents the Boltzmann constant, T represents the absolute temperature, q represents the electron charge, μ n represents the electron mobility, C ox represents gate oxide capacitance, W represents the width of the transistor, and L represents the length of the transistor.

6. The 1T-based in-memory computing method according to claim 1, characterized in that: The method further comprises: Several transistors in the in-memory computing unit are connected in series or in parallel.

7. A 1T-based in-memory computing system, characterized in that: The system comprises: Transistor design module, used to design the width-to-length ratio of transistors to complete different weight mapping and storage; A regulating module, used for a digital-to-analog converter to receive an input signal and convert the input signal into an input voltage; An input module, used for inputting the input voltage to the gates of a plurality of transistors in the in-memory computing unit, and determining a leakage current based on the width-to-length ratio of each transistor and the input voltage; The calculation module is used to determine the final matrix multiplication and addition result according to the leakage current output by each transistor in the internal calculation unit.

8. The 1T-based in-memory computing system according to claim 7, characterized in that: The calculation module is also used for: Use the width-to-length ratio of each transistor to store the parameters of the neural network; Alternatively, the number of transistors connected in series or in parallel is used to represent the stored neural network parameter value.

9. A terminal device, characterized in that: The terminal device includes a memory, a processor, and an in-memory computing method program based on 1T stored in the memory and executable on the processor. When the processor executes the in-memory computing method program based on 1T, the steps of the in-memory computing method based on 1T as described in any one of claims 1 to 6 are implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a 1T-based in-memory computing method program, and when the 1T-based in-memory computing method program is executed by a processor, the steps of the 1T-based in-memory computing method as described in any one of claims 1-6 are implemented.

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