Simplified interrupt control method, device, equipment and medium

Abstract

The invention relates to the technical field of interrupt control, and discloses a simplified interrupt control method and device, equipment and a medium. The method comprises the following steps: judging whether an interrupt vector is enabled or not, wherein the interrupt vector comprises a plurality of ITRs; under the condition that the interrupt vector is successfully enabled, the priority of the interrupt event is obtained, the timing requirement of a first ITR is determined based on the priority, the first ITR is the ITR associated with the interrupt event, and the timing requirement is used for adjusting the bit width of the first ITR; adjusting a timer based on the timing demand of each ITR in the interrupt vector; and after timing of the timer is finished, sending the interrupt vector to the host so as to trigger the interrupt vector. According to the invention, the requirement of the interrupt vector for hardware resources can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of interrupt control, and in particular to a simplified interrupt control method, device, equipment and medium. Background Art

[0002] High-speed network cards receive and send data by reporting interrupts to the host. However, frequent interrupts will reduce the system performance of computer equipment, and high-rate interrupts will increase the utilization of the CPU (Central Processing Unit). In order to reduce the utilization of the CPU, an interrupt regulation mechanism (Interrupt Throttling Register, ITR) is used to limit the interrupt rate.

[0003] As network traffic increases, the demand for interrupt vectors by high-speed network cards increases. In related technologies, the demand for interrupt vectors by high-speed network cards is met by increasing the number of ITRs shared by each interrupt vector, but this places greater demands on hardware resources.

[0004] In view of this, a simplified interrupt control method with small hardware resource requirements is needed. Summary of the invention

[0005] In view of this, the present invention provides a simplified interrupt control method, which can reduce the demand of interrupt vectors on hardware resources.

[0006] In a first aspect, the present invention provides a streamlined interrupt control method, the method comprising: determining whether an interrupt vector is enabled, wherein the interrupt vector includes a plurality of ITRs; when the interrupt vector is successfully enabled, obtaining the priority of the interrupt event, and based on the priority, determining the timing requirement of the first ITR, wherein the first ITR is the ITR associated with the interrupt event, and the timing requirement is used to adjust the bit width of the first ITR; adjusting a timer based on the timing requirements of each ITR in the interrupt vector; after the timer expires, sending the interrupt vector to a host to trigger the interrupt vector.

[0007] In this embodiment, by judging whether the interrupt vector is enabled, and if it is enabled successfully, the timing requirement of the corresponding ITR is determined according to the priority of the interrupt event, wherein the timing requirement is used to adjust the bit width of the ITR associated with the interrupt event; according to the timing requirement of each ITR in the interrupt vector, the value of the timer is determined to trigger the interrupt vector after the timer ends. The bit width of the ITR associated with the interrupt event can be adjusted according to different interrupt events to reduce the demand for hardware resources and improve the response speed and processing efficiency of the system to interrupts.

[0008] In an optional implementation, adjusting the bit width of the first ITR includes: sorting the timing requirements of each interrupt event, and adjusting the bit width of the ITR associated with each interrupt event in sequence according to the sorting result.

[0009] In this embodiment, by sorting the timing requirements of the interrupt events and adjusting the bit width of the corresponding ITR according to the sorting result, the allocation of hardware resources can be optimized and the flexibility of the method can be improved.

[0010] In an optional implementation, adjusting the timer based on the timing requirements of each ITR in the interrupt vector includes: determining a total delay of the interrupt vector based on the timing requirements of each ITR in the interrupt vector; and setting a timer value of the timer according to the total delay.

[0011] In this embodiment, the timing requirements of each ITR in the interrupt vector are obtained to determine the total delay of the interrupt vector, and then the timer value of the timer is set. The timer value of the timer can be adjusted according to the different timing requirements of the ITR, thereby improving the flexibility of the method and reducing unnecessary hardware resource consumption.

[0012] In an optional implementation, the method further includes: when the interrupt vector fails to be enabled, stopping interrupt reporting.

[0013] In this implementation, when the interrupt vector fails to be enabled, interrupt reporting is stopped, thereby avoiding interrupt conflicts and reducing power consumption.

[0014] In an optional embodiment, the method also includes: updating the timing requirements of the target interrupt event, and determining whether the second ITR meets the updated timing requirements, wherein the second ITR is the ITR in the interrupt vector associated with the target interrupt event; if the second ITR does not meet the updated timing requirements, associating the target interrupt event with a third ITR, wherein the third ITR is the ITR in the interrupt vector that meets the timing requirements of the target interrupt event.

[0015] In this embodiment, when the second ITR cannot meet the timing requirement of the updated target interrupt event, the target interrupt event is associated with the third ITR. The timing upper limit of the target interrupt event can be adjusted without modifying the ITR bit width, thereby improving the flexibility and practicality of the method.

[0016] In an optional embodiment, the method sends an interrupt vector to the host to trigger the interrupt vector and further includes: obtaining the logical value of the interrupt source recording logic unit register, and determining whether the logical value matches the ITR corresponding to the interrupt event, wherein the logical value represents the ITR bound to the interrupt event; if the match is successful, sending the interrupt vector to the host to trigger the interrupt vector.

[0017] In this embodiment, the interrupt source records the logic value of the logic unit register, determines whether the logic value matches the ITR associated with the interrupt event, and triggers the interrupt vector when the match is successful, which can improve the accuracy of interrupt processing and thus improve the stability of the method.

[0018] In an optional implementation, the method further includes: when the logical value fails to match the ITR corresponding to the interrupt event, the interrupt vector stops triggering.

[0019] In this implementation, when the logical value fails to match the ITR corresponding to the interrupt event, the interrupt vector is stopped from being triggered, so that the system can avoid processing unnecessary interrupt events.

[0020] In a second aspect, the present invention provides a streamlined interrupt control device, which includes: a judgment module, used to judge whether an interrupt vector is enabled, wherein the interrupt vector includes several ITRs; an adjustment module, used to obtain the priority of the interrupt event when the interrupt vector is successfully enabled, and determine the timing requirement of the first ITR based on the priority, wherein the first ITR is the ITR associated with the interrupt event, and the timing requirement is used to adjust the bit width of the first ITR; a timer adjustment module, used to adjust the timer based on the timing requirements of each ITR in the interrupt vector; an interrupt trigger module, used to send the interrupt vector to the host after the timer ends to trigger the interrupt vector.

[0021] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the simplified interrupt control method of the above-mentioned first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0022] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the simplified interrupt control method of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1is a flow chart of a simplified interrupt control method according to an embodiment of the present invention;

[0025] Figure 2 is a flow chart of another simplified interrupt control method according to an embodiment of the present invention;

[0026] Figure 3 is a schematic diagram of the bit width of an interrupt vector according to an embodiment of the present invention;

[0027] Figure 4 is a flow chart of another simplified interrupt control method according to an embodiment of the present invention;

[0028] Figure 5 is a flow chart of another simplified interrupt control method according to an embodiment of the present invention;

[0029] Figure 6 is a structural block diagram of an interruption device according to an embodiment of the present invention;

[0030] Figure 7 is a structural block diagram of another simplified interrupt control device according to an embodiment of the present invention;

[0031] Figure 8 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0033] As network traffic increases, high-speed network cards have a greater demand for interrupt vectors. Frequent interrupts will reduce the system performance of computer equipment. In order to reduce CPU utilization and CPU latency, an interrupt regulation mechanism is usually used to limit the interrupt rate.

[0034] When the interrupt enable of the interrupt vector is turned on, if there is an interrupt event associated with the ITR and the timing of the ITR expires, the interrupt vector logic unit of the interrupt device will send the interrupt vector to ensure that the interrupt event converges within the setting time of the ITR, and after the ITR expires, the interrupt event will be reported uniformly, thereby reducing the frequency of interrupt reporting and reducing the impact of interrupts on the system performance of computer equipment.

[0035] In the related art, the demand for the number of interrupt vectors of a high-speed network card is met by increasing the number of ITRs with the same timing upper limit shared by the interrupt vectors, which can ensure that the interrupt frequency of the system will not increase. However, this will increase the demand for hardware resources of the interrupt vectors.

[0036] Therefore, an embodiment of the present invention provides a simplified interrupt control method that can reduce the demand of interrupt vectors for hardware resources. According to the timing requirements of the interrupt event, the bit width of the ITR associated with the interrupt event is adjusted, thereby reducing the total bit width of the interrupt vector to reduce the demand of the interrupt vector for hardware resources.

[0037] According to an embodiment of the present invention, a simplified interrupt control method embodiment is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0038] In this embodiment, a simplified interrupt control method is provided. Figure 1 is a flow chart of a simplified interrupt control method according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0039] Step S101, determining whether an interrupt vector is enabled, wherein the interrupt vector includes a number of ITRs.

[0040] By judging whether the interrupt vector is enabled, unnecessary interrupt vectors can be avoided, reducing unnecessary system overhead. In a more complex system, by judging the enable status of the interrupt vector, the priority of several interrupt vectors can be determined to ensure the execution of key tasks.

[0041] The system can obtain whether the interrupt vector is enabled successfully by reading the data of the interrupt enable register. If the interrupt is enabled successfully, the interrupt vector has the ability to report the interrupt. If the interrupt fails to be enabled, the interrupt vector cannot report the interrupt.

[0042] The same interrupt vector includes several ITRs, among which the priorities of the ITRs can be divided. In an actual application, the priorities of the ITRs in the same interrupt vector are different.

[0043] Step S102, when the interrupt vector is enabled successfully, obtain the priority of the interrupt event, and determine the timing requirement of the first ITR based on the priority, wherein the first ITR is the ITR associated with the interrupt event, and the timing requirement is used to adjust the bit width of the first ITR.

[0044] The priority of the interrupt event is first obtained, and the priority of the first ITR is determined according to the priority of the interrupt event. The higher the priority of the interrupt event, the faster the timing corresponding to the interrupt event needs to expire, so the timing requirement of the ITR associated with the interrupt event is less.

[0045] Among them, the priority of the interruption event can be set by the staff according to different businesses.

[0046] The smaller the timing requirement of the interrupt event, the smaller the bit width requirement of the ITR associated with the interrupt event. The bit width of the ITR can be adjusted by configuring the interrupt controller or the hardware module related to the ITR. This reduces the demand for hardware resources for the interrupt. According to the bit width requirements of each ITR in the interrupt vector, the total bit width of the interrupt vector can be determined. The total bit width of the interrupt vector is the product of the bit widths of each ITR.

[0047] In the same interrupt vector, the priority of ITR is different, and the timing upper limit of ITR can be different. The higher the priority of ITR, the smaller the corresponding ITR timing upper limit requirement, and the smaller the corresponding bit width can be. Interrupt events of different priorities can select the ITR in the interrupt vector for binding according to their own priorities and timing requirements.

[0048] In an actual application, each interrupt event in the interrupt vector can be classified into levels according to timing requirements, and the interrupt event and the corresponding ITR can be bound according to the classified levels.

[0049] In an actual application, an interrupt vector includes several ITRs, each of which has a different priority, a different timing upper limit, and a corresponding different bit width. Interrupt events in the interrupt vector are bound to ITRs of different priorities according to their own priorities.

[0050] After adjusting the bit width of the ITR, you can test the system interrupt response time, interrupt frequency, etc. through simulation tasks to ensure that the system's interrupt processing performance meets expectations.

[0051] Step S103: adjusting the timer based on the timing requirements of each ITR in the interrupt vector.

[0052] Obtain the system's functional requirements for the timer's timing accuracy, timing range, etc., and determine the time granularity of the timer based on the functional requirements. Based on the timing requirements of each ITR in the interrupt vector.

[0053] The timer value of the timer can be determined based on the time granularity of the timer and the total bit width of the interrupt vector. In a practical application, the timer value of the timer is the product of the time granularity of the timer and the total delay of the interrupt vector. When the timing range of the timer is large, the timing delay corresponding to the interrupt vector can be directly accumulated on the current timer value. When the timing range of the timer is small, the timer can be reset first and then the corresponding timer value can be set when setting the timer.

[0054] Step S104, after the timer ends, sending an interrupt vector to the host to trigger the interrupt vector.

[0055] After the timer ends, an interrupt vector is sent to the host to trigger the interrupt vector. When the interrupt vector is triggered, the timer value can be reset to trigger subsequent interrupt vectors. The timer value can be directly cleared to prevent the next timer value from exceeding the maximum range of the timer.

[0056] The simplified interrupt control method provided in this embodiment determines whether the interrupt vector is enabled, and if it is enabled successfully, determines the timing requirement of the corresponding ITR according to the priority of the interrupt event, wherein the timing requirement is used to adjust the bit width of the ITR associated with the interrupt event; determines the value of the timer according to the timing requirement of each ITR in the interrupt vector, so as to trigger the interrupt vector after the timer ends. The bit width of the ITR associated with the interrupt event can be adjusted according to different interrupt events to reduce the demand for hardware resources and improve the response speed and processing efficiency of the system to interrupts.

[0057] In this embodiment, a simplified interrupt control method is provided. Figure 2 is a flow chart of a simplified interrupt control method according to an embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0058] Step S201, determining whether an interrupt vector is enabled, wherein the interrupt vector includes a number of ITRs.

[0059] For details, please see Figure 1 Step S101 of the illustrated embodiment will not be described in detail here.

[0060] Step S202, when the interrupt vector is enabled successfully, obtain the priority of the interrupt event, and determine the timing requirement of the first ITR based on the priority, wherein the first ITR is the ITR associated with the interrupt event, and the timing requirement is used to adjust the bit width of the first ITR.

[0061] Specifically, the above step S202 includes:

[0062] Step S2021, obtaining the priority of the interrupt event.

[0063] Among them, the priority of the interrupt event can be obtained by reading the relevant configuration register.

[0064] Step S2022: Determine the timing requirement of the first ITR based on the priority, wherein the first ITR is the ITR associated with the interrupt event.

[0065] The timing requirement of the interrupt event is determined by obtaining the priority of the interrupt event. The higher the priority of the interrupt event, the smaller the timing requirement.

[0066] Step S2023, sorting the timing requirements of each interrupt event, and adjusting the bit width of the ITR associated with each interrupt event in sequence according to the sorting result.

[0067] The smaller the timing requirement of an interrupt event, the smaller the bit width requirement of the ITR associated with the interrupt event. By sorting the timing requirements of the interrupt events and adjusting the bit width of the ITR associated with each interrupt event in sequence according to the sorting results, the bit width resources can be used reasonably and unnecessary bit width waste can be reduced.

[0068] In an application, the interrupt vector contains n ITRs. The timing requirements of the interrupt events are sorted from small to large, and the bit width of the ITR associated with the interrupt event is adjusted according to the sorting result. The adjusted bit width is as follows: Figure 3 As shown, itr0 represents the first ITR in the interrupt vector, ma represents the adjusted bit width of itr0; itr1 represents the second ITR in the interrupt vector, mb represents the adjusted bit width of itr1; itr2 represents the third ITR in the interrupt vector, mc represents the adjusted bit width of itr2; itr3 represents the fourth ITR in the interrupt vector, md represents the adjusted bit width of itr3; itr4 represents the fifth ITR in the interrupt vector, me represents the adjusted bit width of itr4; itr n-1 represents the nth ITR in the interrupt vector, m represents the adjusted bit width of itr n-1; where e <d<c<b<a≤m。

[0069] Step S203: adjusting the timer based on the timing requirements of each ITR in the interrupt vector.

[0070] For details, please see Figure 1 Step S103 of the illustrated embodiment will not be described in detail here.

[0071] In some optional implementations, the above step S203 includes:

[0072] Step S2031, determining the total delay of the interrupt vector based on the timing requirements of each ITR in the interrupt vector.

[0073] Among them, the total delay of the interrupt vector can be the sum of the timing requirements of each ITR in the interrupt vector. The timing upper limit of the ITR can be determined according to the timing requirements of each ITR in the interrupt vector, and the timing upper limits of all ITRs in the interrupt vector are added to obtain the total delay of the interrupt vector.

[0074] Step S2032: Set the timer value of the timer according to the total delay.

[0075] When the system performs different tasks, the requirements for timers are different. The time granularity of the timer can be determined according to the actual situation.

[0076] After obtaining the time granularity of the timer and the total delay of the interrupt vector, the delay of an interrupt trigger can be determined. In a practical application, the delay of an interrupt trigger is the product of the time granularity of the timer and the total delay. The timer value can be set to the sum of the current value of the timer and the delay of an interrupt trigger. The timer value can also be cleared to zero and set to the delay of an interrupt trigger.

[0077] By obtaining the timing requirements of each ITR in the interrupt vector to determine the total delay of the interrupt vector, and then setting the timer value of the timer, the timer value of the timer can be adjusted according to the different timing requirements of the ITR, thereby improving the flexibility of the method and reducing unnecessary hardware resource consumption.

[0078] Step S204, after the timer ends, sending an interrupt vector to the host to trigger the interrupt vector.

[0079] For details, please see Figure 1 Step S104 of the illustrated embodiment will not be described in detail here.

[0080] The simplified interrupt control method provided in this embodiment can optimize the allocation of hardware resources and improve the flexibility of the method by sorting the timing requirements of interrupt events and adjusting the bit width of the corresponding ITR according to the sorting result.

[0081] In this embodiment, a simplified interrupt control method is provided. Figure 4 is a flow chart of a simplified interrupt control method according to an embodiment of the present invention. Figure 4 As shown, the process includes the following steps:

[0082] Step S301, determining whether an interrupt vector is enabled, wherein the interrupt vector includes a number of ITRs.

[0083] For details, please see Figure 1Step S101 of the illustrated embodiment will not be described in detail here.

[0084] Step S302, when the interrupt vector is enabled successfully, obtain the priority of the interrupt event, and determine the timing requirement of the first ITR based on the priority, wherein the first ITR is the ITR associated with the interrupt event, and the timing requirement is used to adjust the bit width of the first ITR.

[0085] For details, please see Figure 1 Step S102 of the illustrated embodiment will not be described in detail here.

[0086] In some optional implementations, step S302 further includes:

[0087] Step a1, updating the timing requirement of the target interrupt event, and determining whether the second ITR meets the updated timing requirement, wherein the second ITR is the ITR in the interrupt vector associated with the target interrupt event.

[0088] When the system is processing tasks, the priority of the interrupt event may change. When the priority of the interrupt event changes, the timing requirements of the target interrupt event will also change.

[0089] When the priority of the target interrupt event is reduced, the timing requirement of the target interrupt event will increase. If the bit width of the second ITR cannot meet the timing requirement of the target interrupt event, the target interrupt event may be lost, affecting system performance. Therefore, it is necessary to determine whether the ITR associated with the target interrupt event meets the timing requirement of the target interrupt event.

[0090] After the priority of the target interrupt event is reduced, the timing requirement of the target interrupt event is increased. If the second ITR can meet the updated timing requirement, it means that the target interrupt event can continue to be associated with the second ITR.

[0091] Step a2: when the second ITR does not meet the updated timing requirement, the target interrupt event is associated with a third ITR, wherein the third ITR is an ITR in the interrupt vector that meets the timing requirement of the target interrupt event.

[0092] If the second ITR does not meet the updated timing requirement, it is determined whether there is a third ITR in the interrupt vector that can meet the updated timing requirement of the target interrupt event. If there is, the target interrupt event is associated with the third ITR to process the target interrupt event.

[0093] When the second ITR cannot meet the timing requirement of the updated target interrupt event, the target interrupt event is associated with the third ITR. The timing upper limit of the target interrupt event can be adjusted without modifying the ITR bit width, thereby improving the flexibility and practicality of the method.

[0094] Step S303: adjusting the timer based on the timing requirements of each ITR in the interrupt vector.

[0095] For details, please see Figure 1 Step S103 of the illustrated embodiment will not be described in detail here.

[0096] Step S304, after the timer ends, obtain the logic value of the interrupt source recording logic unit register, and determine whether the logic value matches the ITR corresponding to the interrupt event, wherein the logic value represents the ITR bound to the interrupt event.

[0097] The logic value of the interrupt source recording logic unit register represents the ITR bound to the interrupt event. The bit width of the interrupt source recording logic unit register can be set according to the number of ITRs included in the interrupt vector.

[0098] In an actual application, the interrupt vector includes 5 ITRs, namely ITR0, ITR1, ITR2, ITR3, and ITR4; the bit width of the interrupt source record logic unit register is also 5, and each bit in the interrupt source record logic unit register represents the corresponding ITR. When the ITR corresponding to the interrupt event is ITR1, the logic value of the interrupt source record logic unit register should be 5'b00010. If the logic value of the interrupt source record logic unit register is not 5'b00010, it is considered a match failure.

[0099] Step S305: if the match is successful, an interrupt vector is sent to the host to trigger the interrupt vector.

[0100] If the match is successful, it means that the interrupt condition is met, and the interrupt vector can be sent to the host to trigger the interrupt vector. After the interrupt vector is triggered, the timer value needs to be reset to facilitate the subsequent interrupt vector triggering.

[0101] In some optional implementations, step S305 further includes:

[0102] Step S306: When the logic value fails to match the ITR corresponding to the interrupt event, the interrupt vector stops triggering.

[0103] After the logical value fails to match the ITR corresponding to the interrupt event, it is necessary to stop the interrupt signal from being sent to prevent the system from performing erroneous interrupt processing and increasing unnecessary system overhead.

[0104] After the match fails, the match failure can be recorded and stored in the system log or other memory area for subsequent fault analysis. The recorded content includes the type of interrupt event, the ITR corresponding to the interrupt event, and the logic value.

[0105] When the logical value fails to match the ITR corresponding to the interrupt event, the interrupt vector is stopped from being triggered, which can prevent the system from processing unnecessary interrupt events.

[0106] The simplified interrupt control method provided in this embodiment records the logical value of the logic unit register through the interrupt source, determines whether the logical value matches the ITR associated with the interrupt event, and triggers the interrupt vector when the match is successful, which can improve the accuracy of interrupt processing and thus improve the stability of the method.

[0107] In this embodiment, a simplified interrupt control method is provided. Figure 5 is a flow chart of a simplified interrupt control method according to an embodiment of the present invention. Figure 5 As shown, the process includes the following steps:

[0108] Step S401, determining whether an interrupt vector is enabled, wherein the interrupt vector includes a number of ITRs.

[0109] For details, please see Figure 1 Step S101 of the illustrated embodiment will not be described in detail here.

[0110] Step S402: when the interrupt vector enabling fails, stop interrupt reporting.

[0111] In the case of interrupt vector enable failure, interrupt reporting is stopped to avoid unnecessary system overhead. After obtaining the result of interrupt vector enable failure, the system interrupt configuration, driver, etc. can be checked to confirm whether a fault occurs.

[0112] The simplified interrupt control method provided in this embodiment stops interrupt reporting when the interrupt vector enabling fails, thereby avoiding interrupt conflicts and reducing power consumption.

[0113] In this embodiment, an interruption device is provided, such as Figure 6 As shown, the interrupt device includes an interrupt vector register 501, an itr interval (interrupt throttling interval) register 502, a mapping register 503, an itr timing logic unit 504, an interrupt source recording logic unit 505 and an interrupt vector logic unit 506.

[0114] Among them, the interrupt vector logic unit 501 is a register of the interrupt vector, and the interrupt vector can be enabled by software configuration. Only after the interrupt vector is successfully enabled can the interrupt be reported. The itr interval register 502 records the bit width of each ITR in the interrupt vector. By reading the itr interval register 502 by software, the total bit width of the ITR of the interrupt vector can be obtained to facilitate setting the timer value of the timer. In an actual application, the value of the timer is set to the sum of the current value of the timer and the timing delay of the ITR in the interrupt vector.

[0115] The itr timing logic unit 504 is connected to the itr interval register 502 and is used to determine whether the timer corresponding to the ITR has expired. When the timer expires, it indicates that the corresponding interrupt vector can be triggered.

[0116] The mapping register 503 is used to receive an interrupt event and set an ITR associated with the interrupt event. According to the timing requirement of the interrupt event, the interrupt event is associated with any ITR in the interrupt vector that meets the timing requirement of the interrupt event. When the priority of the interrupt event changes, if the bit width of the ITR originally associated with the interrupt event cannot meet the timing requirement of the interrupt event, the ITR associated with the interrupt event can be modified through the mapping register 503.

[0117] The interrupt source recording logic unit 505 is used to determine whether the interrupt event and the ITR associated with the interrupt event are correctly associated. If the ITR associated with the interrupt event is the same as the ITR recorded in the interrupt source recording logic unit, it means that the interrupt event is correctly associated with the ITR. If they are not the same, it means that the interrupt event is incorrectly associated with the ITR.

[0118] The interrupt vector logic unit 506 is used to determine whether to trigger an interrupt vector. When the interrupt of the interrupt vector register is successfully enabled, the timer corresponding to the interrupt vector expires, and the interrupt event is correctly associated with the ITR in the interrupt vector, the interrupt vector logic unit 506 sends the interrupt vector to the host and sends an instruction to the itr interval register 502 to set the timer corresponding to the interrupt vector to re-time.

[0119] The interrupt device can process several interrupt vectors. The ITRs in each interrupt vector are timed in parallel, so the interrupt vectors can be sent in parallel, which can improve the efficiency of interrupt reporting.

[0120] In this embodiment, a simplified interrupt control device is also provided, which is used to implement the above embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0121] This embodiment provides a simplified interrupt control device, such as Figure 7 As shown, including:

[0122] A judging module 601 is used to judge whether an interrupt vector is enabled, wherein the interrupt vector includes a number of ITRs;

[0123] An adjustment module 602 is used to obtain the priority of the interrupt event when the interrupt vector is successfully enabled, and determine the timing requirement of the first ITR based on the priority, wherein the first ITR is the ITR associated with the interrupt event, and the timing requirement is used to adjust the bit width of the first ITR;

[0124] A timer adjustment module 603, used to adjust the timer based on the timing requirements of each ITR in the interrupt vector;

[0125] The interrupt triggering module 604 is used to send an interrupt vector to the host after the timer ends, so as to trigger the interrupt vector.

[0126] In some optional implementations, the adjustment module 602 includes:

[0127] The bit width adjustment unit is used to sort the timing requirements of each interrupt event, and adjust the bit width of the ITR associated with each interrupt event in sequence according to the sorting result.

[0128] In some optional implementations, the timer adjustment module 603 includes:

[0129] The delay determination unit is used to determine the total delay of the interrupt vector based on the timing requirements of each ITR in the interrupt vector.

[0130] The timer value setting unit is used to set the timer value of the timer according to the total delay.

[0131] In some optional implementations, the simplified interrupt control device further includes:

[0132] The stop reporting module is used to stop interrupt reporting when the interrupt vector enabling fails.

[0133] In some optional implementations, the simplified interrupt control device further includes:

[0134] An update module is used to update the ITR associated with the target interrupt event.

[0135] The update modules include:

[0136] a timing requirement determination unit, configured to update the timing requirement of the target interrupt event and determine whether the second ITR meets the updated timing requirement, wherein the second ITR is the ITR associated with the target interrupt event in the interrupt vector;

[0137] The association adjustment unit is used to associate the target interrupt event with a third ITR when the second ITR does not meet the updated timing requirement, wherein the third ITR is an ITR in the interrupt vector that meets the timing requirement of the target interrupt event.

[0138] In some optional implementations, the simplified interrupt control device further includes:

[0139] The matching detection module is used to obtain the logic value of the interrupt source recording logic unit register and determine whether the logic value matches the ITR corresponding to the interrupt event, wherein the logic value represents the ITR bound to the interrupt event.

[0140] If the match is successful, the interrupt vector is sent to the host to trigger the interrupt vector.

[0141] In some optional implementations, when the logic value fails to match the ITR corresponding to the interrupt event, the interrupt vector stops triggering.

[0142] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0143] The simplified interrupt control device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0144] The embodiment of the present invention also provides a computer device having the above Figure 7 The simplified interrupt control device shown.

[0145] See also Figure 8 , Figure 8 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 8As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 8 A processor 10 is taken as an example.

[0146] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0147] The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0148] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0149] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0150] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 8 The example of connecting through bus is taken in the following.

[0151] The input device 30 can receive input digital or character information, and generate key signal input related to the user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator bar, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0152] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0153] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0154] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A simplified interrupt control method, characterized in that: The method comprises: Determine whether an interrupt vector is enabled, wherein the interrupt vector includes a plurality of ITRs; When the interrupt vector is successfully enabled, obtaining a priority of the interrupt event, and determining a timing requirement of a first ITR based on the priority, wherein the first ITR is an ITR associated with the interrupt event, and the timing requirement is used to adjust a bit width of the first ITR; adjusting a timer based on a timing requirement of each ITR in the interrupt vector; After the timer ends, the interrupt vector is sent to the host to trigger the interrupt vector.

2. The method according to claim 1, characterized in that The adjusting the bit width of the first ITR comprises: The timing requirements of each interrupt event are sorted, and according to the sorting result, the bit width of the ITR associated with each interrupt event is adjusted in sequence.

3. The method according to claim 1, characterized in that The adjusting the timer based on the timing requirements of each ITR in the interrupt vector includes: Determining a total delay of the interrupt vector based on the timing requirements of each ITR in the interrupt vector; A timer value of the timer is set according to the total delay.

4. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: When the interrupt vector fails to be enabled, interrupt reporting is stopped.

5. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: Updating the timing requirement of the target interrupt event, and determining whether the second ITR meets the updated timing requirement, wherein the second ITR is the ITR in the interrupt vector associated with the target interrupt event; In the case where the second ITR does not meet the updated timing requirement, the target interrupt event is associated with a third ITR, wherein the third ITR is an ITR in the interrupt vector that meets the timing requirement of the target interrupt event.

6. The method according to any one of claims 1 to 3, characterized in that: The method further includes, before sending the interrupt vector to the host to trigger the interrupt vector: Obtaining a logic value of an interrupt source recording logic unit register, and determining whether the logic value matches an ITR corresponding to the interrupt event, wherein the logic value represents the ITR bound to the interrupt event; If the match is successful, the interrupt vector is sent to the host to trigger the interrupt vector.

7. The method according to claim 6, characterized in that The method further comprises: In the case where the logic value fails to match the ITR corresponding to the interrupt event, the interrupt vector stops triggering.

8. A simplified interrupt control device, characterized in that: The device comprises: A judging module, used for judging whether an interrupt vector is enabled, wherein the interrupt vector includes a plurality of ITRs; an adjustment module, configured to obtain a priority of an interrupt event when the interrupt vector is successfully enabled, and determine a timing requirement of a first ITR based on the priority, wherein the first ITR is an ITR associated with the interrupt event, and the timing requirement is used to adjust a bit width of the first ITR; A timer adjustment module, configured to adjust a timer based on a timing requirement of each ITR in the interrupt vector; The interrupt triggering module is used to send the interrupt vector to the host after the timer ends, so as to trigger the interrupt vector.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes a simplified interrupt control method according to any one of claims 1 to 7 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute a simplified interrupt control method according to any one of claims 1 to 7.

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