System and method for designing integrated circuit, and computer readable medium

Abstract

A computer-readable medium including computer-executable instructions for performing a method is provided. The method comprises: generating a schematic diagram of an integrated circuit comprising a plurality of components, each component being associated with a format indicating a matching group representing a respective circuit function; combining a first device array layout corresponding to a first subset of components sharing the first conforming group and a second device array layout corresponding to a second subset of components sharing the second matching group to form a third device array layout, responsive to detecting that the first device array layout and the second device array layout share the same cell type; forming a first layer surrounding the third device array layout; inserting a dummy pattern around the first layer; and further inserting a guard ring surrounding the dummy pattern.

Description

Technical Field

[0001] The present invention relates to a system, method and computer readable medium for designing an integrated circuit. Background Art

[0002] The semiconductor industry has experienced continued rapid growth due to the increasing integration of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.) In large part, the increase in integration density comes from the continuous reduction in minimum feature size, allowing more components to be integrated into a given area. Summary of the invention

[0003] Embodiments of the present invention provide a method for designing an integrated circuit. The method includes generating a schematic diagram of an integrated circuit including a plurality of components, each of the plurality of components being associated with a format indicating a matching group representing a corresponding circuit function. The method includes generating a plurality of first device array layouts of the plurality of components respectively based on the matching groups of the plurality of components. The method includes merging a plurality of first device array layouts to form a second device array layout in response to detecting that a first subset of the first device array layouts share the same first matching group. The method includes generating a first layer surrounding the second device array layout. The method includes merging a plurality of second device array layouts to form a third device array layout in response to detecting that a second subset of the first device array layouts share the same second matching group, the second matching group being different from the first matching group. The method includes generating a second layer surrounding the third device array layout. The method includes merging the second device array layout and the third device array layout to form a fourth device array layout in response to detecting that the second device array layout and the third device array layout share the same cell type. The method includes forming a third layer surrounding the fourth device array layout. The method includes inserting a dummy pattern around the third layer.

[0004] An embodiment of the present invention provides a system for designing an integrated circuit. The system includes at least one processor and at least one memory, the memory including computer program code for one or more programs. At least one memory and computer program code are configured to use at least one processor to enable the system to: generate a schematic diagram of an integrated circuit including multiple components, each of the multiple components is associated with a format, and the format indicates a matching group representing a corresponding circuit function; merge a first device array layout and a second device array layout, the first device array layout corresponds to a first subset of multiple components sharing a first matching group, and the second device array layout corresponds to a second subset of multiple components sharing a second matching group, in response to detecting that the first device array layout and the second device array layout share the same cell type, form a third device array layout; form a first layer surrounding the third device array layout; insert a dummy pattern around the first layer; and insert a guard ring around the dummy pattern.

[0005] An embodiment of the present invention provides a computer-readable medium including computer-executable instructions for performing a method for designing an integrated circuit. The method includes: generating a schematic diagram of an integrated circuit including a plurality of components, each of the plurality of components being associated with a format, the format indicating a matching group representing a corresponding circuit function; merging a first device array layout and a second device array layout, the first device array layout corresponding to a first subset of the plurality of components sharing a first matching group, the second device array layout corresponding to a second subset of the plurality of components sharing a second matching group, forming a third device array layout in response to detecting that the first device array layout and the second device array layout share the same cell type; forming a first layer surrounding the third device array layout; inserting a dummy pattern around the first layer; and further inserting a guard ring around the dummy pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A block diagram of an integrated circuit design system is shown in accordance with some embodiments.

[0008] Figure 2 An example flow chart of a method for operating an integrated circuit design system according to some embodiments is shown.

[0009] Figure 3 An example flow chart of a method for adjusting a layout according to some embodiments is shown.

[0010] Figure 4A schematic design of an example integrated circuit is shown in accordance with some embodiments.

[0011] Figure 5 An adjusted layout including example CAD layers surrounding one or more merged device array layouts is shown in accordance with some embodiments.

[0012] Figure 6 An adjusted layout including example CAD layers surrounding one or more merged device array layouts is shown in accordance with some embodiments.

[0013] Figure 7 According to some embodiments, the Figure 6 The adjusted layout of the dummy pattern around the example CAD layer is shown.

[0014] Figure 8 An adjusted layout including dummy patterns around a number of example CAD layers is shown in accordance with some embodiments.

[0015] Fig. 9 An adjusted layout including example CAD layers surrounding one or more merged device array layouts is shown in accordance with some embodiments.

[0016] Fig.10 An adjusted layout including an example CAD layer surrounding a plurality of staggered device array layouts is shown in accordance with some embodiments.

[0017] Fig.11 An adjusted layout including an example CAD layer surrounding a plurality of staggered device array layouts is shown in accordance with some embodiments.

[0018] Fig.12 An adjusted layout including an example CAD layer surrounding a plurality of device array layouts is shown in accordance with some embodiments.

[0019] Fig.13 A schematic design of an example integrated circuit is shown in accordance with some embodiments.

[0020] Fig.14 An adjusted layout including an example CAD layer surrounding a plurality of device array layouts is shown in accordance with some embodiments.

[0021] Fig.15 An adjusted layout including several example CAD layers each enclosing one or more device array layouts is shown in accordance with some embodiments.

[0022] Fig.16 According to some embodiments, a method for implementing Figure 1 A block diagram of a computing device of an integrated circuit design system is shown. DETAILED DESCRIPTION

[0023] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, a first feature is formed on or on a second feature, which may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments or configurations discussed.

[0024] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0025] While the functionality of integrated circuits continues to shrink, it has become common to model the impact of physical / layout effects in advance in integrated circuit design. For integrated circuit design, process design kits (PDKs) or process access kits (PAKs) have been commercially used to build integrated circuits. Generally, PDKs include geometric descriptions and device models of devices, such as transistors, diodes, resistors, capacitors, etc. Circuit design engineers convert PDKs into transistor netlists and / or gate-level netlists for circuit simulation, such as Simulation Program with Integrated Circuit Emphasis (SPICE) simulation. Based on the simulation results, circuit design engineers predict and / or modify the design of the integrated circuit.

[0026] However, existing SPICE methods cannot accurately predict the impact of certain component variations or integrated circuit performance mismatches. As semiconductor feature sizes decrease, statistical variations in circuit characteristics caused by statistical variations in semiconductor processes may become increasingly severe. Some causes of this mismatch are edge effects, injected and surface state charges, oxide effects, mobility effects, polycrystalline density gradient effects, etc. Among these causes, the polycrystalline density gradient effect (sometimes referred to as the "DGE" effect) is sometimes one of the most critical. For example, a polysilicon density gradient in adjacent areas (e.g., cells) of an array may result in unequal chemical mechanical planarization (CMP) or polishing rates on corresponding metal gates in the array, or have non-uniform rapid thermal annealing (RTA). This in turn affects device characteristics, such as but not limited to device mobility and threshold voltage. Therefore, existing integrated circuit design systems or methods are not completely satisfactory in some aspects.

[0027] The present disclosure provides various embodiments of systems and methods for designing integrated circuits that take into account the DGE effect. The disclosed system can be part of a process design kit (PDK) implemented by an electronic design automation (EDA) tool. For example, a system as disclosed herein can identify multiple subsets of circuit components of an integrated circuit, wherein each subset shares the same matching group based on a schematic design of the integrated circuit. The disclosed system can generate a schematic design indicating a matching group of each circuit component, which can be refined to a unit of a transistor. The matching group can correspond to the circuit function of the corresponding circuit component. After identifying the corresponding matching group of the subset, the system can autonomously generate a first layer of a layout that surrounds each subset. Such a first layer can sometimes be referred to as a first computer-aided design (CAD) layer, which can be a virtual or symbolic layout layer used by an EDA tool. In response to further identifying that two or more adjacent subsets (enclosed by the corresponding first CAD layer) share the same cell type, the system can merge such adjacent subsets and autonomously generate a second layer or second CAD layer that surrounds the merged subset. Based on the size of the second CAD layer, the system can autonomously insert a dummy pattern based on the autonomously generated second CAD layer. For example, the system can add dummy patterns inside and / or outside the second CAD layer. Next, the system can further insert a guard ring around the dummy pattern. By generating such a CAD layer, the system can quickly and accurately identify the boundaries of the active circuit components of the integrated circuit (or its schematic diagram) and surround the boundaries with dummy patterns. In this way, the active circuit components of the integrated circuit can be advantageously protected from the DGE effect. In addition, in the presence of a CAD layer that encloses the active circuit components, the corresponding layout of the schematic design is compatible with various verification steps of the EDA tool, such as Layout Versus Schematic (LVS) check, Layout Parasitic Extraction (LPE) check, Design Rule Check (DRC), etc.

[0028] Figure 1 FIG. 1 is a block diagram of an integrated circuit design system 100 for designing a DGE effect sensing integrated circuit according to various embodiments. The integrated circuit design system 100 may be part of a PDK implemented by an EDA tool. It should be understood that Figure 1 For illustration purposes, Figure 1 To simplify, therefore, the integrated circuit design system 100 may include any of a variety of other components / blocks while still within the scope of the present disclosure.

[0029] The integrated circuit design system 100 enables a reduction in the number of iterations performed during the layout design process by providing a unique and complete design flow that autonomously merges multiple device array layouts and generates CAD layers to surround the merged device arrays. The integrated circuit design system 100 also enables the insertion of dummy patterns around the CAD layers to verify the accuracy of the performance of the electrical design or layout compared to the design specifications.

[0030] As shown, the integrated circuit design system 100 includes a schematic editor 102, a layout editor 104, a user interface 106, a device array editor 108, and a design rule constraint database 110 that are communicatively coupled to each other. In various embodiments of the present disclosure, the schematic editor 102, the layout editor 104, and the device array editor 108 may each include one or more sets of executable instructions executed by at least one processor or similar device.

[0031] The schematic editor 102 can generate and edit a schematic design (e.g., a circuit) of an integrated circuit being designed. The schematic editor 102 can perform a pre-layout simulation (e.g., a simulation with a general purpose simulation program for integrated circuits (SPICE)) on the schematic design. According to various embodiments, the schematic editor 102 includes a set of executable instructions for generating or causing a pre-layout simulation of the schematic design. In other embodiments, a separate device (e.g., a simulator) that communicates with the schematic editor 102 can generate a pre-layout simulation of the schematic design. The layout editor 104 can generate and edit the layout of the integrated circuit (e.g., a device array layout) based on the schematic design generated by the schematic editor 102. The device array editor 108 can communicate with the layout editor 104 to autonomously merge the layouts of one or more integrated circuits. More subsets of the device array layout and generate a CAD layer to surround the merged device array layout. When generating the CAD layer, the device array editor 108 can communicate with the schematic editor 102 to include it in the circuit schematic of the integrated circuit for post-layout simulation. The following will refer to Figure 2 The components of the integrated circuit design system 100 are discussed in more detail in detail.

[0032] The user interface 106 may receive and display the circuit schematic from the schematic editor 102, the layout from the layout editor 104, the device array layout from the device array editor 108, and any calculated circuit performance parameters. The user interface 106 may receive user input to adjust the circuit schematic, device array layout, and layout of the integrated circuit, and select a particular device to display the circuit performance parameters of the particular device selected by the user.

[0033] Figure 2 2 shows a flow chart of an example method 200 for designing an integrated circuit according to various embodiments. The method 200 may be performed by Figure 1 Therefore, the following discussion of method 200 will sometimes refer to Figure 1 For example, schematic editor 102, layout editor 104, device array editor 108. It should be noted that method 200 is only an example and is not intended to limit the present invention. Therefore, it should be understood that in Figure 2 Additional operations are provided before, during, and after method 200, some of which are only briefly described herein.

[0034] The method 200 may begin with an operation 210 of generating a schematic design of an integrated circuit. In various embodiments, the schematic editor 102 may generate a schematic design based on a set of design rule constraints. The schematic editor 102 may query the applicable design rule set in the design rule constraint database 110 and generate a schematic design of the integrated circuit. The schematic of the integrated circuit may include a plurality of circuit components. Each circuit component may be represented as a transistor, which may be implemented as a parametrized cell (PCell) by the integrated circuit design system 100, for example. In some other embodiments, the circuit component may be implemented as any of a variety of other simulation units while still within the scope of the present disclosure. The schematic of the integrated circuit may also include layout-dependent effect (LDE) related information of each circuit component in a component description format (CDF). LDE related information may include the size of each feature of the circuit component (e.g., the number of active regions, channel width, channel length, number of gate structures, gate oxide thickness, etc., which may be implemented as a fin structure).

[0035] In various embodiments, the LDE-related information may include a matching group (MG) of one or more circuit components, which may be defined through the schematic editor 102 or otherwise received by the schematic editor 102 (e.g., operation 215). Specifically, the matching group may be associated with a corresponding circuit function. Such a matching group may be defined by a user of the integrated circuit design system 100. For example, the matching group may include one of the following: a current mirror, a differential pair, a bias circuit, a distributed bias circuit, or a clock sensitive circuit. In some embodiments, the LDE-related information may optionally include a size of a device array layout corresponding to the corresponding circuit component.

[0036] Next, method 200 may proceed to operation 220 of performing a pre-layout simulation on the schematic design of the integrated circuit. In various embodiments, schematic editor 102 may simulate the schematic design of the integrated circuit. The pre-layout simulation may be performed on a simulator, such as the SYNOPSYS simulator commercially available from Synopsys, Inc. (San Jose, CA). Commercially available from Cadence Design Systems, Inc. (San Jose, CA)

[0037] Or any commercially available pre-layout simulator. After completing the pre-layout simulation, the layout of the integrated circuit can be generated by the layout editor 104 and the device array editor 108 together, including one or more CAD layers, each CAD layer defining the boundaries of certain active circuit components. This will be discussed in detail below.

[0038] Furthermore, in various embodiments, the schematic editor 102 may simulate the schematic design with a corresponding scaling factor based on the matching group of the schematic design (e.g., operation 225). For example, the schematic editor 102 may identify whether each circuit component is associated with a corresponding matching group. If so (i.e., associated with an assigned matching factor), the schematic editor 102 may run a pre-layout simulation (including a Monte Carlo simulation) with a relatively small factor; if not (i.e., not associated with a matching factor), the schematic editor 102 may run a pre-layout simulation (including a Monte Carlo simulation) with a relatively large factor.

[0039] Next, method 200 may proceed to operation 230 of generating a layout of the integrated circuit. In various embodiments, layout editor 104 and device array editor 108 may collaborate to generate a layout based on the schematic design (generated at operation 210) and the pre-simulation results (generated at operation 220). For example, layout editor 104 may first generate a layout using a platform such as Cadence Design Systems, Inc. (San Jose, CA). ) generates a layout based on the schematic design and pre-simulation results. Simultaneously or subsequently, the device array editor 108 may update, adjust, or otherwise modify the layout by adding one or more CAD layers (e.g., via operation 235). Such CAD layers may provide symbol boundaries (e.g., identified by one or more CAD layers). The verification tools of the integrated circuit design system 100 are used to package similar circuit components therein, which may advantageously help isolate any possible DGE effects outside of the boundaries.

[0040] For example, in operation 235, the device array editor 108 may detect circuit components that share the same matching group from the schematic design. When such circuit components are detected, the device array editor 108 may communicate with the layout editor 104 and autonomously merge the corresponding first device array layouts of these circuit components. When the first device array layout configuration is merged into a corresponding one of a plurality of second device array layout configurations, the device array editor 108 may autonomously generate a first CAD layer (i.e., a merged first device array layout) surrounding each second device array layout. Next, the device array editor 108 may further detect corresponding circuit components of one or more second device array layouts that share the same cell type from the schematic design. The same cell type may refer to having the same cell identification, the same channel length, the same threshold voltage, or the same active region width. When such a second device array layout is detected, the device array editor 108 may autonomously merge these second device array layouts into a corresponding one of a plurality of third device array layouts. In response, the device array editor 108 may autonomously generate a second CAD layer surrounding each third device array layout (i.e., a merged second device array layout).

[0041] Still referring to operation 235, once the second CAD layer is generated, the device array editor 108 can insert, fill, or otherwise generate a dummy pattern around the second CAD layer. Inserting a dummy pattern is a technique for improving (e.g., thickness) uniformity in an integrated circuit by adding structures or removing existing structures. In general, a dummy pattern can include a plurality of fill patterns / structures that are similar to the active patterns / structures surrounded by the corresponding CAD layer. For example, a dummy pattern can include a plurality of fill structures extending from a corresponding pattern / structure of the active pattern / structure surrounded by the corresponding CAD layer. Therefore, such dummy patterns can sometimes be referred to as identical dummy patterns (e.g., relative to the pattern surrounded by the CAD layer).

[0042] The insertion of dummy patterns may cause unwanted electrical effects. For example, adding dummy features changes the effective pattern density and line spacing. Removing features (oxide fill) changes the effective pattern density and line width. The impact of the fill depends on the designed interconnect structure adjacent to the fill (for metal dummy devices) or the designed interconnect structure itself (for oxide dummy devices). Adding metal fill modifies the coupling capacitance (C) between adjacent interconnects. Adding dummy oxide modifies the coupling capacitance (C) and the interconnect resistance (R). The relative impact depends on the size of the interconnect structure. The degree of change in R and C determines the impact on the circuit. Therefore, by defining a (e.g., a second) CAD layer and adding dummy patterns around the CAD layer, the impact of inserting these dummy patterns can be more accurately evaluated through one or more verification tools (e.g., DRC) of the integrated circuit design system 100.

[0043] In some embodiments, the device array editor 108 may determine the size of the dummy pattern based on at least one of the design rule constraints (e.g., stored in the design rule constraint database 110) or the size of the second CAD layer. For example, the dummy pattern may extend from each edge of the second CAD layer. In this way, the dummy pattern may form a closed loop surrounding the circuit components corresponding to the third device array layout (i.e., the merged second device layout). And the size (e.g., width) of the dummy pattern may be determined by the device array editor 108 based on the extent to which at least the second CAD layer extends in the first lateral direction and / or the second lateral direction, which will be determined in relation to Fig.14 After inserting the dummy pattern around the second CAD layer, the device array editor 108 may further insert a guard ring around the dummy pattern. Thus, multiple device array layouts may share a common guard ring.

[0044] Next, the method 200 may proceed to operation 240 of verifying the layout. In various embodiments, the integrated circuit design system 100 may include a plurality of verification tools to verify or otherwise check the layout. Examples of such checks include design rule checking (DRC), layout vs. schematic (LVS) checking (e.g., layout vs. schematic comparison), layout parasitic extraction (LPE) (e.g., MOS, resistors, capacitors, inductors, and / or other semiconductor devices), resistance and capacitance extraction (RCX) (e.g., interconnect parasitic resistance and capacitance extraction for timing simulation), and other inspection and verification steps.

[0045] After the layout (or the corresponding schematic design) passes the check, the method 200 may proceed to operation 250 of performing a post-layout simulation on the schematic design of the integrated circuit. In various embodiments, the schematic editor 102 may simulate the schematic design of the integrated circuit. The post-layout simulation may be performed on a simulator, such as a commercially available emulator from Synopsys, Inc. (San Jose, CA). Commercially available from Cadence Design Systems, Inc. (San Jose, CA) or any commercially available pre-layout simulator.

[0046] In the post-layout simulation, various layout-related effects are taken into account so that the generated circuit performance parameters more accurately reflect the actual circuit. The circuit performance parameters are then compared with the design specifications associated with the schematic design. If the circuit performance parameters meet the requirements of the design specifications, the schematic design can be approved. Otherwise, the design process returns to the schematic generation and editing steps, which include pre-layout simulation (operation 220), layout creation (operation 230), design verification (operation 240) and post-layout simulation (operation 250) to repeat the operation to modify the schematic design until the circuit performance parameters meet the requirements of the design specifications.

[0047] Figure 3 A flowchart of a method 300 is shown according to various embodiments, which summarizes the steps of designing an integrated circuit by the integrated circuit design system 100 ( Figure 1 ) performs the above operations ( Figure 2 ). In addition, Figures 4 to 8 An example integrated circuit designed by the method 300 is provided, thus combining Figures 4 to 8 The following discussion of method 300 is provided. It should be noted that method 300 is only an example and is not intended to limit the present invention. Therefore, it should be understood that in Figure 3 Additional operations are provided before, during, and after method 300, some of which are only briefly described herein.

[0048] In various embodiments, method 300 may begin at operation 310, where a matching group is defined for each of a plurality of circuit components of an integrated circuit. Figure 4 In the integrated circuit design system 100 ( Figure 1 ) can generate a schematic design 400 that includes a plurality of circuit components, such as transistors or corresponding PCells identified by the integrated circuit design system 100. Specifically, the example schematic design 400 includes circuit components 402, 404, 406, 408, 410, 412, 414, 416, 418, etc.

[0049] When generating schematic design 400, schematic editor 102 may define, receive, or identify matching groups assigned to each of circuit components 402 to 414. According to various embodiments, the matching groups may correspond to the functionality of the respective circuit components. As a non-limiting example, circuit components 402 and 404 may each be associated with a first matching group (e.g., a current mirror); circuit components 406 and 408 may each be associated with a second matching group, such as a differential pair; and circuit components 412 and 414 may each be associated with a third matching group (e.g., a distributed bias circuit). Thus, schematic editor 102 may specify or otherwise indicate matching groups in the corresponding CDF, such as Figure 4 Alternatively or additionally, the schematic editor 102 may indicate other LDE related information in the CDF, such as the number of active areas, channel width, channel length, number of gate structures, gate oxide thickness, etc.

[0050] In addition, schematic editor 102 may indicate the dimensions of the device array layout associated with the corresponding circuit component. Figure 1 In the CDF of Figure 4 As shown, schematic editor 102 may indicate the size of the device array layout of circuit component 406 as one of ANARRAY_S, ANARRAY_M, ANARRAY_H, or ANARRAY_HS; and when no size is indicated or specified (e.g., by a user), schematic editor 102 may assign ANARRAY_S as the size of the device array layout by default. In some embodiments, the size of ANARRAY_S is smaller than the size of ANARRAY_M, the size of ANARRAY_M is smaller than the size of ANARRAY_H, and the size of ANARRAY_H is smaller than the size of ANARRAY_HS.

[0051] Next, the method 300 may proceed to operation 320, where the size of the device array layout of each circuit member is detected, two or more device array layouts are merged, and a CAD layer is generated to surround the merged device array layout. The method 300 may proceed to operation 330 to determine whether there are more device array layouts that need to be merged. If so (for example, one or more device array layouts can be merged), the method 300 may proceed to operation 340 of adding dummy patterns and guard rings; if not (for example, there are no mergeable device array layouts), the method 300 may return to operation 320. In some embodiments, the method 300 may include one or more iterations from operation 320 to 330.

[0052] For example, Figure 5 , the device array editor 108 may communicate with the layout editor 104 to detect device array layouts 502 and 504 corresponding to the circuit components 402 and 404, respectively, of the schematic design 400. Each of the device array layouts 502 and 504 may include a structure for forming at least one active region (e.g., extending in the X direction), one or more gate structures (e.g., extending in the Y direction), one or more first interconnect structures (e.g., extending along the X direction), one or more second interconnect structures (e.g., extending along the Y direction), and one or more via structures, respectively.

[0053] When the layout editor 104 generates the device array layouts 502 and 504, each of the device array layouts 502 and 504 includes one or more CAD layers, such as 512, whose size may be specified in the LDE related information in the CDF or assigned by default. In response to detecting that the device array layouts 502 and 504 share the same matching group (e.g., as specified in the LDE related information in the CDF), the device array editor 108 may update the layout by merging the device array layouts 502 and 504 as a device array layout 506. When merging the device array layouts 502 and 504, the device array editor 108 may further update the layout by replacing the CAD layer 512 with the CAD layer 516 to surround the merged device array layout 506.

[0054] Further Figure 6 As shown, the device array editor 108 can detect another (e.g., merged) device array layout 526 that shares the same cell type as the merged device array layout 506. The cell type can be specified in the LDE related information in the corresponding CDF. In some embodiments, the device array layout 526 can include circuit components 406 and 408 (which are merged and surrounded by a CAD layer 536). Figure 4 ). In addition, the (merged) device array layout 506 and the (merged) device array layout 526 may be arranged adjacent to each other. As such, the device array editor 108 may further update the layout by merging the device array layouts 506 and 526 into the device array layout 546 and replacing the CAD layers 516 and 536 with the CAD layer 556. The CAD layer 556 may surround the two device array layouts 506 and 526.

[0055] As described above, after merging multiple device array layouts that have different matching groups but share the same unit type and then generating a CAD layer to surround them (e.g., creating CAD layer 556), the device array editor 108 can further detect whether there are other device array layouts that need to be merged and then packaged. If so, the device array editor 108 can follow the same Figure 5 and Figure 6 If not, the device array editor 108 can add a dummy pattern around (eg, inside and / or outside) the CAD layer 556 and then generate a guard ring around the CAD layer 556.

[0056] For example, Figure 7, the device array editor 108 may add a dummy pattern 550 around the CAD layer 556. Such a dummy pattern may be "identical" to all the circuit components (e.g., 402, 404, 406, and 408) that are surrounded to account for the DGE effect. In some embodiments, the device array editor 108 may create the dummy pattern 550 by extending the corresponding pattern of the circuit components 402, 404, 406, and / or 408 from or across each edge of the CAD layer 556. The device array editor 108 may extend the dummy pattern 550 by a width (W) in at least one of the X direction or the Y direction. In some embodiments, the device array editor 108 may determine the width W based on the size of the CAD layer 556 or at least one of various other LDE-related information of the enclosed circuit components (or device array layout). For example, such LDE-related information may include the channel length of the circuit components, the first spacing between adjacent active regions of the layout along the X direction, the second spacing between adjacent active regions of the layout along the Y direction, and the like.

[0057] As a non-limiting example, if the CAD layer 556 is approximately the size of ANARRAY_S and the channel length of the closed circuit component has a minimum value achievable for a particular technology node, the device array editor 108 may determine the width W at a first value (e.g., in μm); if the CAD layer 556 is approximately the size of ANARRAY_M, the device array editor 108 may determine the width W at a second value (e.g., in μm); if the CAD layer 556 is approximately the size of ANARRAY_H, the device array editor 108 may determine the width W at a third value (e.g., in μm); and if the CAD layer 556 is approximately the size of ANARRAY_HS and the channel length of the closed circuit component has a maximum value achievable for a particular technology node, the device array editor 108 may determine the width W at a fourth value (e.g., in μm). In some embodiments, the fourth value of the width W may be greater than the third value of the width W, the third value of the width W may be greater than the second value of the width W, and the second value of the width W may be greater than the first value of the width W.

[0058] Figure 8 Another layout is shown, corresponding to Figure 4 A portion of the schematic diagram design 400 is shown in FIG. Figure 4 As shown, it is also updated by the device array editor 108. Figure 8As shown, the layout may include device array layouts 802, 804, 806, and 808 corresponding to circuit components 406 and 408, 410, 416, and 418, respectively, after being updated by the device array editor 108. In addition, the device array editor 108 may generate CAD layers 812, 814, 816, and 810 to surround the device array layouts 802, 804, 806, and 808, respectively.

[0059] In some embodiments, device array editor 108 may also include corresponding device array layouts for one or more other circuit components in each of CAD layers 812, 814, 816, and 810. Such other circuit components may belong to the same layer. Columns of circuit components that were initially surrounded by a corresponding one of CAD layers 812, 814, 816, and 818 (e.g., in schematic design 400). For example, CAD layer 812 may include a second column of device array layouts for circuit components 412-414; CAD layer 814 may include a third column of device array layouts for circuit components 412-414; CAD layer 816 may include a (N-1)th column of device array layouts for circuit components 412-414; and CAD layer 810 may include an Nth column of device array layouts for circuit components 412-414. When generating CAD layers 812 to 818, device array editor 108 may generate dummy pattern 850 to surround each of CAD layers 812 to 818, and generate guard ring 860 to further surround dummy pattern 850. Alternatively or additionally, device array editor 108 may insert dummy patterns into one or more CAD layers, such as 812.

[0060] Reference again Figure 1 , the device array editor 108 can also autonomously detect, identify or otherwise recognize various other information of the schematic design (e.g., schematic information, LDE related information, etc.) to update or adjust the corresponding layout. In some embodiments, these adjustments can be integrated into Figure 3 Method 300 or supplement to Figure 3 Therefore, some of the reference numerals used above (e.g., Figure 1-3 ) can continue to be used in the following discussion of these adjustments. Fig. 9 , 10 , 11, 12, 13, 14 and 15 show examples of such adjustments, which will be discussed in more detail below.

[0061] refer to Fig. 9In communication with the schematic editor 102 and / or the layout editor 104, the device array editor 108 may recognize that some circuit components of the schematic design are configured as stacked gate transistors (e.g., 920), i.e., multiple transistors (e.g., 910) share the same gate terminal, the same drain terminal, and the same source terminal by connecting the gate terminals of the multiple transistors (e.g., 910) together and connecting the drain terminal of one transistor to the source terminal of another adjacent transistor. As such, in some embodiments, the device array editor 108 may autonomously generate a CAD layer 950 of a corresponding device array layout surrounding (e.g., wrapping around) the transistors 910.

[0062] refer to Fig.10 , when communicating with the schematic editor 102 and / or the layout editor 104, the device array editor 108 can identify that some circuit components of the schematic design (e.g., 1000) have respectively different LDE-related information. For example, the circuit components M1 and M2 of the schematic design 1000 can have different numbers of active areas (and thus different drive powers). As such, in some embodiments, the device array editor 108 can update the corresponding layout 1020 by rearranging the corresponding device array layout of transistors M1 and M2, and autonomously generate a CAD layer 1030 around (e.g., surrounding) the layout 1020. In some embodiments, the device array editor 108 can interleave the respective device array layouts of transistors M1 and M2 so that the device array layouts are balanced with each other. For example, Fig.10 As shown, the device array layouts of transistors M1 and M2 may be arranged in a checkerboard manner, ie, the four edges of the device array layout of one of transistors M1 and M2 are adjacent to the device array layout of the other transistor, and its four corners are placed with its own device array layout.

[0063] refer to Fig.11 , when communicating with the schematic editor 102 and / or the layout editor 104, the device array editor 108 can identify that some circuit components of the schematic design (e.g., 1100) have respectively different LDE-related information. For example, the circuit components M1, M2, and M3 of the schematic design 1100 can have different numbers of active areas (and thus different drive powers). As such, in some embodiments, the device array editor 108 can update the corresponding layout 1120 by rearranging the corresponding device array layout of transistors M1, M2, and M3, and autonomously generate a CAD layer 1130 around the layout 1120 (e.g., wrapping). In some embodiments, the device array editor 108 can interleave the respective device array layouts of transistors M1, M2, and M3 so that the device array layouts are balanced with each other. For example, referring to Fig.11, along one of the diagonals of layout 1120 (from upper left to lower right), two device array layouts of transistor M1 may be arranged symmetrically with respect to the center of layout 1120, and dummy patterns may be inserted on both sides, respectively. Along another diagonal of layout 1120 (from lower left to upper right), one device array layout of transistor M2 and one device array layout of transistor M3 may be arranged symmetrically with respect to the center of layout 1120, and additional device array layouts of transistors M2 and M3 may be placed on both sides, respectively.

[0064] refer to Fig.12 , while communicating with schematic editor 102 and / or layout editor 104, device array editor 108 may identify that some circuit components of a schematic design (e.g., 1200) share the same schematic information. For example, multiple circuit components 1210 of schematic design 1200 are used together as a subcircuit, such as a ring oscillator. As such, device array editor 108 may communicate with schematic editor 102 to add multiple dummy circuit components 1220 (each dummy circuit component being identical to at least one circuit component of the identified subcircuit) and update the corresponding circuit components 1220. In some embodiments, layout 1205 surrounds CAD layers 1250 of device array layouts 1230 that surround circuit components 1210 by autonomously generating device array layouts 1240 (corresponding to dummy circuit components 1220, respectively). As shown, each device array layout 1230 may be composed of a first active region (P-ACT) and a second active region (N-ACT). In some embodiments, the device array editor 108 may update the layout 1205 by extending the active area to form a device array layout 1240 (eg, P-DMY and N-DMY).

[0065] refer to Fig.13 , showing a schematic design 1300 including a plurality of circuit components (e.g., 1302, 1304). Schematic editor 102 may generate schematic design 1300. In some embodiments, schematic editor 102 may specify or otherwise indicate whether each circuit component is "match sensitive" in a corresponding CDF, such as Fig.13As shown, when communicating with the schematic editor 102, the device array editor 108 can recognize such LDE related information and autonomously generate a CAD layer to surround the corresponding device array layout. For example, if the match sensitive parameter is indicated as "ON", the device array editor 108 can generate a CAD layer 1350 to surround the device array layout 1305 of the circuit component 1302; if the match sensitive parameter is indicated as "OFF", the device array editor 108 may not generate a CAD layer surrounding the device array layout 1305. In various embodiments, the device array editor 108 can merge device array layouts that share device array layouts. As described above, the same matching group (e.g., 1302 and 1304) and autonomously generate a CAD layer around the merged layout.

[0066] When merging the device array layouts into one or more merged layouts and enclosing each of them through the corresponding CAD layer, the device array editor 108 may expand such match-sensitive layouts in at least one of the X direction or the Y direction. Fig.14 As shown, the merged layout 1365 and its respective CAD layer 1370 are generated autonomously. The device array editor 108 may first extend each of the CAD layers 1370 in the X direction as an extended CAD layer 1375 to surround one or more other device array layouts disposed adjacent to the merged layout 1365 in the X direction. In some embodiments, the device array editor 108 may extend the CAD layer 1370 until the edge of the total layout (e.g., a guard ring or an outermost cutting pattern) is reached. Next, the device array editor 108 may further extend each extended CAD layer 1375 in the Y direction as an extended CAD layer 1380. Similarly, the device array editor 108 may extend the CAD layer 1375 until the edge of the total layout (e.g., to the guard ring or the outermost active area). Therefore, the device array editor 108 may use the extended CAD layer 1380 to generate a CAD layer 1385.

[0067] In some embodiments, to avoid over-expanding the CAD layer, the device array editor 108 may compare the size of the currently expanded CAD layer with the size of the next expanded CAD layer. In addition, the device array editor 108 may consider the size of the dummy pattern associated with the design constraints to determine whether to expand the currently expanded CAD layer. As a non-limiting example, if the size of the currently expanded CAD layer is less than a first threshold and the combination of the size of the currently expanded CAD layer and the allowed size of the dummy pattern exceeds a second threshold, the device array editor 108 may stop expanding the currently expanded CAD layer. On the other hand, if the size of the currently expanded CAD layer is less than the first threshold and the combination does not exceed the second threshold, the device array editor 108 may further expand the currently expanded CAD layer.

[0068] refer to Fig.15 , based on the above discussion, the device array editor 108 can identify one or more match-sensitive circuit components and generate CAD layers 1512 and 1514 to surround the corresponding device array layouts 1502 and 1504, respectively. The device array editor 108 can also identify one or more other non-match-sensitive circuit components and not generate a CAD layer to surround either of the corresponding device array layouts 1506 or 1508. Next, the device array editor 108 can determine whether to merge the device array layouts 1502 to 1508 based on their matching groups and / or cell types (e.g., Figure 3 If yes, the device array editor 108 may generate a CAD layer 1520 to surround these device array layouts 1502 to 1508. However, in some embodiments, the device array editor 108 may insert a dummy pattern based on the CAD layers 1512 and 1514 surrounding the device. The array layouts 1502 and 1504 of the matching sensitive circuit components are not the CAD layer 1520. Fig.15 As shown, dummy patterns may be inserted into region 1530 surrounding CAD layer 1512 and region 1540 surrounding CAD layer 1514 .

[0069] Fig.16 A chip set or chip 1600 on or through which an embodiment is implemented is shown. Chip set 1600 is programmed to design an integrated circuit having an array of devices that is not constrained by a set of system design rules, as described herein, and includes, for example, bus 1601, processor 1603, memory 1605, DSP 1607, and ASIC 1609 components.

[0070] Processor 1603 and memory 1605 are incorporated into one or more physical packages (e.g., chips). For example, a physical package includes the arrangement of one or more materials, components, and / or wires on a structural member (e.g., a substrate) to provide one or more characteristics, such as physical strength, size conservation, and / or limitation of electrical interactions. It is contemplated that in some embodiments, chipset 1600 is implemented in a single chip. It is also contemplated that in some embodiments, chipset or chip 1600 is implemented as a single "system on a chip." Further in some embodiments, for example, a separate ASIC will not be used, and all relevant functions disclosed herein will be performed by one or more processors (e.g., processor 1603). Chipset or chip 1600, or a portion thereof, constitutes a mechanism for performing one or more steps of designing an integrated circuit having an array of devices that is not restricted by a set of system design rules.

[0071] In one or more embodiments, the chipset or chip 1600 includes a communication mechanism such as a bus 1601 for passing messages between components of the chipset 1600. The processor 1603 has connectivity to the bus 1601 to execute instructions and process information stored therein, such as memory 1605. In some embodiments, the processor 1603 is also equipped with one or more dedicated components to perform certain processing functions and tasks, such as one or more digital signal processors (DSPs) 1607, or one or more application specific integrated circuits (ASICs) 1609. The DSP 1607 is generally configured to process real-world signals (e.g., sound) in real time independently of the processor 1603. Similarly, the ASIC 1609 can be configured to perform specialized functions that are not easily performed by the circuits of a more general purpose processor. Other specialized components that assist in performing the functions described herein may optionally include one or more field programmable gate arrays (FPGAs), one or more controllers, or one or more other specialized computer chips.

[0072] In one or more embodiments, the processor (or processors) 1603 performs a set of operations specified by information specified by computer program code, which is related to designing an integrated circuit with an array of devices that is not restricted by a set of system design rules. Computer program code is a set of instructions or statements that provide instructions for the operation of a processor and / or computer system to perform specified functions.

[0073] The processor 1603 and the attached components are connected to the memory 1605 via the bus 1601. The memory 1605 includes volatile memory (e.g., RAM, magnetic disk, writable optical disk, etc.) and static memory (e.g., ROM, CD-ROM, etc.) for storing executable instructions that, when executed, perform the steps described herein to design an integrated circuit having an array of devices that is not constrained by a set of system design rules. The memory 1605 also stores data associated with or generated by the execution of the steps.

[0074] In one or more embodiments, memory 1605, such as random access memory (RAM) or any other dynamic storage, stores information including processor instructions for designing an integrated circuit having an array of devices that is not restricted by a set of system design rules. Volatile memory allows the integrated circuit design system 100 to change the information stored therein. RAM allows information units stored at locations called memory addresses to be stored and retrieved independently of information at adjacent addresses. Memory 1605 is also used by processor 1603 to store temporary values ​​during the execution of processor instructions. In various embodiments, memory 605 is a read-only memory (ROM) or any other static storage device coupled to bus 1601 for storing static information, including instructions, that is not changed by the integrated circuit design system 100. Volatile memory loses the information stored thereon when power is removed. In some embodiments, memory 1605 is a non-volatile (persistent) storage device, such as a magnetic disk, optical disk, or flash memory card, for storing information, including instructions, that remains even when the integrated circuit design system 100 is turned off or otherwise loses power.

[0075] As used herein, the term "computer-readable medium" refers to any medium that participates in providing information (including instructions for execution) to the processor 1603. Such media takes a variety of forms, including but not limited to computer-readable storage media (e.g., non-volatile media, volatile media). Non-volatile media include, for example, optical disks or disks. Volatile media include, for example, volatile memory. Common forms of computer-readable media include, for example, floppy disks, floppy disks, hard disks, tapes, any other magnetic media, CD-ROMs, CDRWs, DVDs, any other optical media, punch cards, paper tapes, optical marker sheets, any other physical media with hole patterns or other optically identifiable markers, RAM, PROM, EPROM, FLASH-EPROM, EEPROM, flash memory, any other storage chip or box, or other media computers can read from. The term computer-readable storage medium is used herein to refer to computer-readable media.

[0076] In one aspect of the disclosure, a method for designing an integrated circuit is disclosed. The method includes generating a schematic diagram of an integrated circuit including a plurality of components, each of the plurality of components being associated with a format, the format indicating a matching group representing a corresponding circuit function. The method includes generating a plurality of first device array layouts of the plurality of components based on the matching groups of the plurality of components, respectively. The method includes merging the first subsets of the plurality of first device array layouts to form a second device array layout in response to detecting that the first subsets of the first device array layouts share the same first matching group. The method includes generating a first layer surrounding the second device array layout. The method includes merging the second subsets of the plurality of first device array layouts to form a third device array layout in response to detecting that the second subsets of the first device array layouts share the same second matching group, the second matching group being different from the first matching group. The method includes generating a second layer surrounding the third device array layout. The method includes merging the second device array layout and the third device array layout to form a fourth device array layout in response to detecting that the second device array layout and the third device array layout share the same cell type. The method includes forming a third layer surrounding the fourth device array layout. The method includes inserting a dummy pattern around the third layer.

[0077] In some embodiments, the matching group includes one of the following: a current mirror, a differential pair, a bias circuit, a distributed bias circuit, or a frequency sensitive circuit.

[0078] In some embodiments, the second device array layout is immediately adjacent to the third device array layout.

[0079] In some embodiments, the method further comprises determining a size of the dummy pattern based at least on a set of system design rule constraints.

[0080] In some embodiments, the method further comprises determining a size of the dummy pattern based at least on a size of the third layer.

[0081] In some embodiments, the cell type includes at least one of the following: a cell identification, a channel length, a threshold voltage, or an active region width.

[0082] In some embodiments, the method further includes inserting a guard ring surrounding the dummy pattern.

[0083] In some embodiments, the method further includes: before generating the first device array layout, performing a first SPICE simulation on the schematic diagram of the integrated circuit; verifying the fourth device array layout through at least one of the following: layout and schematic (LVS) check, layout parasitic extraction (LPE) check or design rule check (DRC); and based on the verification result, selectively performing a second SPICE simulation on the schematic diagram of the integrated circuit.

[0084] In another aspect of the disclosure, a system for designing an integrated circuit is disclosed. The system includes at least one processor and at least one memory, the memory including computer program code for one or more programs. The at least one memory and the computer program code are configured to use the at least one processor to cause the system to: generate a schematic diagram of an integrated circuit including a plurality of components, each of the plurality of components being associated with a format, the format indicating a matching group representing a corresponding circuit function; merge a first device array layout and a second device array layout, the first device array layout corresponding to a first subset of the plurality of components sharing a first matching group, the second device array layout corresponding to a second subset of the plurality of components sharing a second matching group, in response to detecting that the first device array layout and the second device array layout share the same cell type, form a third device array layout; form a first layer surrounding the third device array layout; insert a dummy pattern around the first layer; and insert a guard ring around the dummy pattern.

[0085] In some embodiments, the matching group includes one of the following: a current mirror, a differential pair, a bias circuit, a distributed bias circuit, or a frequency sensitive circuit.

[0086] In some embodiments, the second device array layout is immediately adjacent to the third device array layout.

[0087] In some embodiments, the system is further caused to determine a size of the dummy pattern based at least on a set of system design rule constraints.

[0088] In some embodiments, the system is further caused to determine a size of the dummy pattern based at least on a size of the first layer.

[0089] In some embodiments, the cell type includes at least one of the following: a cell identification, a channel length, a threshold voltage, or an active region width.

[0090] In some embodiments, each of the first subset of the components and / or each of the second subset of the components includes a plurality of transistors stacked on each other.

[0091] In some embodiments, in the third device array layout, the first subset of components and the second subset of components are interleaved with each other.

[0092] In some embodiments, the system is further caused to: generate a second layer surrounding the first device array layout; extend the second layer to a guard ring; generate a third layer surrounding the second device array layout; and extend the third layer to the guard ring.

[0093] In another aspect of the disclosure, a computer-readable medium including computer-executable instructions for performing a method of designing an integrated circuit is disclosed. The method includes: generating a schematic diagram of an integrated circuit including a plurality of components, each of the plurality of components being associated with a format, the format indicating a matching set representing a corresponding circuit function; merging a first device array layout corresponding to a first subset of the plurality of components sharing a first matching set and a second device array layout corresponding to a second subset of the plurality of components sharing a second matching set, forming a third device array layout in response to detecting that the first device array layout and the second device array layout share a same cell type; forming a first layer surrounding the third device array layout; inserting a dummy pattern around the first layer; and further inserting a guard ring around the dummy pattern.

[0094] In some embodiments, the method for designing the integrated circuit further comprises determining a size of the dummy pattern based on at least one of: a set of system design rule constraints or a size of the first layer.

[0095] In some embodiments, the matching group includes one of the following: a current mirror, a differential pair, a bias circuit, a distributed bias circuit, or a frequency sensitive circuit.

[0096] As used herein, the term "about" refers to a specific value that may vary based on a specific technology node associated with the target semiconductor device. Based on the specific technology node, the term "about" may refer to a value that varies within a given amount, such as 10-30% (e.g., ±10%, ±20%, or ±30%) of the above value.

[0097] The foregoing summarizes the features of several embodiments so that those with ordinary knowledge in the art can better understand the various aspects of the present disclosure. Those with ordinary knowledge in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those with ordinary knowledge in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for designing an integrated circuit, characterized in that: include: generating a schematic diagram of an integrated circuit including a plurality of components, each of the plurality of components being associated with a format indicating a matching group representing a corresponding circuit function; generating a plurality of first device array layouts for the plurality of components respectively based on the respective matching groups; merging a first subset of the plurality of first device array layouts to form a second device array layout in response to detecting that the first subset of the first device array layouts share a same first matching set; generating a first layer surrounding the second device array layout; merging a second subset of the plurality of first device array layouts to form a third device array layout in response to detecting that the second subset of the first device array layouts share a same second matching set, the second matching set being different from the first matching set; generating a second layer surrounding the third device array layout; merging the second device array layout and the third device array layout to form a fourth device array layout in response to detecting that the second device array layout and the third device array layout share a same cell type; forming a third layer surrounding the fourth device array layout; and A dummy pattern is inserted around the third layer.

2. The method according to claim 1, characterized in that The second device array layout is immediately adjacent to the third device array layout.

3. The method according to claim 1, characterized in that Also included is determining a size of the dummy pattern based at least on a set of system design rule constraints.

4. The method according to claim 1, characterized in that: The cell type includes at least one of the following: cell identification, channel length, threshold voltage, or active region width.

5. The method according to claim 4, characterized in that Also includes: Before generating the first device array layout, performing a first SPICE simulation on the schematic diagram of the integrated circuit; verifying the fourth device array layout by at least one of: a layout and schematic (LVS) check, a layout parasitic extraction (LPE) check, or a design rule check (DRC); and Based on the verification result, a second SPICE simulation is selectively performed on the schematic diagram of the integrated circuit.

6. A system for designing an integrated circuit, characterized in that: include: at least one processor; as well as at least one memory including computer program code for one or more programs, the at least one memory and the computer program code being configured to, together with the at least one processor, cause the system to: generating a schematic diagram of an integrated circuit including a plurality of components, each of the plurality of components being associated with a format indicating a matching group representing a corresponding circuit function; merging the first device array layout and the second device array layout to form a third device array layout, The first device array layout corresponds to a first subset of the plurality of components that share a first matching set, the second device array layout corresponding to a second subset of the plurality of components sharing a second matching set in response to detecting that the first device array layout and the second device array layout share a same cell type; forming a first layer surrounding the third device array layout; inserting a dummy pattern around the first layer; as well as A guard ring is inserted around the dummy pattern.

7. The system according to claim 6, characterized in that The matching group includes one of the following: a current mirror, a differential pair, a bias circuit, a distributed bias circuit, or a frequency sensitive circuit.

8. The system according to claim 6, characterized in that Further, the system: generating a second layer surrounding the first device array layout; extending the second layer to a guard ring; generating a third layer surrounding the second device array layout; and The third layer is extended to a guard ring.

9. A computer-readable medium comprising computer-executable instructions for performing a method of designing an integrated circuit, characterized in that: The method comprises: generating a schematic diagram of an integrated circuit including a plurality of components, each of the plurality of components being associated with a format indicating a matching group representing a corresponding circuit function; merging a first device array layout corresponding to a first subset of the plurality of components sharing a first matching set and a second device array layout corresponding to a second subset of the plurality of components sharing a second matching set to form a third device array layout in response to detecting that the first device array layout and the second device array layout share a same cell type; forming a first layer surrounding the third device array layout; inserting a dummy pattern around the first layer; and A guard ring is further inserted around the dummy pattern.

10. The computer-readable medium of claim 9, wherein: The method for designing the integrated circuit also includes determining a size of the dummy pattern based on at least one of: a set of system design rule constraints or a size of the first layer.

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