Chip view generation method and device, equipment and medium

Abstract

The invention relates to the technical field of chip design, and discloses a chip view generation method and device, equipment and a medium, and the method comprises the steps: updating the device configuration information, layout configuration information and wiring configuration information of a chip according to the chip model parameter change of each chip design stage, the device configuration information is used for specifying device attribute information of the chip devices, the layout configuration information is used for specifying arrangement positions of the chip devices in the chip, and the wiring configuration information is used for specifying connection relations among the chip devices; drawing a device diagram for representing the chip device according to the device configuration information; arranging a device diagram according to the layout configuration information; and wiring between the device diagrams according to the wiring configuration information to obtain a chip view. The chip development efficiency can be improved.

Description

Technical Field

[0001] The present application relates to the field of chip design technology, and in particular to a chip view generation method, device, equipment and medium. Background Art

[0002] With the continuous development of semiconductor technology, the integration and complexity of chips are gradually increasing, and the chip design process is becoming more and more complicated, resulting in multiple modifications in the design process of many chips (such as large-scale chips). In order to improve chip development efficiency and speed up the iteration cycle of chip design, chip design software is required to quickly respond to such frequent modifications in the chip design process and display the latest chip view in a timely manner to assist designers in correcting design errors and defects and optimizing device layout and routing.

[0003] However, in some current technologies, chip design software cannot quickly respond to such frequent modifications in the chip design process, which greatly affects chip development efficiency. Summary of the invention

[0004] In view of this, embodiments of the present application provide a chip view generation method, a chip view generation device, an electronic device, and a computer-readable storage medium, which can improve chip development efficiency.

[0005] On one hand, the present application provides a chip view generation method, the method comprising:

[0006] According to the chip model parameter changes in each chip design stage, the device configuration information, layout configuration information and wiring configuration information of the chip are updated, wherein the device configuration information is used to specify the device attribute information of the chip device, the layout configuration information is used to specify the arrangement position of each chip device in the chip, and the wiring configuration information is used to specify the connection relationship between the chip devices;

[0007] Draw a device diagram for characterizing chip devices according to device configuration information;

[0008] Arranging the device diagram according to the layout configuration information;

[0009] According to the wiring configuration information, wiring is performed between the device diagrams to obtain a chip view.

[0010] On one hand, the present application provides a chip view generation device, the device comprising:

[0011] A configuration information updating module, used to update the device configuration information, layout configuration information and wiring configuration information of the chip according to the changes in chip model parameters in each chip design stage, wherein the device configuration information is used to specify the device attribute information of the chip device, the layout configuration information is used to specify the arrangement position of each chip device in the chip, and the wiring configuration information is used to specify the connection relationship between the chip devices;

[0012] A device drawing module, used for drawing a device diagram for characterizing chip devices according to device configuration information;

[0013] A position arrangement module, used to arrange the device diagram according to the layout configuration information;

[0014] The wiring module is used to perform wiring between the device diagrams according to the wiring configuration information to obtain a chip view.

[0015] On the other hand, the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium is used to store a computer program, and when the computer program is executed by a processor, the method described above is implemented.

[0016] On the other hand, the present application further provides an electronic device, which includes a processor and a memory, wherein the memory is used to store a computer program, and when the computer program is executed by the processor, the method described above is implemented.

[0017] In the technical solutions of some embodiments of the present application, the chip model parameter changes at each chip design stage are monitored, the device configuration information, layout configuration information and wiring configuration information of the chip are updated, and based on the device configuration information, a device diagram for characterizing the chip device is drawn; the device diagram is arranged according to the layout configuration information; and wiring is performed between the device diagrams according to the wiring configuration information to obtain a chip view. In this way, when parameters are frequently modified during chip development, the changed parameters can be updated to the device configuration information, layout configuration information and wiring configuration information in a timely manner, and then the chip view can be updated in a timely manner, so that chip developers can view the latest chip view in a timely manner, reducing the waiting time of chip developers, thereby improving chip development efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The features and advantages of the present application will be more clearly understood by referring to the accompanying drawings, which are schematic and should not be construed as limiting the present application in any way. In the accompanying drawings:

[0019] Figure 1 A schematic diagram showing a flow chart of a chip view generation method provided by an embodiment of the present application;

[0020] Figure 2A partial schematic diagram of a device configuration file of one of the chip devices provided by an embodiment of the present application is shown;

[0021] Figure 3 A partial schematic diagram of a layout configuration file of a chip device provided by an embodiment of the present application is shown;

[0022] Figure 4 A partial schematic diagram of a wiring configuration file of a chip device provided by an embodiment of the present application is shown;

[0023] Figure 5 A schematic diagram of a layout diagram obtained in the early design stage of a chip provided by an embodiment of the present application is shown;

[0024] Figure 6 A schematic diagram of a layout diagram obtained in a later stage of chip design provided by an embodiment of the present application is shown;

[0025] Figure 7 A schematic diagram of a module of a chip view generating device provided by an embodiment of the present application is shown;

[0026] Figure 8 A schematic diagram of an electronic device provided by an embodiment of the present application is shown. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0028] Before describing the solution of the present application, the relevant concepts of chip design are first explained.

[0029] Chip devices refer to the units or components that constitute a chip. Through specific design and layout, one or more chip devices can be integrated on the chip to realize the functions provided by the chip to the outside. Generally, chip devices can be divided into three levels: Element, Site, and Tile. Among them, Element chip devices can be called the basic elements or units of the chip, including but not limited to logic gates (such as AND gates, OR gates, NOT gates, etc.), triggers, registers, etc. These chip devices are the basis for realizing complex logic functions and data processing. Site chip devices can be circuits placed in a specific area of ​​the chip and composed of one or more Element-level chip devices for realizing specific needs. For example, IO Site chip devices refer to input and output circuits placed in a specific area of ​​the chip. Tile chip devices can be an independent functional unit in the chip. A Tile chip device can include one or more Site chip devices or Element chip devices. Generally, compared with Element chip devices, Site chip devices and Tile chip devices can realize more complex functions. In this application, lower-level chip devices are called sub-devices of upper-level chip devices. For example, when a Site chip device is composed of one or more Element chip devices, the one or more Element chip devices can be called sub-devices of the Site chip device. For another example, when a Tile chip device is composed of one or more Site chip devices, the one or more Site chip devices may be referred to as sub-devices of the Tile chip device.

[0030] Chip views include but are not limited to the physical view and functional view of the chip. The physical view is used to describe the physical appearance and internal structure of the chip. The physical appearance includes but is not limited to the size, shape, packaging form, circuit layout on the chip surface, etc. The internal structure includes but is not limited to the manufacturing process of the chip (such as wafer cutting, transistor layout, metal interconnection layer, etc.). The functional view is used to describe the organization and relationship of the various functional modules inside the chip, as well as the direction of data flow and control flow inside the chip. Functional modules may include processor cores, memory controllers, input and output interfaces, etc. Functional modules are interconnected through internal buses or signal lines to jointly realize the functions provided by the chip to the outside world.

[0031] Chip development is to design the physical appearance, internal structure, organization and relationship of each functional module of the chip through chip design software according to the functions that the chip needs to provide to the outside world. During the chip development process, chip design software can display chip views to facilitate chip developers to correct design errors and defects based on chip views, optimize device layout and routing, etc. However, with the gradual increase in chip integration and complexity, and the increasingly complex chip design process, many chips (such as large-scale chips) often require multiple and frequent modifications during their design process. Current chip design software cannot respond quickly to such frequent modifications and cannot display the latest chip views in a timely manner, which greatly affects chip development efficiency.

[0032] In view of this, the present application provides a chip view generation method that can quickly respond to frequent modifications in the chip design process and display the latest chip view in a timely manner, thereby improving chip development efficiency. The chip view generation method can be applied to chip design software, or can be applied to electronic devices that run chip design software. Among them, electronic devices include but are not limited to tablet computers, laptops, desktop computers, etc. Figure 1 , which is a flow chart of a chip view generation method provided in one embodiment of the present application. Figure 1 In the present invention, the chip view generation method may include the following steps:

[0033] Step S101 , updating the device configuration information, layout configuration information and wiring configuration information of the chip according to the changes of chip model parameters in each chip design stage.

[0034] Specifically, the chip design stage may include but is not limited to the early design stage, mid-term design stage, and late design stage of the chip. Each chip design stage may have its own corresponding chip model parameters. The chip model parameters may include layout planning parameters, wiring parameters, etc. Among them, the layout planning parameters may include but are not limited to the layout parameters of each functional module on the chip, and the wiring parameters may include but are not limited to the routing spacing, number of metal layers and width on the chip.

[0035] During the chip design process (i.e., the chip development process), the chip model parameters can change dynamically, that is, the chip designer can frequently modify the chip model parameters. By monitoring the dynamic changes of the chip model parameters, the device configuration information, layout configuration information, and wiring configuration information of the chip can be dynamically updated.

[0036] In this embodiment, the device configuration information is used to specify the device attribute information of the chip device. The device attribute information may include, but is not limited to, the sub-device layout information, pin information, device name, device shape, etc. of the chip device. Among them, the sub-device layout information is used to specify the sub-devices included in the chip device and the connection relationship between the sub-devices; the pin information is used to specify the pins included in the chip device and the pin shapes of the pins in the device diagram; the device name is used to identify the chip device.

[0037] Device configuration information can be recorded in the device configuration file. Figure 2 , is a partial schematic diagram of a device configuration file of one of the chip devices M provided in one embodiment of the present application. Figure 2 In the figure, BlockA~G can represent the sub-devices included in the chip device M. The lines with arrows can represent the connection relationship between sub-devices, or the connection relationship between chip device M and other chip devices. For example, line AB represents the connection relationship between sub-device A and sub-device B, and line AX represents the connection relationship between chip device M and other chip devices. In this application, the lines between sub-devices or the lines between chip devices can also be called routing, that is, the sub-devices or chip devices are connected by routing.

[0038] In this embodiment, the layout configuration information is used to specify the arrangement position, height and width of each chip device in the chip. Among them, the arrangement position can be expressed by the row and column position in the chip, or by the coordinate position in the chip. For example, in the layout configuration information, the arrangement position of chip device A can be expressed as the X1th row and Y1th column in the chip, or it can be expressed as (startX:x1, startY:y1, endX:x2, endY:y2), where startX, startY, endX, and endY represent the X-axis starting coordinate, Y-axis starting coordinate, X-axis ending coordinate, and Y-axis ending coordinate of chip device A, respectively. The height and width of the chip device can be used to characterize the area that the chip device needs to occupy on the chip.

[0039] Specifically, in the case where a chip device includes a plurality of sub-devices, the layout configuration information of the chip device may specify the arrangement position, height and width of each sub-device in the chip.

[0040] Layout configuration information can be recorded in a layout configuration file. For ease of understanding, refer to Figure 3 , is a partial schematic diagram of a layout configuration file of one of the chip devices M provided in one embodiment of the present application. Figure 3 In the example, the value AAA of the field deviceName can represent the device name of the chip device M. BLOCK1 and BLOCK2 can represent the sub-devices of the chip device M. Figure 3 It can be seen that in the layout configuration information of the chip device M, the arrangement position, height and width of each sub-device are respectively specified.

[0041] In this embodiment, the wiring configuration information is used to specify the connection relationship between chip devices and the routing type between chip devices. The connection relationship between chip devices can be represented by the connection relationship between sub-devices included in the chip devices. Different chip devices (or different sub-devices of the same chip device) can be connected by different types of routing. For example, the routing type may include 1x routing, 2x routing, and 4x routing. Different types of routing can be represented by different colors. For example Figure 2 In the diagram, the green trace can represent the 1x trace, the red trace can represent the 2x trace, and the yellow trace can represent the 4x trace. This makes it easier to distinguish.

[0042] Wiring configuration information can be recorded in a wiring configuration file. Figure 4 , is a partial schematic diagram of a wiring configuration file of one of the chip devices M provided in one embodiment of the present application. Figure 4 In FIG. 1 , OUTPIN may represent a pin provided by a sub-device of chip device M. Two pins located in the same row indicate that there is a connection relationship between the two pins. For example, for Figure 4 For example, "BLOCKA:OUTPIN1":"BLOCKE:OUTPIN1" in the sub-device BLOCKA can indicate that the pin OUTPIN1 of the sub-device BLOCKA is connected to the pin OUTPIN1 of the sub-device BLOCKE.

[0043] Step S102: drawing a device diagram for characterizing the chip device according to the device configuration information.

[0044] Specifically, the device diagram can be a graphical representation of the chip device. In the chip view, the device diagram is used to characterize the chip device. In this embodiment, drawing a device diagram for characterizing the chip device can specifically include: drawing the sub-devices included in the chip device according to the sub-device layout information, and wiring between the sub-devices to obtain the device diagram; drawing the pins included in the chip device in the device diagram according to the pin shape specified by the pin information; when the device attribute information includes the device name of the chip device, marking the device name in the device diagram; when the device attribute information includes the device shape of the chip device, drawing the device diagram according to the device shape. In this way, based on the device diagram, the structure, routing, device identification, etc. corresponding to the chip device represented by the device diagram can be determined.

[0045] Step S103, arranging the device diagram according to the layout configuration information.

[0046] Specifically, in this step, the device diagrams corresponding to the various chip devices are arranged according to the positional relationship of the various chip devices in the chip. In this way, the positional relationship between the device diagrams after arrangement reflects the positional relationship of the chip devices in the chip. At different stages of chip design, the arrangement diagrams of the device diagrams may not be exactly the same. For example, in combination with Figure 5 and Figure 6 . Figure 5 A schematic diagram of a layout diagram obtained in the early design stage of a chip is provided for one embodiment of the present application. Figure 6 A schematic diagram of a layout diagram obtained in a later stage of chip design is provided for one embodiment of the present application. Figure 5 and Figure 6 In the diagram, each shaded box can represent a device diagram. Figure 5 and Figure 6 It can be seen that in the early design stage of the chip, the layout diagram of the obtained device diagram can be relatively simple, but in the later design stage of the chip, the layout diagram of the obtained device diagram can be relatively complex.

[0047] In this embodiment, for any target chip device in the chip devices, when the layout configuration information specifies that the target chip device has multiple target arrangement positions, the target device diagram corresponding to the target chip device can be copied according to the number of target arrangement positions, and then the target device diagram corresponding to the target chip device can be copied according to the target arrangement positions and the target device diagram. Figure 1 A one-to-one relationship is established, and the copied target device diagram is arranged at each target arrangement position. For example, assuming that in the layout configuration information, the target chip device M is specified to have three arrangement positions A, B, and C, and the arrangement position A is located at the 2nd row and 3rd column of the chip, the arrangement position B is located at the 5th row and 8th column of the chip, and the arrangement position C is located at the 10th row and 2nd column of the chip. Then, the device diagram of the target chip device M can be copied three times to obtain three device diagrams E, F, and G of the target chip device M. Among them, the device diagram E can be arranged at the arrangement position A, the device diagram F can be arranged at the arrangement position B, and the device diagram C can be arranged at the arrangement position C. In this way, the device diagram can be reused, the definition of the device diagram can be reduced, and the storage consumption can be reduced.

[0048] In this embodiment, when the layout configuration information specifies the target height and target width of the target chip device, after arranging the copied target device diagrams at each target arrangement position, the height of each target device diagram can be adjusted to the target height, and the width of each target device diagram can be adjusted to the target width at each target arrangement position. In this way, the size of the target device diagram can reflect the size of the target chip device, and the obtained arrangement diagram is more accurate.

[0049] Step S104, performing wiring between device diagrams according to the wiring configuration information to obtain a chip view.

[0050] Specifically, according to the wiring configuration information, it can be determined that there is a connection relationship between the first device diagram and the second device diagram, and the first device diagram and the second device diagram are connected.

[0051] In this embodiment, for the first device diagram and the second device diagram that have a connection relationship, the target routing type between the first device diagram and the second device diagram can be determined, and the first device diagram and the second device diagram are connected using routing corresponding to the target routing type. The layout diagram after wiring is completed can be used as a chip view.

[0052] In summary, in the technical solutions of some embodiments of the present application, by monitoring the chip model parameter changes at each chip design stage, the device configuration information, layout configuration information and wiring configuration information of the chip are updated, and based on the device configuration information, a device diagram for characterizing the chip device is drawn; according to the layout configuration information, the device diagram is arranged; according to the wiring configuration information, wiring is performed between the device diagrams to obtain a chip view. In this way, when the parameters are frequently modified during the chip development process, the changed parameters can be updated to the device configuration information, layout configuration information and wiring configuration information in a timely manner, and then the chip view can be updated in a timely manner, so that chip developers can view the latest chip view in a timely manner, reducing the waiting time of chip developers, thereby improving chip development efficiency.

[0053] In some embodiments, before drawing the device diagram, the method of the present application may further include:

[0054] Obtain element configuration information to generate a chip view based on the element configuration information, wherein the element configuration information is used to specify at least one target graphic, each target graphic is used to represent one of the view elements in the chip view, and the connection relationship between the device diagram and the device diagram can be represented by a combination of one or more view elements. Among them, the target graphics may include but are not limited to circles, rectangles, line segments, polylines, polygons, etc. Each target graphic may have a specific meaning. For example, a rectangle can be used to represent a sub-device, a small dot can be used to represent a pin, and a dotted line can be used to represent a pin. Then, when drawing a device diagram, a combination of a rectangle, a small dot, and a dotted line can be used to represent the device diagram. By defining the target graphics, the generated chip view can be more standardized.

[0055] This completes the description of the chip view generation method of the present application.

[0056] Corresponding to the chip view generation method, the present application also provides a chip view generation device. Figure 7, which is a module diagram of a chip view generating device provided in one embodiment of the present application. Figure 7 In the embodiment, the chip view generating device comprises:

[0057] A configuration information updating module, used to update the device configuration information, layout configuration information and wiring configuration information of the chip according to the changes in chip model parameters in each chip design stage, wherein the device configuration information is used to specify the device attribute information of the chip device, the layout configuration information is used to specify the arrangement position of each chip device in the chip, and the wiring configuration information is used to specify the connection relationship between the chip devices;

[0058] A device drawing module, used for drawing a device diagram for characterizing chip devices according to device configuration information;

[0059] A position arrangement module is used to arrange the device diagram according to the layout configuration information;

[0060] The routing module is used to perform routing between device diagrams according to the routing configuration information to obtain a chip view.

[0061] In some embodiments, the device attribute information includes sub-device layout information of the chip device, and the sub-device layout information is used to specify the connection relationship between sub-devices included in the chip device and the sub-devices; the device drawing module is specifically used to:

[0062] According to the sub-device layout information, the sub-devices included in the chip device are drawn, and wiring is performed between the sub-devices to obtain a device diagram.

[0063] In some embodiments, the device attribute information further includes pin information of the chip device, and the pin information is used to specify the pins included in the chip device and the pin shapes of the pins in the device diagram; the device drawing module is specifically used to:

[0064] Draw the pins included in the chip device in the device diagram according to the pin shape specified by the pin information.

[0065] In some embodiments, the device attribute information further includes a device name and / or a device shape of the chip device; the device drawing module is specifically used for:

[0066] When the device attribute information includes the device name of the chip device, the device name is marked in the device diagram;

[0067] When the device attribute information includes the device shape of the chip device, the device diagram is drawn according to the device shape.

[0068] In some embodiments, the location arrangement module is specifically used to:

[0069] For any target chip device in the chip devices, if the layout configuration information specifies that the target chip device has multiple target arrangement positions, copy the target device diagram corresponding to the target chip device according to the number of the target arrangement positions;

[0070] Arrange positions and target devices according to target Figure 1 A one-to-one relationship is established, and the copied target device diagram is arranged at each target arrangement position.

[0071] In some embodiments, the layout configuration information is further used to specify a target height and a target width of a target chip device;

[0072] After arranging the copied target device diagrams at each target arrangement position, the position arrangement module is further used to:

[0073] At each target arrangement position, the height of each target device image is adjusted to a target height, and the width of each target device image is adjusted to a target width.

[0074] In some embodiments, the chip devices are connected by routing, and the routing configuration information is also used to specify the routing type between the chip devices; the routing module is specifically used to:

[0075] For a first device diagram and a second device diagram that have a connection relationship, determine a target routing type between the first device diagram and the second device diagram;

[0076] Connect the first device diagram and the second device diagram using a trace corresponding to the target trace type.

[0077] In some embodiments, before drawing the device diagram, the device drawing module is further configured to:

[0078] Obtain element configuration information to generate a chip view based on the element configuration information, wherein the element configuration information is used to specify at least one target graphic, each target graphic is used to represent one of the view elements in the chip view, and the connection relationship between the device diagrams is represented by a combination of one or more view elements.

[0079] Combined with reference Figure 8 , is a schematic diagram of an electronic device provided by an embodiment of the present application. The electronic device includes a processor and a memory, the memory is used to store a computer program, and when the computer program is executed by the processor, the above method is implemented.

[0080] The processor may be a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or a combination of the above chips.

[0081] As a non-transitory computer-readable storage medium, the memory can be used to store non-transitory software programs, non-transitory computer executable programs and modules, such as program instructions / modules corresponding to the method in the implementation of the present application. The processor executes various functional applications and data processing of the processor by running the non-transitory software programs, instructions and modules stored in the memory, that is, implementing the method in the above method implementation.

[0082] The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created by the processor, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-transitory memory, such as at least one disk storage device, a flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0083] One embodiment of the present application further provides a computer-readable storage medium, which is used to store a computer program. When the computer program is executed by a processor, the above method is implemented.

[0084] Although the embodiments of the present application have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A chip view generation method, characterized in that: The method comprises: According to the chip model parameter changes in each chip design stage, the device configuration information, layout configuration information and wiring configuration information of the chip are updated, wherein the device configuration information is used to specify the device attribute information of the chip device, the layout configuration information is used to specify the arrangement position of each chip device in the chip, and the wiring configuration information is used to specify the connection relationship between the chip devices; Draw a device diagram for characterizing chip devices according to device configuration information; Arranging the device diagram according to the layout configuration information; According to the wiring configuration information, wiring is performed between the device diagrams to obtain a chip view.

2. The method according to claim 1, characterized in that The device attribute information includes sub-device layout information of the chip device, and the sub-device layout information is used to specify the connection relationship between sub-devices included in the chip device; The drawing of a device diagram for characterizing a chip device comprises: According to the sub-component layout information, the sub-components included in the chip device are drawn, and wiring is performed between the sub-components to obtain the device diagram.

3. The method according to claim 2, characterized in that The device attribute information also includes pin information of the chip device, where the pin information is used to specify the pins included in the chip device and the pin shapes of the pins in the device diagram; The drawing of a device diagram for characterizing a chip device further includes: The pins included in the chip device are drawn in the device diagram according to the pin shapes specified by the pin information.

4. The method according to claim 2 or 3, characterized in that The device attribute information also includes the device name and / or device shape of the chip device; The drawing of a device diagram for characterizing a chip device further includes: When the device attribute information includes a device name of the chip device, marking the device name in the device diagram; When the device attribute information includes a device shape of the chip device, the device diagram is drawn according to the device shape.

5. The method according to claim 1, characterized in that Arranging the device diagram according to the layout configuration information includes: For any target chip device among the chip devices, if the layout configuration information specifies that the target chip device has multiple target arrangement positions, copy the target device diagram corresponding to the target chip device according to the number of the target arrangement positions; According to the one-to-one correspondence between the target arrangement positions and the target device diagrams, the copied target device diagrams are arranged at the respective target arrangement positions.

6. The method according to claim 5, characterized in that The layout configuration information is also used to specify the target height and target width of the target chip device; After arranging the copied target device diagrams at the target arrangement positions respectively, the method further includes: At each of the target arrangement positions, the height of each of the target device images is adjusted to the target height, and the width of each of the target device images is adjusted to the target width.

7. The method according to claim 1, characterized in that The chip devices are connected by routing, and the routing configuration information is also used to specify the routing type between the chip devices; The step of performing wiring between the device diagrams according to the wiring configuration information includes: For a first device diagram and a second device diagram that are in a connection relationship, determining a target routing type between the first device diagram and the second device diagram; The first device diagram and the second device diagram are connected using a routing corresponding to the target routing type.

8. The method according to claim 1, characterized in that Before drawing the device diagram, the method further includes: Obtain element configuration information to generate the chip view based on the element configuration information, wherein the element configuration information is used to specify at least one target graphic, each of the target graphics is used to represent one of the view elements in the chip view, and the connection relationship between the device diagram and the device diagram is represented by a combination of one or more of the view elements.

9. A chip view generating device, characterized in that: The device comprises: A configuration information updating module, used to update the device configuration information, layout configuration information and wiring configuration information of the chip according to the changes in chip model parameters in each chip design stage, wherein the device configuration information is used to specify the device attribute information of the chip device, the layout configuration information is used to specify the arrangement position of each chip device in the chip, and the wiring configuration information is used to specify the connection relationship between the chip devices; A device drawing module, used for drawing a device diagram for characterizing chip devices according to device configuration information; A position arrangement module, used to arrange the device diagram according to the layout configuration information; The wiring module is used to perform wiring between the device diagrams according to the wiring configuration information to obtain a chip view.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium is used to store a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

11. An electronic device, characterized in that: The electronic device comprises a processor and a memory, wherein the memory is used to store a computer program, and when the computer program is executed by the processor, the method according to any one of claims 1 to 8 is implemented.

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