Apparatus and method for refresh target identification based on per-row count

Abstract

The invention relates to an apparatus and method for refresh target identification based on per-row count. A memory device stores a count value associated with a word line. An aggressor detector circuit stores a maximum one of the count values and a row address associated with the maximum count value. In response to a target refresh signal, the stored count value is compared to a threshold. If the count value exceeds the threshold, a target refresh operation may be performed on one or more refresh addresses based on the stored address, and the count value may be reset.

Description

Technical Field

[0001] The present disclosure relates to memory devices, and more particularly, to apparatus and methods for refresh target identification based on per-row counts. Background Art

[0002] Information may be stored on memory cells of a memory device. Memory cells may be organized at the intersection of word lines (rows) and bit lines (columns). Information in a memory cell may decay over time. For example, information may be stored as a charge on a capacitor, which may decay over time. A memory device may perform a refresh operation to restore information and prevent information loss.

[0003] Certain access patterns may cause an increased rate of information decay in nearby memory cells (e.g., memory cells along nearby word lines). The memory may use various schemes to identify which memory cells are affected by such patterns so that targeted refresh operations can be performed before those memory cells lose their information. Targeted refresh operations need to be balanced with the time and power they use. Summary of the invention

[0004] In one aspect, the present disclosure provides an apparatus comprising: a memory array comprising a plurality of word lines each associated with one of a plurality of row addresses and one of a plurality of count values; an aggressor detector circuit configured to store a maximum of the plurality of count values ​​and the associated row address, wherein the aggressor detector circuit is configured to receive a target refresh signal and compare the maximum count value with a threshold, and wherein the aggressor detector circuit is configured to provide the associated row address as an aggressor address if the maximum count value exceeds the threshold; and a refresh address generator circuit configured to provide a refresh address based on the aggressor address in response to the target refresh signal.

[0005] In another aspect, the present disclosure provides an apparatus comprising: a memory array comprising a plurality of word lines; a row decoder configured to access a selected one of the plurality of word lines based on a row address; a counter circuit configured to receive a count value from the selected one of the plurality of word lines and to update the count value; and an aggressor detector circuit configured to compare the updated count value with a stored count value and, if the updated count value exceeds the stored count value, store the row address and the count value, and to provide the stored row address as an aggressor address in response to a target refresh signal if the stored count value exceeds a threshold, wherein the row decoder is configured to refresh at least one row based on the aggressor address in response to the target refresh signal as part of a target refresh operation.

[0006] In another aspect, the present disclosure provides a method comprising: accessing a word line and updating a count value associated with the word line; if the updated count value is a maximum count value, storing a row address and the updated count value in a candidate register; comparing the stored updated count value with a threshold value in response to a target refresh signal; if the stored updated count value exceeds the threshold value, identifying the stored row address as an aggressor address; and if the stored row address is identified as the aggressor address, refreshing one or more word lines as part of a target refresh operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2 is a block diagram of a refresh control circuit according to an embodiment of the present disclosure.

[0009] Figure 3 is a block diagram of an aggressor detector circuit according to some embodiments of the present disclosure.

[0010] Figure 4 is a timing diagram of a refresh operation in a memory according to some embodiments of the present disclosure.

[0011] Figure 5 is a flow chart of a method according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0012] The following description of certain embodiments is merely exemplary in nature and is in no way intended to limit the scope of the present disclosure or its application or use. In the following detailed description of the embodiments of the present system and method, reference is made to the accompanying drawings that form a part thereof and show in an illustrative manner the specific embodiments in which the described system and method can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the currently disclosed system and method, and it should be understood that other embodiments may be utilized and structural and logical changes may be made without departing from the spirit and scope of the present disclosure. In addition, for the purpose of clarity, when certain features will be apparent to those skilled in the art, the detailed description of the features will not be discussed to avoid blurring the description of the embodiments of the present disclosure. Therefore, the following detailed description should not be understood in a limiting sense, and the scope of the present disclosure is defined only by the appended claims.

[0013] Information in a memory array may be accessed through one or more access operations, such as read or write operations. During an example access operation, a word line may be activated based on a row address and then selected memory cells along that actively activated word line may have their information read or written based on which bit lines are accessed, which may be based on a column address. The memory array may be refreshed on a row-by-row basis (e.g., as part of an auto-refresh and / or self-refresh mode), where the memory cells along each row are periodically refreshed. The speed at which a row is refreshed (e.g., the maximum time any given row will experience between refreshes) may be determined based on an expected information decay rate.

[0014] Various access patterns to rows (aggressor rows) may cause an increase in the rate of information decay in nearby memory cells (e.g., along victim rows). For example, 'row hammering' may involve repeated accesses to an aggressor row, which may increase the decay rate in neighboring rows (and / or in rows further away). Therefore, it is important to track the number of accesses to each row to determine if they are aggressors so that victim rows can be identified and refreshed as part of a targeted refresh operation. For example, each word line may have an associated count value that is used to determine how many times that word line has been accessed. Based on those access counts, rows for targeted refresh operations may be identified. It may be necessary to manage how the memory identifies rows to balance detecting rows so that the rows can be refreshed before information is lost with the time and power used by those targeted refresh operations. It may be necessary to ensure that potential aggressors are identified while filtering out unwanted targeted refresh operations.

[0015] The present disclosure relates to apparatus, systems and methods for refresh target identification based on per-row counts. A memory device includes a plurality of word lines, each of which stores a count value. A refresh control circuit of the memory device identifies the row with the N highest count values ​​and stores the row address and the count value in a register. For example, in an example embodiment where N is 1, the row with the highest count value and the count value are stored. In an embodiment where N is 2, two rows with the highest and second highest count values ​​and their count values ​​are stored. When a target refresh operation is called, the stored row with the worst count value is compared to a threshold. If the count value exceeds the threshold, a target refresh operation is performed on a victim associated with the address and the count is reset. If the count value does not exceed the threshold, the target refresh operation can be skipped.

[0016] Figure 1 is a block diagram of a semiconductor device according to at least one embodiment of the present disclosure. The semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip.

[0017] The semiconductor device 100 includes a memory array 118. The memory array 118 is shown as including a plurality of memory banks. Figure 1In the embodiment of the present invention, the memory array 118 is shown to include eight memory banks BANK0 to BANK7. More or fewer memory banks may be included in the memory array 118 of other embodiments. Each memory bank includes a plurality of word lines WL (rows), a plurality of bit lines BL (columns), and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL.

[0018] The selection of the word line WL is performed by the row decoder 108 and the selection of the bit line BL is performed by the column decoder 110. Figure 1 In the embodiment of the present invention, the row decoder 108 includes a corresponding row decoder for each memory bank and the column decoder 110 includes a corresponding column decoder for each memory bank. The bit line BL is coupled to a corresponding sense amplifier (SAMP). The read data from the bit line BL is amplified by the sense amplifier SAMP and transmitted to the read / write amplifier 120 through the complementary local data line (LIOT / B), the transfer gate (TG) and the complementary main data line (MIOT / B). Conversely, the write data output from the read / write amplifier 120 is transmitted to the sense amplifier SAMP through the complementary main data line MIOT / B, the transfer gate TG and the complementary local data line LIOT / B, and is written in the memory cell MC coupled to the bit line BL.

[0019] Some memory cells may be reserved as counter memory cells 126. The counter memory cells may store count values ​​XCount, each of which is associated with one of the word lines. Each count value XCount may be stored in a counter memory cell 126 along the word line associated with the count value. The count value XCount may be stored as a binary number, with each bit stored in a memory cell along the word line. For clarity, Figure 1 1. A single bit line of counter memory cells 126 is shown in FIG. 1. The number of counter memory cells along each word line may be based on the number of bits of the count value XCount. In some embodiments, additional counter memory cells (e.g., of length greater than the number XCount) may be used, for example, to store error correction information for the count value XCount.

[0020] The counter memory cells 126 are so called due to their purpose (storing count values), and in some embodiments may be similar or identical in structure to other memory cells of the array. In some embodiments, the counter memory cells 126 may be grouped together (e.g., at the ends of a word line). In other example embodiments, other distributions of the counter memory cells 126 along the word line may be used. In some embodiments, the counter memory cells 126 cannot be directly accessed by an external device (e.g., a controller) (e.g., to prevent the count value from being overwritten). In other words, the bit lines associated with the counter memory cells 126 cannot be accessed by a normal column address.

[0021] The semiconductor device 100 may employ a plurality of external terminals including a command and address (C / A) terminal coupled to a command and address bus to receive a command and address and a CS signal, a clock terminal for receiving clocks CK and / CK, a data terminal DQ for providing data, and a power supply terminal for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0022] The clock terminal is supplied with external clocks CK and / CK provided to the input circuit 112. The external clocks may be complementary. The input circuit 112 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to the command decoder 110 and the internal clock generator 114. The internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used to time the operation of various internal circuits. The internal data clock LCLK is provided to the input / output circuit 122 to time the operation of the circuit included in the input / output circuit 122, for example, to the data receiver to time the reception of the write data.

[0023] The C / A terminal may be supplied with a memory address. The memory address supplied to the C / A terminal is transmitted to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and supplies the decoded row address XADD to the row decoder 108 and supplies the decoded column address YADD to the column decoder 110. The address decoder 104 may also supply a decoded memory bank address BADD, which may indicate a memory bank of the memory array 118 containing the decoded row address XADD and column address YADD. The C / A terminal may be supplied with a command. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory, such as a read command for performing a read operation and a write command for performing a write operation, and other commands and operations. The access command may be associated with one or more row addresses XADD, column addresses YADD, and memory bank addresses BADD to indicate the (several) memory cells to be accessed.

[0024] The command may be provided as an internal command signal to the command decoder 106 via the command / address input circuit 102. The command decoder 106 includes circuits to decode the internal command signal to generate various internal signals and commands for performing operations. For example, the command decoder 106 may provide a row command signal to select a word line and a column command signal to select a bit line.

[0025] The device 100 may receive an access command as a row activation command ACT. When the row activation command ACT is received, the bank address BADD and the row address XADD are supplied in time with the row activation command ACT.

[0026] The device 100 may receive an access command as a read command. When the read command is received and the memory cell address BADD and the column address YADD are supplied in time with the read command, read data is read from the memory cell corresponding to the row address XADD and the column address YADD in the memory array 118. The read command is received by the command decoder 106, and the command decoder 106 provides an internal command so that the read data from the memory array 118 is provided to the read / write amplifier 120. The read data is output to the outside from the data terminal DQ via the input / output circuit 122. The access count XCount stored in the counter memory cell 126 of the row associated with the row address XADD is read to the refresh address control circuit 116, and the updated value of the access count XCount' is written back to the counter memory cell 126 of the row XADD.

[0027] The device 100 can receive an access command as a write command. When the write command is received and the memory address BADD and the column address YADD are supplied in time with the write command, the write data supplied to the data terminal DQ is written to the memory cell corresponding to the row address and the column address in the memory array 118. The write command is received by the command decoder 106, and the command decoder 106 provides an internal command so that the write data is received by the data receiver in the input / output circuit 122. The write clock can also be provided to the external clock terminal to time the data receiver of the input / output circuit 122 to receive the write data. The write data is supplied to the read / write amplifier 120 via the input / output circuit 122, and is supplied to the memory array 118 through the read / write amplifier 120 to be written into the memory cell MC. Similar to the read operation described above, the access count Xcount stored in the counter memory cell 126 of the row associated with the row address XADD is read to the refresh address control circuit 116, and the updated value of the access count Xcount′ is written back to the counter memory cell 126 of the row XADD.

[0028] The device 100 may also receive a command that causes it to perform a refresh operation. For example, a controller of the memory may place the device 100 in an auto-refresh mode and provide a refresh signal REF. The device 100 may also enter a self-refresh mode in which a refresh signal is generated internally. Since the two operations may be substantially similar except for the source of the refresh signal, the present disclosure will generally describe the auto-refresh operation (e.g., the refresh signal may be referred to as an 'auto-refresh signal'). However, it should be understood that the present disclosure may also be applicable to self-refresh (or other refresh modes).

[0029] The refresh signal REF may be a pulse signal activated when the command decoder 106 receives a signal indicating an automatic refresh command. In some embodiments, the automatic refresh command may be issued to the memory device 100 from the outside. In some embodiments, the automatic refresh command may be periodically generated by a component of the device (e.g., as part of a self-refresh mode). In some embodiments, the refresh signal REF may also be activated when an external signal indicates a self-refresh entry command. The refresh signal REF may be activated once immediately after the command is input, and may be cyclically activated at the desired internal timing thereafter. Therefore, the refresh operation may continue automatically. The self-refresh exit command may stop the automatic activation of the refresh signal REF and return to an idle state.

[0030] The refresh signal REF is supplied to the refresh address control circuit 116. The refresh address control circuit 116 supplies the refresh row address RXADD to the row decoder 108, and the row decoder 108 refreshes the word line WL identified by the refresh row address RXADD. The refresh address control circuit 116 controls the type of refresh operation with the timing based on the refresh signal REF, and generates and provides the refresh address RXADD. The refresh address control circuit 116 may be controlled to change the details of the refresh address RXADD (e.g., how to calculate the refresh address, the timing of the refresh address), or may operate based on internal logic.

[0031] The refresh address control circuit 116 may selectively output a target refresh address (e.g., a victim address) or a sequential refresh address (e.g., an auto-refresh address) as the refresh address RXADD. The sequential refresh address may be generated based on an address sequence. For example, each sequential refresh may be based on a previous sequential refresh address (e.g., RXADD(i)=RXADD(i-1)+1). The refresh address control circuit 116 may cycle through the sequential address sequence at a rate determined by REF. In some embodiments, the sequential address sequence may include all addresses in the memory bank 118. In some embodiments, the auto-refresh signal REF may be issued at a frequency such that most or all addresses in the memory bank 118 are refreshed within a certain cycle (e.g., such that there is a maximum specified time between two consecutive sequential refreshes of a given word line), and the cycle may be based on the expected rate of information decay in the memory cell MC.

[0032] The refresh address control circuit 116 also performs a target refresh operation. As part of the target refresh operation, the refresh address control circuit generates one or more refresh addresses based on the identified aggressor address. The aggressor address is a row address that is identified as an aggressor based on the count value XCount associated with that address. The refresh address control circuit 116 stores one or more candidate addresses and their associated counts in a candidate register. When a row is accessed, the count value XCount is read out and updated (e.g., by incrementing). The updated count value is compared with the stored count value in the candidate register. If the updated count value is larger, it is stored in the register and the current row address is written to the register (overwriting the previous entry). In this way, the candidate register stores the address and count with the highest count value. The depth of the register can determine how many addresses and counts are stored.

[0033] The refresh operation is performed with a timing based on the refresh signal REF or with a timing based on the RFM command. In response to REF, the refresh address control circuit may execute multiple 'pumps' of the internal refresh signal, and a refresh operation may be performed for each of those pumps. Each pump may be used for a sequential refresh operation, a target refresh operation, or may be skipped (e.g., a refresh operation is not performed). In some embodiments, a target refresh address may be issued (e.g., "stolen") in a pump that would otherwise be used for a sequential refresh operation. In some embodiments, certain time slots may be reserved for the target refresh address. In response to the RFM command, the refresh control circuit 116 may execute multiple pumps, all of which may be used for a target refresh operation.

[0034] When a target refresh operation is invoked by the internal logic of the refresh control circuit 116 or due to an external command (e.g., a refresh management (RFM) command), the refresh control circuit 116 may determine whether the stored address in the candidate register is an aggressor. For example, the stored count value may be compared to a threshold and if the count exceeds the threshold (e.g., is greater than the threshold), the stored address may be identified as an aggressor, and one or more target refresh addresses may be generated based on the aggressor. In response to the target refresh operation being performed, the count value XCount associated with the identified aggressor in the counter memory unit 126 may be changed, such as reset (e.g., reset to an initial value, such as 0). If the stored count value does not exceed the threshold, the stored address is not an aggressor and the target refresh operation may be skipped.

[0035] In some embodiments, the threshold value may be a setting of the memory device 100. For example, the mode register 130 may store the value of the threshold value. The mode register 130 may store a set of registers, each of which stores settings and / or information about the memory device. Some registers may be modified by the controller via a mode register write operation (e.g., to change the setting). Some registers may be set by non-volatile storage elements (e.g., fuse arrays) on the memory. The controller may perform a mode register read operation to determine the state of the selected register. The aggressor threshold register may set the value of the threshold value. If the threshold value is increased, fewer target refresh operations will occur, and if the threshold value is decreased, more target refresh operations will occur. If the threshold value is set to 0, then when a target refresh is called, a target refresh will always be performed.

[0036] The refresh address control circuit 116 may use different methods to calculate the target refresh address based on the aggressor address based on the access count. For example, the victim address may include word lines adjacent to the aggressor word line (e.g., XADD+1 and XADD-1) and / or may include word lines further away (e.g., XADD+ / -2, XADD+ / -3, etc.). In some embodiments, more than one victim address may correspond to a given aggressor address. In this case, the refresh address control circuit may queue up multiple target refresh addresses and sequentially provide the multiple target refresh addresses when it determines that a target refresh address should be provided. The refresh address control circuit 116 may provide the target refresh address immediately, or may queue up the target refresh address to be provided at a later time (e.g., in the next time slot available for target refresh).

[0037] The power supply terminal is supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VARY, VPERI, etc. based on the power supply potentials VDD and VSS supplied to the power supply terminal. The internal potential VPP is mainly used in the row decoder 108, the internal potential VARY is mainly used in the sense amplifier SAMP included in the memory array 118, and the internal potential VPERI is used in many peripheral circuit blocks.

[0038] The power supply terminal is also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 122. In an embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminal may be the same potential as the power supply potentials VDD and VSS supplied to the power supply terminal. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminal may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminal. The power supply potentials VDDQ and VSSQ supplied to the power supply terminal are used for the input / output circuit 122 so that the power supply noise generated by the input / output circuit 122 does not propagate to other circuit blocks.

[0039] Figure 2 is a block diagram of a refresh control circuit according to an embodiment of the present disclosure. Figure 2 An example layout of a portion of memory 200 may be shown that may implement a memory device (eg, Figure 1 For example, the memory array 218 may implement Figure 1 The memory array 118, the row decoder 208 may implement Figure 1 The row decoder 108, the refresh control circuit 216 may implement Figure 1 Refresh control circuit 116 and so on.

[0040] Certain internal components and signals of the refresh address control circuit 216 are shown to illustrate the operation of the refresh address control circuit 216. For example, the refresh control circuit 216 may include an RHR state control circuit 242 that determines whether to perform a sequential refresh or a targeted refresh, an aggressor detector circuit 217 that identifies an address as an aggressor HitXADD, and a refresh address generator 250 that generates a refresh address RXADD. A counter circuit 246 that manages the value of XCount stored in the counter memory cell 226 of the memory array 218 is also shown.

[0041] The dashed lines around the refresh address control circuit 216, row decoder 208, and memory array 218 are shown to indicate that in certain embodiments, each of the components within the dashed lines may correspond to a particular memory bank, and these components may be repeated for each of the memory banks. In some embodiments, the components shown within the dashed lines may be associated with each of the memory banks. Thus, there may be multiple refresh address control circuits 216 and row decoders 208. For the sake of brevity, only the components of a single memory bank will be described.

[0042] Figure 2Components grouped together as part of refresh control circuit 216 are shown, such as counter 246, aggressor detector circuit 217, refresh state control circuit 242, and refresh address generator 250. However, one or more of these components may be spatially distributed throughout the memory. For example, aggressor detector circuit 217 and counter circuit 246 may be spatially located in a logical region closer to a bank, while other components of the refresh control circuit may be in a bank logical region. Other distributions may be used in other example embodiments.

[0043] DRAM interface 240 may provide one or more signals to address refresh control circuit 216 and row decoder 208, which (along with column decoders, not shown) may in turn perform access operations on memory array 218. When a row of memory array 218 is accessed, the values ​​of counter memory cells 226 along that row are read to counter circuit 246. For example, counter memory cells 226 may store bits of a binary number representing a count value. For example, if the number is a 16-bit number, 16 or more counter memory cells may store bits of the number.

[0044] The counter 246 may determine the value of the access count for that row based on the value read from the counter memory unit 226. The counter 246 may be a count control circuit that may manage the value of the count stored in the counter memory unit 226 (e.g., by reading the original data in the counter memory unit 226 as a value, writing a new value to the counter memory unit 226, etc.). The counter circuit 246 may change the count value (e.g., by incrementing the count value), write the changed count value back to the counter memory unit, and provide the changed count value to the aggressor detector circuit 217. The aggressor detector circuit 217 includes an aggressor candidate register 244 and a register management circuit 245. The candidate register 244 stores a set of candidate row addresses and their associated count values. During an access operation, the register management circuit 245 compares the accessed row address XADD and its updated count value XCount' with the stored address. If the address XADD matches, its count value in the register 244 is updated to XCount'. If there is no match, the count value is stored and if the count value is greater than one of the stored count values, the address is stored, with the row address XADD and count XCount' replacing the previous entry with the lowest count value.

[0045] During a refresh operation (e.g., in response to REF and / or RFM), the refresh state controller 242 determines the type of refresh operation and provides internal refresh signals IREF and / or RHR. The signal RHR indicates that a target refresh operation should be performed. In response to RHR, the aggressor detector circuit 217 compares the stored value XCount with the highest value to a threshold. If the value exceeds the threshold, the row address associated with that count is identified as an aggressor HitXADD and provided to the refresh address generator 250, which generates one or more refresh addresses RXADD based on the aggressor HitXADD. The row decoder 208 then performs a refresh operation on the word line indicated by RXADD. Additional operations are performed to cause the counter 246 to read out the count value Xcount associated with the aggressor HitXADD from the counter memory unit 226 and reset that count (e.g., to an initial value, such as 0).

[0046] DRAM interface 240 may represent one or more components that provide signals to components of a memory bank. For example, DRAM interface 240 may represent, for example, Figure 1 The DRAM interface 240 may provide a row address XADD, an auto-refresh signal REF and a command address input circuit 102, an address decoder 104 and / or a command decoder 106. Figure 2 218. The DRAM interface 240 may include various other signals not shown in the figure, such as a row activation signal ACT and a precharge signal Pre. The auto-refresh signal REF may be a periodic signal that may indicate when an auto-refresh operation occurs. The row address XADD may be a signal that specifies one or more specific word lines of the memory array 218, and may be a signal that includes multiple bits (which may be transmitted serially or in parallel). The DRAM interface 240 may also provide a refresh management command RFM received from a controller of the memory.

[0047] Aggressor detection circuit 217 includes candidate register 244 storing a set of candidate addresses and their associated count values. Candidate register 244 includes a number of slots, each of which stores an address and a count value. The number of slots determines how many addresses and count values ​​can be stored. Candidate register 244 stores the address with the highest count value. During access operations, aggressor detection circuit 217 receives row addresses XADD and their associated updated count values ​​XCount from counter circuit 246. Register management circuit 245 includes comparator circuit 248 that compares the updated count value with the stored count value. If the updated count value is greater, the row address XADD and the updated count value XCount' overwrite the stored address and count value. In some embodiments, the new row and count may overwrite the stored address with the lowest count value.

[0048] The refresh state controller 242 may receive the auto-refresh signal REF and determine what type of refresh operation should occur and how many refresh operations should occur. The refresh state control circuit 242 provides one or more activations of the internal refresh signals IREF and RHR. In response to the activation of the internal refresh signal, the refresh address generator performs a refresh operation (or skips the execution of the refresh operation if the aggressor detector does not identify the aggressor HitXADD). The refresh state controller 242 provides a signal RHR to indicate a target refresh operation. The refresh state controller 242 provides the signal RHR in response to RFM or based on the internal logic in response to REF. For example, the refresh state controller 242 may provide an RHR signal based on a certain number of activations of REF (e.g., every 4th activation of REF) and / or based on several activations of IREF. In some embodiments, IREF alone may indicate a sequential refresh operation, while IREF and RHR together indicate a target refresh operation. In response to REF or RFM, the refresh state control may generate several activations of IREF (e.g., several pumps) and then activate RHR for the pump used for the target refresh operation.

[0049] In response to signal RHR, aggressor detector circuit 217 determines whether the stored address with the highest count value is an aggressor, and if so, provides it as the aggressor address HitXADD. In response to no address in candidate register 244 being an aggressor, no address is provided as HitXADD (which in turn causes the target refresh operation to be skipped). Aggressor detector circuit 217 determines whether the address with the highest count value is an aggressor by comparing the count value to a threshold value (e.g., using comparator circuit 248). If the count value does not exceed the threshold value (e.g., is below the threshold value), then the address is not an aggressor and no address is provided as HitXADD. If the address exceeds the threshold value (e.g., reaches or exceeds the threshold value), then the address is provided as HitXADD.

[0050] In response to one of the stored addresses being provided as HitXADD, register management circuit 245 may perform an operation to reset the count value associated with that address. Register management circuit 245 may direct row decoder 208 to read the count value associated with HitXADD from counter memory unit 226 to counter circuit 246. Register management circuit 245 may direct counter circuit 246 to reset the count value (e.g., to an initial value) and write the reset value back to counter memory unit 226. Register management circuit 245 also removes the stored address and count value from register 244.

[0051] The refresh address generator 250 includes a sequential refresh address generator 252 and a target refresh address generator 254. When a sequential refresh operation is called (e.g., when IREF is valid but RHR is invalid), the sequential refresh address generator 252 generates a sequential refresh address as a refresh address RXADD. The sequential refresh address may be based on a previous sequential refresh address. For example, the sequential refresh address generator may have a counter circuit that increments the previous sequential refresh address value to achieve the next sequential refresh address.

[0052] The refresh address generator circuit 250 also includes a target refresh address generator circuit 254, which generates a target refresh address as a refresh address RXADD when it receives the RHR signal and the identified aggressor address HitXADD. If the signal RHR is provided, but HitXADD is not provided (for example, because none of the addresses stored in the candidate register 244 exceeds the threshold), the target refresh address generator can skip the target refresh operation by not providing the refresh address RXADD. The target refresh address generator 254 can determine the location of one or more victim rows based on the aggressor address HitXADD and provide it as the refresh address RXADD. In some embodiments, the victim row may include a row that is physically adjacent to the aggressor row (for example, HitXADD+1 and HitXADD-1). In some embodiments, the victim row may also include a row that is physically adjacent to the physically adjacent row of the aggressor row (for example, HitXADD+2 and HitXADD-2). In other examples, other relationships between the victim row and the identified aggressor row can be used.

[0053] The row decoder 208 may perform one or more operations on the memory array 218 based on the received signals and addresses. For example, in response to the activation signal ACT and the row address XADD (and IREF and RHR are at low logic levels), the row decoder 208 may direct one or more access operations (e.g., read operations) to the specified row address XADD. In response to the address RXADD and one or both of the signals IREF and RHR being valid, the row decoder 208 may perform a refresh operation on the word line (or word lines) associated with RXADD. In response to the signal RHR being valid but without the address RXADD (e.g., because no address HitXADD is provided to the refresh address generator 250), the row decoder 208 may then skip the refresh operation.

[0054] Figure 3 is a block diagram of an aggressor detector circuit according to some embodiments of the present disclosure. Figure 3 Display memory 300 (eg Figure 1 The memory 100 and / or Figure 2 In some embodiments, the aggressor detector circuit 310 may implement Figure 2 The aggressor detector circuit 217. Figure 3 In an embodiment, the candidate register (e.g., Figure 2 244) is divided into two registers 313 and 315, each of which stores a single address (e.g., having a depth of 1). In other example embodiments, other depths of one or both of registers 313 and / or 315 may be used. Each of registers 313 and 315 has register management circuitry (e.g., Figure 2 The two registers may be used to store candidate addresses for two different types of target refresh operations (eg, for refreshing + / - 1 victim or + / - 2 victims). Figure 3 Also shown in FIG. 3 is a counter circuit 302 (eg, Figure 2 246) and bank logic 304, which represents various other components of the refresh control circuit (e.g., Figure 2 The refresh state control unit 242, the DRAM interface 240, the refresh address generator 250 and / or Figure 2 row decoder 208).

[0055] Each of the registers 313 and 315 has a single slot that stores a single address and its associated count value. The registers may include a number of content addressable memory (CAM) cells that allow the input to be compared to the stored values. The register management circuits 312 and 314 may each read the stored address CAM_Adr and the stored count CAM_CNT from their respective registers 313 and 315, and also write the address Worst_Adr and count Worst_CNT to their respective registers.

[0056] During an access operation, the bank logic 304 provides the row address XADD along with the activation signal ACT to the memory array, e.g. Figure 1 118 and / or Figure 2 218( Figure 3 In response to signal ACT, the word line associated with the value of XADD is activated and stored in the counter memory cell (e.g., Figure 1 126 and / or Figure 2 The bits in 226 of 226 are read out to the counter circuit 302. The counter circuit 302 updates the count value (eg, by incrementing the count value) and provides the updated count value XCount′ to the aggressor detector circuit 310.

[0057] The two parts of the register management circuit 312 and 314 receive the row address XADD from the row address bus and the updated count value XCount' from the counter. The count goes to the first register management part 312 as RH1 CNT and to the second register management part 314 as RH2 CNT. The register management part 312 compares the count RH1 CNT with the stored CAM_CNT from the first register slot 312, and the register management part 314 compares the count RH2 CNT with the stored CAM_CNT from the second register slot 315. If the count value RH1CNT is greater than the value CAM_CNT read from the register 313, the register management circuit 312 provides XADD and RH1 CNT as Worst_Adr and Worst_CNT to overwrite the value stored in the register 313. Similarly, if the count value RH2 CNT is greater than the value CAM_CNT read from the register 315 , the register management circuit 314 provides XADD and RH2 CNT as Worst_Adr and Worst_CNT to overwrite the value stored in the register 315 .

[0058] During a refresh operation, a first type or a second type of targeted refresh operation may be invoked. The first type of targeted refresh operation may refresh a word line having a first relationship to an identified aggressor, while the second type of targeted refresh operation may refresh a word line having a second relationship to an identified aggressor. For example, the first type of targeted refresh operation may refresh a word line adjacent to the aggressor (e.g., + / -1), while the second type of targeted refresh operation may refresh a word line further away (e.g., + / -2). When the memory bank logic 304 invokes the first type of targeted refresh operation, the first refresh management portion 312 and register 313 may be used. When the memory bank logic invokes the second type of targeted refresh operation, the second refresh management portion 314 and register 315 may be used.

[0059] The memory bank logic 304 may call different types of target refresh operations based on internal logic. For example, every Nth time a first type of target refresh operation is performed, a second type of target refresh operation may be performed as the next target refresh operation. Depending on which type of target refresh operation is called, the row hammer mitigation logic circuit 318 may use different logic to generate the refresh address RXADD.

[0060] Figure 4 4 is a timing diagram of a refresh operation in a memory according to some embodiments of the present disclosure. In some embodiments, the timing diagram 400 may be provided by one or more of the devices and systems discussed herein (e.g., Figure 1 The memory device 100, Figure 2 200 and / or Figure 3 300) to implement. Figure 4 In the example embodiment of , a total of 10 example rows are shown, and the aggressor threshold is set to 200. However, for the sake of explanation, these are example values, and other values ​​may be used in other example embodiments.

[0061] The timing diagram shows three 'rounds' 410 to 430 of commands, each of which ends with a refresh command REF. The top row of each round shows a portion of an example command sequence that may be sent as part of the round, such as a row activation command ACT, a precharge command PRE, and a write command WRT and a read command READ and refresh commands REF and RFM. Each round 410 to 430 also shows a table representing a set of row addresses and their associated count values ​​at the end of that round when a refresh command is received. Each round also shows a set of refresh pumps (e.g., activation of IREF and / or RHR) generated in response to a refresh signal or RFM command and how these pumps may be used.

[0062] At the end of the first round 410, the row address with the highest access count is Row_8 with a count of 186. However, this is below the aggressor threshold. Therefore, a set of pumps is generated in response to the refresh signal REF, the first of which is used for the sequential refresh operation, but the last three of which are skipped.

[0063] At the end of the second round 420, the row with the highest count is now Row_2 with a count of 203. Since this is above the value of the threshold, in response to the refresh signal REF, after executing the sequential refresh pumps, three target refresh pumps are executed. The first pump is used to access the aggressor address (Row_2) and read out and reset its count value. In this example, the count value is reset to an initial value of 0. The next two pumps are used to refresh the victim address based on the address of Row_2. In this case, the victim address is an adjacent row, so Row_1 and Row_3 will be refreshed.

[0064] At the end of the third round 430, both row counts of Row_1 and Row_4 exceed the threshold. However, since the count of Row_4 is higher than the count of Row_1, as part of this refresh operation, the victim of Row_4 will be refreshed, but the victim of Row_1 will not be refreshed. At the end of the third round 430, the refresh management signal RFM is received, so only the targeted refresh operation is performed. Three pumps are executed, one pump is executed to reset the count value of Row_4, and then two pumps are executed to refresh the adjacent rows (Row_3 and Row_5). Since the count of Row_4 has been reset, Row_1 is now the row with the highest count and will be reset as part of the next set of targeted refresh operations unless the count of another row exceeds it.

[0065] Figure 5is a flowchart of a method according to some embodiments of the present disclosure. In some embodiments, method 500 may be performed by one or more of the systems or devices described herein (e.g. Figures 1 to 3 100, 200 and / or 300).

[0066] The method 500 generally begins at block 510, which describes accessing a word line and updating a count value associated with the word line. The method 500 may include receiving a row address associated with a word line, such as along a C / A terminal, from a controller of a memory device. The method 500 may include activating the word line associated with the row address and updating the count value from a counter memory cell (e.g., Figure 1 126 and / or Figure 2 226) is read out to a counter circuit (e.g., Figure 2 246 and / or Figure 3 302 of ). The counter circuit may update the count value (eg, by incrementing the count value). The method 500 may include writing the updated count value back to the counter memory unit.

[0067] Block 510 may be followed by block 520, which depicts storing the row address associated with the word line and the updated value in a candidate register (eg, Figure 2 244 and / or Figure 3 The row address may represent a maximum value of a plurality of count values ​​stored in a bank of the memory array, each of the count values ​​being associated with one of a plurality of word lines in the bank. In some embodiments, method 500 may include storing a plurality of count values ​​representing a highest count value of a plurality of count values ​​in the bank.

[0068] Block 520 may include comparing the updated count value to the stored count value(s) in the candidate register. For example, register management circuitry (e.g., Figure 2 245 and / or Figure 3 If the updated count value is greater than the stored count value, the stored count value may be replaced with the updated count value, and the row address may overwrite the previously stored address in the slot where the count value is stored.

[0069] Block 520 may be followed by block 530, which describes comparing the stored updated count value to a threshold value in response to a target refresh signal. Method 500 may include generating a target refresh signal based on a refresh management command or a refresh signal. For example, a refresh state control circuit (e.g., Figure 2242) may generate one or more activations of a target refresh signal in response to an RFM command or in response to a number of activations of a sequential refresh signal (e.g., IREF) being generated. In some embodiments, method 500 may include receiving a refresh signal and performing a number of sequential refresh operations and generating a number of activations of the target refresh signal. Block 530 may include comparing, using register management circuitry, the highest count value stored in the candidate register with a threshold.

[0070] Block 530 may be followed by block 540, which depicts identifying the stored row address as an aggressor address if the stored updated count value exceeds a threshold. For example, method 500 may include identifying the address with the highest count value in the candidate register as an aggressor if the count value exceeds a threshold.

[0071] If the highest count value exceeds the threshold, block 540 may be followed by block 550, which describes refreshing one or more word lines as part of a targeted refresh operation if the stored row address is identified as an aggressor address. Method 500 may include generating a refresh address based on the identified aggressor address (e.g., using a refresh address generator such as Figure 2 250 and / or Figure 3 318). Method 500 may include performing a target refresh operation in response to a refresh address and a target refresh signal.

[0072] The method 500 may include resetting the count value in response to identifying the stored row address as an aggressor address. For example, the reset may include accessing a word line associated with the aggressor address, reading the count value from a counter memory cell along that word line to a counter circuit, changing the count value (e.g., to reset it to an initial value, such as 0), and writing the changed count value back to the counter memory cell. The reset may be performed in response to one of the activations of the target refresh signal.

[0073] If the highest count value does not exceed the threshold, then the target refresh operation may be skipped after block 540. For example, when none of the stored count values ​​exceed the threshold, then the target refresh operation is skipped. For example, if no aggressor address is identified, then the refresh address generator will not generate a refresh address in response to the target refresh signal.

[0074] In some embodiments, method 500 may include setting a value for a threshold. For example, method 500 may include setting a value for a threshold in a mode register (e.g., Figure 1 The threshold value is set in 130).

[0075] In some embodiments, method 500 may include if the updated count value is higher than the first register or the second register (eg, Figure 3313 or 315 of ), then the row address is stored in that register. Method 500 may include comparing the stored updated count value in the first register with a first threshold when a first type of target refresh operation is invoked (e.g., using a first type of target refresh signal), and comparing the stored updated count value in the second register with a second threshold when a second type of target refresh operation is invoked (e.g., using a second type of target refresh signal). The two thresholds may be the same or different. Method 500 may include refreshing one or more word lines based on the stored address in the first register as part of the first type of target refresh operation, or refreshing one or more word lines based on the stored address in the second register as part of the second type of target refresh operation.

[0076] Of course, it should be understood that any of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and / or processes according to the present systems, devices, and methods, or separated and / or executed in a separate device or device portion.

[0077] Finally, the above discussion is intended only to illustrate the present system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, although the present system has been described in particular detail with reference to exemplary embodiments, it should also be understood that one of ordinary skill in the art may devise numerous modifications and alternative embodiments without departing from the broader and intended spirit and scope of the present system as set forth in the appended claims. Therefore, the specification and drawings should be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. A device comprising: a memory array including a plurality of word lines each associated with one of a plurality of row addresses and one of a plurality of count values; an aggressor detector circuit configured to store a maximum of the plurality of count values ​​and the associated row address, wherein the aggressor detector circuit is configured to receive a target refresh signal and compare the maximum count value to a threshold, and wherein the aggressor detector circuit is configured to provide the associated row address as an aggressor address if the maximum count value exceeds the threshold; and A refresh address generator circuit is configured to provide a refresh address based on the aggressor address in response to the target refresh signal.

2. The apparatus of claim 1, wherein the refresh address generator circuit is configured to skip providing the refresh address in response to the target refresh signal if the aggressor detector circuit does not provide the aggressor address.

3. The apparatus of claim 1, wherein each of the plurality of word lines is configured to store an associated one of the plurality of count values ​​in a memory cell along the word line.

4. The apparatus of claim 1, further comprising a counter circuit configured to change one of the plurality of count values ​​in response to the associated one of the plurality of word lines being accessed.

5. The apparatus of claim 4, wherein the circuit is configured to reset a selected one of the plurality of count values ​​associated with the aggressor address.

6. The apparatus of claim 1, wherein the aggressor detector circuit comprises a candidate register configured to store a plurality of addresses each associated with a highest one of the plurality of count values.

7. The apparatus of claim 1, further comprising a mode register configured to store a threshold setting, wherein the threshold has a value based on the threshold setting.

8. A device comprising: a memory array comprising a plurality of word lines; a row decoder configured to access a selected one of the plurality of word lines based on a row address; a counter circuit configured to receive a count value from the selected one of the plurality of word lines and to update the count value; and an aggressor detector circuit configured to compare the updated count value with a stored count value and, if the updated count value exceeds the stored count value, store the row address and the count value, and to provide the stored row address as an aggressor address in response to a target refresh signal if the stored count value exceeds a threshold, Wherein the row decoder is configured to refresh at least one row based on the aggressor address in response to the target refresh signal as part of a target refresh operation.

9. The apparatus of claim 8, further comprising an address generator circuit configured to generate a refresh address based on the aggressor address and the target refresh signal, wherein the row decoder is configured to refresh the at least one row based on the refresh address in response to the target refresh signal.

10. The apparatus of claim 9, wherein the address generator circuit is configured to skip providing the refresh address if the aggressor detector circuit does not provide the aggressor address, and wherein the row decoder is configured to skip the target refresh operation if the address generator circuit skips providing the refresh address.

11. The apparatus of claim 8, further comprising a mode register, wherein a value of the threshold is based on a setting in the mode register.

12. The apparatus of claim 8, wherein the aggressor detector circuit comprises a candidate register configured to store the row address and the associated count value.

13. The apparatus of claim 12, further comprising register management circuitry configured to compare the updated count value to the stored count value in the candidate register.

14. The apparatus of claim 8, wherein the row decoder is configured to read out the count value in response to the aggressor address, and wherein the counter circuit is configured to reset the count value as part of the target refresh operation.

15. A method comprising: accessing a word line and updating a count value associated with the word line; If the updated count value is a maximum count value, storing a row address and the updated count value in a candidate register; comparing the stored updated count value to a threshold value in response to a target refresh signal; If the stored updated count value exceeds the threshold, identifying the stored row address as an aggressor address; and If the stored row address is identified as the aggressor address, one or more word lines are refreshed as part of a targeted refresh operation.

16. The method of claim 15, further comprising skipping the target refresh operation if the stored updated count value does not exceed the threshold. 17 . The method of claim 15 , further comprising generating the target refresh signal in response to a refresh management command or in response to a refresh signal.

18. The method of claim 15, further comprising: reading the count value from a counter memory cell of the word line in response to accessing the word line; Updating the count value using a counter circuit; and The updated count value is written to the counter memory unit.

19. The method according to claim 18, further comprising: reading the updated count value from the counter memory cell of the word line associated with the aggressor address in response to the target refresh signal; resetting the updated count value using the counter circuit; and The reset count value is written to the counter memory cell.

20. The method of claim 15, further comprising: comparing the updated count value to a stored count value in the candidate register; The stored count value is replaced with the updated count value and if the updated count value is greater, the stored row address is replaced with the row address.

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