Non-volatile memory-sram data transfer unit, heterogeneous integrated storage system and chip system

Abstract

The application provides a nonvolatile storage-SRAM data transfer unit, a heterogeneous integrated storage system and a chip system. The nonvolatile storage-SRAM data transfer unit comprises: M*N nonvolatile storage storage units arranged in a matrix form, an SRAM storage unit and a multiplexing unit between the M*N nonvolatile storage storage units arranged in the matrix form and the SRAM storage unit; the M*N nonvolatile storage storage units multiplex the SRAM storage unit through the multiplexing unit; wherein M and N are both positive integers.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit, and particularly relates to a non-volatile storage-SRAM data transfer unit, a heterogeneous integrated storage system and a chip system. BACKGROUND

[0002] Compared with the traditional transistor-based chip design, the non-volatile storage chip has shown advantages, for example, the MRAM (Magnetic Random Access Memory) using spin devices has a significant advantage in the field of non-volatile storage. The core component of the MRAM, the magnetic tunnel junction (MTJ), has a persistent magnetization state, which can maintain data even under power-off conditions, significantly reducing standby power consumption. At the same time, due to the rapid conversion of electronic spin state, the MRAM can achieve faster read and write speed than traditional storage media.

[0003] Another big advantage of spin devices is that the chip manufacturing process is simple. By utilizing the top metal layer, the back-end process flow is simplified, and it is compatible with the CMOS (Complementary Metal Oxide Semiconductor) process. In addition, the spin chip has good anti-erase performance and radiation resistance, which meets the storage needs of the embedded non-volatile computing platform under the advanced process node in the big data era.

[0004] In the traditional von Neumann architecture, the data transmission between the processor and the memory constitutes a "memory wall", causing a significant performance bottleneck. IMC (In-Memory Computing) effectively alleviates this problem by embedding computing logic inside the memory, greatly shortening the data access delay. More importantly, the energy loss in the data transmission process in the traditional von Neumann architecture is considerable, and the IMC strategy significantly improves energy efficiency by reducing unnecessary data movement. The in-memory computing of the non-volatile memory combines the data storage and data computing capabilities, and uses the high bandwidth of the memory itself to perform computing tasks, which is no longer limited by the transmission rate of the external data bus, thereby significantly enhancing the overall efficiency of the system. The close integration of computing and storage not only saves chip area, but also reduces the overall cost and design complexity of the system.

[0005] Although non-volatile storage has excellent performance in storage density, non-volatility, low power consumption and endurance, it faces certain limitations in in-memory computing. The main challenge comes from its inherent device characteristics, i.e., lower tunneling magnetoresistance ratio (TMR) and smaller magnetic resistance difference, which limit it to binary storage and lack the ability to store multiple values, making it difficult to perform multi-bit operation tasks. If non-volatile storage is to be used for accumulation operations, complex sampling and sensing techniques are required to interpret the results of the accumulation, which increases the difficulty of implementation and energy consumption. In addition, the read and write speed of non-volatile storage is relatively slow, and each read operation involves multiple steps, which cannot meet the requirements of in-memory computing architecture for high-speed data transmission.

[0006] In contrast, SRAM (Static Random-Access Memory) stores data through voltage states, has extremely fast read and write speeds, and is highly compatible with digital computing logic, making it suitable for in-memory computing architecture to achieve high-speed data processing.

[0007] In view of this, the hybrid storage architecture of non-volatile storage and SRAM has become an innovative direction in the field of in-memory computing. In this architecture, non-volatile storage takes advantage of its non-volatility and high-density storage to serve as a weight storage role, particularly suitable for storing neural network weight parameters, while SRAM, with its high performance and ease of collaboration with digital computing units, takes on the task of data caching and computing. This hybrid architecture not only achieves low standby power consumption, but also ensures high computing accuracy.

[0008] In summary, the in-memory computing architecture of non-volatile storage-SRAM hybrid storage combines the advantages of both storage technologies, and can solve the problem of low energy efficiency caused by frequent data movement in traditional computing architectures. SUMMARY

[0009] In view of this, the present application provides a data transfer circuit and an SRAM storage circuit for implementing a non-volatile storage-SRAM hybrid storage architecture.

[0010] In a first aspect, the embodiments of the present application provide a non-volatile storage-SRAM data transfer unit, which includes M*N non-volatile storage storage units arranged in a matrix form, an SRAM storage unit, and a multiplexing unit between the M*N non-volatile storage storage units arranged in a matrix form and the SRAM storage unit; the M*N non-volatile storage storage units multiplex the SRAM storage unit through the multiplexing unit; wherein M and N are both positive integers.

[0011] Optionally, the SRAM storage unit is implemented using MOS tubes, a first metal layer and a second metal layer of the MOS tubes are used to implement the SRAM storage unit, and a metal layer above the second metal layer is used to arrange a data bus.

[0012] Optionally, a protection ring is arranged around the non-volatile storage unit, the SRAM storage unit, and the multiplexing unit, and the protection ring is connected to a high-level power supply network of the data transfer unit.

[0013] Optionally, the non-volatile storage unit includes a magnetic tunnel junction and a MOS tube, and the magnetic tunnel junction is between upper metal layers of the MOS tube.

[0014] Optionally, the magnetic tunnel junction is between high-level metal layers of the MOS tube.

[0015] Optionally, wiring space between a word line, a bit line, and a source line of the non-volatile storage unit is used to arrange a customized bit.

[0016] Optionally, the multiplexing unit is used to select a column of the non-volatile storage unit to be connected to the SRAM storage unit.

[0017] Optionally, the non-volatile storage-SRAM data transfer unit is used in a storage circuit or a computing circuit.

[0018] In a second aspect, an embodiment of the present application provides a heterogeneous integrated storage system, the heterogeneous integrated storage system is composed of the non-volatile storage-SRAM data transfer units as described in the first aspect.

[0019] In a third aspect, an embodiment of the present application provides a chip system including the heterogeneous integrated storage system as described in the second aspect, the chip system is used to complete data transfer or in-memory computing included in the chip system according to the heterogeneous integrated storage system, and the heterogeneous integrated storage system is arranged on one side or two sides in the chip system.

[0020] The non-volatile storage-SRAM data transfer unit provided by the embodiment of the present application can complete a more complex layout design by fully utilizing existing wiring space and available metal layers. The SRAM part only uses two metal layers M1 and M2, and the high-level metal layers above the two metal layers can be used for data bus deployment, further improving the chip area utilization rate. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 FIG. 1 is a schematic diagram of a non-volatile storage-SRAM heterogeneous integrated system architecture provided by an embodiment of the present application;

[0022] Figure 2 is a schematic diagram of a non-volatile storage-SRAM heterogeneous integrated circuit structure provided by an embodiment of the present application;

[0023] Figure 3A is a top view schematic diagram of a non-volatile storage array physical structure provided by an embodiment of the present application;

[0024] Figure 3B is a side view schematic diagram of a non-volatile storage array physical structure provided by an embodiment of the present application;

[0025] Figure 4 is a top view schematic diagram of a non-volatile storage-SRAM data transfer unit structure provided by an embodiment of the present application;

[0026] Figure 5A is a schematic diagram of a chip architecture provided by an embodiment of the present application;

[0027] Figure 5B is a schematic diagram of another chip architecture provided by an embodiment of the present application. DETAILED DESCRIPTION

[0028] The development of computing in memory (CIM) not only subverts the traditional computing architecture, but also promotes the progress of processors, computing architectures and computing modes. Computing in memory solves the problem of power consumption and speed caused by the separation of storage and computing in the von Neumann architecture, and realizes the design concept of integrating storage and computing. By shortening the distance between the computing unit and the memory, the computing in memory method enables the memory to have computing capability, thereby solving the problem of low energy efficiency caused by frequent data movement in the traditional computing architecture.

[0029] Therefore, exploring the computing in memory implementation scheme of non-volatile storage, such as MRAM (Magnetic Random Access Memory) or RRAM (Resistive Random-Access Memory) and SRAM (Static Random-Access Memory) hybrid storage, has become a feasible computing architecture. The hybrid storage aims to take advantage of the non-volatility and high-density storage of non-volatile storage to effectively store weights; at the same time, it utilizes the high performance of SRAM and its natural compatibility with digital computing units to complete data caching and computing processes. Through this combination, a computing in memory implementation method with low standby power consumption and high computing precision can be realized to provide a new computing system architecture.

[0030] Embodiments of the present application provide a heterogeneous integrated storage structure, which is shown in Figure 1 . Figure 1This is a schematic diagram of a heterogeneous integrated system architecture for non-volatile memory-SRAM provided in an embodiment of this application. Taking MRAM as an example, as... Figure 1 The MRAM-SRAM heterogeneous integrated system shown includes: an SRAM array 101, a multiplexing unit (MUX) 102, and an MRAM array 103. It should be noted that the non-volatile memory in this embodiment is described using MRAM as an example, but no specific limitations are imposed on non-volatile memory.

[0031] In this configuration, the MRAM array 103 stores the weight data, while the SRAM array 101 serves as an efficient cache mechanism, extracting the weight data and converting it into voltage signals to provide digital processing circuits for computation. Figure 1 As shown, the MRAM-SRAM heterogeneous integrated system architecture provided in this application embodiment may further include: Input and Output modules or Computing Module modules. If Figure 1 The illustrated embodiment includes Input and Output modules. Figure 1 The architecture shown can be used for storage circuits, if Figure 1 The embodiment shown includes a computing module, then Figure 1 The architecture shown can be used as a memory computing circuit. Of course, Figure 1 The architecture shown can also be used as a storage and computing circuit. The embodiments of this application... Figure 1 The application of the architecture shown is not specifically limited. Considering that the size of the subarray is kept within a small range, the resulting voltage attenuation effect is significantly reduced. That is, digital signals from SRAM can be directly captured by the register group without going through redundant readout circuitry, thereby simplifying circuit design and reducing power consumption and latency.

[0032] The computing circuit design employs mature digital logic technology, with its layout adjacent to the SRAM. This allows for direct processing of operations between input and weighted data, enabling real-time data processing. This near-source computing method not only reduces data transmission distance and improves computational efficiency but also minimizes signal attenuation during long-distance transmission, ensuring the accuracy and stability of the computation results.

[0033] In summary, by tightly integrating computing modules with storage resources, especially through the heterogeneous integration of SRAM and MRAM, fast data access and efficient processing are achieved, which is beneficial for building a high-performance, low-power computing platform suitable for the era of big data.

[0034] In the field of storage technology, the design of traditional sense amplifiers, whether current-mode or voltage-mode, faces significant challenges. These amplifiers are typically complex in structure, occupy a large chip area, and are susceptible to manufacturing process variations, especially when the threshold voltages of MOS transistors in the differential pair do not match, which can lead to unstable performance. Additionally, the operation of sense amplifiers often involves multiple stages, which prolongs the read time and poses challenges to real-time performance and efficiency.

[0035] To address the above issues, an MRAM-SRAM hybrid circuit with a cross-coupled structure provides a simplified and efficient alternative, especially for small storage arrays, as described in Figure 2 . Figure 2 is a schematic diagram of a non-volatile storage-SRAM heterogeneous integrated circuit structure provided by an embodiment of the present application. As Figure 2 indicated, this design can directly implement data migration without the need for additional complex amplifier structures. By cascading or splicing multiple such small arrays, a large-scale storage array can be easily constructed while maintaining low power consumption and high read / write speed.

[0036] The following describes the circuit structure shown in Figure 2 in detail. As Figure 2 indicated, the circuit structure includes a cross-coupled data transfer circuit and an SRAM data transfer array, and the cross-coupled data transfer circuit includes a cross-coupled transistor and a 1T-1M storage array. The cross-coupled transistor includes a first transistor M1, a second transistor M2, and two control transistors. The gate of the first transistor M1 is connected to the first bit line (BL[X]) of the storage circuit; the gate of the second transistor M2 is connected to the second bit line (BL[B]) of the storage circuit; the first electrode of the first transistor M1 is connected to the first electrode of one control transistor; the first electrode of the second transistor M2 is connected to the first electrode of the other control transistor; the second electrode of the first transistor M1 and the second electrode of the second transistor M2 are respectively connected to ground; forming a cross-coupled transistor structure. The second electrodes of the two control transistors are respectively connected to the two source lines SL[X] and SLB of the storage circuit.

[0037] It should be noted that the first electrode of the transistor in the embodiment of the present application is one of the source (S) and the drain (D), and the second electrode of the transistor is the other corresponding electrode.

[0038] The following describes a 1T (transistor)-1M (magnetic tunnel junction) memory array in detail. Embodiments of the present application are described by way of example using a 1T-1M structure, but embodiments of the present application are not limited to the structure of the MRAM memory array. For example, the MRAM memory array can be a 2T-2M (two transistors-two magnetic tunnel junctions) structure. In the 1T-1M structure, one end of the magnetic tunnel junction (MTJ) is connected to the first electrode of the transistor, the gate (G) of the transistor is connected to the word line (exemplarily, WL[0] or WL[1]), the other end of the magnetic tunnel junction (MTJ) is connected to the bit line (exemplarily, BL[X]), and the second electrode of the transistor is connected to the source line (exemplarily, SL[X]).

[0039] Each MTJ can store one bit of data (0 or 1), depending on its magnetization direction. When reading or writing data is needed, the corresponding transistor is enabled by controlling the voltage of the word line (WL). When the transistor is turned on, a path is formed between the bit line (BL) and the MTJ, allowing current to pass through the MTJ. In the read operation, the resistance state of the MTJ is detected by measuring the current or voltage change on the bit line (BL), and the stored data bit is determined. In the write operation, the magnetization direction of the MTJ is changed by applying a specific current or voltage pulse to the bit line (BL) and / or the word line (WL), thereby achieving data writing.

[0040] Figure 2 In the illustrated embodiment, in the read operation, the bit line (BL) and its complementary line (BLB) are first pre-charged, then the enable signal (EN) is turned on, and the word line (WL) of the magnetic random access memory and the control signal (Ctr) are activated, prompting the storage unit to start the discharging process. At this stage, the voltages on the bit line and its complementary line gradually tend to a stable equilibrium state, reflecting the data information in the storage unit. Next, the word line (WL) of the SRAM is activated, and the enable signal (EN) is set to high level, triggering the latching action of the SRAM storage unit, locking the read data state, and completing the data reading and temporary storage. It is worth noting that the entire read process is designed to be extremely compact, and can be completed in as little as 3 nanoseconds (ns), which makes it highly applicable and efficient in various application scenarios of storage acceleration and in-memory computing acceleration cards

[0041] The following describes the SRAM data transfer array, such as Figure 2As shown, the 8T SRAM structure provided by the embodiment of the present application adds extra MOS transistors to the pull-up network and the pull-down network on the basis of the conventional 6-transistor SRAM. This makes it possible to cut off the strong feedback connection of the head-to-tail inverters during data transfer, thereby improving the stability and accuracy of data transfer. The read and write operations of the 8T SRAM are similar to those of the conventional 6-transistor SRAM, but the read and write speed can be slightly different due to the added extra transistors. When reading data, the data is read out from the memory cell (MRAM) through the access transistor; when writing data, the data is written into the memory cell (MRAM) through the access transistor. In addition, a pair of cross-coupled transistors is added to the MRAM memory array to assist the extraction of data from the MRAM to the SRAM. When it is necessary to extract data from the MRAM to the SRAM, the cross-coupled transistors are activated. By controlling the gate voltage of the cross-coupled transistors, the size of the channel current can be adjusted, thereby realizing the amplification and transmission of data. The data is transmitted from the memory cell of the MRAM to the input port of the SRAM through the cross-coupled transistors, and then written into the memory cell of the SRAM.

[0042] The design of the non-volatile storage-SRAM hybrid circuit simplifies the read process of the memory cell and reduces the area overhead, thereby improving the overall storage density. At the same time, since the use of the conventional sense amplifier is omitted, the stability and reliability of the circuit are improved, and the circuit performs more stably in the face of process variations. The storage architecture has faster read speed, smaller chip area, and better energy efficiency.

[0043] The non-volatile storage array in the embodiment of the present application is described in detail below, and reference is made to Figures 3A-3B . Figure 3A is a top view schematic diagram of the non-volatile storage array physical structure provided by the embodiment of the present application.

[0044] Figure 3B is a side view schematic diagram of the non-volatile storage array physical structure provided by the embodiment of the present application. As shown in Figure 3A and 3B As shown, the non-volatile storage array physical structure provided by the embodiment of the present application uses the compatibility of STT-MTJ (spin transfer torque magnetic tunnel junction) and CMOS process. In order to realize heterogeneous integration, the entire manufacturing process is divided into two stages: the front-end process focuses on the construction of the underlying CMOS circuit, and the back-end process is dedicated to the processing of STT-MTJ, ensuring seamless integration of the two. As shown in Figure 3BAs shown, the bottom layer CMOS circuit includes a silicon substrate, a Gate, a source and a Drain formed on the silicon substrate. The upper layer of the MOS tube includes metal layers (e.g., M1, M2, M3, M4, M5, M6) and vias (e.g., V1, V2, V3, V4, V5, V6) between the metal layers.

[0045] It is to be noted that M1, M2, M3, M4, M5 and M6 are respectively a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, a fifth metal layer and a sixth metal layer; and CT is a via between the first metal layer and the Gate, the source and the Drain of the CMOS. Figure 3B As shown, the MTJ is arranged between the sixth metal layer and the seventh metal layer. For example, Figure 3B As shown, a source line (SL) is arranged on the second metal layer, a word line (WL) is arranged on the third metal layer, and a bit line (BL) is arranged on the seventh metal layer. Here, the bit line of T2-M2 is taken as an example for illustration, but the present application is not limited thereto. Therefore, there is a rich wiring area between the word line (WL), the bit line (BL) and the source line (SL), which can be used to provide a customized bit design for the STT-MRAM.

[0046] It is to be noted that the word line (WL), the bit line (BL) and the source line (SL) can also be arranged on other metal layers, and the present application is not limited thereto.

[0047] Figure 3A is a top view of a physical structure of a non-volatile memory array. Figure 3A AA in is an active region of the MOS tube, and Via is a metal via, i.e. Figure 3B V1, V2, V3, V4, V5, V6 and CT in.

[0048] In view of the requirement of a large current for the write operation of the STT-MTJ, the access transistor is usually selected to have a large width-to-length ratio to ensure sufficient current supply. Therefore, the actual area of the non-volatile memory bit is determined by the physical size of the MOS tube and the necessary wiring channels.

[0049] In the design of very large scale integrated circuits, MTJ components are often placed between higher metal layers, such as the sixth metal layer (M6) and the seventh metal layer (M7), to make full use of the wiring capability of the high-level metal layer. Of course, MTJs can also be placed between other high-level metal layers, and the embodiments of the present application do not make specific limitations thereto. Such a layout not only optimizes the signal transmission path, but also provides space for customized bit design of STT-MRAM. In the non-volatile memory architecture, the rich wiring area between the word line (WL), the bit line (BL) and the source line (SL) creates conditions for the deep integration of high-performance computing and storage.

[0050] It should be noted that the WL, SL and BL in the embodiments of the present application are not limited to specific metal layers, but can be flexibly positioned at different levels of the circuit according to design requirements.

[0051] The following describes the non-volatile memory-SRAM data transfer unit in detail, which is described with reference to Figure 4 . Figure 4 is a structure diagram of a non-volatile memory-SRAM data transfer unit provided by the embodiments of the present application. As Figure 4 indicated, the non-volatile memory-SRAM data transfer unit includes M*N non-volatile memory storage units (MRAM ARRAY) arranged in a matrix form, a multiplexing unit (MUX) and an SRAM storage unit (SRAM ARRAY). The MRAM is implemented by the embodiment shown in FIG. 3, which will not be described again here. The SRAM storage unit is implemented by a MOS tube, and the SRAM storage unit only occupies the lowest two metal layers M1 and M2, while the higher metal layers can be used for the expansion of the data bus. Through the selection function of the MUX (multiplexing unit), the MRAM storage unit can be connected with the SRAM storage unit to form a bridge of data flow.

[0052] Due to the relatively large size of the SRAM storage unit, it can share space with multiple columns of non-volatile storage, thereby realizing efficient resource utilization. The number of SRAM modules directly depends on the bit width of single data reading, ensuring that the data throughput matches the system demand.

[0053] In the physical structure implementation, through the selection function of the MUX, the non-volatile memory array can be seamlessly connected with the SRAM unit to form a bridge of data flow. Thanks to sufficient wiring space and available metal layers, complex wiring design can be implemented, which makes the density of the overall physical implementation architecture limited by the spacing between the MTJ and the lower metal layer and the spacing of the wires between the metal layers.

[0054] It should be noted that the SRAM part only occupies the lowest two metal layers M1 and M2, and higher metal layers can be used for the expansion of the data bus, which effectively improves the overall utilization of the chip, further improves the utilization of the chip area, and realizes the optimization of space.

[0055] Figure 4 The M*N non-volatile storage array and the sharing mode of the single SRAM unit represent the basic unit for constructing a heterogeneous integrated storage and computing array. By reusing this basic unit, a larger storage / computing fusion architecture can be constructed. In order to avoid the latch-up effect, a guard ring must be provided around the non-volatile storage array, the MUX, and the SRAM array, which is connected to the high-level power network to ensure the stability and reliability of the circuit.

[0056] In actual deployment, specific process constraints also need to be considered, such as adjusting the wire width to prevent long-term reliability problems caused by electromigration and metal stress, such as metal fatigue or breakdown, which are key factors affecting the life of the circuit. Through fine engineering control, the performance and stability of the architecture under long-term operation can be ensured.

[0057] It should be noted that, Figure 4 The M*N non-volatile storage array and the sharing mode of the single SRAM unit represent the basic unit for constructing a heterogeneous integrated storage and computing array. By reusing this basic unit, a larger storage / computing fusion architecture can be constructed. In order to avoid the latch-up effect, a guard ring must be provided around the non-volatile storage array, the MUX, and the SRAM array, which is connected to the high-level power network to ensure the stability and reliability of the circuit.

[0058] It should be noted that the upper metal layer of the SRAM can be used for arranging the data bus, but the embodiments of the present application do not make specific limitations thereto, and even if the upper metal layer of the SRAM is not used for arranging the data bus deployment, it also needs to be protected.

[0059] In some embodiments, the heterogeneous integrated storage system provided by the embodiments of the present application can be used in a chip system, and the chip system is used to complete the data transfer or in-memory computing included in the chip system according to the above-mentioned heterogeneous integrated storage system. Referring to Figures 5A-5B . Figure 5A is a schematic diagram of a chip architecture provided by the embodiments of the present application, as Figure 5A The heterogeneous integrated storage system (bank) is arranged on one side in the chip system, that is, the data, signal or resource transmission is mainly carried out in one direction, that is, from one bank to another bank, instead of complex interaction in two directions. Figure 5B is a schematic diagram of another chip architecture provided by the embodiments of the present application, as Figure 5BAs shown, the heterogeneous integrated memory banks are arranged on both sides of the chip system, i.e., the banks are distributed on both sides of the chip system, and data, signals or resources are more complexly interacted and transmitted in two directions.

[0060] The integrated units described above, if implemented in the form of software function units and sold or used as independent products, can be stored in a computer readable storage medium. Based on such understanding, all or part of the processes in the above-mentioned embodiment methods can be instructed by a computer program to relevant hardware, and the computer program can be stored in a computer readable storage medium. When the computer program is executed by a processor, the steps of the above-mentioned various method embodiments can be implemented. The computer program includes computer program code, which can be in the form of source code, object code, executable files or some intermediate forms, etc. The computer readable storage medium at least includes any entity or device capable of carrying the computer program code to the photographing device / terminal equipment, recording medium, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal and software distribution medium. For example, U disk, mobile hard disk, magnetic disk or optical disk, etc. In some jurisdictions, according to legislation and patent practice, the computer readable medium cannot be an electrical carrier signal and a telecommunication signal.

[0061] In the above embodiments, the description of each embodiment has its own focus, and the parts not described or recorded in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0062] Those skilled in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0063] In the embodiments of the present application, it should be understood that the disclosed apparatuses / devices and methods can be implemented in other manners. For example, the described apparatus / device embodiments are merely schematic. For example, the division of the modules or units is merely logical function division. There can be another division manner for the actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between the units can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0064] It should be understood that the term "comprises" as used in the specification and the appended claims indicates the presence of the described features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0065] It should also be understood that the term "and / or" as used herein refers to any one of the associated listed items, combinations of one or more of the associated listed items, and all possible combinations thereof.

[0066] As used in the specification and the appended claims, the term "if" can be interpreted as meaning "when" or "once" or "in response to a determination" or "in response to detecting" depending on the context. Similarly, the phrase "if it is determined" or "if [a described condition or event] is detected" can be interpreted as meaning "once it is determined" or "in response to a determination" or "once [the described condition or event] is detected" or "in response to detecting [the described condition or event]" depending on the context.

[0067] In addition, in the description of the specification and the appended claims, the terms "first", "second", "third", and the like are used only to distinguish descriptions, and cannot be understood as indicating or implying relative importance.

[0068] In the present specification, the reference "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in some embodiments" or "in other embodiments" or "in still other embodiments" or the like in various places throughout the specification are not necessarily all referring to the same embodiment, unless otherwise specifically noted. The term "comprising", "containing", "having" and the like are meant to be open-ended terms that do not exclude additional, unrecited elements or options. Thus, such terms should be interpreted as specifying "includes but is not limited to".

[0069] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions recorded in the above embodiments can still be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A non-volatile memory-SRAM data transfer unit, characterized in that, The non-volatile memory-SRAM data transfer unit includes: M*N non-volatile memory cells, SRAM memory cells arranged in a matrix, and a multiplexing unit located between the M*N non-volatile memory cells arranged in a matrix and the SRAM memory cells; The M*N non-volatile memory storage units reuse the SRAM storage units through the multiplexing unit; Where M and N are both positive integers; The SRAM memory cell is implemented using a MOS transistor, wherein the first metal layer and the second metal layer of the MOS transistor are used to implement the SRAM memory cell. The metal layer above the second metal layer is used to arrange the data bus.

2. The non-volatile memory-SRAM data transfer unit according to claim 1, characterized in that, A protection ring is provided around the non-volatile memory storage unit, the SRAM storage unit, and the multiplexing unit, and the protection ring is connected to the upper-layer power network of the data transfer unit.

3. The non-volatile memory-SRAM data transfer unit according to claim 1, characterized in that, The non-volatile memory cell includes a magnetic tunnel junction and a MOS transistor, wherein the magnetic tunnel junction is located between the upper metal layers of the MOS transistor.

4. The non-volatile memory-SRAM data transfer unit according to claim 3, characterized in that, The magnetic tunnel junction is located between the higher metal layers of the MOS transistor.

5. The non-volatile memory-SRAM data transfer unit according to claim 3, characterized in that, The wiring space between the word lines, bit lines, and source lines of the non-volatile memory cell is used to arrange customized bits.

6. The non-volatile memory-SRAM data transfer unit according to claim 1, characterized in that, The multiplexing unit is used to select a column of non-volatile memory cells to connect to the SRAM memory cells.

7. The non-volatile memory-SRAM data transfer unit according to claim 1, characterized in that, The non-volatile memory-SRAM data transfer unit is used in circuits that store or compute or store and compute.

8. A heterogeneous integrated storage system, characterized in that, The heterogeneous integrated storage system is constructed by splicing together the non-volatile memory-SRAM data transfer unit as described in any one of claims 1-7.

9. A chip system, characterized in that, The system includes the heterogeneous integrated storage system as described in claim 8, wherein the chip system is used to complete data transfer or in-memory calculations included in the chip system according to the heterogeneous integrated storage system, wherein the heterogeneous integrated storage system is arranged on one side or both sides of the chip system.

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