Sensing circuit and method for semiconductor non-volatile memory

Abstract

The invention provides a sensing circuit and method for a semiconductor non-volatile memory. The sensing circuit is composed of a half latch, a switching element, a reset device, a PMOSFET (P-channel metal oxide semiconductor field effect transistor) device and an NMOSFET (N-channel metal oxide semiconductor field effect transistor) device. The semi-latch has a voltage signal input node and a digital voltage signal output node. The source of the PMOSFET device is connected to a digital voltage rail, and the drain is connected to a voltage signal input node. The drain of the NMOSFET element is connected to the gate of the PMOSFET element, the gate applies a bias voltage, and the source is connected to a bit line read path. The circuit is adjusted in conjunction with the threshold voltages of the PMOSFET device and the NMOSFET device to sense the threshold voltage of the NVM cell. By sensing the critical voltage state of the NVM cell, one-bit information stored in the NVM cell can be quickly determined.

Description

Technical Field

[0001] The present invention relates to an integrated circuit for reading stored information in a semiconductor non-volatile memory (NVM) device; in particular, multiple threshold voltages of a metal oxide semiconductor field effect transistor (MOSFET) device in a low power sense amplifier circuit are used to quickly determine the threshold voltage of a non-volatile memory cell device to obtain stored bit information. Background Art

[0002] Semiconductor non-volatile memory, especially electronically erasable programmable read-only memory (EEPROM), has shown wide applicability in a variety of electronic devices from computers to communication hardware to consumer appliances. Generally speaking, EEPROM occupies a place in the field of NVM as a mechanism for storing firmware and data, which can be retained even when power is off and can be modified as needed.

[0003] Data is stored in an EEPROM device by adjusting the threshold voltage (device ON / OFF voltage) by injecting charge carriers from the substrate of a metal oxide semiconductor field effect transistor device into a charge storage layer. For example, in the case of an n-channel MOSFET device, when electrons accumulate on the floating gate, dielectric layer, or nano-crystals above the FET channel region, the MOSFET device will have a relatively high threshold voltage state.

[0004] The digital information stored in the semiconductor NVM device is represented by multiple threshold voltage states of the semiconductor NVM device. For example, for a bit stored in a single semiconductor NVM cell device, the high threshold voltage state and the low threshold voltage state of the semiconductor NVM device represent the digital symbols "0" and "1", respectively. In order to read the digital information stored in the semiconductor NVM device, the sensing circuit is designed to sense the multiple threshold voltage states of the semiconductor NVM device. Figure 1The conventional current sensing architecture shown in the prior art is used to compare the responding current I generated by the semiconductor NVM device 140. rs With a reference current I ref , where the voltage V generated by the current source 111 g is applied to the gate of the semiconductor NVM device 140 to generate a response current I rs The voltage-current differential amplifier comparator 110 converts a current greater than the reference current I ref The response current I rs (representing a low threshold voltage state), and outputting a logic high voltage signal (V DD ) to represent the digital symbol "1", and the conversion is less than the reference current I ref The response current I rs (representing a high threshold voltage state), and outputting a logic ground voltage signal V at the output node out SS To represent the digital symbol "0". In this reading process, the memory unit 140 (I rs )、Current amplifier 120 (I am ), voltage-current differential amplifier comparator 110 (I dif ) and a reference current generating circuit 130 (I ref ) generates a large amount of stable direct current (DC). In the process of reading the bit information in the semiconductor NVM cell device, this large amount of stable DC current leads to high power consumption.

[0005] In order to eliminate the large amount of stable DC current in the NVM reading process during sensing and standby, the reading circuit and its operation method have been previously disclosed in the patent document of US Pat. No. 7,995,398. Figure 2 In the prior art reading circuit 200, a node 201 of a half latch is connected to a selected NVM device 202 through a conductive bit line path (including a bit line and a plurality of multiplexer selection transistors). By turning on the semiconductor NVM device 202 with a low threshold voltage, the voltage on the node 201 is increased from an initial precharge voltage (V R ) drops to the ground potential. During the sensing period, for the semiconductor NVM device that is turned off and has a high threshold voltage, since there is no discharge process, the voltage of the node 201 will remain close to the initial pre-charge voltage (V RDuring the discharge process of the semiconductor NVM device that is turned on and has a low threshold voltage, the falling voltage on the node 201 reaches a voltage flip level, causing the half latch to start flipping. The two read voltage signals (V R and ground voltage) are fed to the input of a voltage level-shifter latch to latch the complementary nodes 203D and 204D, respectively. Output two digital voltage signals: V DD and ground voltage (V SS ). In this circuit, the ability of the half latch to flip depends on the threshold voltage and current strength of the P / N MOSFET device, the read voltage V applied to the half latch, and the R , and the driving current intensity of the NVM device 202 with a low threshold voltage. Due to the positive feedback characteristics of the half latch, the driving current intensity of the semiconductor NVM device with a low threshold voltage always competes with the current intensity of the MOSFET device in the sensing circuit for flipping. For example, in a flip failure example, the driving current of the turned-on semiconductor NVM device is too small to compete with the PMOSFET (MP2) current, resulting in the voltage of the node 201 being clamped at a voltage higher than the latch flip voltage point. In this failure example, the large current of the sensing circuit flows through the P / NMOSFET path in series in the latch and consumes a lot of power.

[0006] In order to solve the aforementioned Figure 2 The failure example of the low power reading circuit 200 in FIG. Figure 3 The MOSFET threshold voltage sensing circuit (prior art) disclosed in U.S. Patent No. 10,147,492 (the contents of the above patent are hereby incorporated by reference as a part of the contents of this specification) is shown. The semiconductor NVM sensing circuit 300 includes a threshold voltage sensing circuit 310 (MP1 and MN1), a half latch 320, a voltage level shift latch 330 and a ground reset device MN2. In the threshold voltage sensing circuit 310, the gate 301 of the PMOSFET MP1 is connected to the precharge device MN1, and is connected to a bit line through a bit line multiplexer selection MOSFET device unit 360, and then connected to a selected NVM device 340, wherein Figure 3 Middle, B sel The source electrode and the drain electrode of MP1 are respectively connected to the bias node 304 (which is biased to the read voltage V R) and node 302 of half latch 320. Half latch 320 includes a PMOSFET device MP2 and an inverter composed of devices MP3 and MN3. The gates of devices MP2 and MP3 are cross-connected to nodes 302 and 303 to form half latch 320. The high voltage supply node of half latch 320 is connected to a read voltage bias (V R ). The gate of the ground reset device MN2 receives the signal from the node The digital voltage signal of the half latch 320 is received by the voltage level shift latch 330, and its source and drain are grounded and connected to the node 302, respectively. The input nodes 305 and 306 (gates of devices MN4 and MN5) of the voltage level shift latch 330 are connected to the output nodes 303 and 302 of the half latch 320, respectively. The gates of the two PMOSFET devices MP4 and MP5 are alternately connected to the output nodes 307 and 308 to form the voltage level shift latch 330.

[0007] In the read mode, a pre-charge circuit 350 is activated for a charging time T chg To charge a conductive bit line path (a selected bit line connected to the selected NVM device 340) to a voltage close to the read voltage V R When the node is "Complementary Sensing Enable" A digital low voltage signal V is applied SS When the gate charging device MN1 and the reset device MN2 are turned off, the conductive bit line path is then selected through a plurality of bit line multiplexers of the unit 360 (by activating one of the signals (B sel After the precharge circuit 350 is turned off, a wordline gate voltage V is applied to a selected wordline. WR to the gate of the selected NVM device, causing the connected bit line to discharge to ground voltage potential through the selected NVM device 340. During the bit line discharge process, for a bit line with a "low threshold voltage" (less than the applied word line gate voltage V WR ) of the selected NVM device 340, the voltage potential of the gate 301 of MP1 decreases faster than that of the selected NVM device 340 at the "high threshold voltage" (greater than the applied word line gate voltage V WR ) of the selected NVM devices 340 falls much faster. For those selected NVM devices 340 in the "low threshold voltage" state, the voltage potential at the MP1 gate 301 first reaches the MP1 "on" voltage (V R -V thp ), where Vthp is the threshold voltage of MP1. Then, the “on” current of MP1 is strong enough to flip the half latch 320 with the help of the positive feedback device MP2 to accelerate the half latch flipping process. The voltage signals at the output nodes 302 and 303 are fed to the input nodes of the voltage level shift latch 330 to flip the output nodes Q and Then, the digital voltage signal at the output node Q of the semiconductor NVM sensing circuit 300 is flipped to a high voltage signal (V DD ), indicating a digital symbol "1". At the same time, during the sensing period, for the selected NVM device in the "high threshold voltage" state, the voltage potential at the MP1 gate 301 hardly reaches the threshold voltage of MP1 to turn on MP1, so the digital voltage signal at the output node Q of the semiconductor NVM sensing circuit 300 is maintained at its preset voltage signal V SS , representing the digital symbol "0".

[0008] After the sensing period, the node A digital high voltage signal (V DD ), the pre-charging device MN1 and the reset device MN2 are turned on to restore the voltage potential of the node 301 to the read voltage V R , and restore the voltage potential of node 302 to the ground voltage V SS During the sensing period, the bit line is discharged to read the voltage V R Drops below MP1 critical voltage V thp The time during which the bit line is charged by the precharge circuit 350 from a falling voltage back to the read voltage V R The time required to sense a small MP1 gate capacitance (approximately less than fF (10 -15 Farad)) and a large bit line capacitance (greater than hundreds of fF) form a large total capacitance (with a voltage potential difference (greater than V thp )) for discharging and charging. Summary of the invention

[0009] In order to solve the problems existing in the prior art, the present application provides a sensing circuit and a sensing method for a semiconductor non-volatile memory.

[0010] In one aspect, the present invention provides a sensing circuit for a semiconductor non-volatile memory for sensing a storage bit of a selected NVM cell of a semiconductor non-volatile memory NVM device, the sensing circuit comprising:

[0011] a half latch coupled between a digital voltage rail having a supply voltage and a ground voltage node and having a voltage signal input node and a digital voltage signal output node;

[0012] a PMOSFET device having a source electrode connected to the digital voltage rail and a drain electrode connected to the voltage signal input node;

[0013] a switch device, connected to the digital voltage rail, for selectively charging the gate electrode of the PMOSFET device according to a first control signal;

[0014] an NMOSFET device having a drain electrode connected to the switching device and the gate of the PMOSFET device, a gate electrode to which a bias voltage V is applied b , and a source electrode connected to a bit line read path coupled to the selected NVM cell; and

[0015] A reset transistor is connected between the voltage signal input node and the ground voltage node, and is used to selectively connect the voltage signal input node to the ground voltage node according to a second control signal.

[0016] In one aspect, the present invention provides a sensing method for sensing a storage bit of a selected NVM cell of a semiconductor non-volatile memory NVM device, the semiconductor NVM device comprising a sensing circuit, the sensing circuit comprising a PMOSFET device, an NMOSFET device, and a half latch, the half latch being coupled between a digital voltage rail having a supply voltage and a ground voltage node, and having a voltage signal input node and a digital voltage signal output node, wherein a drain electrode and a source electrode of the PMOSFET device are respectively connected to the voltage signal input node and the digital voltage rail, wherein a drain electrode of the NMOSFET device is connected to a gate electrode of the PMOSFET device, and a bias voltage V is applied to the gate electrode of the NMOSFET device b , the method comprising:

[0017] charging a bit line read path and a gate of the PMOSFET device to an initial voltage and the supply voltage, respectively;

[0018] Resetting the voltage signal input node to a ground voltage;

[0019] Stop charging and reset;

[0020] connecting the bit line read path to the selected NVM cell;

[0021] applying a gate voltage to a word line associated with the selected NVM cell;

[0022] selectively discharge the gate electrode of the PMOSFET device with the bit line read path based on the conductance state of the NMOSFET device and the selected NVM cell and the initial voltage; and

[0023] A voltage is obtained at the voltage signal input node according to the conductance state of the PMOSFET device.

[0024] According to the present invention, the circuit can be adjusted by coordinating the threshold voltages of the PMOSFET device and the NMOSFET device to sense the threshold voltage of the NVM cell. By sensing the threshold voltage state of the NVM cell, a bit of information stored in the NVM cell can be quickly determined. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The present invention will be more fully understood through the following detailed description and the accompanying drawings, which are for illustration purposes only and therefore should not be considered as limiting the present invention. Among them:

[0026] Figure 1 A schematic diagram showing a conventional sensing circuit for reading bit information stored in a semiconductor non-volatile memory cell device.

[0027] Figure 2 A schematic diagram showing a conventional sensing circuit for eliminating Figure 1 The DC current generated by the conventional sensing circuit is used to read the bit information stored in the semiconductor NVM device.

[0028] Figure 3 A schematic diagram showing a conventional sensing circuit for solving Figure 2 The sensing circuit of the semiconductor NVM device fails due to the small driving current.

[0029] Figure 4 According to the present invention, a schematic diagram of a sensing circuit is shown, which applies high sensitivity principles to the critical voltage points of MOSFET devices and semiconductor NVM devices to read bit information stored in the semiconductor NVM devices.

[0030] Figure 5 According to the present invention, display using Figure 4 1 is a timing waveform diagram of a voltage signal of a reading architecture of a sensing circuit.

[0031] Figure 6 FIG. 4 is a schematic diagram showing a sensing circuit 400 used in a 64Mb NOR flash memory array according to an embodiment of the present invention.

[0032] Figure 7 According to an embodiment of the present invention, the display Figure 6 Simulated voltage signal waveforms of the sensing circuit 400 used in a 64Mb NOR flash memory array.

[0033] Figure 8 According to an embodiment of the present invention, a distribution diagram of cell threshold voltages in a memory array obtained by applying the sensing circuit 400 is shown.

[0034] [Refer to Figure Number]

[0035] 110: Voltage-current differential amplifier comparator

[0036] 111: Current Source

[0037] 120: Current amplifier

[0038] 130: Reference current generating circuit

[0039] 140, 202, 340, 462: Semiconductor NVM device

[0040] 200: Reading circuit

[0041] 300, 400: semiconductor NVM sensing circuit

[0042] 201, 203, D, 204, 206, 302~309, 401~403, 405~406, 411~413, 421, 422, 431, Q, 432, 461: Node

[0043] 301: Gate of MP1

[0044] 310: Threshold voltage sensing circuit

[0045] 320, 420: Half latch

[0046] 330: Voltage Level Shift Latch

[0047] 350: Pre-charge circuit

[0048] 205, 341: Gate of NVM device

[0049] 360: Bit Line Multiplexer Select MOSFET Device Unit

[0050] 410: Sense amplifier unit

[0051] 430: Flip-flop buffer

[0052] 450: Bit line charging circuit

[0053] 460: Read path

[0054] 501, 502, 511, 512, 521, 522: curve

[0055] 601: Overall bit line

[0056] 610(i): Multiplexer switch

[0057] 620(i):NOR flash memory array sector

[0058] 621: A pair of NOR flash devices

[0059] 6211, 6212: shared source

[0060] 6212: horizontal common source line

[0061] 6213: Ground potential

[0062] MP1, 414, MP2~MP3, MP chg (417), MP4, MP5: PMOSFET device

[0063] MN1~MN5、415、MN C (416):NMOSFET device

[0064] V C : Clamping voltage potential

[0065] C gb , C lb :Capacitive load

[0066] CS(i): control signal

[0067] C b :Bit Line Capacitance

[0068] R b :Metal bit line resistance

[0069] R bsw : On-switch resistance DETAILED DESCRIPTION

[0070] The present invention includes methods and schematic diagrams for quickly reading stored bit information from non-volatile memory cell devices in a flash memory array. It will be immediately apparent to one of ordinary skill in the art that the embodiments of the present invention described in the context of the methods and schematic diagrams are merely illustrative and are not intended to be limiting in any way. Other embodiments of the present invention will readily occur to those of ordinary skill in the art who have the benefit of this disclosure.

[0071] In order to improve the sensing time of the semiconductor NVM device in the “on” state and reduce the charging time of the large total capacitive load, the present invention provides a sensing circuit 400 using a clamping NMOSFET device ( Figure 4 MN c 416) to separate the sensing node 411 from the reading node 412. With this configuration, the sensing node 411 (equivalent to the gate of MP1, with a small gate capacitance) is relatively DD The voltage potential change is increased to compensate for the larger capacitance of the read node 412 (with a relatively large bit line capacitance) relative to the read voltage V R A small change in voltage potential.

[0072] in particular, Figure 4 The sensing circuit 400 is used to sense the threshold voltage of the PMOSFET device (MP1 414) and clamp the NMOSFET device (MN c 416) to adjust the critical voltage. This can achieve extremely high circuit sensitivity.

[0073] In one aspect of the present invention, since the typical switching characteristics of MOSFET devices (including semiconductor NVM devices) are that in the sub-threshold region of the MOSFET before reaching its critical voltage point, the response current change of several orders of magnitude has a slope of about 60 millivolts to hundreds of millivolts per decade of current, the sensing circuit 400 of the present invention is extremely sensitive to the critical voltage point when the semiconductor NVM unit device is close to being turned on. According to one embodiment of the sensing circuit of the present invention, Figure 8 Displays 10 mV NVM threshold voltage resolution.

[0074] In one aspect of the present invention, the sensing circuit 400 of the present invention is adapted to the critical voltage point of the PMOSFET device 414 and the clamping NMOSFET device (MN c 416) is adjusted to the threshold voltage point, so the circuit output response time (i.e., the time from applying the gate voltage V WR to a word line to the bit information stored at the output node 431) in nanoseconds (10-9 The fast data access time of the bit information stored in the semiconductor NVM by the sensing circuit 400 is comparable to the data access time of dynamic random access memory (DRAM) and static random access memory (SRAM). The fast data access time of the semiconductor NVM can help the program code to be executed quickly directly from the program code storage memory (semiconductor NVM), thereby saving some hierarchical levels of other fast random access buffer memories provided by DRAM or SRAM to execute the program code.

[0075] In one aspect of the present invention, when the voltage potential (V R ) is less than Clamp Voltage V c =(V b -V thn ), the clamping NMOSFET device (MN c 416) will be turned on; when the voltage potential (V R ) is greater than Clamp Voltage V c =(V b -V thn ), the clamping NMOSFET device (MN c 416) will be turned off, where V b and V thn are the bias voltage applied to the gate of the clamping NMOSFET device (MNc 416) and the device MN c 416 critical voltage. About less than V DD The bias voltage V b , a voltage reference circuit can be used to obtain the high voltage power supply V of the memory chip DD To design and generate, as for the clamping NMOSFET device (MN c 416) critical voltage V thn It is provided by the process.

[0076] In one aspect of the present invention, since the threshold voltage of the MOSFET device is given after the manufacturing process, the sensing circuit of the present invention is insensitive to the variation of the voltage supply outside the chip.

[0077] In one aspect of the present invention, the sensing circuit of the present invention is non-differential. The offset caused by the mismatch of the devices in the sensing amplifier circuit becomes insignificant. Figure 4 and Figure 5 Specific instructions.

[0078] Figure 4 The schematic diagram of the sensing circuit 400 of the present invention is shown, which includes a sense amplifier unit 410, a half latch 420 and a flip-flop buffer 430. The sense amplifier unit 410 is used to amplify the NVM bit line analog signal. The sense amplifier unit 410 includes a charging PMOSFET (PFET) device (MP chg 417) and a clamping NMOSFET (NFET) (MN c 416), wherein the device (MP chg 417) charges the sensing node 411 and the read path 460 to an initial voltage potential (V DD ), device (MN c 416) has a clamping voltage potential V at the read node 412 c =(V b -V thn The sense amplifier unit 410 further includes a gate sense PMOSFET device MP1 414 and a ground reset MOSFET (NFET) device (MN3 415). The half latch 420 is used to capture the sense voltage signal on the output node 413 of the sense amplifier unit 410 at node 421 and convert it into a stable latched digital voltage signal (V DD or V SS The flip-flop buffer 430 stores the digital voltage signal on the digital signal output node 422 from the half latch 420 to output the digital voltage signal (V SS or V DD ), which respectively represent the data "0" and "1" of the high / low threshold voltage state of the semiconductor NVM device. Please note that all circuit units in the sensing circuit 400 (sense amplifier unit 410, half latch 420 and flip-flop buffer 430) are biased to a common digital high voltage potential (V DD In another embodiment, the flip-flop buffer 430 stores the digital voltage signal on the node 421 from the half latch 420 and outputs the digital voltage signal at the complementary output node. Outputs a complementary digital voltage signal (V DD or V SS ).

[0079] The read path 460 starts from the gate connection voltage sense node 411 (connected to the gate of the sensing PMOSFET device MP1 414) and extends to the clamping NMOSFET device MN c The drain of 416, whose source is the read node 412, is connected to the multiplexer bitline switches unit (such as Figure 6 The n×1 multiplexer switch 610(i) in FIG. 1 has an equivalent on-state switch resistance R bsw , and then connected to a small metal bit line resistor R b and a large bit line capacitor C b (greater than hundreds of fF). The small metal bit line resistance R b The voltage charging output node 461 of the bit line charging circuit 450 is connected to the read node 412. When a high voltage state (V DD ) to the node 406, the bit line charging circuit 450 is activated to charge the bit line to the read voltage V R After a period of charging time, read the voltage V R reaches a voltage potential equal to or greater than the clamping voltage V c =(V b -V thn ), after which the clamping NMOSFET device MN c 416 is turned off to prevent the voltage potential of the sensing node 411 from increasing from V DD Start discharging, where V thn is the threshold voltage of the clamped NMOSFET device (MNc 416). Conversely, if the read voltage V R Unable to reach the clamping voltage V c =(V b -V thn ), clamping NMOSFET device MN c 416 will always be in the on state, causing the “on” current to flow from the sensing node 411 to the reading node 412, causing the voltage potential of the sensing node 411 to drop, just like the semiconductor NVM device 462 is turned on. Therefore, the PMOSFET device MP1 will be turned on, and the node 413 has the supply voltage (V DD ).

[0080] Figure 5 show Figure 4 The reading timing waveform of the sensing circuit 400 is shown in FIG. Figure 5The first row of the read clock signal and the third row of the voltage signal ChgEnb are shown. When the bit line charging circuit 450 receives the rising edge of the read clock signal, it will be in a high voltage state (V DD ) is activated by the charging enable signal ChgEnb to charge the bit line for a period of time “T chg ”, so that the voltage potential of the read node 412 (as shown in the fifth row) reaches a maximum read voltage potential V Rmax , greater than or equal to a clamping voltage potential Vc=(V b -V thn During the bit line charging period, the SnEnb signal is de-activated because it is at ground voltage. The NMOSFET device MN3 415 and the PMOSFET device MP chg 417 is turned on, so that node 413 is grounded and sensing node 411 is charged to V DD After the bit line charging period, during the data latching period T lch , the bit line charging circuit 450 is disabled (by the ChgEnb signal being equal to the ground voltage), and by applying a high voltage (V DD ) level sensing enable signal SnEnb to node 401 to start the sensing circuit 400. During the sensing period, the charging PMOSFET device MP chg 417 is turned off, stopping charging the sensing node 411. thnvmL (lower than the applied gate voltage (V WR )) of the semiconductor NVM device, the selected NVM device 462 is turned on, and the voltage potential at the read node 412 (such as Figure 5 The solid line curve 502 in FIG. 1 is discharged to the ground potential. Regarding the discharge process of the read path 460 of those semiconductor NVM devices that are "on", the voltage potential at the read node 412 drops below the clamping voltage V c =(V b -V thn ), then, the clamping NMOSFET device MNc416 is turned on to conduct the read current I generated by the selected “on” NVM device 462 on , to discharge the voltage potential of the sensing node 411, such as Figure 5 When the potential V1 of the sensing node 411 drops to the threshold voltage V of the sensing PMOSFET device MP1 414, thp Below (that is, V1 is less than (V DD -V thp )), the half latch 420 starts to change the voltage signal of its output node 422 from V DD Flip to VSS Then, the voltage signal at the output node 422 of the half latch 420 is stored in the flip-flop buffer 430 to output Q at the node 431, which is the storage bit information of the data "1". Figure 5 The solid line curve 522 shown in FIG. 1 is associated with the high electrical conductance state of the selected NVM cell. thnvmH (higher than the applied gate voltage (V WR )) of the semiconductor NVM device, the selected semiconductor NVM device 462 is turned off to be disconnected from the ground potential. The voltage potential of the read node 412 remains unchanged, such as Figure 5 At the same time, after the bit line charging circuit 450 is charged, the initial maximum read potential V Rmax Greater than or equal to the clamping voltage Vc = (V b -V thn ), clamping NMOSFET device MN c 416 is in the off state to prevent the sensing node 411 from DD Discharge, such as Figure 5 The voltage signal at the output node 422 of the half latch 420 is maintained at V DD After that, the voltage signal V on the output node 422 of the half latch 420 DD is stored in the flip-flop buffer 430 to output Q (i.e., the voltage signal V SS ), which is the storage bit information of data “0”, such as Figure 5 The dashed curve 521 is shown. The above-mentioned storage bit information is associated with the low conductance state of the selected NVM cell.

[0081] Figure 6 A schematic diagram showing the application of the sensing architecture of the present invention to a NOR flash memory array. Figure 4 The sensing circuit 400 is connected to a line having a capacitive load C gbThe global bitline 601 is connected to p "n×m" NOR flash memory array sectors 620(i) and p "n×1" multiplexer switches 610(i), where i=0, 1, ..., (p-1). According to the control signal CS(i), the "n×1" multiplexer switch 610(i) connects the global bitline 601 to one of the n local metal bitlines. In the NOR flash array, the sensing circuit 400 is designed to sense p sectors multiplied by the (n×m) cell devices in each sector. The "n×m" NOR flash memory array sector 620(i) is configured with m word lines W0 to W1. m-1 (control gate of the NVM cell device) and n local metal bit lines, each local metal bit line having a local capacitive load C lb Each pair of NOR flash devices 621 includes two NVM cell devices having a common source electrode 6211. A row of common source electrodes 6211 are connected together to form a horizontal common source line 6212, which is connected to a ground potential 6213. In one embodiment of a 64Mb NOR flash memory array, the capacitive load of the word line is approximately 1.5pF (10 -12 Farads), the overall bit line capacitance load is about 800fF, and the local metal bit line capacitance load is about 150fF. c ) is designed to be 1.1V, clamping the NMOSFET device MN c The critical voltage of 416 is about 0.7V. Figure 7 The timing waveform diagram of analog voltage signals on the selected word line node "x", the charging enable (ChgEnb) node, the sensing enable (SnEnb) node, the global bit line node "y" and the four local metal bit line nodes "0", "1", "2" and "3" is shown for reading the bit information of the four selected NVM cell devices on the sensing circuit output node Q. The four selected NVM cell devices have a "high" threshold voltage (data "0"), a "low" threshold voltage (data "1"), a "high" threshold voltage (data "0") and a "low" threshold voltage (data "1") and are respectively connected to the local metal bit lines "0", "1", "2" and "3". Charging time T chg and sensing time T sn 35 nanoseconds and 5 nanoseconds respectively, and the word line gate voltage (V WR ) is equal to 3.7V.

[0082] Figure 8 According to an embodiment of the present invention, the sensing architecture and Figure 4The sensing circuit 400 is applied to the programmed / erased cell NVM threshold voltage distribution in a 1Mb NOR flash array. In the cell memory array, every sixteen cell devices are pre-programmed using the data type 55AAh, i.e. (0101 0101 1010 1010)b. It should be noted that the Q data "0" (output voltage signal V SS ) indicates that the semiconductor NVM cell device has a programmed (or high) threshold voltage, and the Q data is "1" (the output voltage signal is V DD ) indicates that the cell device has an erased (or low) threshold voltage. Therefore, when the data type 55AAh is programmed into the entire memory array, half of the cell devices in the memory array are programmed cell devices with a high threshold voltage, and the other half are erased cell devices with a low threshold voltage. Figure 4 The sensing architecture and sensing circuit 400 in FIG. WR ) from 2V to 6.5V (voltage step is 10mV) to scan the threshold voltage of the semiconductor NVM cell device in the memory array. In the above word line voltage scanning process, if the word line gate voltage V WR If the voltage is greater than the cell threshold voltage, the sensing circuit will output a voltage signal (V DD Then, the word line gate voltage V is obtained by the following formula: WR Cell critical voltage distribution: Read the output voltage (V DD ) of the units (V WR )-Read the output voltage (V DD ) of the units (V WR +ΔV), wherein the word line voltage increment ΔV=10mV. Figure 8 According to a data retention experiment, the initial threshold voltage distribution diagram of the programmed cell and the erased cell at room temperature is shown, as well as the threshold voltage distribution diagram of the programmed cell and the erased cell after baking at 250° C. for 336 hours.

[0083] The above description of the preferred embodiment of the present invention is for the purpose of illustration and explanation. It is not intended to be exhaustive or to limit the present invention to the precise form or exemplary embodiment disclosed. Therefore, the description should be regarded as illustrative rather than restrictive. Obviously, various modifications or variations of the non-volatile random access memory device are obvious to those familiar with the art, and the types of the above non-volatile random access memory devices include but are not limited to traditional MOSFET devices with floating gates, charge trap dielectrics or nanocrystals, and various semiconductor NVM memory array configurations such as NOR flash, NAND flash and EEPROM. The embodiment is selected and described in order to best explain the principles of the present invention and its best practical application, so that those skilled in the art can understand the various embodiments and modifications of the present invention and adapt it to a specific use or intended embodiment. The scope of the present invention is intended to be defined by the appended claims and their equivalents, in which all terms are interpreted in their broadest reasonable meaning unless otherwise stated. The abstract of the present disclosure is provided to comply with the rules requiring abstracts, which will allow searchers to quickly determine the subject matter of the technical disclosure of any patent issued from the present disclosure. The abstract submitted with this understanding will not be used to interpret or limit the scope or meaning of the claims. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the following claims. In addition, the elements and components in this disclosure are not dedicated to the public, regardless of whether the element or component is clearly stated in the following claims.

Claims

1. A sensing circuit for a semiconductor non-volatile memory, characterized in that: A method for sensing a storage bit of a selected NVM cell of a semiconductor non-volatile memory NVM device comprises: a half latch coupled between a digital voltage rail having a supply voltage and a ground voltage node and having a voltage signal input node and a digital voltage signal output node; a PMOSFET device having a source electrode connected to the digital voltage rail and a drain electrode connected to the voltage signal input node; a switch device, connected to the digital voltage rail, for selectively charging the gate electrode of the PMOSFET device according to a first control signal; an NMOSFET device having a drain electrode connected to the switching device and the gate of the PMOSFET device, a gate electrode to which a bias voltage V is applied b , and a source electrode connected to a bit line read path coupled to the selected NVM cell; and A reset transistor is connected between the voltage signal input node and the ground voltage node, and is used to selectively connect the voltage signal input node to the ground voltage node according to a second control signal.

2. The circuit according to claim 1, characterized in that Also includes: A flip-flop buffer is coupled to the digital voltage signal output node, and is used for storing a digital voltage signal on the digital voltage signal output node, and outputting the storage bit according to the digital voltage signal on the digital voltage signal output node.

3. The circuit according to claim 1, characterized in that The storage bit is associated with a conductance state of the selected NVM cell.

4. The circuit according to claim 1, characterized in that The bit line read path is charged to an initial voltage but cannot reach (V b -V thn ), the NMOSFET device and the PMOSFET device are turned on, causing the voltage signal input node to have the supply voltage.

5. The circuit according to claim 1, characterized in that After the bit line read path is charged to an initial voltage greater than or equal to (V b -V thn ) and V thn represents the threshold voltage of the NMOSFET device.

6. The circuit according to claim 5, characterized in that If the selected NVM cell is turned on and is in a high conductance state, a voltage V R will drop, otherwise the voltage V R Remain unchanged.

7. The circuit according to claim 5, characterized in that When a voltage V R drops below (V b -V thn ), the NMOSFET device is turned on, otherwise the NMOSFET device is turned off and is in a low conductance state.

8. The circuit according to claim 7, characterized in that After the gate of the PMOSFET device is charged to the supply voltage, the voltage signal input node is reset by the reset transistor, and the NMOSFET device is turned on, when a voltage V1 on the gate of the PMOSFET device drops below (V DD -V thp ), the PMOSFET device is turned on so that the voltage signal input node has the supply voltage, otherwise the PMOSFET device is turned off and the voltage signal input node is maintained at a ground voltage, wherein V thp represents the threshold voltage of the PMOSFET device and V DD represents the supply voltage.

9. A sensing method, characterized in that: A storage bit of a selected NVM cell of a semiconductor non-volatile memory NVM device, the semiconductor non-volatile memory NVM device comprising a sensing circuit, the sensing circuit comprising a PMOSFET device, an NMOSFET device and a half latch, the half latch being coupled between a digital voltage rail having a supply voltage and a ground voltage node, and having a voltage signal input node and a digital voltage signal output node, wherein the drain electrode and the source electrode of the PMOSFET device are respectively connected to the voltage signal input node and the digital voltage rail, wherein the drain electrode of the NMOSFET device is connected to the gate electrode of the PMOSFET device, and the gate electrode of the NMOSFET device is applied with a bias voltage V b , the method comprising: charging a bit line read path and a gate of the PMOSFET device to an initial voltage and the supply voltage, respectively; Resetting the voltage signal input node to a ground voltage; Stop charging and reset; connecting the bit line read path to the selected NVM cell; applying a gate voltage to a word line associated with the selected NVM cell; selectively discharge the gate electrode of the PMOSFET device with the bit line read path based on the conductance state of the NMOSFET device and the selected NVM cell and the initial voltage; and A voltage is obtained at the voltage signal input node according to the conductance state of the PMOSFET device.

10. The method according to claim 9, characterized in that The selective discharging step comprises: If the initial voltage cannot reach (V b -V thn ), causing the NMOSFET device and the PMOSFET device to be turned on, so that the voltage signal input node has the supply voltage, wherein V thn represents a threshold voltage of the NMOSFET device.

11. The method according to claim 9, characterized in that The step of selectively discharging comprises: If the initial voltage is greater than or equal to (V b -V thn ), selectively discharging the selected NVM cell with the bit line read path according to the conductance state of the selected NVM cell, and, The gate electrode of the PMOSFET device is selectively discharged based on the conductance states of the NMOSFET device and the selected NVM cell.

12. The method according to claim 11, characterized in that The step of selectively discharging the bit line read path comprises: If the selected NVM cell is turned on, causing the bit line read path to discharge, otherwise causing the bit line read path to maintain the initial voltage; and When the voltage on the bit line read path drops below (V b -V thn ), the NMOSFET device is turned on, otherwise the NMOSFET device is turned off.

13. The method according to claim 12, characterized in that The step of selectively discharging the gate electrode of the PMOSFET device comprises: causing the gate electrode of the PMOSFET device to discharge from the supply voltage when the selected NVM cell and the NMOSFET device are turned on; and When the voltage on the gate electrode of the PMOSFET device drops below (V DD -V thp ), the PMOSFET device is turned on so that the voltage signal input node has the supply voltage; otherwise, the PMOSFET device is turned off and the voltage signal input node maintains the ground voltage, wherein V thp represents the threshold voltage of the PMOSFET device and V DD represents the supply voltage.

14. The method according to claim 9, characterized in that Also includes: generating a digital voltage signal at the digital voltage signal output node using the half latch according to the voltage of the voltage signal input node; as well as The storage bit is output according to the digital voltage signal on the digital voltage signal output node.

15. The method according to claim 14, characterized in that The response time from the step of applying the gate voltage to the step of outputting the storage bit is in the range of a few nanoseconds.

16. The method according to claim 9, characterized in that The storage bit is associated with the conductance state of the selected NVM cell.

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