Semiconductor device

Abstract

The invention relates to a semiconductor device. The semiconductor device includes a memory cell array and a peripheral circuit. The memory cell array is coupled to the plurality of word lines and the plurality of bit lines. The peripheral circuit performs a deep erase verify operation by applying a second negative reference voltage lower than the first negative reference voltage to the target memory cell to determine whether the target memory cell has a threshold voltage lower than the first negative reference voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0110004 filed on August 22, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety as if fully set forth herein. Technical Field

[0003] Various embodiments generally relate to a semiconductor device. Background Art

[0004] An electronic device includes many electronic components, and a computer system may include many electronic components including semiconductors. Among the semiconductor devices constituting the computer system, a host device such as a processor or a memory controller may communicate data with a memory device. The memory device may include a plurality of memory cells that store data through word lines and bit lines.

[0005] A memory cell may have a threshold voltage below 0 V in an erased state. However, a memory cell having a threshold voltage that is too low (ie, a deeply erased cell) may cause reliability issues. Therefore, an effective method of identifying deeply erased cells may be needed. Summary of the invention

[0006] In an embodiment, a semiconductor device may include a memory cell array and a peripheral circuit. The memory cell array may be configured to be coupled to a plurality of word lines and a plurality of bit lines. The peripheral circuit may be configured to perform a deep erase verification operation by applying a second negative reference voltage lower than a first negative reference voltage to a target memory cell to determine whether the target memory cell has a threshold voltage lower than the first negative reference voltage.

[0007] In an embodiment, a semiconductor device may include a memory cell array, a control circuit, a decoder, and a buffer circuit. The memory cell array may be configured to be connected to a plurality of word lines and a plurality of bit lines. The control circuit may be configured to control a deep erase verification operation, which is used to determine whether a target memory cell connected to a target word line has a deep erase cell with a threshold voltage lower than a first negative reference voltage. The decoder may be configured to apply a second negative reference voltage to the target word line in a deep erase verification operation under the control of the control circuit. The buffer circuit may be configured to determine the state of a bit line connected to the target memory cell in a deep erase verification operation under the control of the control circuit.

[0008] In an embodiment, a semiconductor device may include a memory cell and a peripheral circuit. The memory cell may be configured to be coupled to a plurality of word lines. The peripheral circuit may be configured to perform a deep erase verification operation on a target memory cell coupled to a target word line by applying a negative reference voltage to the target word line, applying the negative reference voltage to subsequent word lines of the target word line, and applying a pass voltage to the remaining word lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram showing a semiconductor device according to an embodiment.

[0010] Figure 2 is a block diagram illustrating a memory block according to an embodiment.

[0011] Figure 3 is a schematic diagram showing a buffer circuit according to an embodiment.

[0012] Figure 4 is a diagram showing a method according to an embodiment of the present invention. Figure 3 1 is a timing diagram of the operation of the buffer circuit in normal verification operation.

[0013] Figure 5A is a diagram illustrating a management operation of a deep erase unit according to an embodiment.

[0014] Figure 5B is a diagram illustrating a deep erase verification operation according to an embodiment.

[0015] Fig. 6A and Figure 6B is a diagram for illustrating a method of generating a right-shift effect according to an embodiment.

[0016] Figure 7 is a timing diagram illustrating a method for performing a deep erase verification operation according to an embodiment.

[0017] Figure 8 is a timing diagram illustrating a method for performing a deep erase verification operation according to an embodiment.

[0018] Fig. 9 is a timing diagram illustrating a method of performing a deep erase verification operation according to an embodiment. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0020] Figure 1 is a block diagram of a semiconductor device 100 according to an embodiment. Figure 1, the semiconductor device 100 may operate under the control of an external device 10 such as a controller. The semiconductor device 100 may send a signal CS to the external device 10 and receive a signal CS from the external device 10. The signal CS may include, for example, a command, an address, data, etc. In response to the signal CS sent from the external device 10, the semiconductor device 100 may perform various internal operations such as a programming operation, a reading operation, an erasing operation, etc.

[0021] The semiconductor device 100 may be a semiconductor memory device, which may be a NAND flash memory, a 3D NAND flash memory, a NOR flash memory, a resistance random access memory, a phase change memory, a magnetoresistive random access memory, a ferroelectric random access memory, or a spin transfer torque random access memory.

[0022] The semiconductor device 100 may include a cell region 110 and a peripheral circuit 120. The cell region 110 may include a plurality of memory blocks MB1 to MBk. A memory block may be a unit of measurement in which the semiconductor device 100 performs an erase operation (i.e., data stored in the memory block may be erased at the same time). Each of the memory blocks MB1 to MBk may be coupled to the peripheral circuit 120 via word lines WL1 to WLn and bit lines BL1 to BLm. Each of the memory blocks MB1 to MBk may include a memory cell array storing data. The memory cell array may include a plurality of memory cells coupled to the word lines WL1 to WLn and the bit lines BL1 to BLm.

[0023] The peripheral circuit 120 may perform an internal operation on the cell region 110 in response to a signal CS transmitted from the external device 10. In response to the signal CS, the peripheral circuit 120 may store data in the cell region 110 and read data from the cell region 110. The peripheral circuit 120 may include a control circuit 121, a buffer region 122, and a decoder 123. Each of the control circuit 121, the buffer region 122, and the decoder 123 may include hardware, software, firmware, or a combination thereof.

[0024] The control circuit 121 may control various operations of the semiconductor device 100 based on the signal CS received from the external device 10. For example, the control circuit 121 may generate a buffer region control signal BCS in response to the signal CS, and may control the buffer region 122 using the buffer region control signal BCS. The control circuit 121 may transmit data received from the external device 10 to the buffer region 122, and may output data received from the buffer region 122 to the external device 10. Further, the control circuit 121 may generate a decoder control signal DCS in response to the signal CS, and may control the decoder 123 using the decoder control signal DCS. The decoder control signal DCS may include, for example, various levels of operating voltages required in a programming operation, a read operation, and an erase operation (e.g., a programming voltage, a read voltage, an erase voltage, a reference voltage, etc.).

[0025] Although not shown, the control circuit 121 may include an interface configured to communicate with the external device 10 and a voltage generating circuit configured to generate various operating voltages.

[0026] The buffer area 122 may transmit and receive data to and from the cell area 110 and the control circuit 121. The buffer area 122 may receive data to be stored in the cell area 110 from the control circuit 121 and may store the data. The buffer area 122 may store data read from the cell area 110 until the data is output to the control circuit 121.

[0027] The buffer region 122 may be associated with each of the memory blocks MB1 to MBk through the bit lines BL1 to BLm. The buffer region 122 may include buffer circuits BF1 to BFm, each of which is connected to the bit lines BL1 to BLm. The buffer circuits BF1 to BFm may be associated with the memory cells through the bit lines BL1 to BLm. The buffer circuits BF1 to BFm may store data to be stored in the memory cells. The buffer circuits BF1 to BFm may store data read from the memory cells. The buffer circuits BF1 to BFm may transmit data to and from the control circuit 121. The buffer circuits BF1 to BFm may operate simultaneously in response to the buffer control signal BCS, so that the memory cells respectively connected to the bit lines BL1 to BLm may be accessed simultaneously.

[0028] Further, each of the buffer circuits BF1 to BFm can determine the state of the bit line (i.e., the voltage level of the bit line or the amount of current flowing in the bit line) that changes according to the state of the memory cell in a verification operation (i.e., a normal verification operation and a deep erase verification operation to be described later) for determining the state of the memory cell. For example, each of the buffer circuits BF1 to BFm can precharge the bit line at a first interval, stop precharging the bit line at a second interval so that the state of the bit line changes according to the state of the memory cell, and determine the state of the bit line at a third interval. Each of the buffer circuits BF1 to BFm can determine the state of the memory cell based on the state of the bit line. According to an embodiment, each of the buffer circuits BF1 to BFm may include: a precharge circuit configured to supply a voltage to precharge the bit line in response to a precharge signal; and a connection circuit configured to connect the bit line to the precharge circuit in response to the connection signal. The precharge signal and the connection signal may be sent from the control circuit 121 as a buffer control signal BCS.

[0029] The decoder 123 may be associated with each of the memory blocks MB1 to MBk via word lines WL1 to WLn. The decoder 123 may select one or more of the word lines WL1 to WLn coupled to memory cells to be programmed, read, or erased under the control of the control circuit 121, and may apply various operating voltages to the selected word lines.

[0030] The peripheral circuit 120 may apply a second negative reference voltage less than the first negative reference voltage to the target memory cell to perform a deep erase verification operation to determine whether the target memory cell is a deep erase cell having a threshold voltage lower than the first negative reference voltage. For example, when the first negative reference voltage is -3.5V, the second negative reference voltage may be -2.5V. In other words, the peripheral circuit 120 does not use the first negative reference voltage as an actual reference for determining the deep erase cell, but uses the second negative reference voltage to perform the deep erase verification operation, thereby alleviating the burden of the circuit generating a large negative voltage.

[0031] In order to perform a deep erase verification operation using a second negative reference voltage instead of a first negative reference voltage, the peripheral circuit 120 may be configured and operated according to various embodiments. Specifically, according to an embodiment, the peripheral circuit 120 may apply the second negative reference voltage to a target word line coupled to a target memory cell and a subsequent word line of the target word line in a programming sequence. And, when the peripheral circuit 120 applies the second negative reference voltage to the target word line and the subsequent word line, a pass voltage may be applied to the remaining word lines.

[0032] According to an embodiment, the peripheral circuit 120 may apply a connection signal to each of the buffer circuits BF1 to BFm in a deep erase verification operation. The connection signal may be generated at a voltage level lower than a voltage level at which the connection signal is generated in a normal verification operation. Each of the buffer circuits BF1 to BFm may precharge a bit line in response to the connection signal at a first interval of the normal verification operation, and the voltage level at which the bit line is precharged is lower than the voltage level at which the bit line is precharged at the first interval of the deep erase verification operation.

[0033] According to an embodiment, the second interval in the deep erase verification operation may be shorter than the second interval in the normal verification operation. The control circuit 121 may control the buffer circuits BF1 to BFm via the buffer control signal BCS so that the second interval in the deep erase verification operation is shorter than the second interval in the normal verification operation.

[0034] After performing the deep erase verification operation, the peripheral circuit 120 may perform a management operation, which may include an operation of applying a programming pulse to the deep erase unit. The peripheral circuit 120 may perform the management operation before performing a programming operation on a previous word line of a target word line associated with the target memory cell. The previous word line may be an adjacent word line of the target word line, which is located before the target word line in the programming order.

[0035] Figure 2 is a schematic diagram illustrating a memory block MB according to an embodiment. Figure 1 Each of the memory blocks MB1 to MBk in the Figure 2 The storage blocks MB in are configured similarly.

[0036] Reference Figure 2 , the memory block MB may include strings ST11 to ST1m, ST21 to ST2m. Each of the strings ST11 to ST1m, ST21 to ST2m may extend in a vertical direction (Z direction). Within the memory block MB, m strings may be arranged in a row direction (X direction). Figure 2 , two strings are shown to be arranged along the column direction (Y direction), but this is for illustrative purposes only, and three or more strings may be arranged along the column direction (Y direction).

[0037] Strings ST11 to ST1m, ST21 to ST2m may be configured identically. For example, string ST11 may include a source select transistor SST, memory cells MC1 to MCn, and a drain select transistor DST connected in series to each other between a source line SL and a bit line BL1. The source of the source select transistor SST may be connected to the source line SL, and the drain of the drain select transistor DST may be connected to the bit line BL1. Memory cells MC1 to MCn may be connected in series to each other between the source select transistor SST and the drain select transistor DST. According to an embodiment, a plurality of source select transistors may be connected in series between the source line SL and the memory cell MC1. According to an embodiment, a plurality of drain select transistors may be connected in series between the bit line BL1 and the memory cell MCn.

[0038] The source select transistors at the same position in the vertical direction may be organized as shown below. Specifically, the gates of the source select transistors arranged in the same row of the string may be connected to the same source select line. For example, the gates of the source select transistors in the first row of the strings ST11 to ST1m may be connected to the source select line SSL1. For example, the gates of the source select transistors in the second row of the strings ST21 to ST2m may be connected to the source select line SSL2.

[0039] In an embodiment, source select transistors of two or more rows of a string may be connected together to a single source select line. For example, source select transistors of the first and second rows of strings ST11 to ST1m, ST21 to ST2m may be connected together to one source select line, and source select transistors of the third and fourth rows of the string may be connected together to one source select line.

[0040] The drain selection transistors at the same position in the vertical direction can be configured as shown below. Specifically, the gates of the drain selection transistors arranged in the same row of the string can be connected to the same drain selection line. For example, the gates of the drain selection transistors in the first row of the strings ST11 to ST1m can be connected to the drain selection line DSL1. For example, the gates of the drain selection transistors in the second row of the strings ST21 to ST2m can be connected to the drain selection line DSL2.

[0041] Strings arranged in the same column may be connected to the same bit line. For example, strings ST11, ST21 in the first column may be connected to the bit line BL1. For example, strings ST1m, ST2m in the mth column may be connected to the bit line BLm.

[0042] Gates of memory cells located at the same position in the vertical direction may be coupled to the same word line. For example, memory cells in the same vertical position as the memory cell MC1 in the strings ST11 to ST1m and ST21 to ST2m may be coupled to the word line WL1.

[0043] Among the memory cells, the memory cells connected to the same word line in the same row may constitute a memory region MR11. For example, the memory cells connected to the word line WL1 in the first row may constitute a memory region MR11. For example, the memory cells connected to the word line WL1 in the second row may constitute a memory region MR12. For example, the memory cells connected to the word line WL2 in the first row may constitute a memory region MR21. Depending on the number of rows, each word line may be associated with a plurality of memory regions. The memory cells constituting a memory region may be accessed simultaneously.

[0044] According to an embodiment, the memory block MB may be further coupled to one or more dummy word lines in addition to the word lines WL1 to WLn. In this case, the memory block MB may further include dummy memory cells coupled to the dummy word lines.

[0045] Reference Figure 3 , in a verification operation, the buffer circuit BF may precharge the bit line BL and the sensing node SO, determine the state of the sensing node SO changed by the state of the bit line BL, and store a value corresponding to the determination result. The state of the bit line BL may be determined by the state of the target memory cell connected to the bit line BL. Therefore, the value stored according to the state of the sensing node SO may refer to the state of the bit line BL and the state of the target memory cell. The buffer circuit BF may operate in response to a buffer control signal BCS sent from the control circuit 121. The buffer control signal BCS may include a connection signal SS1, a sensing signal SS2, a first precharge signal PS1, a second precharge signal PS2, a discharge signal DCS, a set signal SET, a first reset signal RS1, and a second reset signal RS2.

[0046] The buffer circuit BF may include a connection circuit 210 , a precharge circuit 220 , a discharge circuit 230 , a storage circuit 240 , and a set circuit 250 .

[0047] The connection circuit 210 may be coupled between the bit line BL and the first intermediate node CN1. The connection circuit 210 may connect the bit line BL to the first intermediate node CN1 in response to an enable connection signal SS1. The connection circuit 210 may transfer the voltage supplied from the precharge circuit 220 to the bit line BL in response to the enable connection signal SS1 (logic high). The connection circuit 210 may disconnect the bit line BL from the first intermediate node CN1 in response to a disable connection signal SS1 (logic low). For example, the connection circuit 210 may include a first NMOS transistor N1. The first NMOS transistor N1 may connect the bit line BL to the first intermediate node CN1 in response to the enable connection signal SS1. The first NMOS transistor N1 may disconnect the bit line BL from the first intermediate node CN1 in response to the disable connection signal SS1.

[0048] The precharge circuit 220 may connect the first operating voltage node VOP1N to the first intermediate node CN1 in response to enabling the first precharge signal PS1 (logic high). The precharge circuit 220 may precharge the first intermediate node CN1 using the first operating voltage VOP1 in response to enabling the first precharge signal PS1. The precharge circuit 220 may disconnect the first operating voltage node VOP1N from the first intermediate node CN1 in response to disabling the first precharge signal PS1 (logic low). The precharge circuit 220 may connect the first operating voltage node VOP1N to the sensing node SO in response to the logic low value of the data node QS and enabling the second precharge signal PS2. The precharge circuit 220 may precharge the sensing node SO using the first operating voltage VOP1 in response to the logic low value of the data node QS and enabling the second precharge signal PS2. The precharge circuit 220 may connect the first intermediate node CN1 to the sensing node SO in response to enabling the sensing signal SS2. The precharge circuit 220 may disconnect the first intermediate node CN1 from the sensing node SO in response to the disable sensing signal SS2 .

[0049] For example, the precharge circuit 220 may include a second NMOS transistor N2, a first PMOS transistor P1, a second PMOS transistor P2, and a third NMOS transistor N3. The second NMOS transistor N2 may connect the first operating voltage node VOP1N to the first intermediate node CN1 in response to enabling the first precharge signal PS1 (logic high). The second NMOS transistor N2 may disconnect the first operating voltage node VOP1N from the first intermediate node CN1 in response to disabling the first precharge signal PS1 (logic low). The first PMOS transistor P1 may connect the first operating voltage node VOP1N to the second intermediate node CN2 in response to a logic low value of the data node QS. The first PMOS transistor P1 may disconnect the first operating voltage node VOP1N from the second intermediate node CN2 in response to a logic high value of the data node QS. The second PMOS transistor P2 may connect the second intermediate node CN2 to the sensing node SO in response to enabling the second precharge signal PS2 (logic low). The second PMOS transistor P2 may disconnect the second intermediate node CN2 from the sensing node SO in response to disabling the second precharge signal PS2 (logic high). The third NMOS transistor N3 may connect the first intermediate node CN1 to the sensing node SO in response to enabling the sensing signal SS2 (logic high). The third NMOS transistor N3 may disconnect the first intermediate node CN1 from the sensing node SO in response to disabling the sensing signal SS2 (logic low).

[0050] The discharge circuit 230 may be coupled between the sensing node SO and the second operating voltage node VOP2N. The second operating voltage node VOP2N may be a node to which the second operating voltage VOP2 is supplied. The second operating voltage VOP2 may be, for example, a ground voltage. The second operating voltage VOP2 may be an internal ground voltage generated by the control circuit 121 based on the ground voltage supplied from the controller 10. The discharge circuit 230 may connect the sensing node SO to the second operating voltage node VOP2N in response to a logic high value of the data node QS and an enable charging signal DCS. The discharge circuit 230 may discharge the sensing node SO in response to a logic high value of the data node QS and an enable charging signal DCS. For example, the discharge circuit 230 may include a fourth NMOS transistor N4 and a fifth NMOS transistor N5. The fourth NMOS transistor N4 may connect the sensing node SO to the third intermediate node CN3 in response to an enable discharge signal DCS (logic high). The fourth NMOS transistor N4 may disconnect the sensing node SO from the third intermediate node CN3 in response to a disable discharge signal DCS (logic low). The fifth NMOS transistor N5 may connect the third intermediate node CN3 to the second operating voltage node VOP2N in response to a logic high value of the data node QS. The fifth NMOS transistor N5 may disconnect the third intermediate node CN3 from the second operating voltage node VOP2N in response to a logic low value of the data node QS.

[0051] The storage circuit 240 may store a value corresponding to the voltage level of the sensing node SO. For example, the storage circuit 240 may include a first inverter IV1 and a second inverter IV2. Each of the first inverter IV1 and the second inverter IV2 may be coupled between the data node QS and the inverted data node QSN. The first inverter IV1 may receive an input value from the data node QS, and may output an inverted value of the input value to the inverted data node QSN. The second inverter IV2 may receive the value of the inverted data node QSN as an input, and may output an inverted value of the input value to the data node QS. The first inverter IV1 and the second inverter IV2 may be used as latches to maintain the values ​​of the data node QS and the inverted data node QSN.

[0052] The set circuit 250 can initialize the storage circuit 240 in response to the first reset signal RS1, the second reset signal RS2, the set signal SET and the voltage level of the sensing node SO, and can store a value corresponding to the voltage level of the sensing node SO in the storage circuit 240. When the voltage level of the sensing node SO is higher than a predetermined voltage, the set circuit 250 can be enabled. For example, the set circuit 250 may include a sixth NMOS transistor N6 to a ninth NMOS transistor N9. The sixth NMOS transistor N6 may be connected between the data node QS and the set node SN. The sixth NMOS transistor N6 may connect the data node QS to the set node SN in response to enabling the first reset signal RS1 (logic high). The sixth NMOS transistor N6 may disconnect the data node QS from the set node SN in response to disabling the first reset signal RS1 (logic low). The seventh NMOS transistor N7 may be connected between the set node SN and the second operating voltage node VOP2N. The seventh NMOS transistor N7 may connect the set node SN to the second operating voltage node VOP2N in response to enabling the second reset signal RS2 (logic high). The seventh NMOS transistor N7 may disconnect the set node SN from the second operating voltage node VOP2N in response to disabling the second reset signal RS2 (logic low). The eighth NMOS transistor N8 may be connected between the inverted data node QSN and the set node SN. The eighth NMOS transistor N8 may connect the inverted data node QSN to the set node SN in response to enabling the set signal SET (logic high). The eighth NMOS transistor N8 may disconnect the inverted data node QSN from the set node SN in response to disabling the set signal SET (logic low). The ninth NMOS transistor N9 may be connected between the set node SN and the second operating voltage node VOP2N. The ninth NMOS transistor N9 may connect the set node SN to the second operating voltage node VOP2N in response to the voltage level of the sensing node SO. When the voltage level of the sensing node SO is higher than a predetermined voltage, the ninth NMOS transistor N9 may connect the set node SN to the second operating voltage node VOP2N. When the voltage level of the sensing node SO is lower than a predetermined voltage, the ninth NMOS transistor N9 may disconnect the third node SN from the second operating voltage node VOP2N. The predetermined voltage may be a minimum voltage level of the sensing node SO at which the ninth NMOS transistor N9 may be turned on.

[0053] Therefore, the value of the data node QS may be determined according to whether the voltage level of the sensing node SO is higher or lower than a predetermined voltage. For example, when the voltage level of the sensing node SO is lower than a predetermined voltage, the data node QS may store a first value (or a logic low value), and when the voltage level of the sensing node SO is higher than a predetermined voltage, the data node QS may store a second value (or a logic high value).

[0054] Figure 4 is a diagram showing a method according to an embodiment of the present invention. Figure 3 FIG. 1 is a timing diagram of the operation of the buffer circuit BF in a normal verification operation.

[0055] Reference Figure 4 , a normal verification operation may be an operation of determining the state of a target memory cell by applying a reference voltage NRV to the target memory cell via a target word line WLS, that is, an operation of determining whether the target memory cell has a threshold voltage lower than the reference voltage NRV or a threshold voltage higher than the reference voltage NRV. When the reference voltage NRV is applied via the target word line WLS, the target memory cell may be turned on / off based on its threshold voltage. Specifically, the target memory cell may be turned on in response to its threshold voltage being lower than the reference voltage NRV, and may be turned off in response to its threshold voltage being higher than the reference voltage NRV. When the target memory cell is turned on and off, different voltages or currents may be induced in the bit line BL, and the buffer circuit BF may determine whether the threshold voltage of the target memory cell is lower than or higher than the reference voltage NRV by determining the state of the bit line BL.

[0056] The threshold voltage NRV may vary depending on which threshold voltage distribution of the target memory cell is to be determined. Figure 4 , NRV is shown as a positive voltage, but NRV may also be a negative voltage. During a normal verification operation, a reference voltage NRV may be applied to a target word line WLS, and a pass voltage PV may be applied to a remaining word line WLR. A normal verification operation may include a first time interval T1 to a third time interval T3.

[0057] The first interval T1 may be a precharge interval T1. In the precharge interval T1, the precharge circuit 220 may precharge the bit line BL, the first intermediate node CN1, and the sensing node SO under the control of the control circuit 121. Specifically, the first NMOS transistor N1 may be turned on in response to a connection signal SS1 that changes from a logic low level to a logic high level. The second NMOS transistor N2 may be turned on in response to a first precharge signal PS1 that changes from a logic low level to a logic high level. The third NMOS transistor N3 may be turned on in response to a sensing signal SS2 that changes from a logic low level to a logic high level. The first PMOS transistor P1 may be turned on in response to a logic low value of the reset data node QS. The second PMOS transistor P2 may be turned on in response to a second precharge signal PS2 that changes from a logic high level to a logic low level. According to an embodiment, the second precharge signal PS2 and the sensing signal SS2 may be enabled later than the first precharge signal PS1 and the connection signal SS1. The end point of the precharge interval T1 and the starting point of the second interval T2 may be defined by the disabled second precharge signal PS2.

[0058] The second interval T2 may be an evaluation interval T2. In the evaluation interval T2, the state of the bit line BL may change according to the state of the target memory cell connected to the bit line BL, and the voltage level of the sensing node SO may change according to the state of the bit line BL. Specifically, the second PMOS transistor P2 may be turned off in response to the second precharge signal PS2 that changes from a logic low level to a logic high level. Therefore, when the target memory cell connected to the bit line BL is turned on in response to the reference voltage NRV, the voltage level of the sensing node SO may drop when the current flows from the sensing node SO to the source line SL through the bit line BL. As shown in the figure, when the target memory cell connected to the bit line BL is turned off in response to the reference voltage NRV, the voltage level at the sensing node SO may be maintained without any current flowing through the bit line BL. The end point of the evaluation interval T2 and the starting point of the determination interval T3 may be defined by the disabled sensing signal SS2. On the other hand, the time of the evaluation interval T2, i.e., the evaluation time EVT1, may be the time from when the second precharge signal PS2 is deactivated to when the sensing signal SS2 is deactivated. The evaluation time EVT1 may be a time during which a voltage level of the sensing node SO changes according to a state of the bit line BL.

[0059] The third interval T3 may be a determination interval T3. In the determination interval T3, the third NMOS transistor N3 may be turned off in response to the sensing signal SS2 changing from a logic high level to a logic low level. In the determination interval T3, the sensing node SO may maintain the voltage level of the sensing node SO at the end of the evaluation interval T2. The storage circuit 240 may store a value corresponding to the voltage level of the sensing node SO. Specifically, depending on whether the voltage level of the sensing node SO is higher or lower than the predetermined voltage VREF, the value of the data node QS may be determined by turning on or off the ninth NMOS transistor N9. More specifically, when the voltage level of the sensing node SO is lower than the predetermined voltage VREF, the data node QS may store a first value (or, a logic low value), and based on the value of the data node QS, it may be determined that the target memory cell has a threshold voltage lower than the reference voltage NRV, i.e., is in a first state. Then, when the voltage level of the sensing node SO is higher than the predetermined voltage VREF, the data node QS may store a second value (or, a logic high value), and based on the value of the data node QS, the target memory cell may be determined to have a threshold voltage higher than the reference voltage NRV, i.e., to be in the second state.

[0060] Figure 5A is a diagram illustrating a management operation of a deep erase unit according to an embodiment.

[0061] Reference Figure 5A , memory cells in an erased state may form a threshold voltage distribution ES. The horizontal axis VTH may represent the threshold voltage of the memory cell, and the vertical axis # may represent the number of memory cells having the corresponding threshold voltage. A deep erase cell may be a memory cell in an erased state whose threshold voltage is significantly lower than the threshold voltage of other memory cells in an erased state. A deep erase cell may be a memory cell whose threshold voltage is lower than the first negative reference voltage RV1. A deep erase cell may occur for a variety of reasons.

[0062] The peripheral circuit 120 may determine the deep erase unit through the deep erase verification operation, and then may perform a management operation on the deep erase unit. The management operation may include increasing the threshold voltage of the deep erase unit. In order to increase the threshold voltage of the deep erase unit, a programming voltage may be applied to the deep erase unit. After performing the management operation, the threshold voltage distribution ES may be changed to the threshold voltage distribution MES.

[0063] On the other hand, the lower the first negative reference voltage RV1 for determining the deep erase cell becomes, the larger the circuit for generating the first negative reference voltage RV1 can be, resulting in more wasted area within the semiconductor device 100. However, if the deep erase cell is determined based on a level higher than the first negative reference voltage RV1, unnecessary program voltages may be applied to memory cells other than the deep erase cell in a management operation.

[0064] Figure 5B is a diagram illustrating a deep erase verification operation according to an embodiment. Figure 5B , the peripheral circuit 120 may determine a deep erase cell having a threshold voltage lower than the first negative reference voltage RV1 by using a second negative reference voltage RV2 which is smaller than the first negative reference voltage RV1 instead of the first negative reference voltage RV1.

[0065] Specifically, the peripheral circuit 120 can shift the threshold voltage distribution ES of the memory cell in the direction of increasing the threshold voltage (hereinafter, referred to as the right shift effect) to form the threshold voltage distribution SES. In other words, under the control of the peripheral circuit 120, the memory cells may appear to form the threshold voltage distribution SES, but in fact they form the threshold voltage distribution ES. Therefore, even when the second negative reference voltage RV2 is used, the deep erase cell of the threshold voltage distribution ES can be effectively determined.

[0066] More specifically, the peripheral circuit 120 may apply the second negative reference voltage RV2 to the target word line WLS associated with the target memory cell in the deep erase verification operation. When the peripheral circuit 120 determines that the threshold voltage of the target memory cell is lower than the second negative reference voltage RV2, the peripheral circuit 120 may determine that the target memory cell is actually a deep erase cell having a threshold voltage lower than the first negative reference voltage RV1. And when it is determined that the threshold voltage of the target memory cell is higher than the second negative reference voltage RV2, the peripheral circuit 120 may determine that the target memory cell is not a deep erase cell having a threshold voltage higher than the first negative reference voltage RV1.

[0067] Fig. 6A and Figure 6B is a diagram for illustrating a method of generating a right-shift effect according to an embodiment.

[0068] Reference Fig. 6A, the graph GF1 may represent the characteristics of the memory cell on the threshold voltage distribution ES. The graph GF1 may represent the amount of current (hereinafter referred to as cell current CI) flowing through the memory cell to the bit line for the gate voltage VG applied to the memory cell through the word line. The determination current RI corresponding to the first negative reference voltage RV1 in the graph GF1 may be a criterion for determining whether the threshold voltage of the memory cell is lower than or higher than the first negative reference voltage RV1. That is, when the first negative reference voltage RV1 is applied to the target word line, the memory cell having a cell current CI higher than the determination current RI among the memory cells may be determined to have a threshold voltage lower than the first negative reference voltage RV1, and the memory cell having a cell current CI lower than the determination current RI may be determined to have a threshold voltage higher than the gate voltage VG.

[0069] On the other hand, when the cell current CI decreases relative to the gate voltage VG, the curve GF1 may be changed to the curve GF2. In the curve graph GF2, the same determination current RI may correspond to the second negative reference voltage RV2, that is, when the cell current CI decreases, the state of the memory cell may be determined using the second negative reference voltage RV2 that is less than the first negative reference voltage RV1, which is the same as the result of determining the state of the memory cell using the first negative reference voltage RV1.

[0070] In summary, since the right shift effect occurs in the memory cell when the cell current CI of the memory cell decreases, the second negative reference voltage RV2 which is smaller than the first negative reference voltage RV1 may be used to determine the state of the memory cell.

[0071] Reference Figure 6B , the determination current RI may be increased, that is, from the first determination current RI1 to the second determination current RI2. In the graph GF1, the gate voltage VG corresponding to the first determination current RI1 may be the first negative reference voltage RV1, and the gate voltage VG corresponding to the second determination current RI2 may be the second negative reference voltage RV2. Therefore, even when the determination current RI increases, the memory cell may have a right shift effect, and the state of the memory cell may be determined using the second negative reference voltage RV2 which is less than the first negative reference voltage RV1.

[0072] On the other hand, since the determination current RI and the evaluation time EVT1 can be inversely proportional to each other according to the equation I=ΔQ / T (where Q is the amount of charge on the sensing node SO in the evaluation interval T2), increasing the determination current RI can represent reducing the evaluation time EVT1. Therefore, when the evaluation time EVT1 is reduced, the memory cell may experience a right shift effect.

[0073] Figure 7is a timing diagram illustrating a method of performing a deep erase verification operation according to an embodiment.

[0074] Reference Figure 7 , when a deep erase verification operation is performed on a target memory cell connected to a target word line WLS, the peripheral circuit 120 may apply a second negative reference voltage RV2 to the target word line WLS and a subsequent word line WLF of the target word line WLS. The subsequent word line WLF may be an adjacent word line of the target word line WLS, following the target word line in the programming sequence. For example, when the target word line is word line WL1, the subsequent word line may be word line WL2.

[0075] When the second negative reference voltage RV2 is applied to the memory cell connected to the subsequent word line WLF (i.e., the subsequent memory cell) through the subsequent word line WLF, the source voltage of the subsequent memory cell may be lower than the source voltage when the higher pass voltage PV is applied to the subsequent memory cell. Fig. 6A As described above, the cell current of the target memory cell coupled to the subsequent memory cell may decrease, and a right shift effect may occur. Therefore, the peripheral circuit 120 can use the second negative reference voltage RV2 instead of the first negative reference voltage RV1 to determine whether there is a deep erase cell having a threshold voltage lower than the first negative reference voltage RV1.

[0076] The peripheral circuit 120 may apply a pass voltage PV to the remaining word lines WLR while applying a second negative reference voltage RV2 to the target word line WLS and the subsequent word line WLF. The remaining word lines WLR may be word lines other than the target word line WLS and the subsequent word line WLF among all word lines WL1 to WLn coupled to the memory block. The pass voltage PV may be a high voltage capable of fully turning on the memory cell. Figure 7 The other signals shown in Figure 4 Control is performed similarly to that described.

[0077] Figure 8 is a timing diagram illustrating a method of performing a deep erase verification operation according to an embodiment.

[0078] Reference Figure 8 , the control circuit 121 may generate the connection signal SS1 at a voltage level V2 lower than the voltage level V1 generated in the normal verification operation in the deep erase verification operation. The buffer circuit BF may precharge the bit line BL to a voltage level lower than the voltage level at which the bit line BL is precharged in response to the connection signal SS1 at the voltage level V2 in the precharge interval T21 of the deep erase verification operation in response to the connection signal SS1 at the voltage level V2 in the precharge interval T21 of the normal verification operation.

[0079] Therefore, the cell current IC flowing through the target memory cell can be reduced, and a right shift effect can occur, as shown in FIG. Fig. 6A Therefore, the peripheral circuit 120 may use the second negative reference voltage RV2 instead of the first negative reference voltage RV1 to determine whether there is a deep erase cell having a threshold voltage lower than the first negative reference voltage RV1. Figure 8 The other signals shown in Figure 4 Control is performed similarly to that described. Figure 8 In the embodiment, the remaining word lines WLR may be word lines except the target word line WLS among all the word lines WL1 to WLn coupled to the memory block.

[0080] Fig. 9 is a timing diagram illustrating a method of performing a deep erase verification operation according to an embodiment.

[0081] Reference Fig. 9 , the control circuit 121 may set the evaluation time EVT2 of the deep erase verification operation to be shorter than the evaluation time EVT1 of the normal verification operation. For example, the control circuit 121 may set the time when the sense signal SS2 is disabled in the deep erase verification operation to be earlier than the time when the sense signal SS2 is disabled in the normal verification operation. Therefore, the voltage level of the sense node SO coupled to the target memory cell may drop less, and it may appear that a right shift effect has occurred relative to the target memory cell. In addition, as shown in FIG. Figure 6B As described above, since reducing the evaluation time EVT1 to the evaluation time EVT2 corresponds to increasing the first determination current RI1 to the second determination current RI2 , a right shift effect may occur.

[0082] Therefore, the peripheral circuit 120 may use the second negative reference voltage RV2 instead of the first negative reference voltage RV1 to determine whether there is a deep erase cell having a threshold voltage lower than the first negative reference voltage RV1. Figure 4 Control similarly to the one described Fig. 9 Other signals are shown in Fig. 9 In the embodiment, the remaining word lines WLR may be word lines except the target word line WLS among all the word lines WL1 to WLn coupled to the memory block.

[0083] The semiconductor device according to the embodiment may perform a deep erase verification operation using a negative reference voltage that is smaller than a negative reference voltage actually required.

[0084] Although specific embodiments have been described above, it will be understood by those skilled in the art that the described embodiments are merely examples. Therefore, the semiconductor device should not be limited according to the described embodiments. On the contrary, the semiconductor device described herein should only be limited according to the appended claims in combination with the above specific embodiments and drawings.

Claims

1. A semiconductor device comprising: a memory cell array coupled to a plurality of word lines and a plurality of bit lines; as well as The peripheral circuit performs a deep erase verification operation by applying a second negative reference voltage lower than a first negative reference voltage to a target memory cell to determine whether the target memory cell has a threshold voltage lower than the first negative reference voltage.

2. The semiconductor device according to claim 1, wherein The peripheral circuit applies the second negative reference voltage to a target word line coupled to the target memory cell and a subsequent word line of the target word line in the deep erase verification operation.

3. The semiconductor device according to claim 2, wherein: The peripheral circuit applies a pass voltage to the remaining word lines while applying the second negative reference voltage to the target word line and the subsequent word lines.

4. The semiconductor device according to claim 1, wherein The deep erase verification operation and the normal verification operation include a first interval, a second interval, and a third interval, and The peripheral circuit includes a buffer circuit that precharges a bit line associated with the target memory cell at the first interval, stops precharging the bit line at the second interval so that a state of the bit line changes based on a state of the target memory cell, and determines the state of the bit line at the third interval.

5. The semiconductor device according to claim 4, wherein: The peripheral circuit applies a connection signal to the buffer circuit in the deep erase verification operation, and The connection signal is generated at a voltage level lower than a voltage level generated in the normal verification operation.

6. The semiconductor device according to claim 5, wherein: The buffer circuit precharges the bit line to a voltage level lower than a voltage level at which the bit line is precharged in a first interval of the normal verification operation in response to a connection signal in a first interval of the deep erase verification operation.

7. The semiconductor device according to claim 5, wherein: The buffer circuit comprises: a precharge circuit that supplies a voltage to precharge the bit line; and A connection circuit connects the bit line to the precharge circuit in response to the connection signal.

8. The semiconductor device according to claim 4, wherein: The second interval in the deep erase verification operation is shorter than the second interval in the normal verification operation.

9. The semiconductor device according to claim 1, wherein: The peripheral circuit performs a management operation including an operation of applying a program pulse to the target memory cell after performing the deep erase verification operation.

10. The semiconductor device according to claim 9, wherein The peripheral circuit performs the management operation before performing a program operation on a previous word line of a target word line associated with the target memory cell.

11. A semiconductor device comprising: a memory cell array coupled to a plurality of word lines and a plurality of bit lines; a control circuit that controls a deep erase verification operation for determining whether a target memory cell coupled to a target word line is a deep erase cell having a threshold voltage lower than a first negative reference voltage; a decoder, under the control of the control circuit, applying a second negative reference voltage to the target word line in the deep erase verification operation; as well as A buffer circuit determines a state of a bit line coupled to the target memory cell in the deep erase verification operation under the control of the control circuit.

12. The semiconductor device according to claim 11, wherein The second negative reference voltage is less than the first negative reference voltage.

13. The semiconductor device according to claim 11, wherein Under the control of the control circuit, the decoder applies the second negative reference voltage to the subsequent word line and applies a pass voltage to the remaining word lines when applying the second negative reference voltage to the target word line and a subsequent word line of the target word line.

14. The semiconductor device according to claim 11, wherein Before determining the state of the bit line in the deep erase verification operation, the buffer circuit precharges the bit line to a voltage level lower than a voltage level at which the bit line is precharged in the normal verification operation under the control of the control circuit.

15. The semiconductor device according to claim 11, wherein The control circuit controls an evaluation interval in the deep erase verification operation, during which a state of the bit line changes according to a state of the target memory cell in response to the second negative reference voltage, to be shorter than an evaluation interval in the normal verification operation.

16. A semiconductor device comprising: A memory cell connected to a plurality of word lines; as well as The peripheral circuit performs a deep erase verification operation on a target memory cell coupled to the target word line by applying a negative reference voltage to the target word line, applying the negative reference voltage to subsequent word lines of the target word line, and applying a pass voltage to the remaining word lines.

17. The semiconductor device according to claim 16, wherein: The peripheral circuit determines, in the deep erase verification operation, that target memory cells having threshold voltages lower than an actual negative reference voltage are deep erase cells, and that target memory cells having threshold voltages higher than the actual negative reference voltage are not deep erase cells.

18. The semiconductor device according to claim 17, wherein: The negative reference voltage is smaller than the actual negative reference voltage.

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