Flexible address swap column redundancy

Abstract

The invention relates to flexible address swap column redundancy. A memory device includes a memory array including memory cells grouped into one or more address ranges. Control logic is coupled to the memory array and configured to detect one or more errors associated with one or more stored data items corresponding to a first address range of one or more address ranges. The control logic may determine that a number of the one or more stored data items exceeds a number of redundant memory locations of a first address space. Control logic may remap an association of a first memory address of at least one of the stored data items from a first address within the first address space to a second address in a second address range, wherein the second address range includes one or more available redundant memory locations.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to a flexible address swapping column redundancy scheme. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] According to one aspect of the present disclosure, a memory device is provided. The memory device includes: a memory array including a plurality of memory cells addressable by respective addresses grouped into one or more address ranges; and control logic operatively coupled to the memory array to perform operations including: detecting one or more errors associated with one or more stored data items corresponding to a first address range in the one or more address ranges; determining that the number of the one or more stored data items exceeds the number of available redundant memory locations for the first address range; and remapping an association of a first memory address of at least one of the stored data items from a first address in the first address range to a second address in a second address range in the one or more address ranges, wherein the second address range includes the one or more available redundant memory locations.

[0004] According to another aspect of the present disclosure, a method is provided. The method includes: detecting one or more errors associated with one or more stored data items corresponding to a first address range of one or more address ranges, wherein a memory cell is addressable by a corresponding address of the one or more address ranges; determining that the number of the one or more stored data items exceeds the number of available redundant memory locations of the first address range; and remapping an association of a first memory address of at least one of the stored data items from a first address in the first address range to a second address in a second address range of the one or more address ranges, wherein the second address range includes the one or more available redundant memory locations.

[0005] According to another aspect of the present disclosure, a memory device is provided. The memory device includes: a memory array including a plurality of memory cells addressable by respective addresses grouped into one or more address ranges; control logic operatively coupled to the memory array to perform operations including: receiving a memory address; detecting one or more errors associated with a memory address corresponding to a first address range in the one or more address ranges; determining that the number of the one or more errors fails to satisfy the number of redundant memory locations for the first address range; and remapping the association of the memory address from a first address in the first address range to a second address associated with a second address range, wherein the second address range includes one or more available redundant memory locations. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure. However, the drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0007] Figure 1A An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 1B is a block diagram of a memory device in communication with a memory subsystem controller of a memory subsystem according to some embodiments of the present disclosure.

[0009] Figure 2 is a system diagram of an example communication system using a flexible address swapping redundancy scheme according to some embodiments of the present disclosure.

[0010] Figure 3 is a system diagram of an example communication system using a flexible address swapping redundancy scheme according to some embodiments of the present disclosure.

[0011] Figure 4 A diagram illustrating a flexible address swap column redundancy scheme according to an embodiment of the present disclosure.

[0012] Figure 5 An example computing system 500 is illustrated that utilizes a flexible address swap column redundancy scheme according to some embodiments of the present disclosure.

[0013] Figure 6 Flowchart of an example method of a flexible address swapping redundancy scheme according to some embodiments of the present disclosure.

[0014] Figure 7 An example machine of computer system 700 is illustrated within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, may be executed. DETAILED DESCRIPTION

[0015] Various aspects of the present disclosure relate to a flexible address swap column redundancy scheme. The memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. Figure 1A Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as a memory device, that stores data. The host system may provide data for storage at the memory subsystem and may request retrieval of data from the memory subsystem.

[0016] The memory subsystem may include a high-density non-volatile memory device, where data needs to be retained when power is not supplied to the memory device. For example, NAND memory, such as 3D flash NAND memory, provides storage in a compact, high-density configuration. A non-volatile memory device is a package of one or more dies, each die including one or more planes. For some types of non-volatile memory devices (e.g., NAND memory), each plane includes a set of physical blocks. Each block includes a set of pages. Each page includes a set of memory cells ("cells"). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more bits of binary information and have various logical states related to the number of bits being stored. The logical state can be represented by a binary value such as "0" and "1" or a combination of such values.

[0017] The memory device may include a plurality of memory cells arranged in a two-dimensional or three-dimensional grid. The memory cells may be formed on a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line may refer to one or more conductive lines coupled to a memory cell of a memory device, the one or more conductive lines being used together with one or more bit lines to generate an address for each of the memory cells. The intersection of a bit line and a word line constitutes the address of a memory cell. Hereinafter, a block refers to a cell of a memory device for storing data, and may include a group of memory cells, a word line group, a word line, or an individual memory cell. One or more blocks may be grouped together to form a separate partition (e.g., a plane) of a memory device in order to allow parallel operations on each plane. Each data block may include several sub-blocks, each of which is defined by an associated pillar (e.g., a vertical conductive trace) extending from a shared bit line. A memory page (also referred to herein as a "page") stores one or more bits of binary data corresponding to data received from a host system. To achieve high density, a string of memory cells in a nonvolatile memory device may be constructed to include several memory cells that at least partially surround a pillar of channel material. The memory cells may be coupled to access lines (which are often referred to as "word lines") that are typically fabricated together with the memory cells to form an array of strings in a memory block. The compact nature of certain nonvolatile memory devices, such as 3D flash NAND memory, means that word lines are common to many memory cells within a memory block.

[0018] Data (e.g., bytes) stored by a memory device may become defective due to time, temperature, or use. For example, a memory cell storing a first logic state (e.g., '0') may have a charge level change (e.g., the threshold voltage of the memory cell may shift), and during a read operation, a second logic state (e.g., '1') may be read instead of the first logic state corresponding to the initial charge level. Defects may be single-bit or multi-bit errors and may occur at a memory cell string, a bit line, or a page buffer. Various solutions may mitigate defects and errors in a memory array by utilizing a column redundancy scheme. For example, a memory array may store data at a certain area. A memory array may also include redundant memory cells that may be used to replace defective bits or bytes.

[0019] Some solutions may specify the number of redundant bytes for a region of a memory array. For example, a memory array may include rows of memory cells, each row being associated with the number of redundant bytes. In other solutions, the number of redundant bytes may correspond to a column of memory cells or a page of memory cells, etc. However, some solutions may not be able to effectively reduce defects and errors in a memory array. For example, one region of a memory array may have more errors than available redundant bytes, while another region of the memory array may have very few errors. This may cause the first region to be unable to compensate for certain errors or defects, even if the overall memory array still includes available redundant bytes. Therefore, when a region of a memory array runs out of available redundant bytes, the memory array may be forced to abandon the region. Attempting to increase the number of redundant bytes available for each region requires the use of additional regions and reduces array area efficiency—for example, more arrays will be dedicated to redundant bytes, thereby compromising the overall use of the memory array. Attempting to reduce the number of regions in a memory array (for example, attempting to utilize more redundant bytes in each region) may force the array undercircuitry (for example, the memory array undercircuitry) to include additional circuitry and logic, resulting in an overall increase in the size of the memory die.

[0020] Aspects of the present disclosure address the above and other deficiencies by implementing a flexible address swapping column redundancy scheme. A memory array may remap the association of a received memory address from within a first address space that has exhausted available redundant memory locations (e.g., additional memory cells that may store a copy of data originally stored at a now defective memory cell) to a second address space that includes available redundant memory locations. That is, each address space of the memory array may be associated with a row or column of the memory array. During a read operation, the entire address space may be read onto a data bus. A redundant address space (e.g., an address associated with an additional memory cell that may store a copy of data originally stored at a now defective memory cell) may be used to replace one address of a corresponding address space of the memory array—e.g., when data is read onto the bus, one redundant address may be read from the redundant address space. Thus, if an address space has two or more errors, a memory address associated with one of the errors may be remapped from the first address space to a second address space that does not have an error—e.g., to a second address space that has not yet utilized a redundant address. In some examples, any redundant address may be used to replace a defective memory cell—eg, a redundant address space may be associated with the memory array as a whole, but any corresponding redundant address may be used in any of the memory array address spaces.

[0021] For example, control logic of a memory array may receive a memory address. The control logic may detect one or more errors exhibited by a memory cell identified by the memory address—e.g., determining that the memory address contains errors and is associated with a first address range. In such instances, the control logic may attempt to correct the errors using available redundant memory locations. If the control logic determines that there are not enough redundant memory locations to relocate the affected data items (e.g., the first address range has already used redundant addresses to correct errors), then the control logic may remap the logical locations associated with the memory address from the first address range to a second address range, where the second address range includes available redundant addresses—e.g., the second address range has not yet utilized redundant addresses. Therefore, the control logic may use the available redundant memory locations of the second address range to correct the original defects in the first address range. Reference Figure 5 Additional details are described regarding remapping memory addresses from a first address range to a second address range.

[0022] By utilizing a flexible address swap column redundancy scheme, a memory array can more efficiently repair defects and errors. For example, a memory array can avoid including additional redundant memory locations or additional circuitry, and instead use redundant memory locations across address ranges. Thus, a memory device can avoid discarding a region of memory if the redundant memory locations associated with that region have been fully utilized.

[0023] Figure 1A An example computing system 100 is illustrated that includes a memory subsystem 110 in accordance with some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0024] The memory subsystem 110 may be a storage device, a memory module, or a mixture of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0025] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, automobile, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0026] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1A An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intermediate components), whether a wired or wireless pair, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0027] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more cache memories, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0028] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access memory components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1AMemory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0029] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM) such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0030] Some examples of non-volatile memory devices (e.g., memory device 130) include "NAND" (NAND) type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device. A cross-point array of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grid data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0031] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, for example, a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of the same. In some embodiments, a particular memory device may include an SLC portion and an MLC portion, a TLC portion, or a QLC portion of a memory cell. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0032] Although nonvolatile memory components such as a 3D cross-point nonvolatile memory cell array and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selected memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), "NOR" (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM).

[0033] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0034] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0035] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1A The example memory subsystem 110 in FIG. 1 has been illustrated as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0036] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address conversion between logical addresses (e.g., logical block addresses (LBA), name spaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0037] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0038] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) may manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is a raw memory device 130 with control logic (e.g., the local controller 135) on the die and a controller (e.g., the memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device. For example, the memory device 130 may represent a single die with some control logic (e.g., the local media controller 135) embodied thereon. In some embodiments, one or more components of the memory subsystem 110 may be omitted.

[0039] In one embodiment, the memory device 130 includes a flexible column redundancy component 113. In some embodiments, the flexible column redundancy component 113 can repair errors that occur at the memory array 104. For example, the flexible column redundancy component 113 can correct errors at the memory array 104 by replacing bytes stored at the memory array 104 with redundant bytes—for example, the flexible column redundancy component 113 can remap the association of a memory address from a first address range associated with a defective memory cell to a second address range associated with an available redundant memory location—for example, remap to a second address range that has not yet utilized a redundant address. Therefore, data associated with the memory address is stored in the redundant memory location instead of the defective memory cell in the first address range. In some embodiments, the memory cells of the memory array can be addressed by corresponding addresses that can be grouped into one or more address ranges. The redundant address ranges of the memory array can be associated with a common address range—for example, any corresponding redundant address of the redundant address range can be used to correct one or more errors at the corresponding address range of the memory array. In one embodiment, the flexible column redundancy component 113 can receive a memory address associated with an address range (for example, associated with a first address range of multiple address ranges associated with the memory array 104). In some embodiments, the flexible column redundancy component 113 may determine one or more physical locations associated with the memory address by looking up the received memory address in an address table—for example, determining the physical location associated with the received logical address, wherein the table stores the physical location of each logical address. In some embodiments, the flexible column redundancy component 113 may detect (for example, by receiving an indication from an error correction code (ECC) component) one or more errors associated with the received memory address. In such embodiments, the flexible column redundancy component 113 may also determine whether there are any available redundant bytes for the address range. That is, each address range may be read onto the bus in its entirety during a read operation. In some instances, the addresses of the address range may be replaced by the addresses of the redundant address range—for example, when reading the corresponding memory address range, the bus may read one redundant address. Therefore, if there is more than one error in the address range, the flexible column redundancy component 113 may remap the memory addresses associated with the errors from the first address range to the second address range that has not yet utilized redundant addresses.

[0040] In some embodiments, the flexible column redundancy component 113 may determine that there are available redundant memory addresses for the address range and continue to correct the one or more errors—e.g., continue to remap memory addresses from a first address range associated with a defective memory cell to a second address range having available redundant memory locations or addresses. In other embodiments, the flexible column redundancy component 113 may determine that there are not enough available redundant memory locations for the address range—e.g., the number of errors in the address range exceeds the number of available redundant memory locations for the address range. In such embodiments, the flexible column redundancy component 113 may send a signal to a pre-decoder (e.g., as described in reference to FIG. 1 ). Figure 3 The pre-decoder 320 described above transmits an indication to remap a memory address from a first address to a second address associated with a second address range. In some embodiments, the second address range may include available redundant memory locations. In some embodiments, the decoder may receive the updated or remapped address and determine that a second address in the second address space corresponds to the received memory address. Thus, the flexible column redundancy component 113 may repair the error by utilizing the redundant bytes of the second address range.

[0041] In some embodiments, the memory subsystem controller 115 includes at least a portion of the flexible column redundancy component 113. For example, the memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in the local memory 119 for performing the operations described herein. In some embodiments, the flexible column redundancy component 113 is part of the host system 120, an application, or an operating system. In other embodiments, the local media controller 135 includes at least a portion of the flexible column redundancy component 113 and is configured to perform the functionality described herein. In this embodiment, the flexible column redundancy component 113 may be implemented using hardware or as firmware that is stored on the memory device 130 and executed by the control logic (e.g., the flexible column redundancy component 113) to perform operations related to program recovery described herein.

[0042] Figure 1B A first device in the form of a memory device 130 according to an embodiment and a memory subsystem (eg, Figure 1A 1 is a simplified block diagram of a second device in the form of a memory subsystem 110 of the present invention communicating with a memory subsystem controller 115 of the present invention. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, game consoles, electrical appliances, vehicles, wireless devices, mobile phones, etc. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) can be a memory controller or other external host device. The memory subsystem controller 115 can include a flexible column redundancy component 113.

[0043] Memory device 130 includes a memory cell array 104 that is logically arranged in rows and columns. Memory cells of a logical row are typically connected to the same access line (e.g., word line), while memory cells of a logical column are typically selectively connected to the same data line (e.g., bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. Memory cells of at least a portion of memory cell array 104 ( Figure 1B In one embodiment, memory cell array 104 (ie, "memory array") may include a number of sacrificial memory cells for detecting the occurrence of read disturbance in memory device 130, as described in detail herein.

[0044] Row decoding circuitry 108 and column decoding circuitry 109 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 130 also includes input / output (I / O) control circuitry 160 to manage the input of commands, addresses, and data to memory device 130 and the output of data and status information from memory device 130. Address register 114 communicates with I / O control circuitry 160 and row decoding circuitry 108 and column decoding circuitry 109 to latch address signals prior to decoding. Command register 124 communicates with I / O control circuitry 160 and local media controller 135 to latch incoming commands.

[0045] The controller (e.g., the local media controller 135 inside the memory device 130) controls access to the memory cell array 104 in response to a command and generates state information of the external memory subsystem controller 115, that is, the local media controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on the memory cell array 104. The local media controller 135 communicates with the row decoding circuit system 108 and the column decoding circuit system 109 to control the row decoding circuit system 108 and the column decoding circuit system 109 in response to an address. In one embodiment, the local media controller 135 may include the flexible column redundancy component 113 (e.g., including at least a portion thereof), as described with reference to FIG. Figure 1B described.

[0046] The local media controller 135 also communicates with a cache register 172. The cache register 172 latches incoming or outgoing data as directed by the local media controller 135 to temporarily store the data while the memory cell array 104 is busy writing or reading other data, respectively. During a memory access operation (e.g., a write operation), data may be transferred from the cache register 172 to the data register 170 for transmission to the memory cell array 104; the new data may then be latched in the cache register 172 from the I / O control circuitry 160. During a read operation, data may be transferred from the cache register 172 to the I / O control circuitry 160 for output to the memory subsystem controller 115; the new data may then be transferred from the data register 170 to the cache register 172. The cache register 172 and / or the data register 170 may form a page buffer of the memory device 130 (e.g., may form part of a page buffer). The page buffer may further include a sensing device ( Figure 1B 1 (not shown) to sense the data state of the memory cells of the memory cell array 104, for example, by sensing the state of the data lines of the memory cells. The status register 122 can communicate with the I / O control circuitry 160 and the local memory controller 135 to latch the status information for output to the memory subsystem controller 115.

[0047] The memory device 130 receives control signals at the memory subsystem controller 115 from the local media controller 135 through the control link 132. For example, the control signals may include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protect signal WP#. Depending on the nature of the memory device 130, additional or alternative control signals (not shown) may be further received through the control link 132. In one embodiment, the memory device 130 receives a command signal (which represents a command), an address signal (which represents an address), and a data signal (which represents data) from the memory subsystem controller 115 through a multiplexed input / output (I / O) bus 134, and outputs the data to the memory subsystem controller 115 through the I / O bus 134.

[0048] For example, a command may be received at I / O control circuitry 160 through input / output (I / O) pins [7:0] of I / O bus 134, and the command may then be written into command register 124. An address may be received at I / O control circuitry 160 through input / output (I / O) pins [7:0] of I / O bus 134, and the address may then be written into address register 114. Data may be received at I / O control circuitry 160 through input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices, and the data may then be written into cache register 172. The data may then be written into data register 170 for use in programming memory cell array 104.

[0049] In an embodiment, cache register 172 may be omitted and data may be written directly into data register 170. Data may also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. Although reference may be made to an I / O pin, it may include any conductive node, such as a commonly used conductive pad or conductive bump, that enables electrical connection to memory device 130 by an external device (e.g., memory subsystem controller 115).

[0050] Those skilled in the art will appreciate that additional circuitry and signals may be provided and simplified. Figure 1B It should be appreciated that reference Figure 1B The functionality of the various block components described may not necessarily be separated into different components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device may be adapted to perform Figure 1B Alternatively, one or more components or component parts of an integrated circuit device may be combined to perform Figure 1B Additionally, although specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or other numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0051] Figure 2 An example computing system 200 utilizing a flexible address swap column redundancy scheme according to some embodiments of the present disclosure is illustrated. For example, the system 200 can repair one or more errors that occur in the memory array 104 as described with reference to FIG. 1. In some embodiments, the system 200 can be located in a memory array 104 as described with reference to FIG. Figure 1AThe system 200 may be configured to receive a memory address and output at least one physical address associated with the received memory address—for example, the received memory address may be a logical address, and the system 200 may be configured to output the physical address associated with the received logical address. In some embodiments, the system 200 is configured to output the physical address to a data bus—for example, the system 200 may be coupled to the data bus. The system 200 may include a memory array 210 including memory array sub-segments 220 and a transposition component 215. The system 200 may also include a content addressable memory (CAM) 235, redundant memory locations 245 (e.g., spare memory cells that may store copies of data originally stored at now defective memory cells of the memory array 210), and a multiplexer 255. In some embodiments, the system 200 may include an additional CAM to control the transposition component 215. In some embodiments, CAM 235 may control transposition component 215 .

[0052] In one embodiment, the memory array 210 may store data associated with a host system (eg, as described in reference Figure 1A In some embodiments, the memory array 210 may include a plurality of memory cells (e.g., memory cell 225-a, memory cell 225-b, memory cell 225-c, memory cell 225-d, etc.) for storing data. In some embodiments, the memory array 210 may be divided into array sub-segments 220. That is, although Figure 2 2, but the memory array 210 may have any number of array subsections 220. In some embodiments, each array subsection 220 may include groups of memory cells 225 that are each associated with a different address range. For example, memory cell 225-a may be associated with a first address range, memory cell 225-b may be associated with a second address range, memory cell 225-c may be associated with a third address range, and memory cell 225-d may be associated with a fourth address range. In some embodiments, an address range may refer to a set of row addresses or column addresses—e.g., an address range may refer to a physical row of memory cells or a physical column of memory cells. In other examples, an address range may refer to a different partition of memory cells—e.g., a page of memory cells.

[0053] In some embodiments, the memory array 210 may receive a column address 205—for example, from a local media controller 135 or a memory subsystem controller 115 as described with reference to FIG. 1 . In some embodiments, each array sub-segment 220 may include a transposition component 215. In some embodiments, the transposition component 215 may transpose or remap a first address of a first address range associated with the received column address 205 to a second address in a second address range. For example, the column address 205 may indicate a first physical location corresponding to one or more memory cells 225-a. The transposition component 215 may be configured to remap the first physical location from being associated with the first address range to being associated with the second address range. In one embodiment, the transposition component 215 is configured to remap the physical address when no available redundant memory location 245 is available for the address range—for example, when no available redundant memory location 245 is available for the address range corresponding to the memory cell 225-a. In some embodiments, the memory array 210 may output data input / output (I / O) 230. In some embodiments, data I / O 230 may indicate a physical location associated with column address 205. In some embodiments, data I / O 230 may include data associated with column address 205. In at least one embodiment, transposition component 215 may transpose addresses at the pre-decoder, as described with reference to FIG. Figure 5 As described—for example, the transposition component 215 may include a pre-decoder having one or more multiplexers to which the transposition component 215 may send a signal to swap the addresses. In other embodiments, the transposition component 215 may remap the addresses by performing an inversion of the addresses before receiving them at the pre-decoder, as described in reference to Figure 5 described.

[0054] In some embodiments, a content addressable memory (CAM) 235 may store corresponding physical addresses (e.g., physical locations) associated with all logical addresses received from a host system or a memory subsystem controller—for example, the CAM 235 may compare a received memory address with a table of stored memory addresses, wherein the table indicates the physical locations associated with the stored memory addresses. For example, the CAM 235 may receive a column address 205. In some embodiments, the CAM 235 may compare the received column address 205 with the stored column addresses to determine the physical location associated with the column address 205—for example, the CAM 235 may be configured to map between the received logical address and the physical address of the stored data. In some embodiments, the CAM 235 may also store an indication of any redundant memory locations 245 for the received corresponding column address 205. In at least one embodiment, the system 200 may determine the number of available redundant memory locations for the corresponding address range based on the comparison between the column address 205 and the stored column address 240. For example, the system 200 may determine the number of redundant memory locations utilized based on the physical location output by the CAM 235. In such embodiments, the system 200 may determine the number of available redundant memory locations by subtracting the utilized redundant memory locations 245 from the threshold number of redundant memory locations 245 for the address range. In one embodiment, the CAM 235 is configured to output a stored column address 240—e.g., to output an actual address indicating the physical location of the data associated with the column address 205.

[0055] In some embodiments, redundant memory locations 245 can replace or repair errors associated with data stored at memory array 210—e.g., system 200 can remap a physical location associated with a received memory address from a first physical location corresponding to a defective memory cell at memory array 210 to a second physical location corresponding to a redundant memory location stored at redundant memory location 245. In some embodiments, there can be a threshold number of redundant memory locations available for each address space—e.g., a certain number of redundant memory locations can be used for each address space. For example, during a read operation, the entire corresponding address range can be read onto the data bus. In such instances, a threshold number of addresses of the corresponding address range can be replaced by one or more redundant memory locations 245. When the threshold number of addresses that can be replaced is met, additional addresses of the corresponding address range cannot be replaced. Therefore, a received address can be mapped from the corresponding address range to a second address range that has not yet met the threshold number of addresses that can be replaced. In at least one embodiment, the threshold number of addresses that can be replaced can be based on the size of the array, ECC limitations, or a memory management algorithm (e.g., an algorithm programmed into system 200 that indicates the type of error that is corrected using redundant memory locations). In some embodiments, the redundant memory location 245 may receive a stored column address 240 and output a redundant input / output (I / O) 250—e.g., a redundant memory location 245 component may receive a stored column address 240, determine the physical location of a redundant memory location storing associated data, and output the redundant memory location 245.

[0056] In some embodiments, multiplexer 255 may receive data I / O 230 from memory array 210 and redundant I / O 250 from redundant memory locations 245. In one embodiment, system 200 may determine the number of redundant memory locations available for a corresponding address range based on the number of redundant memory locations 245 in redundant I / O 250—for example, system 200 may subtract the number of redundant memory locations 245 outputted from a threshold number of redundant memory locations or a threshold number of addresses that may be replaced. In some embodiments, system 200 may determine that one or more errors associated with column address 205 exceed the number of redundant memory locations 245 available for a corresponding address range. In such embodiments, system 200 may remap a first address associated with the received memory address and corresponding to a first address range to a second address associated with a second address range at transpose 215, wherein the second address range includes available redundant memory locations. Thus, system 200 may repair errors even if there are no available redundant memory locations for the corresponding address range. In at least one embodiment, multiplexer 255 is configured to output management data input / output (I / O) 260. In some embodiments, management data I / O 260 may represent a management reference. Figure 1A The physical components or physical layer of the described memory device 130 are serial buses. The management data I / O 260 may include operation codes, physical addresses, register addresses, and / or data.

[0057] Figure 3 An example computing system 300 is illustrated that utilizes a flexible address swap column redundancy scheme according to some embodiments of the present disclosure. For example, the system 300 may be configured to repair one or more errors that occur at the memory array 104 as described with reference to FIG. 1. In some embodiments, the system 300 may be located at a memory array 104 as described with reference to FIG. Figure 1A In some embodiments, portions of system 300 may be included in the flexible column redundancy component 113 or local media controller 135 as described above. Figure 2 In some embodiments, the system 300 may be configured to receive an external address 305 and determine the physical location of a byte associated with the received external address 305. In some embodiments, the system 300 may include an address register 114, a column select line pre-decoder 320, and a decoder 330.

[0058] In some embodiments, address register 114 may store a physical address (e.g., a physical location) and determine the physical address at which the data of a received memory address is located. For example, address register 114 may receive external address 305 (e.g., a logical address associated with a host system) and use a stored table to look up internal address 315 (e.g., a physical address associated with a location where data is stored) that corresponds to external address 305. In some embodiments, address register 114 is configured to store a physical address (e.g., a physical location) at which the data of a received memory address is located. Figure 1B In some embodiments, the address register 114 is included in the reference Figure 2 In at least one embodiment, system 300 can update the table stored at address register 114 when internal address 315 changes—for example, when reference is made to CAM 235. Figure 2 When describing remapping a first address associated with a first address range to a second address associated with a second address range to use available redundant memory locations at the second address range, the system 300 can update a table stored at the address register 114 .

[0059] In one embodiment, the column select line (CSL) pre-decoder 320 may receive the internal address 315 from the address register 114. In some embodiments, the CSL pre-decoder 320 is configured to generate a column select line (CSL) signal 325 for the decoder 330. For example, the CSL pre-decoder 320 may generate a signal indicating a column associated with the internal address 315. That is, the CSL pre-decoder 320 may generate a select control signal indicating which column the decoder 330 should select. In at least one embodiment, the system 300 may swap a first address associated with a first address range to a second address associated with a second address range, as described in reference to FIG. Figure 2 As described—for example, when the first address range contains one or more errors to be repaired and no additional redundant addresses are available for the first address range, the system 300 can swap the first address. In some embodiments, the system 300 can remap the incoming address associated with the first location to the second physical location of the address before or after the CSL pre-decoder 320 receives the incoming address, as described in reference to Figure 5 For example, the system 300 may perform incoming address remapping and change the address before the CSL predecoder 320 receives the address. In some embodiments, the system 300 may perform pre-decoding address swapping and change the address after the CSL predecoder 320 outputs the CSL signal 325, as described in reference to Figure 5 In any embodiment, decoder 330 may be configured to receive the remapped address in embodiments where system 300 transposes a first address to a second address.

[0060] In an embodiment, the decoder 330 may receive the column select line signal 325 and select one or more memory cells associated with the received column select line signal 325. For example, the decoder 330 may receive the CSL signal 325 and select the first memory cell in the column associated with the column select line signal 325. As described with reference to the CSL pre-decoder 320, in some embodiments, the decoder 330 may receive an address that has been changed compared to the address generated by the address register 114—e.g., the system 300 may swap addresses due to the address range including one or more errors and a lack of available redundant memory locations. In such embodiments, the decoder 330 may select an updated or new memory cell—e.g., the decoder 330 may select a memory location associated with the second physical address.

[0061] Figure 4 An example diagram 400 illustrates an example of utilizing a flexible address swap column redundancy scheme according to some embodiments of the present disclosure. In one embodiment, diagram 400 illustrates a memory array 104 (eg, as shown in FIG. 1 ) at a first time 405 and a second time 410. Figure 1A 4. In one embodiment, the memory array 104 may include memory cells addressable by respective addresses of n number of address ranges 415, wherein each address range includes four (4) bytes (e.g., four memory cells) and one redundant location. It should be noted that diagram 400 illustrates one possible example of the memory array 104, and other examples are possible—e.g., each address range 415 may include any number of bytes or memory cells, any number of redundant locations, and any number of errors other than that illustrated in diagram 400.

[0062] At time 405, the memory array 104 may detect (e.g., as an ECC component within the memory device 130 described with reference to FIG. 1) one or more errors in the array. For example, the memory array 104 may determine that three (3) defective bytes 430 are associated with the address range 415-a, two (2) defective bytes 430 are associated with the address range 415-b, one (1) defective byte 430 is associated with the address range 415-c, and two (2) defective bytes 430 are associated with the address range 415-d. In at least one embodiment, the memory array 104 may utilize an algorithm (e.g., a memory management algorithm) to determine whether to repair the determined errors. For example, the memory management algorithm may indicate the types of errors to be corrected based on the capabilities of the memory device 130 or based on testing or manufacturing processes—e.g., a testing operation may indicate which types of errors the memory device 130 can avoid correcting while staying below an ECC limit. In one embodiment, the memory array 104 may determine to correct all of the defective bytes 430.

[0063] As reference Figure 1A As described, each address range 415 may use a threshold number of redundant locations or redundant addresses. Diagram 400 illustrates that each address range 415 has one available redundant location 440—e.g., each address range 415 may use one redundant location 440. It should be noted that each address range 415 may use any of the available redundant locations 440—e.g., although redundant locations 440 are shown in each address range 415, redundant locations 440 may be used for address ranges 415. For example, the redundant locations 440 shown for address range 415-n may be used to replace errors in any of the other address ranges 415. Because, the redundant addresses of the redundant address ranges may be used to replace the addresses of any address range 415. In this example, the memory array may utilize redundant locations in address ranges 415-a to 415-d for repair—e.g., address ranges 415-a to 415-d may have unavailable redundant locations 435 after repairing at least one error in each respective address range 415. For example, the memory array 104 may remap the association of the received memory address from the first physical location associated with the defective byte 430 to the second physical location associated with the unusable redundant location 435. After utilizing the redundant locations of each of the address ranges 415-a through 415-d, the memory array 104 may still include the defective byte 430—e.g., the memory array 104 may determine that the number of errors associated with the respective address range 415 fails to meet (e.g., exceeds) the number of available redundant bytes for the address range 415. For example, after repair, address range 415-a may include one (1) replaced defective byte 425 and two (2) defective bytes 430, address range 415-b may include one (1) replaced defective byte 425 and one defective byte 430, address range 415-c may include one (1) replaced defective byte 425, and address range 415-d may include one (1) replaced defective byte 425 and one (1) defective byte 430. In one embodiment, memory array 104 may replace the remaining defective bytes between time 405 and time 410 using a flexible address swap column redundancy scheme as described herein.

[0064] In one embodiment, after time 405, the memory array 104 may detect one or more available redundant bytes 440 (e.g., the available redundant bytes shown in address ranges 415-e through 415-n, but the redundant bytes 440 are available for any address range 415 and are not associated with the respective address ranges 415, but are associated with the entirety of address ranges 415-a through 415-n). In such embodiments, the memory array 104 may remap the defective bytes 430 to the respective address ranges 415-e through 415-n to utilize the available redundant locations 440. For example, the association with the memory address is remapped from the defective bytes 430 of address range 415-a to the non-error bytes 420 of address range 415-e—e.g., from a first address (e.g., the leftmost defective byte 430 illustrated at time 405) to a second address (e.g., the non-error bytes 420 of address range 415-e). In at least one embodiment, the memory array 104 may utilize the available redundant locations 440 of the address range 415-e to repair the defective bytes 430 remapped from the address range 415-a—e.g., at time 410, after repairing the remapped defective bytes 430 from the address range 415-a, the address range 415-e may include the replaced defective bytes 425 and the unavailable redundant locations 435. For example, the memory array 104 may remap from the first address to the available redundant locations 440 of the address range 415-e. The memory array 104 may continue to replace the remaining defective bytes 430 illustrated at time 405 in a similar manner.

[0065] For example, the memory array may remap a defective byte 430 of address range 415-b to an error-free byte 420 of address range 415-f, and then utilize an available redundant location 440 to repair the defective byte 430—e.g., at time 410, after swapping the defective byte 430 from address range 415-b to address range 415-f, address range 415-f may include a replaced defective byte 425 and an unavailable redundant location 435. In one embodiment, the memory array may also remap the memory address association of the second defective byte 430 of address range 415-a (e.g., the rightmost defective byte 430 illustrated at time 405) to an error-free byte 420 of address range 415-g, and then repair the defective byte 430 using an available redundant location 440 of address range 415-g—e.g., at time 410, after remapping the defective byte 430 from address range 415-a to address range 415-g, address range 415-g may include a replaced defective byte 425 and an unavailable redundant location 435. In some embodiments, the memory array may further remap the defective bytes 430 of the address range 415-d to the error-free bytes 420 of the address range 415-n, and then repair the defective bytes 430 using the available redundant locations 440 of the address range 415-n—e.g., at time 410, after remapping the defective bytes 430 from the address range 415-d to the address range 415-n, the address range 415-n may include the replaced defective bytes 425 and the unavailable redundant locations 435. Thus, the memory array 104 may repair all defective bytes 430 even if, at time 405, the number of errors in the address range 415-a, the address range 415-b, and the address range 415-d fails to meet (e.g., exceeds) the number of available redundant locations of the respective address ranges.

[0066] Figure 5 An example computing system 500 is illustrated that utilizes a flexible address swap column redundancy scheme according to some embodiments of the present disclosure. For example, the system 500 may be configured to repair one or more errors that occur at the memory array 104 as described with reference to FIG. 1. In some embodiments, the system 500 may be located at a memory array 104 as described with reference to FIG. Figure 1A In some embodiments, portions of system 500 may be included in the flexible column redundancy component 113 or the local media controller 135 as described above. Figure 2 and 3300. In some embodiments, the system 500 may be configured to receive an external address 305 and determine an internal memory location 530 to access, as described herein. In some embodiments, the system 500 may include an address register 114, a column select line pre-decoder 320, and a decoder 330. The system 500 may also include one or more memory locations 530 (e.g., physical memory cells storing data) and include an incoming address swap component 535, a pre-decode address swap component 540, or both.

[0067] In at least one embodiment, system 500 may receive a reference Figure 3 In at least one embodiment, the address register 114 may receive the external address 305 and determine a corresponding column address 505—eg, a column address 505 associated with the incoming external address 305. In at least one embodiment, the address register 114 may include or be a column address as described in reference Figure 2 An example of a content addressable memory (CAM) 235 is depicted. In at least one embodiment, the address register 114 can transmit a column address to one or more column select line (CSL) pre-decoders 320 .

[0068] In at least one embodiment, the CSL pre-decoder 320 may be as shown in FIG. Figure 2 215 described. In one embodiment, each pre-decoder 320 may pre-decode a subset of the address space—e.g., a subset of the column address 505 received from the address register 114. For example, the column address 505 may be [2:0] and decomposed into a first column address 510 including [2:1] and a second column address 515 including [0]. Thus, each CSL pre-decoder 320 may receive a respective column address 505 or 510 and output a column select signal (e.g., column select B 520 or column select A 525) to the decoder 330. In one embodiment, the decoder 330 may be an instance of AND logic, and the memory location 530 may be selected by the column select signal 536 based on the received column select signal.

[0069] In one embodiment, the column address may be swapped or otherwise modified before it is received by decoder 330. For example, as shown in FIG. Figures 2 to 4As described, redundant memory locations can replace or repair errors associated with data stored at the memory array. When there are no additional redundant memory locations available for the corresponding address space, the system 500 can remap the association of the external address 305 from the first address space to the second address space. In at least one embodiment, the system 500 can remap the association at the incoming address swap component 535. In another embodiment, the system 500 can remap the association at the pre-decoding address swap component 540. In some embodiments, the system 500 can include both the incoming address swap component 535 and the pre-decoding address swap component 540.

[0070] For example, the incoming address swap component 535 may receive a column address associated with each address space—e.g., receiving column addresses (CA) [2], CA [1], and CA [0]. In at least one embodiment, the external address 305 may initially be associated with CSL A [0] and CSL B [0]. In such embodiments, typically, the CSL pre-decoder 320-a may output a value CSL A [0] = 1 (e.g., a signal indicating that the external address 305 is associated with A [0]) and a value CSL B [0] = 1 (e.g., a signal indicating that the external address 305 is also associated with B [0]). However, in embodiments where the system 500 performs remapping, the CAM may transmit a signal to one or more corresponding circuits coupled to the CSL pre-decoder 320 in order to swap the column addresses. For example, Figure 5 The CA[2] circuit may receive a signal (e.g., receive a one (1) from the CAM) and cause the output of the CSL pre-decoder 320 to change. That is, the CAM may store the location of the error and also store whether the address is associated with a redundant memory location. In at least one embodiment, the CAM may determine where to remap an incoming memory address before the pre-decoder receives the address and transmit a signal to the circuit accordingly as needed. Figure 5 , by transmitting one (1) to the CA[2] circuit, the CSL pre-decoder may output the values ​​CSL B[2]=1 and CSL B[0]=0—e.g., outputting a column select signal indicating that B[2] is selected instead of B[0]. Thus, the decoder 330 may select the memory location 530-b instead of the memory location 530-a based on the incoming address swap component 535 swapping CSL B[0] to zero (0) and CSL B[2] to one (1). Because, when the incoming address swap component 535 swaps the address before it is received at the corresponding pre-decoder 320, the CSL pre-decoder 320-b may output a different column select B[3:0] 520.

[0071] In other embodiments, the system 500 may swap addresses after the CSL pre-decoder 320 outputs a column select signal (e.g., column select B 520 or column select A 525). For example, the external address may again be associated with A[0] and B[0]. Thus, the CSL pre-decoder 320-b may output a one (1) for address space B[0] (e.g., B[0] may go high) and a zero (0) for the remaining address spaces (e.g., B[1], B[2], and B[3] may go low). Similarly, the CSL pre-decoder 320-a may output CSL A[0]=1 and CSL A[1]=0 to select the A[0] address space. In embodiments where the addresses are swapped, the CAM may transmit signals to one or more multiplexers coupled to the CSL pre-decoder 320. For example, each multiplexer may receive all CSL select values ​​output by the corresponding predecoder 320—e.g., each multiplexer coupled to the CSL predecoder 320-b may receive CSLs B[0] to B[3]. The multiplexers may also receive signals from the CAM (e.g., signals '11', '00', '01', or '10'). In some embodiments, the received signals may cause the column select signals to be swapped from one address space to another. For example, by transmitting '10' to the multiplexer associated with B[0] and '00' to the multiplexer associated with B[2], the column select signal for B[0] may become zero (0) and the column select signal for B[2] may become one (1). Thus, CSL B[2] goes high and is selected instead of CSL B[0]. In such embodiments, due to the address swapping at the pre-decode address swapping component 540, the decoder 330 may select the memory location 530-b instead of the memory location 530-a.

[0072] It should be noted that the number of address spaces associated with a column address is shown for illustration purposes only. A column address may have any number of address spaces. Additionally, a column address may be broken down into any number of subsets for any number of predecoders—for example, the system 500 may include additional CSL predecoders based on the number of subsets of column address 505. By remapping addresses at either the incoming address swap component 535 or the pre-decoding address swap component 540, the system 500 may utilize a flexible address swap column redundancy scheme to repair or correct errors at address spaces where additional redundant memory locations cannot be used.

[0073] Figure 6600 is a flowchart of an example method of a flexible address swapping redundancy scheme according to some embodiments of the present disclosure. The method 600 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 600 is performed by Figure 1A The local media controller 135 or the flexible column redundancy component 113 of the embodiment is executed. Although shown in a specific order or sequence, the order of the process can be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are only examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0074] At operation 605, one or more errors associated with one or more stored data items corresponding to a first address range in the one or more address ranges are detected. For example, a processing device (e.g., flexible column redundancy component 113) may detect one or more errors associated with one or more stored data items corresponding to a first address range in the one or more address ranges. In at least one embodiment, the one or more errors may be single-bit, double-bit, or other errors associated with a bit line or page buffer as described with reference to FIG. 1. For example, a processing device may detect a defective byte, as described with reference to FIG. Figure 4 Described—for example, determining defective bytes 430 in address range 415-a. In some embodiments, a processing device may receive a memory address associated with a first address range in one or more address ranges. In such embodiments, the processing device may detect one or more errors associated with the memory address.

[0075] At operation 610, the processing device determines whether the number of one or more data item address ranges exceeds the number of available redundant memory locations for the first address range. For example, the processing device may determine that the number of one or more stored data items exceeds the number of available redundant memory locations for the first address range. Figures 2 to 4 As described above, the respective address ranges of the memory device 130 may use a threshold number of redundant locations—for example, each address range may use a number of redundant memory locations configured to replace defective stored data items. In one embodiment, the processing device may utilize a method as described in reference to Figure 2A content addressable memory (CAM) is described herein to determine that the number of data items exceeds the number of available redundant memory locations. For example, a processing device may receive a memory address associated with a first address range and compare the received memory address to a second stored memory address associated with the received memory address—e.g., the CAM may look up the received memory address in a table storing all memory addresses and determine one or more physical locations associated with the received memory address. In this example, the processing device may determine that redundant memory locations of the first address range are utilized—e.g., the CAM may determine a physical location that includes multiple redundant bytes for the received memory address. In other embodiments, the processing device may determine that the number of redundant bytes for the received memory address is greater than the number of available redundant memory locations based on a multiplexer (e.g., as described in reference to FIG. 1 ). Figure 2 In one embodiment, the processing logic may determine that the number of data items exceeds the number of available redundant memory locations based on an input received at a multiplexer 255 described above—e.g., the multiplexer 255 may allow the memory device 130 to determine the number of redundant memory locations for the received memory address, and whether the number of redundant memory locations meets a threshold number of available redundant memory locations. For example, the processing logic may compare the received memory address with a second stored memory address indicating a physical location associated with the memory address, and determine the number of unavailable redundant memory locations in response to comparing the received memory address. In such embodiments, the processing logic may determine the difference between the threshold number of available redundant memory locations and the number of unavailable redundant memory locations—e.g., determine the number of available redundant memory locations. In at least one embodiment, the processing logic may compare the difference with the number of one or more stored data items, wherein the processing logic may determine in response to the comparison that the number of one or more stored data items exceeds the number of available redundant memory locations.

[0076] In response to determining at operation 610 that one or more stored data items exceed the number of available redundant memory locations of the first address range, at operation 615, the processing device remaps an association of a first memory address from a first address within the first address space to a second address in a second address range of the one or more address ranges, wherein the second address range includes the one or more available redundant memory locations. For example, the processing device may remap an association of a first memory address of at least one of the stored data items from a first address associated with the first address space to a second address in a second address range of the plurality of address ranges, wherein the second address range includes the one or more available redundant memory locations. In one embodiment, the processing device may remap from a first address (e.g., a defective byte 430 of address range 415-a) to a second address (e.g., to a location previously occupied by a non-error byte 420 of address range 415-e), as described with reference to FIG. Figure 4As described. In such embodiments, the processing device may utilize available redundant memory locations of the second address range (e.g., in address range 415-e) to repair at least one error—e.g., utilize available redundant location 440 of address range 415-e to replace defective byte 430. Thus, the second physical address is associated with a redundant memory cell of the second address range. In some embodiments, before remapping the first address to the second address, the processing logic may determine that the number of one or more available redundant memory locations in the second address range satisfies the number of physical locations of the one or more physical locations—e.g., determine that the number of one or more available redundant memory locations of the second address range satisfies the number of errors of the one or more errors. For example, the processing logic may track the number of used redundant locations for each respective address range, and determine an address range that has enough available redundant locations to satisfy the number of errors. In one embodiment, the processing device is configured to remap from a first address of one or more stored data items to a second address before receiving the address at a predecoder of the memory device. In another embodiment, the processing logic is configured to remap from a first address of one or more stored data items to a second address at a predecoder of the memory device. In at least one embodiment, the processing device may remap from the first address to the second address based on a memory management algorithm—for example, the processing device may remap from the first address to the second address based on a memory management algorithm as described in reference Figure 2 In one embodiment, a processing device may receive a memory address associated with a first address range and determine that at least one physical location associated with the memory address is located in a redundant memory data item of a second address range—for example, the processing device may utilize a decoder (e.g., decoder 330) to determine an address remapping of the at least one physical location from the first address range to the redundant memory data item.

[0077] In at least one embodiment, processing logic may detect one or more errors associated with one or more stored data items corresponding to a second address range in the one or more address ranges after remapping the first memory address. Processing logic may determine that the number of the one or more stored data items exceeds the number of available redundant memory locations in response to remapping the association of the first memory address. In at least one embodiment, processing logic may remap the association of the second memory address of at least one of the stored data items from a third address within the second address space to a fourth address in a third address range in the one or more address ranges, wherein the third address range includes the one or more available redundant memory locations.

[0078] In one embodiment, processing logic may detect one or more additional errors associated with one or more stored data items corresponding to the first address range. In some embodiments, processing logic may determine that the number of the one or more stored data items exceeds the number of available redundant memory locations for the first address range. Processing logic may also determine that the number of the one or more stored data items exceeds the number of available redundant memory locations for the second address range. In some embodiments, processing logic may remap an association of a second memory address of at least one of the stored data items from a third address within the first address space to a fourth address in a third address range of the one or more address ranges, wherein the third address range includes the one or more available redundant memory locations.

[0079] In some embodiments, processing logic may receive a memory address and determine that at least one physical address associated with the memory address is located in a redundant memory location within a second address range.

[0080] Figure 7An example machine of a computer system 700 is illustrated, within which a set of instructions for causing the machine to perform any one or more of the methods discussed herein may be executed. In some embodiments, the computer system 700 may correspond to a host system (e.g., the host system 120 of FIG. 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., the memory subsystem 110 of FIG. 1 ), or may be used to perform operations of a controller (e.g., execute an operating system to perform operations corresponding to the flexible column redundancy component 113 of FIG. 1 to perform operations). In one embodiment, the flexible column redundancy component 113 is configured to repair one or more errors of the main memory 704 by utilizing redundant or spare bytes. In one embodiment, the main memory 704 may be divided into address ranges, wherein each address range has a number of available redundant bytes. The flexible column redundancy component 113 is configured to utilize all available redundant bytes to correct one or more errors associated with the corresponding address range. In some embodiments, the flexible column redundancy component 113 may determine that the number of available redundant bytes in the corresponding address range fails to meet (e.g., is equal to or greater than) the number of errors in the corresponding address range. In such embodiments, the flexible column redundancy component 113 may swap a physical address associated with a first address range having unavailable redundant bytes to a physical address associated with a second address range, wherein the second address range has available redundant bytes. The flexible column redundancy component 113 may utilize the available redundant bytes of the second address range to correct one or more errors after swapping the physical address from the first address range to the second address range. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment as a peer machine in a peer-to-peer (or distributed) network environment or as a server or a client machine in a cloud computing infrastructure or environment.

[0081] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0082] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or RDRAM, etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718 that communicate with each other via a bus 730.

[0083] The processing device 702 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 702 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. The computer system 700 may further include a network interface device 708 to communicate over a network 720.

[0084] The data storage system 718 may include a machine-readable storage medium 724 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 726 or software embodying any one or more of the methods or functions described herein. The instructions 726 may also reside, completely or at least partially, within the main memory 704 and / or within the processing device 702 during execution by the computer system 700, the main memory 704 and the processing device 702 also constituting machine-readable storage media. The machine-readable storage medium 724, the data storage system 718, and / or the main memory 704 may correspond to the memory subsystem 110 of FIG. 1 .

[0085] In one embodiment, the instructions 726 include instructions to implement functionality corresponding to the flexible column redundancy component 113 to perform memory access operations initiated by the processing device 702. Although the machine-readable storage medium 724 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" should therefore be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0086] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively convey the substance of their work to others skilled in the art. In this article, and in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is one that requires physical manipulation of physical quantities. Typically (but not necessarily), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for common reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, and the like.

[0087] It should be borne in mind, however, that all of these and similar terms will be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0088] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the desired purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, each coupled to a computer system bus, including floppy disks, optical disks, CD-ROMs and magnetic optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions.

[0089] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used in conjunction with the programs according to the teachings herein, or it may prove convenient to construct a more specialized device to perform the method. The structures of various such systems will be presented as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that the teachings of the present disclosure as described herein may be implemented using various programming languages.

[0090] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0091] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the following claims. Accordingly, the description and drawings should be viewed in an illustrative rather than a restrictive sense.

Claims

1. A memory device, comprising: a memory array comprising a plurality of memory cells addressable by respective addresses grouped into one or more address ranges; and control logic operatively coupled to the memory array to perform operations including: detecting one or more errors associated with one or more stored data items corresponding to a first address range of the one or more address ranges; determining that the number of the one or more stored data items exceeds the number of available redundant memory locations of the first address range; and An association of a first memory address of at least one of the stored data items is remapped from a first address within the first address range to a second address within a second address range of the one or more address ranges, wherein the second address range includes one or more available redundant memory locations.

2. The memory device of claim 1 , wherein the control logic is to perform other operations including: detecting one or more errors associated with one or more stored data items corresponding to the second one of the one or more address ranges; determining, responsive to the association of remapping the first memory address, that the number of the one or more stored data items exceeds the number of available redundant memory locations; and An association of a second memory address of at least one of the stored data items is remapped from a third address within the second address range to a fourth address in a third address range of the one or more address ranges, wherein the third address range includes one or more available redundant memory locations.

3. The memory device of claim 1 , wherein the control logic is to perform other operations including: detecting one or more additional errors associated with the one or more stored data items corresponding to the first address range; determining that the number of the one or more stored data items exceeds the number of available redundant memory locations for the first address range; determining that the number of the one or more stored data items exceeds the number of available redundant memory locations for the second address range; and An association of a second memory address of at least one of the stored data items is remapped from a third address within the first address range to a fourth address in a third address range of the one or more address ranges, wherein the third address range includes one or more available redundant memory locations.

4. The memory device of claim 1 , wherein to determine that the number of one or more data items exceeds the number of available redundant memory locations, the control logic is to perform operations comprising: receiving a memory address associated with the first address range; comparing the received memory address to a second stored memory address indicating a physical location associated with the memory address; and The number of unusable redundant memory locations is determined.

5. The memory device of claim 4, wherein the control logic is to further perform operations comprising: determining a difference between a threshold number of available redundant memory locations and the number of unavailable redundant memory locations; The difference is compared to the number of one or more stored data items, wherein the control logic may determine, in response to the comparison, that the number of one or more stored data items exceeds the number of available redundant memory locations.

6. The memory device of claim 1 , wherein to remap the association of the first memory address from the first address of the one or more stored data items to the second address in the second address range, the control logic is to perform operations comprising: A determination is made that a number of the one or more available redundant memory locations in the second address range equals or exceeds an error number of the one or more errors.

7. The memory device of claim 1, wherein the control logic is configured to remap the association of the first memory address before a predecoder of the memory device receives the first address.

8. The memory device of claim 1, wherein the control logic is configured to remap the association of the first memory address at a predecoder of the memory device.

9. A method comprising: detecting one or more errors associated with one or more stored data items corresponding to a first address range of one or more address ranges, wherein memory cells are addressable by respective addresses of the one or more address ranges; determining that the number of the one or more stored data items exceeds the number of available redundant memory locations of the first address range; and An association of a first memory address of at least one of the stored data items is remapped from a first address within the first address range to a second address within a second address range of the one or more address ranges, wherein the second address range includes one or more available redundant memory locations.

10. The method according to claim 9, further comprising: detecting one or more errors associated with one or more stored data items corresponding to the second one of the one or more address ranges; determining, responsive to the association of remapping the first memory address, that the number of the one or more stored data items exceeds the number of available redundant memory locations; and An association of a second memory address of at least one of the stored data items is remapped from a third address within the second address range to a fourth address in a third address range of the one or more address ranges, wherein the third address range includes one or more available redundant memory locations.

11. The method according to claim 9, further comprising: detecting one or more additional errors associated with the one or more stored data items corresponding to the first address range; determining that the number of the one or more stored data items exceeds the number of available redundant memory locations for the first address range; determining that the number of the one or more stored data items exceeds the number of available redundant memory locations of the second address range; and An association of a second memory address of at least one of the stored data items is remapped from a third address within the first address range to a fourth address in a third address range of the one or more address ranges, wherein the third address range includes one or more available redundant memory locations.

12. The method according to claim 9, further comprising: receiving a memory address associated with the first address range; comparing the received memory address to a second stored memory address indicating a physical location associated with the memory address; and A number of unusable redundant memory locations for the first address range is determined.

13. The method according to claim 12, further comprising: determining a difference between a threshold number of available redundant memory locations and the number of unavailable redundant memory locations; and The difference is compared to the number of one or more stored data items, wherein a determination that the number of one or more stored data items exceeds the number of available redundant memory locations is responsive to the comparison.

14. The method according to claim 9, further comprising: determining that a number of the one or more available redundant memory locations in the second address range satisfies an error number of the one or more errors, wherein remapping the association of the first memory address from the first address of the one or more stored data items to the second address in the second address range is responsive to determining the number of the one or more available redundant memory locations.

15. The method of claim 9, wherein remapping the first memory address from the first address to the second address is before a pre-decoder of a memory device receives the first memory address.

16. The method of claim 9, wherein remapping the first memory address from the first address to the second address is performed at a pre-decoder of a memory device.

17. A memory device comprising: a memory array comprising a plurality of memory cells addressable by respective addresses grouped into one or more address ranges; control logic operatively coupled to the memory array to perform operations including: receiving a memory address; detecting one or more errors associated with the memory address corresponding to a first address range of the one or more address ranges; determining that a number of one or more errors fails to satisfy a number of redundant memory locations of the first address range; and The association of the memory addresses is remapped from a first address within the first address range to a second address associated with a second address range, wherein the second address range includes one or more available redundant memory locations.

18. The memory device of claim 17, wherein the control logic is to further: A determination is made as to whether the number of the one or more available redundant memory locations equals or exceeds an error number of the one or more errors.

19. The memory device of claim 17, wherein the control logic is to perform operations comprising: receiving the memory address; and At least one physical address associated with the memory address is determined to be a redundant memory location within the second address range.

20. The memory device of claim 17, wherein the control logic is configured to remap the association of the first address before a predecoder of the memory device receives the first address.

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