Arm level bad block detection

Abstract

The invention relates to arm level bad block detection. An apparatus includes one or more circuits. The one or more circuits can receive a request associated with a first data set stored by a memory device of a plurality of memory devices. The one or more circuits can generate a first value corresponding to a first portion of a first graph based on information associated with the memory device and the request. The one or more circuits can determine that a first row of a plurality of rows includes a bad block based on a first value of the first portion of the first graph.

Description

Technical Field

[0001] The present disclosure relates to logical drives. Background Art

[0002] A logical drive and / or its components may store data. Summary of the invention

[0003] In one aspect, the present disclosure relates to a system comprising: a memory device comprising a plurality of portions having a plurality of segments located in a plurality of rows of the memory device; and a device in communication with the memory device, the device comprising: one or more circuits configured to: receive a request associated with a first data set stored by the memory device, the first data set being located in a first segment of the plurality of segments, and the first segment being contained in a first portion of the plurality of portions; generate a first value for identifying a first segment of a first graph based on information associated with the memory device and the request; determine, based on the first value of the first segment, that a first row of the plurality of rows contains a bad block, and wherein the first segment is located in the first row of the plurality of rows; identify a first element of a second graph based on an association between the first segment and the first element; determine a first value of the first element to identify one or more first portions of the plurality of portions; and in response to a determination that the one or more first portions contain the first portion, transfer the request based on one or more rules for addressing the bad block.

[0004] In another aspect, the present disclosure relates to a device that communicates with a memory device, the memory device including multiple parts, the multiple parts having multiple segments located in multiple rows of the memory device, the device comprising: one or more circuits configured to: receive a request associated with a first data set stored by the memory device, the first data set being located in a first segment of the multiple segments, and the first segment being included in the first portion of the multiple parts; generate a first value for identifying a first segment of a first diagram based on information associated with the memory device and the request; determine, based on the first value of the first segment, that a first row of the multiple rows includes a bad block, and wherein the first segment is located in the first row of the multiple rows; identify the first element of a second diagram based on an association between the first segment and the first element; determine a first value of the first element to identify one or more first portions of the multiple portions; and in response to a determination that the one or more first portions include the first portion, transfer the request based on one or more rules for addressing the bad block.

[0005] In another aspect, the present disclosure relates to a method, comprising: receiving, by one or more circuits, a request associated with a first data set stored by a memory device, the memory device comprising a plurality of portions, the plurality of portions having a plurality of segments, the plurality of segments being located in a plurality of rows of the memory device, the first data set being located in a first segment of the plurality of segments, and the first segment being contained in the first portion of the plurality of portions; generating, by the one or more circuits, a first value identifying a first segment of a first graph based on information associated with the memory device and the request; determining, by the one or more circuits, based on the first value of the first segment, that a first row of the plurality of rows contains a bad block, and wherein the first segment is located in the first row of the plurality of rows; identifying, by the one or more circuits, a first element of a second graph based on an association between the first segment and the first element; determining, by the one or more circuits, a first value of the first element to identify one or more first portions of the plurality of portions; and diverting, by the one or more circuits, the request based on one or more rules for addressing the bad block in response to a determination that the one or more first portions contain the first portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various objects, aspects, features and advantages of the present disclosure will become more apparent and better understood by reference to the detailed description taken in conjunction with the accompanying drawings, in which like reference characters identify corresponding elements throughout the text. In the drawings, like reference numerals generally indicate identical, functionally similar and / or structurally similar elements.

[0007] Figure 1 is a block diagram of a system for handling bad blocks in a memory device according to some embodiments.

[0008] Figure 2 A system including multiple portions for defining logical drives according to some embodiments.

[0009] Figure 3 is a map for use in identifying bad blocks according to some embodiments.

[0010] Figure 4 is a diagram for use in associated portions of one or more memory devices, according to some embodiments.

[0011] Figure 5 is a diagram for use in identifying portions of one or more memory devices, according to some embodiments.

[0012] Figure 6 is a flow chart of a process for detecting and migrating bad blocks according to some embodiments.

[0013] Figure 7is a flow chart of a process for handling bad blocks according to some embodiments. DETAILED DESCRIPTION

[0014] Some embodiments relate to systems and methods for logical drive bad block detection. A logical drive may include at least one of a physical drive, an arm, and / or a portion. The logical drive may also be implemented within a physical drive array and / or included as a physical drive array. The arm of the logical drive may include at least one stripe and / or segment. The stripe of the logical drive may be oriented and / or otherwise positioned as one or more sequential streams along one or more rows. For example, a first logical drive may include a first arm and a second arm. The first arm and the second arm may include one or more segments positioned as a sequential stream. The sequential stream is contained in one or more rows and / or defines one or more rows. As another example, a first segment of a first arm may be followed by a first segment of a second arm, and the first segment may follow a sequential stream along a first row.

[0015] During one or more circumstances, a physical drive may become damaged. For example, a physical drive may become damaged during the manufacturing process, during various operations, and / or in response to external forces applied to the physical drive. Damage to a physical drive may cause and / or result in the physical drive generating bad blocks. A bad block may refer to and / or include at least one of a bad sector, a portion of a physical drive that no longer provides reliable data storage, and / or an area of ​​a physical drive that has become damaged.

[0016] Processing circuits, packet processors, switches, routers, etc. may interact with physical drives and / or their logical drives. During interaction with the logical drive, bad blocks may be detected on the underlying physical drive. As described herein, the logical drive may include segments directed in a sequential stream. During interaction with the sequential stream of the segments, instances of bad blocks may be recorded in registers. However, recording instances of bad blocks may not include identifying a given portion of the logical drive. Therefore, during subsequent interactions involving the sequential stream, one or more messages and / or requests corresponding to the segments along the sequential stream may be transferred to the bad block manager. The transfer of one or more messages may affect the overall performance of the system (e.g., processing circuits and logical drives) because some of the transferred messages may correspond to portions of the logical drive that do not contain bad blocks.

[0017] Some technical solutions of the present application provide a system including a device that records information to identify a portion of a logical drive that includes a detected bad block. The device may generate and / or update one or more bitmaps. The device may update the bitmap based on the various interactions described herein. For example, the device may update the first bitmap to indicate bad blocks corresponding to various rows and / or sequential streams. The device may also link the second bitmap to the first bitmap. For example, the device may associate a portion and / or segment of the first bitmap with a portion and / or element of the second bitmap. The second bitmap may include values ​​for identifying one or more portions of the logical drive. For example, the second bitmap may identify a first arm and a second arm of the logical drive. During interaction with the logical drive, the device may detect that at least one of the first arm and / or the second arm includes a bad block. The device may set a given value in the first bitmap to indicate that a given row includes a bad block, and the device may set a specified value in the second bitmap to indicate that a given arm includes a bad block.

[0018] During subsequent interactions with the segments of the logical drive, the device may utilize the first bitmap and the second bitmap to identify a given message to be transferred and a given message to be processed. For example, the device may receive a message corresponding to a first segment located in a row having a bad block. Continuing with this example, the device may determine based on the first bitmap that the row contains a bad block. In addition, the device may then check the second bitmap to determine whether the first segment is located in an arm containing a bad block. The device may transfer the message in response to the second bitmap indicating that the arm contains a bad block. The device may process the message in response to the second bitmap indicating that the arm does not contain a bad block.

[0019] The device may communicate with a host. For example, the device may communicate with an application running on a given operating system, and the host may provide one or more requests (e.g., messages) to the device. The host may refer to and / or include a switch, a router, and / or other possible packet delivery devices. The host may refer to and / or include a computing system, a computing device, and / or a computer running and / or executing an application. In some embodiments, the communication between the device and the host may be direct (e.g., the device is directly connected to the host) and / or indirect (e.g., the component receives a signal from the host, and the component provides a signal to the device). The communication between the host and the device may include the device and the host being electrically coupled to each other.

[0020] The system may refer to and / or include at least one of an application specific integrated circuit (ASIC), a capacitive load component, a display driver, a touch screen, a keyboard sensor, a mobile device, a computing device, a computer, a desktop computer, a laptop computer, and / or other possible touch controllers. In some embodiments, the device may refer to and / or include at least one of an integrated circuit, a general purpose processor, a multi-core processor, a software programmable device, a programmable logic controller, and / or other possible circuit systems and / or hardware. Similarly, the functions of the device may be stored as software and / or instructions in a memory, and when the software and / or instructions are executed by a processor, the processor may perform the functions of the device.

[0021] In some embodiments, one or more circuits may refer to and / or include a memory and one or more processors. In some embodiments, the memory may store instructions, and one or more processors may execute the instructions. In some embodiments, the processor executing the instructions may cause the processor to perform operations based on the instructions. In some embodiments, one or more circuits may refer to and / or include at least one of an integrated circuit, a general-purpose processor, a multi-core processor, a software programmable device, a programmable logic controller, and / or other possible circuit systems and / or hardware.

[0022] In some embodiments, a request may refer to and / or include a request to perform a write operation, a request to perform a read operation, a request to access information, a request to provide information, a request to view information, a request to record information, a request to replace information, an update information, and / or at least one of various other possible read and / or write operations.

[0023] In some embodiments, a map may refer to and / or include at least one of a bitmap, an arm map, a bad block map, a table containing one or more bits corresponding to various types of information, a data structure containing one or more rows storing various types of information, an array containing various types of information, a database storing various types of information, and / or various other possible data storage repositories. In some embodiments, a segment may refer to and / or include at least one of a logical location, a stripe, a set of bits, a portion of a storage body, and / or an element contained in an array of a given piece of information stored in a memory. In some embodiments, a memory device may refer to and / or include at least one of a device for storing data and / or computer code, a logical drive, a physical drive, an array of logical drives, a solid-state drive, a hard drive, a hard disk storage device, a RAM, a ROM, a flash memory, a DRAM bank, and / or various types of computer storage media. In some embodiments, a portion of a memory device may refer to and / or include at least one of an arm, a drive, a disk drive, and / or other possible portions, components, and / or elements of a drive device containing a logical drive and / or contained in an array of logical drives.

[0024] In some embodiments, a segment of a graph may refer to and / or include a set of bits, a row within a graph, a column within a graph, and / or at least one of various identifiable aspects of a graph. In some embodiments, an element of a graph may refer to and / or include a set of bits, a row within a graph, a column within a graph, and / or at least one of various identifiable aspects of a graph. In some embodiments, a data set may refer to and / or include a set of information, a binary number, an instruction, a variable, a value, a shared library, and / or program code.

[0025] Some embodiments relate to a system. The system may include a memory device. The memory device may include a plurality of portions. The plurality of portions may have a plurality of segments. The plurality of segments may be located in a plurality of rows of the memory device. The system may also include a device. The device may communicate with the memory device. The device may include one or more circuits. The one or more circuits may receive a request associated with a first data set stored by the memory device. The first data set may be located in a first segment of the plurality of segments. The first segment may be included in a first segment of the plurality of portions. The one or more circuits may also generate a first value for identifying a first segment of a first graph based on information associated with the memory device and the request. The one or more circuits may also determine that a first row of the plurality of rows includes a bad block based on the first value of the first segment, and the first segment may be located in the first row of the plurality of rows. The one or more circuits may also identify the first element based on an association between the first segment and a first element of a second graph. The one or more circuits may also determine a first value of the first element to identify one or more first portions of the plurality of portions, and in response to a determination that the one or more first portions include the first portion, transfer the request based on one or more rules for addressing the bad block.

[0026] In some embodiments, the one or more circuits may also receive a second request associated with a second data set stored by the memory device, the second data set may be located in a second segment of the plurality of segments, the second segment may be located in the first row, and the second segment may be included in a second portion of the plurality of portions. The one or more circuits may also identify the second element of the second graph based on an association between a second segment of the first graph and a second element. The one or more circuits may also determine a first value of the second element to identify one or more second portions of the plurality of portions, and in response to a determination that the second portion is not present in the one or more second portions, perform one or more actions to process the second request.

[0027] In some embodiments, the first map may include a plurality of sections, and the plurality of sections may have corresponding values. The second map may include a plurality of elements, and the plurality of elements may have corresponding values. The one or more circuits may also update at least one of the plurality of sections to identify a second row of the plurality of rows that includes the second bad block, and update at least one of the plurality of elements to identify one or more second portions of the plurality of portions in response to detection of a second bad block.

[0028] In some embodiments, the first row may include a second segment of the plurality of segments, the second segment may be included in a second portion of the plurality of portions. The first row may also include a third segment of the plurality of segments, the third segment may be included in a third portion of the plurality of portions. The one or more circuits may also perform one or more actions in response to a determination that the second portion is not present in the one or more first portions to process a second request associated with a second data set located in the second segment, and in response to a determination that the one or more first portions include the third portion, to transfer a third request associated with a third data set located in the third segment.

[0029] In some embodiments, the one or more circuits may receive a second request associated with a second data set stored by the memory device, the second data set may be located in a second segment of the plurality of segments, the second segment may be included in a second segment of the plurality of portions, the second segment may be located in a second segment of the plurality of rows, and the second row may include at least one bad block. The one or more circuits may also receive a third request associated with a third data set stored by the memory device, the third data set may be located in a third segment of the plurality of segments, the third segment may be included in a third segment of the plurality of portions, and the third segment may be located in the second row. The one or more circuits may also determine a second value of a second element of the second map to identify one or more second segments of the plurality of portions. The one or more circuits may also transfer the second request based on the one or more rules in response to a determination that the one or more second segments include the second segment, and transfer the third request based on the one or more rules in response to a determination that the one or more second segments include the third segment.

[0030] In some embodiments, a second request may be associated with a second data set stored by the memory device. The second data set may be located in a second segment of the plurality of segments, and the second request may be processed by the one or more circuits, wherein the second segment is located in the first row of the plurality of rows.

[0031] In some embodiments, the second request may be associated with a second data set stored by the memory device. The second data set may be located in a second segment of the plurality of segments. The second segment may be included in a second portion of the plurality of portions, and the second request may be transferred by the one or more circuits in response to a determination that the one or more first portions include the second portion.

[0032] In some embodiments, in response to the determination that the one or more first portions include the first portion, transferring the request based on the one or more rules for addressing the bad block may include identifying, by the one or more circuits, a given segment of the multiple segments to locate the first data set, or providing, by the one or more circuits, the first data set to a given memory device of a plurality of memory devices.

[0033] Some embodiments relate to a device. The device may communicate with a memory device. The memory device may include a plurality of portions. The plurality of portions may have a plurality of segments located in a plurality of rows of the memory device. The device may include one or more circuits. The one or more circuits may receive a request associated with a first data set stored by the memory device, the first data set may be located in a first segment of the plurality of segments, and the first segment may be included in a first segment of the plurality of portions. The one or more circuits may also generate a first value for identifying a first segment of a first graph based on information associated with the memory device and the request. The one or more circuits may also determine that a first row of the plurality of rows includes a bad block based on a first value of the first segment, and the first segment may be located in the first row of the plurality of rows. The one or more circuits may also identify a first element of a second graph based on an association between the first segment and the first element. The one or more circuits may also determine a first value of the first element to identify one or more first portions of the plurality of portions, and in response to a determination that the one or more first portions include the first portion, transfer the request based on one or more rules for addressing the bad block.

[0034] In some embodiments, the one or more circuits may receive a second request associated with a second data set stored by the memory device, the second data set may be located in a second segment of the plurality of segments, the second segment may be located in the first row, and the second segment may be included in a second segment of the plurality of portions. The one or more circuits may also identify the second element based on an association between a second segment of the first graph and a second element of the second graph. The one or more circuits may also determine a first value of the second element to identify one or more second segments of the plurality of segments, and in response to a determination that the second segment is not present in the one or more second segments, perform one or more actions to process the second request.

[0035] In some embodiments, the first map may include a plurality of sections, and the plurality of sections may have corresponding values. The second map may include a plurality of elements, and the plurality of elements may have corresponding values. The one or more circuits may also update at least one of the plurality of sections to identify a second row of the plurality of rows that includes the second bad block, and update at least one of the plurality of elements to identify one or more second portions of the plurality of portions in response to detection of a second bad block.

[0036] In some embodiments, the first row may include a second segment of the plurality of segments, the second segment may be included in a second portion of the plurality of portions. The first row may also include a third segment of the plurality of segments, the third segment may be included in a third portion of the plurality of portions. The one or more circuits may also perform one or more actions in response to a determination that the second portion is not present in the one or more first portions to process a second request associated with a second data set located in the second segment, and in response to a determination that the one or more first portions include the third portion, to transfer a third request associated with a third data set located in the third segment.

[0037] In some embodiments, the one or more circuits may receive a second request associated with a second data set stored by the memory device, the second data set may be located in a second segment of the plurality of segments, the second segment may be included in a second segment of the plurality of portions, the second segment may be located in a second segment of the plurality of rows, and the second row may include at least one bad block. The one or more circuits may also receive a third request associated with a third data set stored by the memory device, the third data set may be located in a third segment of the plurality of segments, the third segment may be included in a third segment of the plurality of portions, and the third segment may be located in the second row. The one or more circuits may also determine a second value of a second element of the second map to identify one or more second segments of the plurality of portions. The one or more circuits may also transfer the second request based on the one or more rules in response to a determination that the one or more second segments include the second segment, and transfer the third request based on the one or more rules in response to a determination that the one or more second segments include the third segment.

[0038] In some embodiments, a second request may be associated with a second data set stored by the memory device. The second data set may be located in a second segment of the plurality of segments, and the second request may be processed by the one or more circuits, wherein the second segment is located in the first row of the plurality of rows.

[0039] In some embodiments, the second request may be associated with a second data set stored by the memory device. The second data set may be located in a second segment of the plurality of segments. The second segment may be included in a second portion of the plurality of portions, and the second request may be transferred by the one or more circuits in response to a determination that the one or more first portions include the second portion.

[0040] In some embodiments, in response to the determination that the one or more first portions include the first portion, transferring the request based on the one or more rules for addressing the bad block may include identifying, by the one or more circuits, a given segment of the multiple segments to locate the first data set, or providing, by the one or more circuits, the first data set to a given memory device of a plurality of memory devices.

[0041] Some embodiments relate to a method. The method may include receiving, by one or more circuits, a request associated with a first data set stored by a memory device. The memory device may include a plurality of portions, the plurality of portions may have a plurality of segments, the plurality of segments may be located in a plurality of rows of the memory device, the first data set may be located in a first segment of the plurality of segments, and the first segment may be included in the first portion of the plurality of portions. The method may also include generating, by the one or more circuits, a first value identifying a first segment of a first graph based on information associated with the memory device and the request. The method may also include determining, by the one or more circuits, based on the first value of the first segment, that a first row of the plurality of rows includes a bad block, and the first segment may be located in the first row of the plurality of rows. The method may also include identifying, by the one or more circuits, a first element of a second graph based on an association between the first segment and the first element. The method may also include determining, by the one or more circuits, a first value of the first element to identify one or more first portions of the plurality of portions, and transferring, by the one or more circuits, the request based on one or more rules for addressing the bad block in response to a determination that the one or more first portions include the first portion.

[0042] In some embodiments, the method may also include receiving, by the one or more circuits, a second request associated with a second data set stored by the memory device. The second data set may be located in a second segment of the plurality of segments, the second segment may be located in the first row, and the second segment may be included in a second portion of the plurality of portions. The method may also include identifying, by the one or more circuits, the second element based on an association between a second segment of the first graph and a second element of the second graph. The method may also include determining, by the one or more circuits, a first value of the second element to identify one or more second portions of the plurality of portions, and performing, by the one or more circuits, in response to a determination that the second portion is not present in the one or more second portions, one or more actions to process the second request.

[0043] In some embodiments, the first map may include a plurality of sections having respective values, and the second map may include a plurality of elements having respective values. The method may also include updating, by the one or more circuits, at least one of the plurality of sections in response to detection of a second bad block to identify a second row of the plurality of rows that includes the second bad block, and updating, by the one or more circuits, at least one of the plurality of elements to identify one or more second portions of the plurality of portions.

[0044] In some embodiments, the first row may include a second segment of the plurality of segments, the second segment may be included in a second portion of the plurality of portions, the first row may include a third segment of the plurality of segments, and the third segment may be included in a third portion of the plurality of portions. The method may also include performing, by the one or more circuits, one or more actions in response to a determination that the second portion is not present in the one or more first portions to process a second request associated with a second data set located in the second segment, and transferring, by the one or more circuits, a third request associated with a third data set located in the third segment in response to a determination that the one or more first portions include the third portion.

[0045] Figure 1 A block diagram of a system 100 is depicted in accordance with some embodiments. System 100 may include a host 105, a controller 110, and a logical drive 145. In some embodiments, controller 110 may include and / or be implemented as a device described herein. In some embodiments, controller 110 may perform operations similar to the operations of the devices described herein. In some embodiments, host 105 may include a host described herein. In some embodiments, logical drive 145 may include and / or be implemented as a logical drive described herein.

[0046] The controller 110 may communicate with the host 105. For example, the controller 110 and the host 105 may exchange messages with each other and / or communicate in other ways. For example, the host 105 may provide one or more input / output (I / O) messages to the controller 110. The I / O messages are Figure 1 145. The controller 110 may communicate with the logical drive 145. For example, the controller 110 may access the logical drive 145 and / or provide information to the logical drive 145. In some embodiments, the controller 110 may perform and / or otherwise perform one or more operations to interact with the logical drive 145. For example, the controller 110 may perform a given action based on and / or in response to receiving one or more I / O messages. As another example, the controller may perform one or more first operations in response to receiving a write request (e.g., an I / O message). Continuing with this example, the controller 110 may perform one or more second operations in response to receiving a read request (e.g., an I / O message).

[0047] The controller 110 includes a processing circuit 115 and a bad block manager 140. The processing circuit 115 and / or circuit 115 may refer to and / or include at least one of the processing circuits, circuit systems, circuits, and / or components described herein. The processing circuit 115 includes at least one processor 120 and a memory 125. The memory 125 may be and / or include one or more devices (e.g., RAM, ROM, flash memory, hard disk storage devices) for storing data and / or computer code. The data and / or computer code may be executed to complete and / or facilitate the various processes described herein. The memory 125 may be or include non-transitory volatile memory, non-volatile memory, and non-transitory computer storage media. The memory 125 may include a database component, an object code component, a script component, or any other type of information structure for supporting the various activities and information structures described herein.

[0048] The memory 125 may be communicatively coupled to the processor 120, and the memory 125 may include computer code or instructions (e.g., firmware or software) for performing one or more processes described herein. The processor 120 may be implemented as one or more application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), a set of processing components, or other suitable electronic processing components. The memory 125 may store one or more instructions that, when executed by the processor 120, cause the processor 120 to perform one or more of the various operations described herein. The memory 125 may store a bad block bitmap 130 and an arm bitmap 135. The bad block bitmap 130 and / or the arm bitmap 135 may refer to and / or include at least one of the various figures described herein.

[0049] The bad block manager 140 may perform one or more actions to handle the bad block. For example, the processing circuit 115 may transfer one or more I / O messages to the bad block manager 140. In some embodiments, the processing circuit 115 may transfer the message corresponding to the portion of the logical drive 145 that includes the bad block. In some embodiments, the bad block manager 140 may address the bad block based on one or more rules. For example, the bad block manager 140 may identify and / or otherwise determine one or more subsequent portions and / or segments of the logical drive 145 for executing the one or more I / O messages. As another example, the bad block manager 140 may identify portions and / or segments of the logical drive 145 that are free and / or otherwise include unutilized memory space.

[0050] In some embodiments, the bad block manager 140 may utilize the free portions and / or free segments to execute and / or process one or more I / O messages. For example, the bad block manager 140 may locate one or more data sets in the portions and / or segments of the logical drive 145. As another example, the bad block manager 140 may identify a given segment of the memory device, and the bad block manager 140 may locate a given data set in the given segment. In some embodiments, the processing circuit 115 may perform functions similar to those of the bad block manager 140. For example, the processing circuit 115 may address bad blocks based on one or more rules. As another example, the processing circuit 115 may identify a free segment located in the logical drive 145.

[0051] The logical drive 145 may include one or more logical drives 145. For example, the logical drive 145 may include multiple logical drives. As another example, the logical drive 145 may include an array of physical disk drives. In some embodiments, the logical drive 145 may include a redundant array of independent disks (RAID) array. The logical drive 145 may include multiple parts. For example, the logical drive 145 may include a first arm (e.g., a first part) and a second arm (e.g., a second part). In some embodiments, the multiple parts of the logical drive 145 may include the parts described herein.

[0052] In some embodiments, each portion of the logical drive 145 may include one or more segments. For example, a first arm of the logical drive 145 may include a first segment and a second segment. In some embodiments, a segment may refer to and / or include a stripe. For example, a first segment may be located in a first row, and the first segment may be implemented as a stripe. In some embodiments, one or more segments may be located in a row. In some embodiments, a row of a memory device may include multiple segments. For example, a row may include a first segment and a second segment. In some embodiments, a row may include segments associated with various portions of the logical drive 145. For example, the logical drive 145 may include a first portion and a second portion. Continuing with this example, both the first portion and the second portion may include a first segment. In addition, a first segment may be located in a given row of a memory device.

[0053] Processing circuit 115 may receive one or more requests. For example, processing circuit 115 may receive one or more I / O messages. As another example, processing circuit 115 may receive a first request and a second request. The requests may be associated with one or more data sets stored by a memory device. For example, the first request may be associated with a first data set stored by logical driver 145 (e.g., a memory device), and the second request may be associated with a second data set stored by logical driver 145.

[0054] In some embodiments, processing circuit 115 may receive requests continuously and / or semi-continuously. For example, processing circuit 115 may receive a first request, followed by a second request, and then followed by a third request. In some embodiments, processing circuit 115 may receive a first request, and processing circuit 115 may then receive a second request after a given amount of time. Data sets associated with one or more requests may be located and / or otherwise associated with one or more segments. For example, a first request may be associated with a first data set. Continuing with this example, the first data set may be located in a first segment. As another example, a second request may be associated with a second data set, and the second data set may be located in a second segment. In some embodiments, one or more segments may be included in a first portion. For example, both the first segment and the second segment may be located in a first portion of logical drive 145. As another example, the first segment may be located in the first portion, and the second segment may be located in the second portion. Continuing with this example, the first portion and the second portion may be included in a first logical drive 145.

[0055] In some embodiments, the data set described herein may be located and / or associated with one or more rows of memory. For example, the logical drive 145 may include a first portion, and the first portion may include a first segment. Continuing this example, the first segment may be located in the first row of memory. As another example, the first segment may be located in the first row, and the second segment may be located in the second row. As described herein, the presence of a bad block in a given row of memory may cause messages associated with the segments of the given row to be transferred. Even when one or more portions do not contain bad blocks, the transfer of messages may occur. For example, the first row of memory may have a bad block. Continuing this example, the bad block may be located in the first portion. Messages associated with the segments located in the second portion may be transferred based on the first row containing the bad block. In this example, the processing of messages associated with the second portion may be negatively affected because it may be more time-consuming to transfer messages relative to simply executing the messages.

[0056] Processing circuit 115 may generate one or more values ​​to identify one or more segments and / or one or more elements of one or more graphs. For example, processing circuit 115 may generate a first value to identify a first segment of a first graph. As another example, processing circuit 115 may generate a second value to identify a second segment of the first graph. In some embodiments, one or more segments and / or one or more elements may include portions of a graph. For example, a first graph may include a first portion. Continuing with this example, a first portion may include a first element. In some embodiments, processing circuit 115 may generate one or more values ​​based on information associated with a request and a memory device. For example, processing circuit 115 may generate a first value to identify a first segment of a first graph based on information associated with a memory device and a request. As another example, processing circuit 115 may generate a first value to identify a first portion of a first graph.

[0057] In some embodiments, the first map may refer to and / or include at least one of the various maps described herein. For example, the first map may refer to the bad block bitmap 130. In some embodiments, the value identifying the segment of the first map may refer to and / or include a hash number. In some embodiments, one or more segments of the first map may refer to and / or include one or more bits. For example, the bad block bitmap 130 may include a first segment (e.g., a first portion) and a second segment. Continuing with this example, the first segment may include bits 0 to 4 of the bad block bitmap 130. In some embodiments, one or more values ​​of the segment may indicate the presence of a bad block. For example, the first segment may include three bits, and the bits being set (e.g., set to 1) may indicate the presence of a bad block.

[0058] In some embodiments, processing circuit 115 may generate one or more values ​​to identify one or more segments in response to receiving one or more requests. For example, processing circuit 115 may generate a first value to identify a first segment of a first graph based on a first request. Continuing with this example, processing circuit 115 may generate a second value to identify a second segment of the first graph based on a second request.

[0059] Processing circuitry 115 may determine that one or more rows include bad blocks. For example, processing circuitry 115 may determine that a first row includes a bad block. In some embodiments, processing circuitry 115 may determine that a first row includes a bad block based on a first value of a first segment of a first graph. For example, the first value may be associated with a bit having a value (e.g., 0 or 1) indicating the presence of a bad block. A first row may include and / or otherwise be associated with one or more segments of a logical drive 145. For example, a first row may include a first segment of one or more logical drives 145. As another example, a first row may include a first segment located in a first portion (e.g., a first arm) of a logical drive 145, and a first row may include a second segment located in a second portion of a logical drive 145.

[0060] Processing circuit 115 may identify one or more elements of the second figure. For example, processing circuit 155 may identify a first element and a second element of the second figure. In some embodiments, one or more elements of the second figure may be associated with the first figure. For example, a first section of the first figure may be linked to a first element of the second figure. Continuing with this example, the first section may have a given placement in the first figure, and the first element may have a similar placement in the second figure. In addition, processing circuit 115 may detect the placement of the first section. In some embodiments, processing circuit 115 may identify the first element based on the placement of the first section. As another example, the first section of the first figure may include a given position that identifies the first element of the second figure. As another example, the placement of the first section in the first figure may identify a given row of the second figure. In some embodiments, the second figure may refer to one or more of the various figures described herein. For example, the second figure may refer to arm position diagram 135.

[0061] Processing circuit 115 may determine one or more values ​​of one or more elements of the second graph. For example, processing circuit 115 may determine a first value of a first element of the second graph. As another example, processing circuit 115 may determine a first value of a second element of the second graph. In some embodiments, the value of the element may identify one or more portions. For example, the first element of the second graph may represent a first arm and a second arm of logical drive 145. Continuing with this example, the first element may have a first value. In some embodiments, the first value may indicate that at least one of the first arm and / or the second arm includes a bad block. In some embodiments, the elements of the second graph may identify one or more portions. For example, the first element of the second graph may identify one or more portions of logical drive 145.

[0062] In some embodiments, the elements of the second graph may include one or more bits. The bits may include various values ​​(e.g., 0 or 1) that may indicate and / or identify the presence of a bad block. For example, the logical drive 145 may include 8 portions (e.g., 8 arms). Continuing with this example, a given bit of the second graph may represent arm 0 (e.g., the first portion of the logical drive 145), and a second given bit of the second graph may represent arm 1 (e.g., the second portion of the logical drive 145). In some embodiments, a given bit may be set to 1 to indicate that a bad block exists in arm 0.

[0063] Processing circuit 115 may transfer one or more requests. For example, processing circuit 115 may transfer requests associated with a portion containing a bad block. As another example, processing circuit 115 may receive a first message. In some embodiments, the first message may be associated with a first data set. Continuing with this example, the first data set may be located in a first segment. The first segment may be located in an arm containing a bad block. In some embodiments, processing circuit 115 may detect that the arm contains a bad block based on a given element of the second graph. In addition, processing circuit 115 may transfer the first message.

[0064] In some embodiments, processing circuit 115 may transfer the request based on one or more rules for addressing bad blocks. For example, processing circuit 115 may transfer in response to a determination that the one or more first portions include the first portion. In this example, the one or more first portions may be identified by a given bit (e.g., a given element) of the second graph. In some embodiments, the one or more first portions may include the first portion. The second graph may have a given value to indicate that the one or more portions include a bad block. For example, a bit representing the one or more first portions may be set to 1. Processing circuit 115 may transfer the request to bad block manager 140. For example, processing circuit 115 may provide an I / O request to bad block manager 140, and bad block manager 140 may handle the I / O request.

[0065] Figure 2 A system 200 is depicted according to some embodiments. System 200 includes one or more arrays 203. Arrays 203 may refer to and / or include logical drivers 145. For example, a first array 203 may include a first logical driver 145, and a second array 203 may include a second logical driver 145. Arrays 203 include portions 205 and / or arms 205. Arms 205 may refer to and / or include portions of a memory device described herein. For example, a first arm 205 may include a first portion of a memory device. Arms 205 include one or more segments (in Figure 2 0, 1, 2, N-2, and N-1 in the memory). For example, the first segment of the first arm 205 may refer to and / or include stripe 0. The corresponding stripes of the corresponding arm may be included in the corresponding row of the memory. For example, Figure 2 It is illustrated that for each corresponding arm 205 , stripe 0 is included in the first row 210 .

[0066] In some embodiments, row 210 may refer to and / or include a row as described herein. For example, first row 210 may include a first row of a memory device. In some embodiments, first row 210 may include a bad block. In some embodiments, a value of a given section of bad block bitmap 130 may identify that first row 210 includes a bad block. In some embodiments, processing circuit 115 may receive a first request associated with a first data set located in stripe 0 (e.g., a first segment) of first arm 205. Stripe 0 of first arm 205 may be located in first row 210 (e.g., a row with bad blocks). In some embodiments, processing circuit 115 may generate a value to identify a section of bad block bitmap 130. The value of the section may indicate that a bad block exists in first row 210. For example, a section may include one or more bits, and a bit may be set to a given value (e.g., 0 or 1). In some embodiments, a given value may indicate that a bad block exists in first row 210. For example, a given section of bad block bitmap 130 may be associated with first row 210. Continuing with this example, a given value for the sector may indicate that the first row 210 contains bad blocks.

[0067] Figure 3 A map 300 is depicted according to some embodiments. In some embodiments, the map 300 may refer to and / or include the bad block bitmap 130. In some embodiments, the map 300 may include at least one of the various maps described herein. The map 300 includes one or more portions 305 and / or one or more sections 305. Figure 3 An example of a portion 305 corresponding to one or more bits 305 is depicted. For example, a first portion 305 may correspond to bit 0. In some embodiments, a given portion 305 may correspond to one or more bits. For example, a first portion 305 may correspond to bit 0 and bit 1. Bits 305 are shown to include and / or correspond to a hash value 310. For example, a first bit 305 and / or a set of first bits 305 may identify a first hash value 310. In some embodiments, a hash value 310 may refer to and / or include one or more values. In some embodiments, a hash value 310 may identify one or more sections of a first map. For example, the processing circuit 115 may identify a first section of the bad block bitmap 130 based on the first hash value 310. In some embodiments, the hash value 310 may include values ​​of one or more sections. For example, a first hash value 310 may identify a first section, and the first hash value 310 may be a first value for the first section. Continuing with this example, the first hash value 310 may have a first value in response to the first row having a bad block, and the first value 310 may have a second value in response to the first row not containing a bad block.

[0068] In some embodiments, processing circuit 115 may update one or more portions of map 300 in response to detection of a bad block. For example, processing circuit 115 may update a given hash value 310 from a first value (indicating that a given row does not contain a bad block) to a second value (indicating that a given row contains a bad block). The updated hash value 310 may identify that a given row contains a bad block. For example, processing circuit 115 may set (e.g., to 1) a given bit when a given row has a bad block, and processing circuit 115 may zero (e.g., set to 0) a given bit when a given row does not contain a bad block.

[0069] Figure 4 A diagram 400 is depicted according to some embodiments. The diagram includes one or more bits 405. In some embodiments, the bits 405 may refer to and / or include an element of a second diagram described herein. For example, the first bit 405 may include a first element. In some embodiments, the diagram 400 may refer to and / or include at least one of the diagrams described herein. For example, the diagram 400 may refer to the arm bitmap 135. Although Figure 4Graph 400 is shown to include eight bits (e.g., bits 0 to 7), but graph 400 may include various numbers of bits. For example, graph 400 may include five bits. As another example, graph 400 may include 15 bits. In some embodiments, the number of bits 405 may correspond to and / or be based on the number of portions of a memory device (e.g., logical drive 145). For example, logical drive 145 may include eight portions, and graph 400 may therefore include eight bits (e.g., bits 0 to 7). In some embodiments, corresponding bits of graph 400 may represent corresponding portions of logical drive 145. For example, first bit 405 may represent a first arm and / or first portion of a first logical drive 145.

[0070] In some embodiments, the bits 405 may represent one or more arms of the logical drive 145. For example, bit 0 (eg, the first bit 405) is shown as including set 410. Figure 4 Set 410 is shown to include arm 0, arm 8, arm 16, and arm 24. As another example, diagram 400 may include a second set 410. Continuing with this example, second set 410 may include and / or represent one or more arms of a logical drive. In some embodiments, second set 410 may represent the arms of bit 1 (e.g., arm 1, arm 9, arm 17, arm 25). In some embodiments, arm 0 may refer to the first arm of the first logical drive 145, arm 8 may refer to the ninth arm of the first logical drive 145, arm 16 may refer to the seventeenth arm of the first logical drive 145, and arm 24 may refer to the twenty-fifth arm of the first logical drive 145. Although Figure 4 A set 410 is depicted as including four arms associated with the logical drive 145 , but the set 410 may include various numbers of arms. For example, the set 410 may include 10 arms associated with the logical drive 145 .

[0071] Graph 400 may provide some technical solutions described herein. For example, graph 400 is shown as representing and / or including 32 arms, and a given bit 405 is shown as representing four arms of a logical drive 145. In some embodiments, graph 400 may represent and / or correspond to a logical drive 145 having various numbers of arms and / or portions. For example, graph 400 may represent and / or include 100 arms for a given logical drive 145. In some embodiments, a given bit 405 may represent various numbers of arms. For example, graph 400 may include five bits 405, and each bit (e.g., bits 0 to 4) may represent six arms (e.g., 30 arms in total). As another example, graph 400 may include 10 bits 405, and each bit (e.g., bits 0 to 9) may represent two arms (e.g., 20 arms in total).

[0072] As described herein, the logical drive 145 may include segments that span and / or are included in one or more rows, and a bad block in a given row may cause I / O messages associated with the one or more segments of the given row to be diverted. The diagram 400 page may prevent I / O messages from being diverted even when the I / O messages are associated with a row having a bad block. For example, when only a given portion of the logical drive 145 includes a bad block, the diagram 400 may prevent I / O messages associated with one or more portions of the logical drive 145. Continuing with this example, the diagram 400 may prevent I / O messages associated with portions of the logical drive 145 that do not contain bad blocks by recording the portion (e.g., arm) having the bad block in bit 405. The processing circuit 115 recording the portion having the bad block in the diagram 400 may cause the diversion of I / O messages associated with the portion having the bad block while also processing I / O messages contained in the same row.

[0073] As a non-limiting example, a system may include a logical drive 145 having 32 arms. In this non-limiting example, each arm (e.g., arms 0-31) may include at least one segment within a given row. Continuing with this non-limiting example, a segment may refer to a stripe (e.g., stripe 0) within row 210. In this non-limiting example, processing circuitry 115 may detect, via bad block bitmap 130 and / or map 300, that a given I / O message (e.g., a request) is associated with a segment included in a row (e.g., row 210) having a bad block. Continuing with this non-limiting example, processing circuitry 115 may divert a given I / O message without map 400 even if the bad block is located on an arm that is not associated with the given I / O message. In this non-limiting example, this may result in an increased amount of time to process the given I / O message because the portion associated with the given I / O message does not contain the bad block, yet the given I / O message is still diverted. Continuing with this non-limiting example, subsequent I / O messages associated with a given row having bad blocks may be diverted even when the subsequent I / O messages are associated with a portion that does not contain bad blocks.

[0074] In the non-limiting example described above, the diversion of I / O messages associated with a portion (e.g., an arm) of the logical drive 145 that does not contain a bad block may be referred to as false diversions and / or false diverts (e.g., the I / O message is diverted even when the portion of the logical drive 145 associated with the I / O message does not contain a bad block). Diagram 400 may provide some of the technical solutions described herein by reducing, limiting, and / or preventing the occurrence of false diversions.

[0075] In some embodiments, processing circuit 115 may detect that a portion (e.g., a given arm) has a bad block. Processing circuit 115 may record in map 400 that the portion has a bad block. For example, processing circuit 115 may detect that arm 0 has a bad block, and processing circuit 115 may then set (e.g., set to 1) a corresponding bit in map 400 to reflect the presence of the bad block. Processing circuit 115 recording the presence of the bad block in map 400 may prevent the transfer of I / O messages associated with rows having bad blocks. For example, processing circuit 115 may detect via bad block bitmap 130 that an I / O message is associated with a row having a bad block. Continuing with this example, processing circuit 115 may then check map 400 to see if the portion associated with the I / O message contains a bad block before only transferring the I / O message. In some embodiments, processing circuit 115 may process the I / O message in response to determining that map 400 indicates that the portion does not contain a bad block. Continuing with this example, map 400 prevents the transfer of I / O messages associated with the portion that does not contain a bad block.

[0076] As a non-limiting example, the system may include 32 arms, and each arm may include a single segment located in a single row (e.g., a row includes 32 segments located in respective arms of the 32 arms). In this non-limiting example, the row including 32 segments (e.g., one segment per 32 arms) may include a bad block. Continuing with this non-limiting example, the processing circuitry 115 may receive an I / O message associated with the 32 segments. In this non-limiting example, the processing circuitry 115 may receive a single I / O message for each segment (e.g., 32 I / O messages). Continuing with this non-limiting example, the processing circuitry 115 may detect that the row including the 32 segments has a bad block, and the processing circuitry 115 may divert each of the 32 I / O messages.

[0077] In the non-limiting example described above, the graph 400 can reduce the number of I / O messages transferred for a given row with a bad block to 12.5%. For example, the graph 400 can reduce the number of I / O messages transferred from 32 (e.g., 32 I / O messages) to 4 I / O messages (e.g., I / O messages associated with one or more elements of a given position in the graph 400). As described above (and not limited in any way), if Figure 4, diagram 400 includes 8 bits, and each bit is shown as being associated with 4 arms of a 32-arm system. For example, bit 0 is shown as being associated with arms 0, 8, 16, and 24. Continuing with this example, processing circuit 115 may set bit 0 (e.g., to 1) to indicate that at least one of the arms (e.g., arms 0, 8, 16, 24) includes a bad block. In some embodiments, arms 0, 8, 16, and 24 may refer to and / or include one or more portions described herein. Processing circuit 115 indicating that at least one of arms 0, 8, 16, and 24 includes a bad block may reduce the number of I / O messages transferred from 32 to 4. For example, processing circuit 115 may receive 32 I / O messages (simultaneously, sequentially, one after another, etc.), and processing circuit 115 may detect that the row associated with the 32 I / O messages includes a bad block. Continuing with this example, processing circuit 115 may then examine diagram 400 and determine that bit 0 is set. Furthermore, the processing circuit 115 may then process 28 of the 32 I / O messages (e.g., I / O messages associated with arms other than arm 0, 8, 16, or 24), and the processing circuit 115 may then transfer 4 of the 32 I / O messages (e.g., I / O messages associated with arm 0, 8, 16, or 24).

[0078] Figure 5 Depicted is a diagram 500 according to some embodiments. In some embodiments, diagram 500 may refer to and / or include at least one of the diagrams described herein. For example, diagram 500 may include arm bitmap 135. In some embodiments, diagram 500 may refer to and / or include diagram 400. In some embodiments, diagram 500 may be an extension and / or implementation of diagram 400. For example, diagram 400 provides an example of how bits may represent an arm of a logical drive 145, and diagram 500 may include an example of an arm bitmap 135 including one or more values. Diagram 500 includes bit 405, hit column and / or hit 505, and row number column 510 and row number 510. Although Figure 5 Map 500 is shown including bits 405, but the number of bits and / or information associated with the bits may be different than the number of bits 405. For example, map 500 may include 10 bits 405, and bits 405 may correspond to information other than information identifying a bad block.

[0079] In some embodiments, row number 510 may be associated with and / or otherwise correspond to a given row of map 300, a given sector, a given sector of bad block bitmap 130, a given sector of first map, and / or a given I / O message. For example, row 0 may be associated with a given bit 305 and / or a given hash value 310 of map 300. Continuing with this example, processing circuit 115 may determine a hash value based on the request, and the hash value may include and / or correspond to row 0. In other words, a given row number of row number 510 may be linked to a given bit and / or hash value of map 300.

[0080] In some embodiments, hit 505 may represent and / or otherwise indicate that one or more portions of logical drive 145 contain a bad block. For example, bits 405 associated with row 0 are shown as all 0s, and thus, the hit is marked as no (e.g., none of the portions contain a detected bad block). As another example, bit 1 of row 1 is shown as set to 1, and the hit is marked as yes (e.g., a portion contains a detected bad block). As a non-limiting example, bit 1 may indicate at least one of arms 1, 9, 17, and / or 25 (e.g., Figure 4 Continuing with this example, processing circuitry 115 may divert I / O messages associated with row 1 and at least one of arms 1, 9, 17, and / or 25. Processing circuitry 115 may process I / O messages that are not associated with arms 1, 9, 17, and / or 25.

[0081] Figure 6 is a flow chart of a process 600 for detecting and migrating bad blocks according to some embodiments. Figure 6 Several steps of process 600 are shown to be performed by controller 110, but at least one step of process 600 may be performed by one or more devices described herein. For example, various processing circuits described herein may perform at least one step of process 600.

[0082] At step 605, a determination may be made as to whether the I / O message is included in the transfer set. For example, the controller 110 may receive the I / O message. The controller 110 may determine whether the I / O message is associated with a logical drive 145 having a bad block. For example, the I / O message may be associated with information stored by a given logical drive 145, and the transfer set may be linked to the given logical drive 145. Continuing with this example, the controller 110 may determine that the I / O message is included in the transfer set. The process 600 may proceed to step 630 in response to the controller 110 determining that the I / O message is not present in the transfer set. The process 600 may proceed to step 610 in response to the controller 110 determining that the I / O message is included in the transfer set.

[0083] A hash value may be calculated from the logical drive and row number at step 610. For example, controller 110 may determine a hash value based on the logical drive 145 associated with the I / O message and a given row containing a segment storing information associated with the I / O message.

[0084] In some embodiments, processing circuit 115 may generate one or more values ​​(e.g., one or more hash values). For example, processing circuit 115 may generate a value to identify a segment of a first map based on information associated with a memory device and an I / O message. In some embodiments, the first map may refer to and / or include bad block bitmap 130. The hash value generated in step 610 may refer to and / or include hash value 310. Process 600 may proceed to step 615 in response to generating a hash value in step 610.

[0085] At step 615, a determination is made as to whether a bad block map (BBM) is set. For example, the controller 110 may determine, based on the hash value generated in step 610, that the value of the hash value indicates that the I / O message is associated with a row of the memory device that includes bad blocks. As another example, the processing circuit 115 may determine that the value of the hash value generated in step 610 includes and / or indicates a bad block in a given row. In some embodiments, the BBM may refer to and / or include a bad block bitmap 130. For example, the hash value generated in step 610 may include one or more bits in the bad block bitmap 130, and the value (e.g., 0 or 1) may indicate a bad block in a given row. The process 600 may proceed to step 630 in response to a determination that the BBM is not set (e.g., the I / O message is associated with a row that does not include bad blocks). The process 600 may proceed to step 620 in response to a determination that the BBM is set.

[0086] At step 620, a determination is made as to whether the arm BBM is set. For example, the value determined in step 615 may be linked and / or associated with the arm BBM. The arm BBM may refer to and / or include the arm bitmap 135. The controller 110 may determine that the arm BBM is set in response to identifying and / or detecting that an element of the arm BBM indicates that the I / O message is associated with an arm having a bad block. For example, the controller 110 may determine that the bit 405 of the diagram 500 is set to 1 (e.g., the arm contains a bad block). As another example, the controller 110 may determine that the bit 405 is set to 0 (e.g., the arm does not contain a bad block). Continuing this example, the I / O message may be associated with a row of a memory containing a bad block, but the portion associated with the I / O does not contain a bad block. The process 600 may proceed to step 625 in response to the determination that the arm BBM is set. The process may proceed to step 630 in response to the determination that the arm BBM is not set.

[0087] At step 625, the logical drive bad block manager (LDBBM) may process the I / O message that may have been transferred in step 620. For example, the controller 110 may transfer the I / O message in response to the controller 110 determining in step 620 that an element of the arm BBM is set. The controller 110 transferring the I / O message after step 620 (e.g., after determining that the arm BBM is set) may provide some of the technical solutions described herein. For example, at step 615, a determination may be made that the I / O message is associated with a row having a bad block, however, the I / O message is transferred only after determining in step 620 that the arm BBM is set. This two-step process may reduce some of the false transfers described herein. The LDBBM's processing of the I / O message may include an action of the LDBBM performing an action similar to that of the bad block manager 140. In some embodiments, the I / O message may be transferred to the bad block manager 140, and the bad block manager 140 may process the I / O message.

[0088] At step 630, the I / O message may be executed. For example, the I / O message may be a read request, and the controller 110 may access information stored in the logical drive 145. The controller 110 may then provide the accessed information to the host 105. As another example, the I / O message may be a write request, and the controller 110 may write information to the logical drive 145.

[0089] Although process 600 has been described with respect to one I / O message, it should be understood that process 600 may be performed for one or more I / O messages, and the steps of process 600 may be performed one after the other, in lockstep, and / or various other possibilities. For example, controller 110 may perform step 610 with respect to a first I / O message while also performing step 605 with respect to a second I / O message.

[0090] Figure 7 700 is a flow chart of a process 700 for handling bad blocks according to some embodiments. In some embodiments, process 700 may be performed by one or more components and / or devices of system 100. For example, controller 110 may perform one or more steps of process 700. As another example, processing circuit 115 may perform one or more steps of process 700.

[0091] In some embodiments, at step 705, a request may be received. For example, processing circuit 115 may receive a request from host 105. The request may include an I / O message. For example, the request may be at least one of the various I / O messages described herein. As another example, the request may be at least one of the various messages and / or requests described herein. In some embodiments, processing circuit 115 may receive one or more requests. For example, processing circuit 115 may receive a first request and a second request.

[0092] In some embodiments, the request received by the processing circuit 115 may be associated with one or more data sets. For example, a first request may be associated with a first data set, and a second request may be associated with a second data set. In some embodiments, the data sets may be stored by a memory device. For example, the data sets may be stored by a logical drive 145 and / or a physical drive including the logical drive 145. In some embodiments, the requests may be associated with similar data sets. For example, a first request may be associated with a first data set, and a second request may also be associated with the first data set. In some embodiments, the data sets may be located within one or more segments of a memory device. For example, a first data set may be located within a first segment of a first logical drive 145, and a second data set may be located within a second segment of the first logical drive 145.

[0093] In some embodiments, the segments may be located in different sections. For example, a first segment may be located in a first section of a logical drive 145, and a second segment may be located in a second section of a logical drive 145. In some embodiments, the segments may be located in similar sections. For example, a first segment and a second segment may be located in a first section of a logical drive 145. In some embodiments, the segments may be located in one or more rows. For example, a logical drive 145 may include one or more segments, and the segments may be located in corresponding rows 210.

[0094] In some embodiments, at step 710, a value may be generated to identify a first segment of the first map. For example, processing circuitry 115 may generate a value to identify a segment of bad block bitmap 130. Continuing with this example, the value may be and / or include a hash value (e.g., hash value 310). In some embodiments, the hash value may be generated based on information associated with a memory device and a request. For example, processing circuitry 115 may generate a hash value based on an identification of a logical drive 145 and a data set associated with the request. The hash value generated by processing circuitry 115 may specify and / or identify a given segment of bad block bitmap 130.

[0095] In some embodiments, processing circuit 115 may generate values ​​identifying one or more segments of the first graph in response to processing circuit 115 receiving a subsequent request. For example, processing circuit 115 may generate a first value in response to receiving a first request, and processing circuit 115 may generate a second value in response to receiving a second request.

[0096] In some embodiments, at step 715, a first row containing a bad block may be determined. For example, the value generated in step 710 may identify a given section of the first graph, and the given section may include a first value. Continuing with this example, the first value of the first section may indicate that the given row contains a bad block. In some embodiments, the first value of the first section may include a set of bits, and the value of the bit (e.g., 0 or 1) may indicate the presence of a bad block. For example, the first section of the first graph may include a bad block bit. Continuing with this example, the bad block bit may be set (e.g., set to 1), and the bad block bit that has been set may indicate a bad block. As another example, the first section may include at least one of the bits 305, and the value of the first section may include a value to which the bit has been set.

[0097] In some embodiments, at step 720, a first element of the second map may be identified. For example, processing circuitry 115 may identify an element of arm bitmap 135. In some embodiments, processing circuitry 115 may identify the element based on an association with bad block bitmap 130. For example, the value of the segment identified in step 715 may be associated with and / or linked to a given element of the second map. Continuing with this example, the value of the segment may include a set of bits that identify a given element of the second map.

[0098] In some embodiments, at step 725, a first value of the first element of the second graph may be determined. For example, processing circuitry 115 may inspect, analyze, and / or otherwise view the first element of the second graph to determine the first value. For example, processing circuitry 115 may determine the first value by viewing the values ​​of the bits included in the first element. As another example, the first value of the first element may include the value of at least one of bits 405.

[0099] In some embodiments, processing circuit 115 may use the first value identified in step 725 to identify one or more portions. For example, the second map may include map 400, and map 400 includes bit 405. Continuing with this example, a given bit 405 may identify one or more arms (e.g., portions of a memory device). In some embodiments, processing circuit 115 may identify one or more portions by determining that a given bit 405 is set. For example, processing circuit 115 may determine that bit 0 of map 400 is set. Continuing with this example, processing circuit 115 may then identify arms 0, 8, 16, and / or 24 (e.g., one or more portions). As described herein, a given bit of map 400 being set may indicate that at least one of the arms associated with the given bit includes a bad block.

[0100] In some embodiments, at step 730, the request may be transferred based on one or more rules. For example, processing circuitry 115 may transfer the request received in step 705. Processing circuitry 115 may transfer the request in response to determining that one or more portions (as determined in step 725) include a portion associated with the request. In other words, the request received in step 705 may be associated with a given data set. The data set may be located in a given portion of a memory device, and processing circuitry 115 may determine that the given portion of the memory device includes a bad block based on the first value determined in step 725. In some embodiments, processing circuitry 115 may transfer the request in response to determining that the request is associated with a data set located within a portion having a bad block.

[0101] In some embodiments, at least one of the steps of process 700 may be repeated and / or performed in response to processing circuit 115 receiving a subsequent request. For example, processing circuit 115 may perform steps 710-725 in response to processing circuit 115 receiving a second request.

[0102] The hardware systems described herein can be implemented in many different ways and in many different combinations of hardware, software, and circuit design. For example, all or part of an implementation may be a circuit system including an instruction processor, such as a central processing unit (CPU), a microcontroller, or a microprocessor; an application specific integrated circuit (ASIC), a programmable logic device (PLO), or a field programmable gate array (FPGA); or a circuit system including discrete logic or other circuit components, including analog circuit components, digital circuit components, or both; or any combination thereof. As an example, the circuit system may include discrete interconnected hardware components and / or may be combined on a single integrated circuit die, distributed among multiple integrated circuit dies, or implemented in a multi-chip module (MCM) of multiple integrated circuit dies in a common package. In some embodiments, the circuit system may be provided on one or more integrated circuit dies in an integrated circuit package. In some embodiments, the integrated circuit package may be a combination of two or more packages.

[0103] The circuit system may further include or access instructions (e.g., software or firmware) for execution by the circuit system. The instructions may be stored in a tangible storage medium other than a temporary storage medium, such as flash memory, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM); or on a magnetic or optical disk, such as a compact disk read-only memory (CDROM), a hard disk drive (HDD), or other magnetic or optical disk; or in or on another machine-readable medium. A product, such as a computer program product, may include a storage medium and instructions stored in or on the medium, and when executed by the circuit system in a device, the instructions may cause the device to implement any of the processes described above or illustrated in the accompanying drawings.

[0104] The implementation scheme may be distributed as a circuit system among multiple system components, such as among multiple processors and memories, optionally including multiple distributed processing systems. Parameters, databases, and other data structures may be stored and managed separately, may be incorporated into a single memory or database, may be logically and physically organized in many different ways, and may be implemented in many different ways, including as data structures such as linked lists, hash tables, arrays, records, objects, or implicit storage mechanisms. Programs may be parts of a single program (e.g., subroutines), separate programs, distributed across several memories and processors, or implemented in many different ways, such as in a library, such as a shared library (e.g., a dynamic link library (DLL)). For example, a DLL may store instructions that, when executed by the circuit system, perform any of the processes described above or illustrated in the accompanying drawings.

[0105] The term "coupled" and its variants include two components directly or indirectly joined to each other. The term "electrically coupled" and its variants include two components directly or indirectly joined to each other through a conductive material (e.g., a metal or copper trace). Such joining may be static (e.g., permanent or fixed) or movable (e.g., removable or releasable). Such joining may be achieved by two components directly coupled to each other, wherein the two components are coupled to each other using separate intervening components and any additional intermediate components that are coupled to each other, or wherein the two components are coupled to each other using an intervening component that is integrally formed with one of the two components as a single, unitary body. If "coupled" or its variants are modified by additional terms (e.g., directly coupled), the general definition of "coupled" provided above is modified by the colloquial language meaning of the additional terms (e.g., "directly coupled" means that the two components are joined without any separate intervening components), resulting in a narrower definition than the general definition of "coupled" provided above. Such coupling may be mechanical, electrical, or fluidic.

[0106] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

[0107] It should be noted that certain paragraphs of the present disclosure may refer to terms such as "first" and "second" in connection with subsets of transmission spatial streams, sounding frames, responses, and devices for the purpose of identifying or distinguishing one from another or others. These terms are not intended to relate entities (e.g., first device and second device) only in time or according to a sequence, but in some cases, these entities may include such a relationship. These terms also do not limit the number of possible entities that can operate in a system or environment. It should be understood that the system described above may provide multiple of any one or each of those components, and these components may be provided on a stand-alone machine, or in some embodiments, on multiple machines in a distributed system. In addition, the above-described systems and methods may be provided as one or more computer-readable programs or executable instructions embodied on or in one or more articles of manufacture (e.g., floppy disk, hard disk, CD-ROM, flash memory card, PROM, RAM, ROM, or tape). The program may be implemented in any programming language (e.g., LISP, PERL, C, C++, C#) or in any byte code language (e.g., JAVA). A software program or executable instructions may be stored as object code on or in one or more articles of manufacture.

[0108] Although the foregoing written description of the methods and systems enables one of ordinary skill in the art to make and use embodiments thereof, one of ordinary skill in the art will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiments, methods, and examples herein. Therefore, the methods and systems should not be limited to the embodiments, methods, and examples described above, but should be limited to all embodiments and methods within the scope and spirit of the present disclosure.

Claims

1. A system comprising: a memory device comprising a plurality of portions having a plurality of segments located in a plurality of rows of the memory device; and A device in communication with the memory device, the device comprising: One or more circuits configured to: receiving a request associated with a first data set stored by the memory device, the first data set being located in a first segment of the plurality of segments and the first segment being included in a first portion of the plurality of portions; generating a first value identifying a first segment of a first map based on information associated with the memory device and the request; determining, based on a first value of the first segment, that a first row of the plurality of rows contains a bad block, and wherein the first segment is located in the first row of the plurality of rows; identifying the first element based on an association between the first section and the first element of the second graph; determining a first value of the first element to identify one or more first portions of the plurality of portions; and Responsive to a determination that the one or more first portions include the first portion, the request is diverted based on one or more rules for addressing the bad block.

2. The system according to claim 1, further comprising: The one or more circuits are further configured to: receiving a second request associated with a second data set stored by the memory device, the second data set being located in a second segment of the plurality of segments, the second segment being located in the first row, and the second segment being included in a second portion of the plurality of portions; identifying a second element of the second graph based on an association between a second section of the first graph and a second element of the second graph; determining a first value of the second element to identify one or more second portions of the plurality of portions; and Responsive to a determination that the second portion is not present in the one or more second portions, one or more actions are performed to process the second request.

3. The system of claim 1, further comprising: The first map includes a plurality of segments, and the plurality of segments have corresponding values; The second graph includes a plurality of elements, and the plurality of elements have corresponding values; and The one or more circuits are further configured to: updating at least one of the plurality of sectors in response to detection of a second bad block to identify a second row of the plurality of rows that includes the second bad block; and At least one element of the plurality of elements is updated to identify one or more second portions of the plurality of portions.

4. The system of claim 1, further comprising: The first line contains: a second segment of the plurality of segments, the second segment being contained in a second portion of the plurality of portions; and a third segment of the plurality of segments, the third segment being contained in a third portion of the plurality of portions; and The one or more circuits are further configured to: performing one or more actions to process a second request associated with a second data set located in the second segment in response to a determination that the second portion is not present in the one or more first portions; and Responsive to a determination that the one or more first portions include the third portion, a third request associated with a third data set located in the third segment is transferred.

5. The system of claim 1, further comprising: The one or more circuits are further configured to: receiving a second request associated with a second data set stored by the memory device, the second data set being located in a second segment of the plurality of segments, the second segment being contained in a second portion of the plurality of portions, the second segment being located in a second row of the plurality of rows, and wherein the second row includes at least one bad block; receiving a third request associated with a third data set stored by the memory device, the third data set being located in a third segment of the plurality of segments, the third segment being included in a third portion of the plurality of portions, and the third segment being located in the second row; determining a second value of a second element of the second map to identify one or more second portions of the plurality of portions; responsive to a determination that the one or more second portions include the second portion, diverting the second request based on the one or more rules; and Responsive to a determination that the one or more second portions include the third portion, the third request is transferred based on the one or more rules.

6. The system of claim 1, wherein: a second request associated with a second data set stored by the memory device; The second data set is located in a second segment of the plurality of segments; and The second request is processed by the one or more circuits, wherein the second segment is located in the first row of the plurality of rows.

7. The system of claim 1, wherein: a second request associated with a second data set stored by the memory device; The second data set is located in a second segment of the plurality of segments; The second segment is included in a second portion of the plurality of portions; and The second request is transferred by the one or more circuits in response to a determination that the one or more first portions include the second portion.

8. The system of claim 1 , wherein in response to the determination that the one or more first portions include the first portion, diverting the request based on the one or more rules for addressing the bad block comprises: identifying, by the one or more circuits, a given segment of the plurality of segments to locate the first data set; or The first data set is provided, by the one or more circuits, to a given memory device of a plurality of memory devices.

9. A device in communication with a memory device, the memory device comprising a plurality of portions having a plurality of segments located in a plurality of rows of the memory device, the device comprising: One or more circuits configured to: receiving a request associated with a first data set stored by the memory device, the first data set being located in a first segment of the plurality of segments and the first segment being included in a first portion of the plurality of portions; generating a first value identifying a first segment of a first map based on information associated with the memory device and the request; determining, based on a first value of the first segment, that a first row of the plurality of rows contains a bad block, and wherein the first segment is located in the first row of the plurality of rows; identifying the first element based on an association between the first section and the first element of the second graph; determining a first value of the first element to identify one or more first portions of the plurality of portions; and Responsive to a determination that the one or more first portions include the first portion, the request is diverted based on one or more rules for addressing the bad block.

10. The device of claim 9, the one or more circuits being further configured to: receiving a second request associated with a second data set stored by the memory device, the second data set being located in a second segment of the plurality of segments, the second segment being located in the first row, and the second segment being included in a second portion of the plurality of portions; identifying a second element of the second graph based on an association between a second section of the first graph and a second element of the second graph; determining a first value of the second element to identify one or more second portions of the plurality of portions; and Responsive to a determination that the second portion is not present in the one or more second portions, one or more actions are performed to process the second request.

11. The device according to claim 9, wherein: The first map includes a plurality of segments, and the plurality of segments have corresponding values; The second graph includes a plurality of elements, and the plurality of elements have corresponding values; and The one or more circuits are further configured to: updating at least one of the plurality of sectors in response to detection of a second bad block to identify a second row of the plurality of rows that includes the second bad block; and At least one element of the plurality of elements is updated to identify one or more second portions of the plurality of portions.

12. The device according to claim 9, wherein: The first line contains: a second segment of the plurality of segments, the second segment being contained in a second portion of the plurality of portions; and a third segment of the plurality of segments, the third segment being contained in a third portion of the plurality of portions; and The one or more circuits are further configured to: performing one or more actions to process a second request associated with a second data set located in the second segment in response to a determination that the second portion is not present in the one or more first portions; and Responsive to a determination that the one or more first portions include the third portion, a third request associated with a third data set located in the third segment is transferred.

13. The device of claim 9, the one or more circuits being further configured to: receiving a second request associated with a second data set stored by the memory device, the second data set being located in a second segment of the plurality of segments, the second segment being contained in a second portion of the plurality of portions, the second segment being located in a second row of the plurality of rows, and wherein the second row includes at least one bad block; receiving a third request associated with a third data set stored by the memory device, the third data set being located in a third segment of the plurality of segments, the third segment being included in a third portion of the plurality of portions, and the third segment being located in the second row; determining a second value of a second element of the second map to identify one or more second portions of the plurality of portions; responsive to a determination that the one or more second portions include the second portion, diverting the second request based on the one or more rules; and Responsive to a determination that the one or more second portions include the third portion, the third request is transferred based on the one or more rules.

14. The device according to claim 9, wherein: a second request associated with a second data set stored by the memory device; The second data set is located in a second segment of the plurality of segments; and The second request is processed by the one or more circuits, wherein the second segment is located in the first row of the plurality of rows.

15. The device according to claim 9, wherein: a second request associated with a second data set stored by the memory device; The second data set is located in a second segment of the plurality of segments; The second segment is included in a second portion of the plurality of portions; and The second request is transferred by the one or more circuits in response to a determination that the one or more first portions include the second portion.

16. The apparatus of claim 9, wherein in response to the determination that the one or more first portions include the first portion, diverting the request based on the one or more rules for addressing the bad block comprises: identifying, by the one or more circuits, a given segment of the plurality of segments to locate the first data set; or The first data set is provided, by the one or more circuits, to a given memory device of a plurality of memory devices.

17. A method comprising: receiving, by one or more circuits, a request associated with a first data set stored by a memory device, the memory device comprising a plurality of portions, the plurality of portions having a plurality of segments, the plurality of segments being located in a plurality of rows of the memory device, the first data set being located in a first segment of the plurality of segments, and the first segment being included in the first portion of the plurality of portions; generating, by the one or more circuits, a first value identifying a first segment of a first map based on information associated with the memory device and the request; determining, by the one or more circuits, based on a first value of the first segment, that a first row of the plurality of rows includes a bad block, and wherein the first segment is located in the first row of the plurality of rows; identifying, by the one or more circuits, a first element of a second graph based on an association between the first section and the first element; determining, by the one or more circuits, a first value of the first element to identify one or more first portions of the plurality of portions; and The request is transferred, by the one or more circuits, responsive to a determination that the one or more first portions include the first portion based on one or more rules for addressing the bad block.

18. The method according to claim 17, further comprising: receiving, by the one or more circuits, a second request associated with a second data set stored by the memory device, the second data set being located in a second segment of the plurality of segments, the second segment being located in the first row, and the second segment being included in a second portion of the plurality of portions; identifying, by the one or more circuits, a second element of the second graph based on an association between a second segment of the first graph and a second element of the second graph; determining, by the one or more circuits, a first value of the second element to identify one or more second portions of the plurality of portions; and One or more actions are performed, by the one or more circuits, in response to a determination that the second portion is not present in the one or more second portions, to process the second request.

19. The method of claim 17, wherein the first map comprises a plurality of segments having respective values, wherein the second map comprises a plurality of elements having respective values, and the method further comprises: updating, by the one or more circuits, at least one of the plurality of sectors in response to detection of a second bad block to identify a second row of the plurality of rows that includes the second bad block; and At least one element of the plurality of elements is updated, by the one or more circuits, to identify one or more second portions of the plurality of portions.

20. The method of claim 17, wherein the first row includes a second segment of the plurality of segments, wherein the second segment is included in a second segment of the plurality of portions, wherein the first row includes a third segment of the plurality of segments, wherein the third segment is included in a third segment of the plurality of portions, and the method further comprises: performing, by the one or more circuits, one or more actions in response to a determination that the second portion is not present in the one or more first portions, to process a second request associated with a second data set located in the second segment; and A third request associated with a third data set located in the third segment is transferred, by the one or more circuits, in response to a determination that the one or more first portions include the third portion.

Images