Chip self-destruct device and manufacturing method

Abstract

The present invention provides a chip self-destruct device and manufacturing method, comprising: a chip, a through-silicon via (TSV), a silicon dioxide layer, a metal microheater layer, a first parylene layer, a second parylene layer, and a backplane layer; the TSVs are arranged in the thickness direction of the chip; a chip groove structure is arranged on the back of the chip and located between adjacent TSVs; the silicon dioxide layer, the metal microheater layer, the first parylene layer, the second parylene layer, and the backplane layer are arranged in sequence with the chip active surface facing the back of the chip; the silicon dioxide layer covers the back of the chip and the interior of the groove of the chip groove structure; the second parylene layer covers the first parylene layer and the opening of the chip groove structure, sealing the chip groove structure into a sealed groove, wherein a filler is provided in the sealed groove; and the backplane layer covers the surface of the second parylene layer. This achieves the purpose of effectively self-destructing the chip using a small-volume self-destruct device.

Description

Technical Field

[0001] The present invention relates to the technical field of chip manufacturing, and in particular to a chip self-destruction device and a manufacturing method. Background Art

[0002] As core components for data processing, transmission, and storage, chips play an especially crucial role in today's rapidly evolving information age. They have also become a prime target for various attacks. Attackers can dissect chips through physical attacks and reverse engineering to obtain critical information stored within. Furthermore, reverse analysis of chips can also lead to intellectual property theft and malicious chip cloning. Consequently, chip security is receiving increasing attention.

[0003] However, traditional protection technologies primarily focus on enhancing security and physical protection within the chip's architecture, circuit design, and packaging. These measures merely increase the difficulty of attacks or render them ineffective, but fail to fundamentally eliminate potential vulnerabilities. In recent years, chip self-destruction technology, as a new microelectronics technology, has gained increasing attention and widespread adoption in chip security. Currently developed chip self-destruction technologies primarily include board-level assisted self-destruction, self-destruction based on self-degradation, stress-induced self-destruction, and microfluidic corrosion-based self-destruction. These technologies have significant practical limitations, restricting their widespread adoption.

[0004] In existing technology, chips can be crushed by installing a special movable plate on the PCB. Alternatively, a boost circuit can be used to provide a set high-voltage signal to the protection chip to destroy the protected chip. An assembly, a control unit board, and a pin adapter board form a sealed cavity. Within this cavity, a micro-explosion structure, an isolation layer, and a storage chip are positioned from top to bottom, destroying the chip through micro-explosion. Alternatively, piezoelectric ceramics and a pressure mechanism can be used to physically destroy the chip. All of these methods suffer from large size and limited self-destruction effectiveness. Summary of the Invention

[0005] In view of this, the embodiments of this specification provide a chip self-destruct device and a manufacturing method to achieve the purpose of effectively self-destructing the chip through a small-sized self-destruct device.

[0006] The embodiments of this specification provide the following technical solutions:

[0007] A chip self-destruct device, comprising:

[0008] chip, through silicon via, silicon dioxide layer, metal micro heater layer, first parylene layer, second parylene layer and backplane layer;

[0009] The chip includes a chip back surface and a chip active surface that are arranged opposite to each other;

[0010] The through-silicon via is arranged in the thickness direction of the chip and penetrates the back side of the chip and the active side of the chip;

[0011] The chip groove structure is arranged on the back side of the chip and is located between adjacent through-silicon vias;

[0012] The silicon dioxide layer, the metal microheater layer, the first parylene layer, the second parylene layer and the backplane layer are sequentially arranged along the direction from the active surface of the chip to the back of the chip;

[0013] The silicon dioxide layer covers the back of the chip and the inside of the groove of the chip groove structure;

[0014] The metal microheater layer covers the silicon dioxide layer between the through-silicon vias;

[0015] A first parylene layer covers the surface of the silicon dioxide layer and the metal microheater layer;

[0016] The second parylene layer covers the first parylene layer and the opening direction of the chip groove structure, sealing the chip groove structure into a sealed groove, and a filler is arranged in the sealed groove;

[0017] The backplane layer covers the surface of the second parylene layer.

[0018] Furthermore, the backplane layer is a silicon or glass substrate, and the backplane layer is bonded to the chip covered with the second parylene layer through an adhesive.

[0019] Furthermore, the self-destruct device also includes:

[0020] Rewiring layers and solder balls;

[0021] The chip also includes chip pads;

[0022] The redistribution layer is arranged on the active surface of the chip, and the solder balls are arranged on the redistribution layer;

[0023] The chip bonding pad is arranged on the active surface of the chip.

[0024] Furthermore, the chip groove structure is in an inverted trapezoidal shape on the back side of the chip toward the active surface of the chip.

[0025] A method for manufacturing a chip self-destruct device, used for manufacturing a chip self-destruct device, the manufacturing method comprising the following steps:

[0026] Processing a chip groove structure on the back of the chip;

[0027] Prepare a redistribution layer on the surface of the chip and lead out solder balls;

[0028] Leading the pins of the metal microheater layer to the back side of the chip through through-silicon vias;

[0029] Prepare a silicon dioxide layer on the back side of the chip with the chip groove structure;

[0030] preparing a metal microheater layer on the silicon dioxide layer;

[0031] After the metal microheater layer is prepared, a first parylene layer is coated on the metal microheater layer;

[0032] Select a filler based on the chip material, fill the filler into the chip groove structure, and use a second parylene layer to seal the opening direction of the chip groove structure;

[0033] The backplane layer is bonded to the chip prepared with the second polyparaxylene layer by using an adhesive.

[0034] Furthermore, a chip groove structure is processed on the back side of the chip, including:

[0035] Use KOH solution to etch the chip groove structure on the back of the chip and / or,

[0036] The chip groove structure is etched on the back of the chip using reactive ion etching method.

[0037] Furthermore, a second parylene layer is used to seal the opening direction of the chip groove structure, including:

[0038] If the filler is in powder and / or gel form, a coating process is used to cover the second parylene layer to the opening direction of the chip groove structure;

[0039] If the filler is a solution, a coating process is used to cover the second polyparaxylene layer to the opening direction of the chip groove structure in an environment with a temperature below the freezing point of the solution.

[0040] Furthermore, the metal micro heater layer is made of a serpentine metal wire, and the resistance of the metal wire is 10 ohms to 1000 ohms.

[0041] Furthermore, the adhesive is SU-8 photoresist and / or LCP material.

[0042] Furthermore, if the chip is made of silicon, the filler is a mixed solution of HF and HNO3, powder and / or gel of energetic materials; if the chip is made of gallium arsenide or gallium nitride, the filler is powder and / or gel of energetic materials.

[0043] Compared with the prior art, the at least one technical solution adopted in the embodiments of this specification can achieve the following beneficial effects:

[0044] Utilizing the space on the back of the chip to store corrosive liquid and energetic materials can be accomplished using wafer-level packaging technology, resulting in higher integration, smaller size, greater storage capacity for corrosive liquid / energetic materials, and more significant self-destruction effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0046] Figure 1 1 is a schematic diagram of the overall structure of the chip self-destruct device according to an embodiment of the present invention;

[0047] Figure 2 2. It is a schematic diagram of a chip self-destruct device of an embodiment of the present invention;

[0048] Figure 3 is a schematic diagram of the first step in manufacturing the self-destruct device according to an embodiment of the present invention;

[0049] Figure 4 is a schematic diagram of the second step in the manufacturing process of the self-destruct device according to an embodiment of the present invention;

[0050] Figure 5 FIG. 4 is a schematic diagram of the third step in the manufacturing process of the self-destruct device according to an embodiment of the present invention.

[0051] Reference numerals in the figure: 1. chip; 101. chip active surface; 102. chip pad; 103. chip groove structure; 2. redistribution layer; 3. solder ball; 4. through-silicon via; 5. silicon dioxide layer; 6. metal microheater layer; 7. first polyparaxylene layer; 8. second polyparaxylene layer; 9. adhesive; 10. backplane layer. DETAILED DESCRIPTION

[0052] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0053] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0054] like Figure 1 As shown, the self-destruct device of chip 1 includes:

[0055] Chip 1, redistribution layer 2, solder balls 3, through-silicon vias 4, silicon dioxide layer 5, metal microheater layer 6, first parylene layer 7, second parylene layer 8, and backplane layer 10. Chip 1 includes a chip backside and a chip active surface 101 that are oppositely disposed, as well as a chip groove structure 103 and a chip pad 102.

[0056] The through-silicon vias 4 are arranged in the thickness direction of the chip 1 and pass through the chip backside and the chip active surface 101. The chip groove structure 103 is arranged on the chip backside and located between adjacent through-silicon vias 4.

[0057] The silicon dioxide layer 5, the metal microheater layer 6, the first polyparaxylene layer 7, the second polyparaxylene layer 8, and the backplane layer 10 are arranged in sequence along the direction from the chip active surface 101 to the back of the chip. The silicon dioxide layer 5 covers the back of the chip and the interior of the groove of the chip groove structure 103. The metal microheater layer 6 covers the silicon dioxide layer 5 between the through-silicon vias 4. The first polyparaxylene layer 7 covers the surface of the silicon dioxide layer 5 and the metal microheater layer 6. The second polyparaxylene layer 8 covers the first polyparaxylene layer 7 and the opening direction of the chip groove structure 103, sealing the chip groove structure 103 into a sealed groove, and a filler is provided in the sealed groove. The backplane layer 10 covers the surface of the second polyparaxylene layer 8.

[0058] The backplane layer 10 is a silicon or glass substrate, and is bonded to the chip 1 covered with the second polyparaxylene layer 8 through an adhesive.

[0059] The redistribution layer 2 is disposed on the chip active surface 101 , and the solder balls 3 are disposed on the redistribution layer 2 . The chip pad 102 is disposed on the chip active surface 101 .

[0060] The chip groove structure 103 is in an inverted trapezoidal shape on the back side of the chip toward the chip active surface 101 .

[0061] An inverted trapezoidal chip groove structure 103 is formed by etching the back of the chip. An etching solution (such as HF / HNO3) or a gel-like energetic material (such as Al / CuO) is placed in the groove. The etching solution or energetic material is surrounded by parylene, which can withstand chemical attack from the etchant for a long time and has excellent barrier properties. A resistive heater formed by metal wiring is located above the parylene. The heater is connected to the chip active surface 101 (i.e., the control circuit) through a rewiring layer 2 (TSV). If the chip 1 encounters a threat, the chip 1 outputs a high-power current through the rewiring layer 2 (TSV), causing the metal heater of the metal microheater layer 6 to heat up, thereby dissolving the parylene (first parylene layer 7 and second parylene layer 8), causing the etching solution to flow out, or the energetic material to explode due to the heat, causing the entire chip 1 to self-destruct.

[0062] During the design, in order to isolate the corrosive liquid or energetic materials in the chip groove structure 103 while maintaining the rigidity of the entire chip 1, a backplane layer 10 is added to the back of the chip. The material can be silicon, glass, etc., which is bonded to the chip 1 through a polymer colloid such as SU-8.

[0063] Combined with the solution, the manufacturing process of the chip's self-destruct device is as follows:

[0064] like Figure 2 As shown, a chip groove structure 103 is formed on the back of the chip. For silicon materials, a KOH solution can be used to etch an inverted stepped groove on the back of the chip. Alternatively, reactive ion etching can be used to form the chip groove structure 103. Wafer-level packaging technology is then used to create a redistribution layer 2 on the surface of chip 1, leading to solder balls 3. At the same time, the pins for the metal-controlled microheater are connected to the back of the chip through through-silicon vias 4 (TSVs).

[0065] like Figure 3 As shown, a layer of silicon dioxide (silicon dioxide layer 5) is deposited on the back of the chip. The thickness of silicon dioxide layer 5 is very thin (5-100nm) and mainly plays an isolation role. A metal microheater is then made on the silicon dioxide layer 5 to generate a metal microheater layer 6. The typical shape of the metal microheater is a serpentine metal wire, and the material can be aluminum, copper, etc. The metal microheater is designed using the core value resistance design method. The metal microheater usually has a resistance of 10 ohms to 1000 ohms. Chip 1 heats the metal microheater through a through-silicon via 4 (TSV). The current output by chip 1 needs to be calculated based on the resistance of the metal microheater and the power consumption required by the metal microheater.

[0066] After the metal microheater layer 6 is prepared, a layer of parylene is applied to the back of the entire structure, forming a first parylene layer 7. Parylene is very stable and can form an inverted trapezoidal container for storing the corrosive liquid and energetic materials required for self-destruction. Because the chip groove structure 103 is an inverted trapezoid, coating can be achieved using chemical vapor deposition or spraying. Specifically, the parylene thickness can be 5 microns, and the coating effect is generally thinner at the top of the trapezoidal groove.

[0067] like Figure 4As shown, an etching liquid or energetic material is placed as a filler in the chip groove structure 103 and sealed with parylene. If the chip 1 is made of silicon, in order to achieve self-destruction, the etching liquid can be a mixed solution of HF and HNO3 (concentration ratio of 3:1). When the microheater heats and destroys the parylene layer, the etching liquid can quickly pass through the silicon dioxide to corrode the silicon. Alternatively, energetic material powder and / or gel can be used. If the chip 1 is made of materials such as gallium arsenide and gallium nitride, the groove can also be filled with energetic material powder or gel. When heated, the parylene layer is destroyed, and then the high temperature detonates the energetic material to achieve self-destruction.

[0068] After the chip groove structure 103 is filled with the filler, a layer of parylene needs to be coated on the surface to form a second parylene layer 8 to achieve sealing and isolation of the corrosive liquid or energetic material.

[0069] If the filler is a powder or gel-like energetic material, it can be directly coated using a coating process; if the filler is a corrosive solution, it needs to be coated at a low temperature, and the temperature should be set below the freezing point of the corrosive solution.

[0070] like Figure 5 As shown, in order to further improve the reliability and stability of the entire structure, a backplane layer 10 needs to be prepared on the back side. The backplane layer 10 can be implemented using a silicon or glass substrate. The backplane layer 10 and the chip 1 (the chip 1 prepared with the second polyparaxylene layer 8) can be bonded using an adhesive 9. The adhesive 9 can be made of organic materials such as SU-8 photoresist and LCP.

[0071] Beneficial effects of the embodiments of the present invention:

[0072] An embodiment of the present invention provides a chip self-destruction device that utilizes the space behind the chip to store corrosive liquid and energetic materials. This device can be completed using a wafer-level packaging process, resulting in higher integration, smaller size, greater storage capacity for corrosive liquid / energetic materials, and a more significant self-destruction effect. To address the rapid self-destruction of chips, particularly the difficulties in high-density integration of corrosive solutions and incomplete self-destruction due to small amounts of corrosive solutions in microfluidic corrosive self-destruction technology, the present invention adopts wafer-level packaging technology to propose a novel high-density self-destruction structure and method, which increases the capacity of corrosive solution within the chip and achieves a faster and more significant corrosion effect.

[0073] The above description is merely a specific embodiment of the present invention and should not be construed as limiting the scope of the invention. Therefore, substitutions of equivalent components, or equivalent changes and modifications made within the scope of patent protection, should still fall within the scope of this patent. Furthermore, the technical features of the present invention may be freely combined with one another, with other technical solutions, and with other technical solutions.

Claims

1. A chip self-destruct device, characterized in that: include: A chip (1), a through-silicon via (4), a silicon dioxide layer (5), a metal microheater layer (6), a first parylene layer (7), a second parylene layer (8), and a backplane layer (10); The chip (1) comprises a chip back surface and a chip active surface (101) arranged opposite to each other; A through-silicon via (4) is provided in the thickness direction of the chip (1) and penetrates the back surface of the chip and the active surface (101) of the chip; The chip groove structure (103) is arranged on the back side of the chip and is located between adjacent through-silicon vias (4); The silicon dioxide layer (5), the metal microheater layer (6), the first polyparaxylene layer (7), the second polyparaxylene layer (8) and the backplane layer (10) are sequentially arranged along the chip active surface (101) in a direction toward the back of the chip; A silicon dioxide layer (5) covers the back of the chip and the interior of the groove of the chip groove structure (103); A metal microheater layer (6) covers the silicon dioxide layer (5) between the through-silicon vias (4); The first parylene layer (7) covers the surface of the silicon dioxide layer (5) and the metal microheater layer (6); The second polyparaxylene layer (8) covers the first polyparaxylene layer (7) and the opening direction of the chip groove structure (103), sealing the chip groove structure (103) into a sealed groove, and a filler for self-destruction is provided in the sealed groove; The backplane layer (10) covers the surface of the second polyparaxylene layer (8).

2. The chip self-destruct device according to claim 1, characterized in that: The backplane layer (10) is a silicon or glass substrate, and the backplane layer (10) is bonded to the chip (1) covered with the second polyparaxylene layer (8) via an adhesive.

3. The chip self-destruct device according to claim 1, characterized in that: The self-destruct device also includes: Rewiring layer (2) and solder balls (3); The chip (1) further includes a chip pad (102); The rewiring layer (2) is arranged on the chip active surface (101), and the solder balls (3) are arranged on the rewiring layer (2); The chip pad (102) is arranged on the chip active surface (101).

4. The chip self-destruct device according to claim 1, characterized in that: The chip groove structure (103) is in an inverted trapezoidal shape on the back side of the chip in a direction toward the chip active surface (101).

5. A method for manufacturing a chip self-destruct device, used to manufacture the chip self-destruct device according to any one of claims 1 to 4, characterized in that: The manufacturing method comprises the following steps: Processing a chip groove structure (103) on the back side of the chip; A redistribution layer (2) is prepared on the surface of the chip (1), and solder balls (3) are led out; Leading the pins of the metal microheater layer (6) to the back side of the chip (1) through a through-silicon via (4); Preparing a silicon dioxide layer (5) on the back side of the chip processed with the chip groove structure (103); preparing a metal microheater layer (6) on the silicon dioxide layer (5); After the metal microheater layer (6) is prepared, a first polyparaxylene layer (7) is coated on the metal microheater layer (6); Selecting a filler according to the material of the chip (1), filling the filler into the chip groove structure (103), and using a second polyparaxylene layer (8) to seal the opening direction of the chip groove structure (103); The backplane layer (10) is bonded to the chip (1) on which the second polyparaxylene layer (8) is prepared using an adhesive (9).

6. The method for manufacturing a self-destruct device according to claim 5, characterized in that: Processing a chip groove structure (103) on the back side of the chip includes: A chip groove structure (103) is etched on the back of the chip using a KOH solution and / or, A chip groove structure (103) is etched on the back of the chip using a reactive ion etching method.

7. The method for manufacturing a self-destruct device according to claim 5, characterized in that: The second polyparaxylene layer (8) is used to seal the opening direction of the chip groove structure (103), including: If the filler is in powder and / or gel form, a coating process is used to cover the second polyparaxylene layer (8) in the direction of the opening of the chip groove structure (103); If the filler is a solution, a coating process is used to cover the second polyparaxylene layer (8) in the direction of the opening of the chip groove structure (103) in an environment with a temperature below the freezing point of the solution.

8. The method for manufacturing a self-destruct device according to claim 5, characterized in that: The metal microheater layer (6) is made of a serpentine metal wire, and the resistance of the metal wire is 10 ohms to 1000 ohms.

9. The method for manufacturing a self-destruct device according to claim 5, wherein: The adhesive (9) is SU-8 photoresist and / or LCP material.

10. The method for manufacturing a self-destruct device according to claim 5, wherein: The filler is selected according to the material of the chip (1), including: If the chip (1) is made of silicon, the filler is a mixed solution of HF and HNO3, powder of energetic material and / or gel; If the chip (1) is made of gallium arsenide or gallium nitride, the filler is powder and / or gel of an energetic material.

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