Full-localization solid-state power distributor based on TTE and standard Ethernet fusion

Abstract

The invention discloses a TTE and standard Ethernet fusion-based full-localization solid-state power distributor. The TTE and standard Ethernet fusion-based full-localization solid-state power distributor comprises a control module, a state acquisition module, a TTE interface module and a power distribution module, wherein the control module is used for receiving a standard Ethernet power distribution instruction and analyzing the standard Ethernet power distribution instruction to obtain a power distribution module control instruction; the power distribution channel current and voltage data receiving module receives power distribution channel current and voltage data and transmits the power distribution channel current and voltage data to the TTE interface module; the TTE interface module is used for receiving a standard Ethernet power distribution instruction of an external controller and transmitting the standard Ethernet power distribution instruction to the control module; receiving the current and voltage data of the power distribution channel, and transmitting the current and voltage data of the power distribution channel to an external controller; the power distribution module receives the power distribution module control instruction and isolates and drives a power distribution channel switch according to the power distribution module control instruction; and the state acquisition module acquires current and voltage data of the power distribution channel and transmits the current and voltage data of the power distribution channel to the control module. According to the invention, the reliability and real-time performance of the communication system are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of solid-state power distributors, and in particular relates to a nationally produced solid-state power distributor based on the fusion of time-triggered Ethernet (TTE) and standard Ethernet. Background Art

[0002] The communication method used by the traditional solid-state power distributors in existing spacecraft has low speed, few transmitted bytes and short transmission distance. Standard Ethernet has the characteristics of high speed and low cost, but the communication method of standard Ethernet is based on "event triggering", which makes it difficult to guarantee the certainty of time in complex network communications. Summary of the invention

[0003] The technical problem solved by the present invention is: to overcome the deficiencies of the prior art, to provide a nationally produced solid-state power distributor based on the fusion of time-triggered Ethernet (TTE) and standard Ethernet, and to improve the reliability and real-time performance of the communication system.

[0004] The object of the present invention is achieved through the following technical solutions: a nationally produced solid-state power distributor based on the integration of TTE and standard Ethernet, comprising: a control module, a state acquisition module, a TTE interface module and a power distribution module; wherein the control module: receives the standard Ethernet power distribution instruction of the TTE interface module, parses the standard Ethernet power distribution instruction to obtain the power distribution module control instruction, and transmits the power distribution module control instruction to the power distribution module; receives the power distribution channel current and voltage data of the state acquisition module, and transmits the power distribution channel current and voltage data to the TTE interface module; the TTE interface module: receives the standard Ethernet power distribution instruction of the external controller, and transmits the standard Ethernet power distribution instruction to the control module; receives the power distribution channel current and voltage data, and transmits the distribution channel current and voltage data to the external controller; the power distribution module: receives the power distribution module control instruction, and isolates and drives the power distribution channel switch according to the power distribution module control instruction; the state acquisition module: collects the power distribution channel current and voltage data, and transmits the distribution channel current and voltage data to the control module.

[0005] The above-mentioned nationally produced solid-state power distributor based on the integration of TTE and standard Ethernet also includes: a power supply module; wherein the power supply module is used to supply power to the control module, the status acquisition module, the TTE interface module and the power distribution module.

[0006] In the above-mentioned domestically produced solid-state power distributor based on the integration of TTE and standard Ethernet, the power supply module includes a filter, a DC / DC and a power module; wherein the filter processes the external input 28V voltage to obtain a filtered external input 28V voltage, and transmits the external input 28V voltage to the DC / DC; the DC / DC converts the external input 28V voltage into an internal 5V voltage, and transmits the internal 5V voltage to the power module; the power module converts the internal 5V voltage into multiple required voltages.

[0007] In the above-mentioned nationally produced solid-state power distributor based on the integration of TTE and standard Ethernet, the multiple required voltages include 1.2V, 1.5V, 2.5V, and 3.3V.

[0008] In the above-mentioned nationally produced solid-state power distributor based on the integration of TTE and standard Ethernet, the power distribution module includes a plurality of isolation drive circuits.

[0009] In the above-mentioned domestically produced solid-state power distributor based on the integration of TTE and standard Ethernet, the isolation drive circuit includes an isolation drive module and a power MOSFET; wherein, when the isolation drive module receives a high-level signal in the distribution module control instruction of the control module, it isolates the high-level signal and performs boost and voltage regulation, and controls the gate voltage drive of the power MOSFET after the boost and voltage regulation processing, thereby realizing the opening of the distribution channel; when the isolation drive module receives a low-level signal in the distribution module control instruction of the control module, it isolates the low-level signal and controls the gate voltage of the power MOSFET to realize the closing of the distribution channel.

[0010] In the above-mentioned domestically produced solid-state power distributor based on the integration of TTE and standard Ethernet, the status acquisition module includes an AD acquisition chip, a Hall sensor and a magnetic isolation chip; wherein the AD acquisition chip collects the distribution channel voltage, and transmits the distribution channel voltage to the control module after isolation through the magnetic isolation chip; the Hall sensor collects the current signal, converts the current signal into a voltage signal, and sends it to the AD chip for acquisition.

[0011] In the above-mentioned nationally produced solid-state power distributor based on the integration of TTE and standard Ethernet, the TTE interface module includes a PHY chip, a network transformer, a resistor FB3, a resistor FB5, a resistor FB7, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C15, a capacitor C16, a capacitor C17, a capacitor C18, a capacitor C19, a capacitor C20, a capacitor C21, a capacitor C49, a capacitor C50, a capacitor C51, a capacitor C52, a capacitor C53, a capacitor C54, a resistor FB1, a capacitor C29, a capacitor C30, a capacitor C31, a capacitor C32, a capacitor C33, a capacitor C 34, capacitor C35, capacitor C36, capacitor C37, capacitor C38, resistor R2, resistor R10, resistor R14, resistor R27, resistor R30, resistor R31, capacitor C73, resistor R42, resistor R36, resistor R63, chip U3, capacitor C77, capacitor C78, ​​capacitor C75, capacitor C81, capacitor C82, capacitor C85, capacitor C88, resistor FB9, resistor R71, resistor R72, resistor R74, resistor R76, capacitor C83, resistor R9, resistor R11, resistor R19, resistor R21, capacitor C66, capacitor C68, resistor R35, resistor R37, resistor R38, Resistor R39, resistor R40, resistor R41, resistor R51, resistor R53, resistor R54, resistor R57, resistor R59, resistor R61, resistor R64, resistor R67, resistor R69, resistor R1, resistor R6, resistor R7, resistor R13, resistor R22, resistor R25, resistor R28, resistor R33, capacitor C8, capacitor C9, capacitor C10, capacitor C11; wherein one end of the resistor FB3 is respectively connected to one end of the resistor FB5 and one end of the resistor FB7 and then connected to GTX_2V5; the capacitors C1, C2, C3, C4, C5, C6 and The capacitor C7 is connected in parallel; the other end of the resistor FB3 is connected to the capacitor C1, and the AVDDF pin of the PHY chip, the AVDD_1 pin of the PHY chip, the AVDD_2 pin of the PHY chip, the AVDD_3 pin of the PHY chip, the AVDD_4 pin of the PHY chip and the AVDDH pin of the PHY chip are connected and then connected to the capacitor C7; the capacitors C15, C16, C17, C18, C19, C20 and C21 are connected in parallel; the other end of the resistor FB5 is connected to the capacitor C11, and the VDD OX_1 pin of the PHY chip, the VDD OX_2 pin of the PHY chip, the VDD OH_1 pin of the PHY chip, the VDD OH_2 pin of the PHY chip and the VDD OH_3 pin of the PHY chip are connected and then connected to the capacitor C20;The capacitors C49, C50, C51, C52, C53 and C54 are connected in parallel; the other end of the resistor FB7 is connected to the capacitor C49, the VDDD_1 pin of the PHY chip, the VDDD_2 pin of the PHY chip and the VD The DD_3 pins are connected and then connected to capacitor C54; the TXD0 pin of the PHY chip, the TXD1 pin of the PHY chip, the TXD2 pin of the PHY chip, the TXD3 pin of the PHY chip, the TXD4 pin of the PHY chip, the TXD5 pin of the PHY chip, the TXD6 pin of the PHY chip and the TXD7 pin of the PHY chip are connected and then connected to resistor R2; the TX_EN pin of the PHY chip is connected to one end of resistor R10, the TX_ER pin of the PHY chip is connected to one end of resistor R14, the other end of resistor R10 is connected to the other end of resistor R14 and then connected to GND; the MDC pin of the PHY chip is connected to one end of resistor R27, the MDIO pin of the PHY chip is connected to one end of resistor R30, the INT pin of the PHY chip is connected to one end of resistor R31, the other end of resistor R27, the other end of resistor R30 and the other end of resistor R31 are connected and then connected to GTX 2V5; the RESRT pins of the PHY chip are connected to one end of the resistor R42 and one end of the capacitor C73; the other end of the resistor R42 and the other end of the capacitor C73 are connected to GND; the COMA pin of the PHY chip is connected to one end of the resistor R36; the other end of the resistor R36 is connected to GND; the CLKOUT pin of the chip U3 is connected to one end of the resistor R63, and the other end of the resistor R63 is connected to the XTAL1 pin of the PHY chip; the VCC pin of the chip U3 is connected to GTX_2V5, and the capacitors C77 and C78 are connected in parallel and then connected to the VCC pin of the chip U3; the GND pin of the chip U3 is connected to one end of the capacitor C75, and the OE pin of the chip U3 is connected to the other end of the capacitor C75, and the OE pin of the chip U3 is connected to the chip U3 The capacitor C81, the capacitor C82 and the capacitor C85 are connected in parallel and then connected to the TCT1 pin of the network transformer, the TCT2 pin of the network transformer, the TCT3 pin of the network transformer and the TCT4 pin of the network transformer respectively; the MCT1 pin of the network transformer is connected to one end of the resistor R71, the MCT2 pin of the network transformer is connected to one end of the resistor R72, the MCT3 pin of the network transformer is connected to one end of the resistor R74, the MCT4 pin of the network transformer is connected to one end of the resistor R76, the other end of the resistor R71, the other end of the resistor R72, the other end of the resistor R74 and the other end of the resistor R76 are connected and then connected to one end of the capacitor C83, and the other end of the capacitor C83 is connected to TTE_GND;Capacitor C29, capacitor C30, capacitor C31, capacitor C32, capacitor C33, capacitor C34, capacitor C35, capacitor C36, capacitor C37 and capacitor C38 are connected in parallel; the DVDD_1 pin, DVDD_2 pin, DVDD_3 pin, DVDD_4 pin, DVDD_5 pin, DVDD_6 pin, DVDD_7 pin and DVDD_8 pin of the PHY chip are connected and then connected to the resistor FB1, and the resistor FB1 is connected to the capacitor C29; the MD I0p pin of the PHY chip is connected to one end of the resistor R1, and the other end of the resistor R1 is respectively connected to one end of the capacitor C8 and one end of the resistor R6, and the MD I0n pin of the PHY chip is connected to the other end of the resistor R6; the MD I1p pin of the PHY chip is connected to one end of the resistor R7, and the other end of the resistor R7 is respectively connected to one end of the capacitor C9 and one end of the resistor R13, and the MD I0n pin of the PHY chip is connected to the other end of the resistor R6; The MD I1n pin is connected to the other end of the resistor R13; the MD I2p pin of the PHY chip is connected to one end of the resistor R22, the other end of the resistor R22 is respectively connected to one end of the capacitor C10 and one end of the resistor R25, and the MD I2n pin of the PHY chip is connected to the other end of the resistor R25; the MD I3p pin of the PHY chip is connected to one end of the resistor R28, the other end of the resistor R28 is respectively connected to one end of the capacitor C11 and one end of the resistor R33, and the MD I3p pin of the PHY chip is connected to one end of the resistor R28. The I3n pin is connected to the other end of the resistor R33; the RSRT pin of the PHY chip is respectively connected to one end of the resistor R9 and one end of the resistor R11, the HSDACp pin of the PHY chip is connected to one end of the resistor R19, the HSDACh pin of the PHY chip is connected to one end of the resistor R21, the other end of the resistor R9, the other end of the resistor R11, the other end of the resistor R19 and the other end of the resistor R21 are connected and then connected to GND; the SINp pin of the PHY chip is connected to the capacitor C66, and the SINn pin of the PHY chip is connected to the capacitor C68; the P The CONFIG0 pin of the HY chip is connected to the resistor R54, the CONFIG1 pin of the PHY chip is connected to the resistor R57, the CONFIG2 pin of the PHY chip is connected to the resistor R59, the CONFIG3 pin of the PHY chip is connected to the resistor R61, the CONFIG3 pin of the PHY chip is connected to the resistor R61, the CONFIG4 pin of the PHY chip is connected to the resistor R64, the CONFIG5 pin of the PHY chip is connected to the resistor R67, and the CONFIG6 pin of the PHY chip is connected to the resistor R69;The LED_LINK10 pin of the PHY chip is connected to the resistor R35, the LED_LINK100 pin of the PHY chip is connected to the resistor R37, the LED_LINK1000 pin of the PHY chip is connected to the resistor R38, the LED_DUPLEX pin of the PHY chip is connected to the resistor R39, the LED_RX pin of the PHY chip is connected to the resistor R40, the LED_TX pin of the PHY chip is connected to the resistor R41, the TD1 pin of the PHY chip is connected to the resistor R51, and the TRST pin of the PHY chip is connected to the resistor R53. ;

[0012] In the above-mentioned nationally produced solid-state power distributor based on the integration of TTE and standard Ethernet, standard Ethernet uses the UDP protocol to transmit data, and its data frame format consists of a preamble, a frame start delimiter, a destination MAC address, a source MAC address, a type, a destination IP address, a source IP address, a UDP header, a source port number, a destination port number, a UDP length, a UDP checksum, and data.

[0013] In the above-mentioned nationally produced solid-state power distributor based on the integration of TTE and standard Ethernet, the PHY chip is a B88E1111MCB type PHY chip.

[0014] Compared with the prior art, the present invention has the following beneficial effects:

[0015] The present invention is a domestically produced solid-state power distributor based on the fusion of time-triggered Ethernet (TTE) and standard Ethernet, which fully combines the advantages of time-triggered Ethernet (TTE) and standard Ethernet, collects current and voltage state parameters through the time-triggered Ethernet transmission distribution channel, and controls the distribution channel by receiving distribution commands through standard Ethernet, effectively avoiding resource conflicts between the collected state parameters and the distribution instructions. At the same time, the network based on the time trigger mechanism drives communication through the time process, the triggering factors are stable, and the system behavior is determined, which greatly improves the communication rate and reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0017] Figure 1 The present invention is a schematic diagram of a circuit framework structure of a nationally produced solid-state power distributor based on the fusion of time-triggered Ethernet (TTE) and standard Ethernet in an embodiment of the present invention.

[0018] Figure 2 It is a schematic diagram of the principle of a power supply module of a domestically produced solid-state power distributor based on the fusion of time-triggered Ethernet (TTE) and standard Ethernet in an embodiment of the present invention.

[0019] Figure 3 It is a schematic diagram of the control module principle of a domestically produced solid-state power distributor based on the fusion of time-triggered Ethernet (TTE) and standard Ethernet in an embodiment of the present invention.

[0020] Figure 4 It is a schematic diagram of the principle of a power distribution module of a domestically produced solid-state power distributor based on the fusion of time-triggered Ethernet (TTE) and standard Ethernet in an embodiment of the present invention.

[0021] Figure 5 It is a schematic diagram of the principle of a collection module of a domestically produced solid-state power distributor based on the fusion of time-triggered Ethernet (TTE) and standard Ethernet in an embodiment of the present invention.

[0022] Figure 6 The present invention is a schematic diagram of a TTE interface circuit principle of a nationally produced solid-state power distributor based on the fusion of time-triggered Ethernet (TTE) and standard Ethernet in an embodiment of the present invention. DETAILED DESCRIPTION

[0023] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to be able to fully convey the scope of the present disclosure to those skilled in the art. It should be noted that, in the absence of conflict, the embodiments of the present invention and the features described in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0024] The communication method of Time-triggered Ethernet (TTE) is based on "time triggering". Data packets are transmitted strictly according to an exact time schedule, and the transmission delay of the packet is determined. Therefore, the method of integrating Time-triggered Ethernet (TTE) and standard Ethernet can be used to give full play to their respective advantages.

[0025] Figure 1 1 is a schematic diagram of the circuit framework structure of a nationally produced solid-state power distributor based on the fusion of time-triggered Ethernet (TTE) and standard Ethernet in an embodiment of the present invention. Figure 1As shown, the domestically produced solid-state power distributor based on the integration of time-triggered Ethernet (TTE) and standard Ethernet includes: a control module, a state acquisition module, a TTE interface module and a power distribution module; wherein the control module: receives the standard Ethernet power distribution instruction of the TTE interface module, parses the standard Ethernet power distribution instruction to obtain the power distribution module control instruction, and transmits the power distribution module control instruction to the power distribution module; receives the power distribution channel current and voltage data of the state acquisition module, and transmits the power distribution channel current and voltage data to the TTE interface module; the TTE interface module: receives the standard Ethernet power distribution instruction of the external controller, and transmits the standard Ethernet power distribution instruction to the control module; receives the power distribution channel current and voltage data, and transmits the power distribution channel current and voltage data to the external controller; the power distribution module: receives the power distribution module control instruction, and isolates and drives the power distribution channel switch according to the power distribution module control instruction; the state acquisition module: collects the power distribution channel current and voltage data, and transmits the distribution channel current and voltage data to the control module.

[0026] like Figure 1 As shown, the domestically produced solid-state power distributor based on the fusion of time-triggered Ethernet (TTE) and standard Ethernet also includes: a power supply module; wherein the power supply module is used to supply power to the control module, the status acquisition module, the TTE interface module and the power distribution module.

[0027] like Figure 2 As shown, the power supply module includes a filter, a DC / DC and a power module; wherein the filter processes the external input 28V voltage to obtain a filtered external input 28V voltage, and transmits the external input 28V voltage to the DC / DC; the DC / DC converts the external input 28V voltage into an internal 5V voltage, and transmits the internal 5V voltage to the power module; the power module converts the internal 5V voltage into multiple required voltages.

[0028] Multiple required voltages include 1.2V, 1.5V, 2.5V, and 3.3V.

[0029] like Figure 4 As shown, the power distribution module includes multiple isolation drive circuits.

[0030] The isolation driving circuit includes an isolation driving module and a power MOSFET; wherein, when the isolation driving module receives a high-level signal in a power distribution module control instruction of the control module, the high-level signal is isolated and boosted and stabilized, and after the boost and voltage stabilization processing, the gate voltage drive of the power MOSFET is controlled to realize the opening of the power distribution channel; when the isolation driving module receives a low-level signal in a power distribution module control instruction of the control module, the low-level signal is isolated and the gate voltage of the power MOSFET is controlled to realize the closing of the power distribution channel.

[0031] like Figure 5 As shown, the state acquisition module includes an AD acquisition chip, a Hall sensor and a magnetic isolation chip; wherein the AD acquisition chip acquires the distribution channel voltage, and transmits the distribution channel voltage to the control module after isolation through the magnetic isolation chip; the Hall sensor acquires the current signal, converts the current signal into a voltage signal, and sends it to the AD chip for acquisition.

[0032] like Figure 6 As shown, the TTE interface module includes a PHY chip, a network transformer, a resistor FB3, a resistor FB5, a resistor FB7, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C15, a capacitor C16, a capacitor C17, a capacitor C18, a capacitor C19, a capacitor C20, a capacitor C21, a capacitor C49, a capacitor C50, a capacitor C51, a capacitor C52, a capacitor C53, a capacitor C54, a resistor FB1, a capacitor C29, a capacitor C30, a capacitor C31, a capacitor C32, a capacitor C33, a capacitor C34, a capacitor C35, a capacitor C36, a capacitor C37, a capacitor C38, a resistor R2, a resistor R10, a resistor R14, a resistor R27, a resistor R30, a resistor R31, a capacitor C73, a resistor R42, a resistor R36, and a resistor R6 3. Chip U3, capacitor C77, capacitor C78, ​​capacitor C75, capacitor C81, capacitor C82, capacitor C85, capacitor C88, resistor FB9, resistor R71, resistor R72, resistor R74, resistor R76, capacitor C83, resistor R9, resistor R11, resistor R19, resistor R21, capacitor C66, capacitor C68, resistor R35, resistor R37, resistor R38, resistor R39, resistor R40, resistor R41, resistor R51, resistor R53, resistor R54, resistor R57, resistor R59, resistor R61, resistor R64, resistor R67, resistor R69, resistor R1, resistor R6, resistor R7, resistor R13, resistor R22, resistor R25, resistor R28, resistor R33, capacitor C8, capacitor C9, capacitor C10, capacitor C11; wherein,

[0033] One end of the resistor FB3 is respectively connected to one end of the resistor FB5 and one end of the resistor FB7 and then connected to GTX_2V5; the capacitors C1, C2, C3, C4, C5, C6 and C7 are connected in parallel; the other end of the resistor FB3 is connected to the capacitor C1, and the AVDDF pin of the PHY chip, the AVDD_1 pin of the PHY chip, the AVDD_2 pin of the PHY chip, the AVDD_3 pin of the PHY chip, the AVDD_4 pin of the PHY chip and the AVDDH pin of the PHY chip are connected and then connected to the capacitor C7; the capacitors C15, C16, C17, C18, C19, C20 and C21 are connected in parallel; the other end of the resistor FB5 is connected to the capacitor C11, and the VDD OX_1 pin of the PHY chip, the VDD OX_2 pin of the PHY chip, the VDD The VDD OH_1 pin of the PHY chip, the VDD OH_2 pin of the PHY chip and the VDD OH_3 pin of the PHY chip are connected and then connected to the capacitor C20; capacitors C49, C50, C51, C52, C53 and C54 are connected in parallel; the other end of the resistor FB7 is connected to the capacitor C49, the VDD DD_1 pin of the PHY chip, the VDD DD_2 pin of the PHY chip and the VDD OH_3 pin of the PHY chip are connected. The DD_3 pins are connected and then connected to capacitor C54; the TXD0 pin of the PHY chip, the TXD1 pin of the PHY chip, the TXD2 pin of the PHY chip, the TXD3 pin of the PHY chip, the TXD4 pin of the PHY chip, the TXD5 pin of the PHY chip, the TXD6 pin of the PHY chip and the TXD7 pin of the PHY chip are connected and then connected to resistor R2; the TX_EN pin of the PHY chip is connected to one end of resistor R10, the TX_ER pin of the PHY chip is connected to one end of resistor R14, the other end of resistor R10 is connected to the other end of resistor R14 and then connected to GND; the MDC pin of the PHY chip is connected to one end of resistor R27, the MDIO pin of the PHY chip is connected to one end of resistor R30, the INT pin of the PHY chip is connected to one end of resistor R31, the other end of resistor R27, the other end of resistor R30 and the other end of resistor R31 are connected and then connected to GTX 2V5; the RESRT pin of the PHY chip is connected to one end of the resistor R42 and one end of the capacitor C73; the other end of the resistor R42 and the other end of the capacitor C73 are connected to GND; the COMA pin of the PHY chip is connected to one end of the resistor R36; the other end of the resistor R36 is connected to GND;The CLKOUT pin of chip U3 is connected to one end of resistor R63, and the other end of resistor R63 is connected to the XTAL1 pin of PHY chip; the VCC pin of chip U3 is connected to GTX_2V5, and capacitors C77 and C78 are connected in parallel and then connected to the VCC pin of chip U3; the GND pin of chip U3 is connected to one end of capacitor C75, and the OE pin of chip U3 is connected to the other end of capacitor C75, and the OE pin of chip U3 is connected to the VCC pin of chip U3; capacitors C81, C82 and C85 are connected in parallel and then connected to the TCT1 pin of network transformer, the TCT2 pin of network transformer, the TCT3 pin of network transformer, and the TCT4 pin of network transformer respectively; the MCT1 pin of network transformer is connected to one end of resistor R71, the MCT2 pin of network transformer is connected to one end of resistor R72, and the The MCT3 pin is connected to one end of the resistor R74, the MCT4 pin of the network transformer is connected to one end of the resistor R76, the other end of the resistor R71, the other end of the resistor R72, the other end of the resistor R74 and the other end of the resistor R76 are connected and then connected to one end of the capacitor C83, and the other end of the capacitor C83 is connected to TTE_GND; capacitors C29, C30, C31, C32, C33, C34, C35, C36, C37 and C38 are connected in parallel; the DVDD_1 pin, DVDD_2 pin, DVDD_3 pin, DVDD_4 pin, DVDD_5 pin, DVDD_6 pin, DVDD_7 pin and DVDD_8 pin of the PHY chip are connected and then connected to the resistor FB1, and the resistor FB1 is connected to the capacitor C29; the MD of the PHY chip The I0p pin is connected to one end of the resistor R1, and the other end of the resistor R1 is respectively connected to one end of the capacitor C8 and one end of the resistor R6, and the MD I0n pin of the PHY chip is connected to the other end of the resistor R6; the MD I1p pin of the PHY chip is connected to one end of the resistor R7, and the other end of the resistor R7 is respectively connected to one end of the capacitor C9 and one end of the resistor R13, and the MD I1n pin of the PHY chip is connected to the other end of the resistor R13; the MD I2p pin of the PHY chip is connected to one end of the resistor R22, and the other end of the resistor R22 is respectively connected to one end of the capacitor C10 and one end of the resistor R25, and the MD I2n pin of the PHY chip is connected to the other end of the resistor R25; the MD I3p pin of the PHY chip is connected to one end of the resistor R28, and the other end of the resistor R28 is respectively connected to one end of the capacitor C11 and one end of the resistor R33, and the MD I3n pin of the PHY chip is connected to the other end of the resistor R33;The RSRT pin of the PHY chip is respectively connected to one end of the resistor R9 and one end of the resistor R11, the HSDACp pin of the PHY chip is connected to one end of the resistor R19, the HSDACh pin of the PHY chip is connected to one end of the resistor R21, the other end of the resistor R9, the other end of the resistor R11, the other end of the resistor R19 and the other end of the resistor R21 are connected and then connected to GND; the SINp pin of the PHY chip is connected to the capacitor C66, and the SINn pin of the PHY chip is connected to the capacitor C68; the CONFIG0 pin of the PHY chip is connected to the resistor R54, the CONFIG1 pin of the PHY chip is connected to the resistor R57, the CONFIG2 pin of the PHY chip is connected to the resistor R59, the CONFIG3 pin of the PHY chip is connected to the resistor R61, and the CONFIG3 pin of the PHY chip is connected to the resistor R62. The pin of the PHY chip is connected to the resistor R61, the CONFIG4 pin of the PHY chip is connected to the resistor R64, the CONFIG5 pin of the PHY chip is connected to the resistor R67, and the CONFIG6 pin of the PHY chip is connected to the resistor R69; the LED_LINK10 pin of the PHY chip is connected to the resistor R35, the LED_LINK100 pin of the PHY chip is connected to the resistor R37, the LED_LINK1000 pin of the PHY chip is connected to the resistor R38, the LED_DUPLEX pin of the PHY chip is connected to the resistor R39, the LED_RX pin of the PHY chip is connected to the resistor R40, the LED_TX pin of the PHY chip is connected to the resistor R41, the TD1 pin of the PHY chip is connected to the resistor R51, and the TRST pin of the PHY chip is connected to the resistor R53. ;

[0034] Standard Ethernet uses the UDP protocol to transmit data. Its data frame format consists of a preamble, a frame start delimiter, a destination MAC address, a source MAC address, a type, a destination IP address, a source IP address, a UDP header, a source port number, a destination port number, a UDP length, a UDP checksum, and data.

[0035] The PHY chip is a B88E1111MCB type PHY chip.

[0036] The TTE interface module in the power distributor is composed of a PHY chip and a network transformer, supporting time-triggered communication, standard Ethernet communication, dual / triple redundant communication, and 1000Mbps communication capability. The PHY chip model is 88E1111-B2-BAB2I000, and the network transformer model is GST5009MLF.

[0037] The distributor transmits the current and voltage status parameters of the distribution channel through time-triggered Ethernet, and receives distribution commands through standard Ethernet to control the distribution channel.

[0038] The power supply module consists of a filter, a DC / DC, and a power module. The filter mainly provides filtering, rectification, and short-circuit protection functions. The DC / DC is responsible for converting the external input 28V voltage into an internal 5V voltage to power internal devices. The power module has two HCE4644HB chips and one SM51200 chip that convert VCC5V into multiple voltages for use by the SoC system.

[0039] like Figure 3 As shown in the figure, the control module is built with the LSoCAM2A902 SOC chip as the core, and its chip peripheral configuration circuit mainly includes FLASH chip SM25QH256CK, DDR3 chip SM41J256M16HA, reset circuit SM708S, level conversion chip HWD16T245 and crystal oscillator CJZA515-125M-V3-A4-C3-A. The control module collects the switch status, voltage and current of each power distribution channel from the state acquisition module, and sends the collected data to the external controller through the TTE interface. The power distribution control command of the external controller is received through the standard Ethernet interface, and the power distribution instruction is output to the power distribution switch of the specified channel.

[0040] The control module outputs high and low levels through the I / O port to control the opening and closing of the specified power distribution channel.

[0041] The power distribution channel is composed of N isolation drive circuits (N≥1). The isolation drive circuit is composed of an isolation drive module and a power MOSFET. When the isolation drive module receives a high-level signal from the I / O port of the SOC chip, it isolates the signal and performs voltage boost and voltage regulation. After the voltage boost and voltage regulation, the gate voltage drive of the power MOSFET is controlled to realize the opening of the specified power distribution channel. When the isolation drive module receives a low-level signal from the I / O port of the SOC chip, the power distribution channel is turned off by controlling the gate voltage of the MOSFET after isolation. At the same time, the isolation drive module has the function of collecting the switching status of the MOSFET, which can collect the switching information of the MOSFET in real time and feed it back to the SOC chip.

[0042] The state acquisition module consists of an AD acquisition chip, a Hall sensor, a level conversion chip, and a magnetic isolation chip. The output voltage of the distribution branch enters the AD acquisition chip for acquisition after passing through a voltage divider resistor. The acquisition result is isolated by the magnetic isolation chip and reported to the control module through the SPI bus. The current acquisition uses a Hall chip to isolate the power circuit from the control circuit, convert the current signal into a voltage signal, and send it to the AD chip for acquisition. The power supply used by the AD acquisition chip and the magnetic isolation chip is the power supply generated after isolation, realizing the isolation design between the power circuit and the acquisition circuit.

[0043] The TTE interface module consists of a B88E1111MCB PHY chip and a T31S1108BT network transformer. The PHY chip is connected to an external SOC chip to achieve 1-way SGMII signal transmission, supporting 10Mbps, 100Mbps, and 1000Mbps self-adaptation, and supports TCP / IP, UDP, and MAC protocols.

[0044] The PHY chip and network transformer adopt a dual redundant structure.

[0045] When sending data, the PHY chip receives the data sent by the MAC, encodes the data into analog signals according to the physical layer encoding rules, and sends it out; when receiving data, the PHY converts the external data into serial data according to the encoding rules; the network transformer isolates the chip end from the outside to enhance anti-interference ability, while enhancing the signal to make the transmission distance longer.

[0046] Standard Ethernet uses the UDP protocol to transmit data. Its data frame format consists of a preamble, a frame start delimiter, a destination MAC address, a source MAC address, a type, a destination IP address, a source IP address, a UDP header, a source port number, a destination port number, a UDP length, a UDP checksum, and data.

[0047] TTE communication is compatible with standard Ethernet communication methods.

[0048] The parameters of TTE communication such as end system ID, virtual link ID, cycle, time delay, etc. need to be set according to the overall configuration table.

[0049] After TTE communication is configured according to the schedule table, the SOC chip encapsulates the transmission data into TT frames and sends them according to the rules of the configuration table.

[0050] This embodiment is a domestically produced solid-state power distributor based on the fusion of time-triggered Ethernet (TTE) and standard Ethernet. It fully combines the advantages of time-triggered Ethernet (TTE) and standard Ethernet, collects current and voltage state parameters through the time-triggered Ethernet transmission distribution channel, and controls the distribution channel by receiving distribution commands through standard Ethernet, effectively avoiding resource conflicts between the collected state parameters and the distribution instructions. At the same time, the network based on the time trigger mechanism drives communication through the time process, the triggering factors are stable, and the system behavior is determined, which greatly improves the communication rate and reliability of the system.

[0051] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A nationally produced solid-state power distributor based on the integration of TTE and standard Ethernet, characterized in that include: Control module, status acquisition module, TTE interface module and power distribution module; among them, The control module: receives the standard Ethernet power distribution instruction of the TTE interface module, parses the standard Ethernet power distribution instruction to obtain the power distribution module control instruction, and transmits the power distribution module control instruction to the power distribution module; receives the power distribution channel current and voltage data from the status acquisition module, and transmits the power distribution channel current and voltage data to the TTE interface module; The TTE interface module receives a standard Ethernet power distribution instruction from an external controller and transmits the standard Ethernet power distribution instruction to the control module; receives current and voltage data of a power distribution channel and transmits the current and voltage data of a power distribution channel to an external controller; The power distribution module receives a power distribution module control instruction and isolates and drives the power distribution channel switch according to the power distribution module control instruction; The state acquisition module is used to collect current and voltage data of the power distribution channel, and transmit the current and voltage data of the power distribution channel to the control module.

2. The nationally produced solid-state power distributor based on the integration of TTE and standard Ethernet according to claim 1 is characterized in that Also includes: A power supply module; wherein: The power supply module is used to supply power to the control module, the status acquisition module, the TTE interface module and the power distribution module.

3. The nationally produced solid-state power distributor based on the integration of TTE and standard Ethernet according to claim 2 is characterized in that: The power supply module includes a filter, a DC / DC and a power supply module; wherein, The filter processes the external input 28V voltage to obtain a filtered external input 28V voltage, and transmits the external input 28V voltage to the DC / DC; The DC / DC converts the external input 28V voltage into an internal 5V voltage, and transmits the internal 5V voltage to the power module; The power module converts the internal 5V voltage into multiple required voltages.

4. The nationally produced solid-state power distributor based on the integration of TTE and standard Ethernet according to claim 2 is characterized in that: Multiple required voltages include 1.2V, 1.5V, 2.5V, and 3.3V.

5. The nationally produced solid-state power distributor based on the integration of TTE and standard Ethernet according to claim 1 is characterized in that: The power distribution module includes a plurality of isolation drive circuits.

6. The nationally produced solid-state power distributor based on the integration of TTE and standard Ethernet according to claim 5 is characterized in that: The isolation driving circuit includes an isolation driving module and a power MOSFET; wherein, When the isolation drive module receives a high-level signal in the power distribution module control instruction of the control module, it isolates the high-level signal and performs voltage boost and voltage regulation, and controls the gate voltage drive of the power MOSFET after the voltage boost and voltage regulation process, thereby realizing the opening of the power distribution channel; When the isolation driving module receives a low-level signal in the power distribution module control instruction of the control module, it isolates the low-level signal and controls the gate voltage of the power MOSFET to realize the shutdown of the power distribution channel.

7. The nationally produced solid-state power distributor based on the integration of TTE and standard Ethernet according to claim 1 is characterized in that: The state acquisition module includes an AD acquisition chip, a Hall sensor and a magnetic isolation chip; wherein, The AD acquisition chip acquires the distribution channel voltage, and transmits the distribution channel voltage to the control module after isolation through the magnetic isolation chip; The Hall sensor collects current signals, converts the current signals into voltage signals, and sends them to the AD chip for collection.

8. The nationally produced solid-state power distributor based on the integration of TTE and standard Ethernet according to claim 1 is characterized in that: The TTE interface module includes a PHY chip, a network transformer, a resistor FB3, a resistor FB5, a resistor FB7, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C15, a capacitor C16, a capacitor C17, a capacitor C18, a capacitor C19, a capacitor C20, a capacitor C21, a capacitor C49, a capacitor C50, a capacitor C51, a capacitor C52, a capacitor C53, a capacitor C54, a resistor FB1, a capacitor C29, a capacitor C30, a capacitor C31, a capacitor C32, a capacitor C33, a capacitor C34, a capacitor C35, a capacitor C36, a capacitor C37, a capacitor C38, a resistor R2, a resistor R10, a resistor R14, a resistor R27, a resistor R30, a resistor R31, a capacitor C73, a resistor R42, a resistor R36, and a resistor R63 , chip U3, capacitor C77, capacitor C78, ​​capacitor C75, capacitor C81, capacitor C82, capacitor C85, capacitor C88, resistor FB9, resistor R71, resistor R72, resistor R74, resistor R76, capacitor C83, resistor R9, resistor R11, resistor R19, resistor R21, capacitor C66, capacitor C68, resistor R35, resistor R37, resistor R38, resistor R39, resistor R40, resistor R41, resistor R51, resistor R53, resistor R54, resistor R57, resistor R59, resistor R61, resistor R64, resistor R67, resistor R69, resistor R1, resistor R6, resistor R7, resistor R13, resistor R22, resistor R25, resistor R28, resistor R33, capacitor C8, capacitor C9, capacitor C10, capacitor C11; wherein, One end of the resistor FB3 is respectively connected to one end of the resistor FB5 and one end of the resistor FB7 and then connected to GTX_2V5; The capacitors C1, C2, C3, C4, C5, C6 and C7 are connected in parallel; The other end of the resistor FB3 is connected to the capacitor C1, and the AVDDF pin of the PHY chip, the AVDD_1 pin of the PHY chip, the AVDD_2 pin of the PHY chip, the AVDD_3 pin of the PHY chip, the AVDD_4 pin of the PHY chip and the AVDDH pin of the PHY chip are connected and then connected to the capacitor C7; The capacitor C15, capacitor C16, capacitor C17, capacitor C18, capacitor C19, capacitor C20, and capacitor C21 are connected in parallel; The other end of the resistor FB5 is connected to the capacitor C11, and the VDD OX_1 pin of the PHY chip, the VDD OX_2 pin of the PHY chip, the VDD OH_1 pin of the PHY chip, the VDD OH_2 pin of the PHY chip and the VDD OH_3 pin of the PHY chip are connected and then connected to the capacitor C20; Capacitor C49, capacitor C50, capacitor C51, capacitor C52, capacitor C53 and capacitor C54 are connected in parallel; The other end of the resistor FB7 is connected to the capacitor C49, and the VDD_1 pin of the PHY chip, the VDD_2 pin of the PHY chip and the VDD_3 pin of the PHY chip are connected and then connected to the capacitor C54; The TXD0 pin of the PHY chip, the TXD1 pin of the PHY chip, the TXD2 pin of the PHY chip, the TXD3 pin of the PHY chip, the TXD4 pin of the PHY chip, the TXD5 pin of the PHY chip, the TXD6 pin of the PHY chip and the TXD7 pin of the PHY chip are connected and then connected to the resistor R2; The TX_EN pin of the PHY chip is connected to one end of the resistor R10, the TX_ER pin of the PHY chip is connected to one end of the resistor R14, and the other end of the resistor R10 is connected to the other end of the resistor R14 and then connected to GND; The MDC pin of the PHY chip is connected to one end of the resistor R27, the MDIO pin of the PHY chip is connected to one end of the resistor R30, the INT pin of the PHY chip is connected to one end of the resistor R31, the other end of the resistor R27, the other end of the resistor R30 and the other end of the resistor R31 are connected and then connected to GTX 2V5; The RESRT pin of the PHY chip is connected to one end of the resistor R42 and one end of the capacitor C73; the other end of the resistor R42 and the other end of the capacitor C73 are connected to GND; The COMA pin of the PHY chip is connected to one end of the resistor R36; the other end of the resistor R36 is connected to GND; The CLKOUT pin of the chip U3 is connected to one end of the resistor R63, and the other end of the resistor R63 is connected to the XTAL1 pin of the PHY chip; the VCC pin of the chip U3 is connected to GTX_2V5, and the capacitors C77 and C78 are connected in parallel and then connected to the VCC pin of the chip U3; the GND pin of the chip U3 is connected to one end of the capacitor C75, and the OE pin of the chip U3 is connected to the other end of the capacitor C75, and the OE pin of the chip U3 is connected to the VCC pin of the chip U3; Capacitor C81, capacitor C82 and capacitor C85 are connected in parallel and then connected to the TCT1 pin of the network transformer, the TCT2 pin of the network transformer, the TCT3 pin of the network transformer and the TCT4 pin of the network transformer respectively; the MCT1 pin of the network transformer is connected to one end of the resistor R71, the MCT2 pin of the network transformer is connected to one end of the resistor R72, the MCT3 pin of the network transformer is connected to one end of the resistor R74, the MCT4 pin of the network transformer is connected to one end of the resistor R76, the other end of the resistor R71, the other end of the resistor R72, the other end of the resistor R74 and the other end of the resistor R76 are connected and then connected to one end of the capacitor C83, and the other end of the capacitor C83 is connected to TTE_GND; Capacitor C29, capacitor C30, capacitor C31, capacitor C32, capacitor C33, capacitor C34, capacitor C35, capacitor C36, capacitor C37 and capacitor C38 are connected in parallel; The DVDD_1 pin, DVDD_2 pin, DVDD_3 pin, DVDD_4 pin, DVDD_5 pin, DVDD_6 pin, DVDD_7 pin, and DVDD_8 pin of the PHY chip are connected and then connected to the resistor FB1, and the resistor FB1 is connected to the capacitor C29; The MD I0p pin of the PHY chip is connected to one end of the resistor R1, the other end of the resistor R1 is respectively connected to one end of the capacitor C8 and one end of the resistor R6, and the MD I0n pin of the PHY chip is connected to the other end of the resistor R6; The MD I1p pin of the PHY chip is connected to one end of the resistor R7, the other end of the resistor R7 is respectively connected to one end of the capacitor C9 and one end of the resistor R13, and the MD I1n pin of the PHY chip is connected to the other end of the resistor R13; The MD I2p pin of the PHY chip is connected to one end of the resistor R22, the other end of the resistor R22 is respectively connected to one end of the capacitor C10 and one end of the resistor R25, and the MD I2n pin of the PHY chip is connected to the other end of the resistor R25; The MD I3p pin of the PHY chip is connected to one end of the resistor R28, the other end of the resistor R28 is respectively connected to one end of the capacitor C11 and one end of the resistor R33, and the MD I3n pin of the PHY chip is connected to the other end of the resistor R33; The RSRT pin of the PHY chip is respectively connected to one end of the resistor R9 and one end of the resistor R11, the HSDACp pin of the PHY chip is connected to one end of the resistor R19, the HSDACh pin of the PHY chip is connected to one end of the resistor R21, and the other end of the resistor R9, the other end of the resistor R11, the other end of the resistor R19 and the other end of the resistor R21 are connected and then connected to GND; The SINp pin of the PHY chip is connected to the capacitor C66, and the SINn pin of the PHY chip is connected to the capacitor C68; The CONFIG0 pin of the PHY chip is connected to the resistor R54, the CONFIG1 pin of the PHY chip is connected to the resistor R57, the CONFIG2 pin of the PHY chip is connected to the resistor R59, the CONFIG3 pin of the PHY chip is connected to the resistor R61, the CONFIG3 pin of the PHY chip is connected to the resistor R61, the CONFIG4 pin of the PHY chip is connected to the resistor R64, the CONFIG5 pin of the PHY chip is connected to the resistor R67, and the CONFIG6 pin of the PHY chip is connected to the resistor R69; The LED_LINK10 pin of the PHY chip is connected to the resistor R35, the LED_LINK100 pin of the PHY chip is connected to the resistor R37, the LED_LINK1000 pin of the PHY chip is connected to the resistor R38, the LED_DUPLEX pin of the PHY chip is connected to the resistor R39, the LED_RX pin of the PHY chip is connected to the resistor R40, the LED_TX pin of the PHY chip is connected to the resistor R41, the TD1 pin of the PHY chip is connected to the resistor R51, and the TRST pin of the PHY chip is connected to the resistor R53.

9. The nationally produced solid-state power distributor based on the integration of TTE and standard Ethernet according to claim 1 is characterized in that: Standard Ethernet uses the UDP protocol to transmit data. Its data frame format consists of a preamble, a start frame delimiter, a destination MAC address, a source MAC address, a type, a destination IP address, a source IP address, a UDP header, a source port number, a destination port number, a UDP length, a UDP checksum, and data.

10. The nationally produced solid-state power distributor based on the integration of TTE and standard Ethernet according to claim 9 is characterized in that: The PHY chip is a B88E1111MCB type PHY chip.

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