Linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier

Abstract

The application discloses a linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier, which comprises a power divider, a delay network, a main path input matching network, an auxiliary path input matching network, a main path driving stage transistor, an auxiliary path driving stage transistor module, a main path intermediate stage matching network, an auxiliary path intermediate stage matching network, a main transistor, an auxiliary transistor module and a distributed output combining network based on a band-pass T structure. The application adopts a distributed unit circuit based on a band-pass T structure to replace a traditional capacitor-loaded transmission line network, so that the matching bandwidth of the distributed output combining network based on the band-pass T structure at the optimal impedance value Qopt of the transistor is significantly improved. Compared with the prior art, the distributed output combining network based on the band-pass T structure has certain gain expansion characteristics and improves the high-linearity DEPA design expansion performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of wireless communication power amplifier technology, and particularly relates to a linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier. BACKGROUND

[0002] In the current communication power amplifier circuit design, gallium nitride transistors are usually used to provide high power density and excellent thermal performance in the millimeter wave frequency band, so as to improve the average efficiency of the power amplifier under high average peak ratio modulation signals.

[0003] Several existing broadband high back-off efficiency functions include load-modulated balanced amplifier (LMBA), unbalanced amplifier and distributed efficient power amplifier (DEPA) and the like. Among them, the DEPA structure includes a traveling wave network and a plurality of sub-power amplifiers. By virtue of the particularity of the non-uniform traveling wave network, the DEPA can support multiple impedance modulation, and theoretically has the potential to realize broadband operation and high back-off efficiency. For example, the implementation method of the DEPA input network is improved, and the amplitude and phase control of the sub-power amplifier is realized by means of the traveling wave network, so as to realize a compact volume, excellent bandwidth and efficiency performance in the sub-6GHz frequency band. However, the application of DEPA technology in the millimeter wave frequency band faces the following problems: first, in the existing DEPA technology, when the auxiliary transistor is turned on, the operation of the main transistor will enter or approach the saturation region, which leads to high gain compression and poor linearity. Secondly, the high frequency characteristics of the millimeter wave and the high bias voltage characteristics of the gallium nitride device lead to a very high transistor optimal impedance value Q (Q = ωRoptMCout), which increases the complexity of the design of the traveling wave network.

[0004] Therefore, the prior art still needs to be improved and developed. SUMMARY

[0005] In view of the deficiencies of the prior art, the purpose of the present application is to provide a linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier, so as to solve the problems of serious parasitic parameter efficiency of the gallium nitride transistor in the existing distributed high-efficiency power amplifier, the operation of the main transistor entering or approaching the saturation region when the auxiliary transistor is turned on, and high transistor impedance value and narrow matching bandwidth.

[0006] The technical scheme of the present application is as follows:

[0007] The linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier comprises a power divider, a delay network, a main path input matching network, an auxiliary path input matching network, a main path drive stage transistor, an auxiliary path drive stage transistor module, a main path intermediate stage matching network, an auxiliary path intermediate stage matching network, a main transistor, an auxiliary transistor module and a distributed output combining network based on a band-pass T structure; wherein the output end of the power divider is connected with the input end of the main path input matching network and the input end of the delay network respectively, for non-equal power distribution of the accessed radio frequency input signal;

[0008] The output end of the delay network is connected with the input end of the auxiliary path input matching network, for adjusting the phase difference between the signal at the input end of the auxiliary path input matching network and the main path signal.

[0009] The output end of the main path input matching network is connected with the gate of the main path drive stage transistor, and the main path input matching network is used for matching the port output impedance of the main path input matching network to the source impedance of the main path drive stage transistor.

[0010] The input end of the auxiliary path input matching network is connected with the output end of the delay network, and the output end of the auxiliary path input matching network is connected with the auxiliary path drive stage transistor module, for matching the port output impedance of the auxiliary path input matching network to the source impedance of the auxiliary path drive stage transistor module.

[0011] The input end of the main path intermediate stage matching network is connected with the drain of the main path drive stage transistor, the output end of the main path intermediate stage matching network is connected with the gate of the main transistor, and the main path intermediate stage matching network is used for impedance transformation of the radio frequency input signal.

[0012] The input end of the auxiliary path intermediate stage matching network is connected with the auxiliary path drive stage transistor module, and the output end of the auxiliary path intermediate stage matching network is connected with the auxiliary path drive stage transistor module, for impedance transformation of the radio frequency input signal.

[0013] The input end of the distributed output combining network based on the band-pass T structure is connected with the drain of the main transistor and the output end of the auxiliary transistor module respectively, and the distributed output combining network based on the band-pass T structure is used for realizing a wide-band traveling wave network and absorbing the parasitic parameters of the main transistor and the auxiliary transistor module.

[0014] Further provided in the application, the distributed output combining network based on the band-pass T structure comprises a first band-pass T structure unit, a second band-pass T structure unit, a third band-pass T structure unit, a first output capacitor, a second output capacitor, a third output capacitor, a fourth output capacitor, a first output resistor and a post-matching network.

[0015] One end of the first band-pass T structure unit is connected with the drain of the main transistor and one end of the first output capacitor respectively, and the other end of the first band-pass T structure unit is connected with the first output end of the auxiliary transistor module, the second output capacitor and the common connection end of the second band-pass T structure unit;

[0016] The other end of the second band-pass T structure unit is connected with the second output end of the auxiliary transistor module, one end of the third output capacitor and the common connection end of the third band-pass T structure unit;

[0017] The other end of the third band-pass T structure unit is connected with the third output end of the auxiliary transistor module, the fourth output capacitor and the common connection end of the post matching network;

[0018] The other end of the first output capacitor, the other end of the second output capacitor, the other end of the third output capacitor and the other end of the fourth output capacitor are grounded;

[0019] The other end of the post matching network is connected with the radio frequency output end through the first output resistor.

[0020] Further provided in the application, in the band-pass T structure based distributed output combining network, the first band-pass T structure unit comprises a first transmission line, a second transmission line and a third transmission line; the second band-pass T structure unit comprises a fourth transmission line, a fifth transmission line and a sixth transmission line; the third band-pass T structure unit comprises a seventh transmission line and an eighth transmission line; and the post matching network comprises a ninth transmission line, a tenth transmission line and a direct current blocking capacitor C1;

[0021] One end of the first transmission line is connected with the drain of the main transistor and one end of the first output capacitor respectively; one end of the second transmission line is connected with one end of the first transmission line and one end of the third transmission line respectively, and the other end of the second transmission line is grounded; the other end of the third transmission line is connected with the common connection end of the fourth transmission line, the first output end of the auxiliary transistor module and the second output capacitor;

[0022] The other end of the fourth transmission line is connected with one end of the fifth transmission line and the sixth transmission line respectively, the other end of the fifth transmission line is grounded, and the other end of the sixth transmission line is connected with one end of the seventh transmission line and the second output end of the auxiliary transistor module respectively;

[0023] The other end of the seventh transmission line is connected with one end of the eighth transmission line, and the other end of the eighth transmission line is connected with the common connection end of the third output end of the auxiliary transistor module, the fourth output capacitor and one end of the ninth transmission line;

[0024] The other end of the ninth transmission line is connected with one end of the direct-current blocking capacitor C1 and the tenth transmission line respectively, and the other end of the first output capacitor, the other end of the second output capacitor, the other end of the third output capacitor and the other end of the fourth output capacitor are grounded.

[0025] Further provided in the application, the auxiliary road driving stage transistor module comprises a first auxiliary road driving stage transistor, a second auxiliary road driving stage transistor and a third auxiliary road driving stage transistor.

[0026] The gate of the first auxiliary road driving stage transistor, the gate of the second auxiliary road driving stage transistor and the gate of the third auxiliary road driving stage transistor are connected with the output end of the auxiliary road input matching network respectively, the source of the first auxiliary road driving stage transistor, the source of the second auxiliary road driving stage transistor and the source of the third auxiliary road driving stage transistor are grounded, and the drain of the first auxiliary road driving stage transistor, the drain of the second auxiliary road driving stage transistor and the drain of the third auxiliary road driving stage transistor are connected with the auxiliary road intermediate stage matching network respectively.

[0027] Further provided in the application, the auxiliary transistor module comprises a first auxiliary transistor, a second auxiliary transistor and a third auxiliary transistor, the gate of the first auxiliary transistor, the gate of the second auxiliary transistor and the gate of the third auxiliary transistor are connected with the auxiliary road intermediate stage matching network respectively, the source of the first auxiliary transistor, the source of the second auxiliary transistor and the source of the third auxiliary transistor are grounded, and the drain of the first auxiliary transistor, the drain of the second auxiliary transistor and the drain of the third auxiliary transistor are connected with the distributed output combining network based on the band-pass T structure respectively.

[0028] Further provided in the application, the auxiliary road intermediate stage matching network comprises a first auxiliary road intermediate stage matching network, a second auxiliary road intermediate stage matching network and a third auxiliary road intermediate stage matching network, the input end of the first auxiliary road intermediate stage matching network is connected with the drain of the first auxiliary road driving stage transistor, the input end of the second auxiliary road intermediate stage matching network is connected with the drain of the second auxiliary road driving stage transistor, and the third auxiliary road intermediate stage matching network is connected with the drain of the third auxiliary road driving stage transistor, the first auxiliary road intermediate stage matching network, the second auxiliary road intermediate stage matching network and the third auxiliary road intermediate stage matching network are cascaded with each other, for absorbing the parasitic parameters in the first auxiliary road driving stage transistor, the second auxiliary road driving stage transistor and the third auxiliary road driving stage transistor respectively.

[0029] Further arrangement of the present application, the circuit structure and size of the first auxiliary road intermediate level matching network, the second auxiliary road intermediate level matching network and the third auxiliary road intermediate level matching network are same, the main road intermediate level matching network comprises: first intermediate transmission line, second intermediate transmission line, third intermediate transmission line, fourth intermediate transmission line, fifth intermediate transmission line, sixth intermediate resistance, seventh intermediate resistance, first intermediate capacitor, second intermediate capacitor, third intermediate capacitor, fourth intermediate capacitor, fifth intermediate capacitor and sixth intermediate capacitor;Wherein,

[0030] One end of the first intermediate capacitor is connected with the drain of the main road driving stage transistor, the other end of the first intermediate capacitor is connected with the common connection end of the second intermediate transmission line, the third intermediate transmission line and the second intermediate capacitor respectively, the other end of the second intermediate transmission line is connected with one end of the first intermediate capacitor, and the other end of the first intermediate capacitor is grounded;The other end of the second intermediate capacitor is connected with the common connection end of the fourth intermediate transmission line and the fifth intermediate transmission line, the sixth intermediate resistance and the fifth intermediate capacitor are connected in parallel and connected with the gate of the main transistor;The other end of the fifth intermediate transmission line is connected with the common connection end of the sixth intermediate capacitor and the seventh intermediate resistance respectively, the other end of the fourth intermediate transmission line is connected with one end of the fourth intermediate capacitor, the other end of the third intermediate transmission line is connected with one end of the third intermediate capacitor, and the other end of the third intermediate capacitor and the other end of the fourth intermediate capacitor are grounded.

[0031] Further arrangement of the present application, the main road input matching network comprises: first main road input transmission line, second main road input transmission line, third main road input transmission line, fourth main road input resistance, fifth main road input transmission line, sixth main road input resistance, first main road input capacitor, second main road input capacitor, third main road input capacitor and fourth main road input capacitor;Wherein, one end of the first main road input transmission line is connected with the main road output end of the power divider, the other end of the first main road input transmission line is connected with one end of the first main road input capacitor, the other end of the first main road input capacitor is connected with the common connection end of the second main road input capacitor and the second main road input transmission line, the other end of the second main road input capacitor is grounded, and the other end of the second main road input transmission line is connected with one end of the third main road input transmission line and one end of the fifth main road input transmission line respectively;The other end of the third main road input transmission line is connected with the common connection end of the fourth main road input resistance and the third main road input capacitor, the other end of the fourth main road input resistance is connected with the input end of the driving voltage, the other end of the third main road input capacitor is grounded, the common connection end of the sixth main road input resistance and the fourth main road input capacitor is connected with the fifth main road input transmission line, and the sixth main road input resistance and the fourth main road input capacitor are connected in parallel and connected with the gate of the main road driving stage transistor.

[0032] Further, the delay network comprises a first delay transmission line, a second delay transmission line, a third delay transmission line, a fourth delay transmission line, a fifth delay transmission line, a sixth delay transmission line, a first delay capacitor, a second delay capacitor, a third delay capacitor, a fourth delay capacitor, a fifth delay capacitor and a sixth delay capacitor, wherein,

[0033] One end of the first delay transmission line is connected to the auxiliary path output end of the power divider, and the other end of the first delay transmission line is connected to the common connection end of the second delay capacitor and the second delay transmission line, respectively;

[0034] The other end of the second delay transmission line is connected to one end of the first delay capacitor, the other end of the second delay capacitor is connected to one end of the third delay transmission line, the other end of the third delay transmission line is connected to the common connection end of the third delay capacitor, the fourth delay transmission line, the other end of the fourth delay transmission line is connected to the common connection end of the fourth delay capacitor, the fifth delay transmission line, the other end of the fifth delay transmission line is connected to one end of the fifth delay capacitor, the other end of the fifth delay capacitor is connected to the input end of the auxiliary path input matching network and one end of the sixth delay transmission line, respectively, the other end of the sixth delay transmission line is connected to the sixth delay capacitor, and the other end of the first delay capacitor, the other end of the third delay capacitor, the other end of the fourth delay capacitor and the other end of the sixth delay capacitor are grounded.

[0035] The further arrangement of the application, the auxiliary road input matching network comprises: a first auxiliary road input capacitor, a second auxiliary road input capacitor, a first auxiliary road input transmission line, a third auxiliary road input resistor, a third auxiliary road input capacitor, a second auxiliary road input transmission line, a fourth auxiliary road input capacitor, a fourth auxiliary road input transmission line, a fifth auxiliary road input resistor, a fifth auxiliary road input capacitor, a sixth auxiliary road input transmission line, a sixth auxiliary road input capacitor, a seventh auxiliary road input transmission line, an eighth auxiliary road input resistor, a seventh auxiliary road input capacitor, a ninth auxiliary road input transmission line, a tenth auxiliary road input resistor and an eighth auxiliary road input capacitor. Wherein, one end of the first auxiliary road input capacitor is connected to the delay network, the other end of the first auxiliary road input capacitor is connected to the common connection end of the second auxiliary road input capacitor and the first auxiliary road input transmission line, and the other end of the second auxiliary road input capacitor is grounded; the other end of the first auxiliary road input transmission line is connected to the common connection end of the second auxiliary road input transmission line, the third auxiliary road input resistor and the third auxiliary road input capacitor respectively; the third auxiliary road input resistor and the third auxiliary road input capacitor are connected in parallel to the first auxiliary road drive stage transistor; the other end of the second auxiliary road input transmission line is connected to the common connection end of the fourth auxiliary road input capacitor and the fourth auxiliary road input transmission line, and the other end of the fourth auxiliary road input transmission line is connected to the common connection end of the sixth auxiliary road input transmission line, the fifth auxiliary road input resistor and the fifth auxiliary road input capacitor; the fifth auxiliary road input resistor and the fifth auxiliary road input capacitor are connected in parallel to the second auxiliary road drive stage transistor for outputting the matched traveling wave signal; the other end of the sixth auxiliary road input transmission line is connected to the common connection end of the sixth auxiliary road input capacitor and the seventh auxiliary road input transmission line, and the other end of the seventh auxiliary road input transmission line is connected to the common connection end of the ninth auxiliary road input transmission line, the eighth auxiliary road input resistor and the seventh auxiliary road input capacitor respectively; the eighth auxiliary road input resistor and the seventh auxiliary road input capacitor are connected in parallel to the third auxiliary road drive stage transistor; the other end of the ninth auxiliary road input transmission line is connected to one end of the tenth auxiliary road input resistor, the other end of the tenth auxiliary road input resistor is connected to the driving signal and the eighth auxiliary road input capacitor respectively, and the other end of the fourth auxiliary road input capacitor, the other end of the sixth auxiliary road input capacitor and the other end of the eighth auxiliary road input capacitor are grounded.

[0036] The linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier provided by the application comprises a power divider, a delay network, a main path input matching network, an auxiliary path input matching network, a main path drive stage transistor, an auxiliary path drive stage transistor module, a main path intermediate stage matching network, an auxiliary path intermediate stage matching network, a distributed output combining network based on a band-pass T structure, a main transistor and an auxiliary transistor module. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of the drawings shown.

[0038] Figure 1 The structural block diagram of the linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier provided by the application is shown in the figure.

[0039] Figure 2 The circuit principle diagram of the traditional capacitor-loaded transmission line equivalent transmission line in the prior art is shown in the figure.

[0040] Figure 3 The T structure schematic diagram in the linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier provided by the application is shown in the figure.

[0041] Figure 4 The circuit principle diagram of the distributed output combining network based on the band-pass T structure in the linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier provided by the application is shown in the figure.

[0042] Figure 5 The circuit principle diagram of the main path intermediate stage matching network in one preferred embodiment of the present application is shown in the figure.

[0043] Figure 6 The circuit principle diagram of the main path input matching network in one preferred embodiment of the present application is shown in the figure.

[0044] Figure 7 Circuit schematic diagram of the delay network in a preferred embodiment of the present application;

[0045] Figure 8 Circuit schematic diagram of the auxiliary path input matching network in a preferred embodiment of the present application;

[0046] Figure 9 Gain and power added efficiency of the DEPA under different power split ratios in a preferred embodiment of the present application;

[0047] Figure 10 Amplitude distortion of the distributed output combining network based on bandpass T structure, the internal current source plane of the main transistor, the input network and the DEPA when PSR=3dB in a preferred embodiment of the present application;

[0048] Figure 11 Large signal test results of the backoff efficiency enhancement mode in a preferred embodiment of the present application;

[0049] Figure 12 Large signal test results of the bandwidth enhancement mode in a preferred embodiment of the present application.

[0050] Figure 13 Gain variation of the distributed output combining network based on bandpass T structure, the internal current source plane of the main transistor, the input network and the DEPA with the increase of input power in a preferred embodiment of the present application. DETAILED DESCRIPTION

[0051] The present application provides a linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier. In order to make the purpose, technical scheme and effect of the present application more clear and explicit, the present application is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0052] In the embodiments and the scope of the application, unless the article is specifically limited in the text, "a", "an", "said" and "the" can also include plural forms. If the description of "first", "second" and the like is involved in the embodiments of the present application, the description of "first", "second" and the like is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include at least one of the features.

[0053] It should be further understood that the word "comprise" or "comprising", when used in this specification, specifies the presence of stated features, integers, steps, operations, elements, or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. It will be understood that when an element or component is referred to as being "connected" or "coupled" to another element or component, it can be directly connected or coupled to the other element or component or intervening elements or components can be present. In addition, the word "connected" or "coupled" as used herein can include wirelessly connected or wirelessly coupled. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0054] Those skilled in the art will understand that the terms used herein are for the purpose of describing specific embodiments and are not intended to limit the present application. Unless otherwise defined, all terms used herein, including technical terms and scientific terms, have the same meanings as those generally understood by those skilled in the art in the field of the present application. It will be further understood that terms, such as those defined in a generally used dictionary, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0055] In addition, the technical solutions among various embodiments can be combined with each other, but it must be based on the fact that a person skilled in the art can realize the combination, and when the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, nor is it within the scope of protection required by the present application.

[0056] Please refer to Figure 1The application provides a linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier, which comprises a power divider 100, a delay network 200, a main path input matching network 300, an auxiliary path input matching network 400, a main path drive stage transistor Q510, an auxiliary path drive stage transistor module 500, a main path intermediate stage matching network 600, an auxiliary path intermediate stage matching network 700, a main transistor Q810, an auxiliary transistor module 800 and a distributed output combining network 900 based on a bandpass T structure. The output end of the power divider 100 is connected with the input end of the main path input matching network 300 and the input end of the delay network 200 respectively, the output end of the delay network 200 is connected with the input end of the auxiliary path input matching network 400, the output end of the main path input matching network 300 is connected with the gate of the main path drive stage transistor Q510, the input end of the auxiliary path input matching network 400 is connected with the output end of the delay network 200, and each output end of the auxiliary path input matching network 400 is connected with the auxiliary path drive stage transistor module 500. The input end of the main path intermediate stage matching network 600 is connected with the drain of the main path drive stage transistor Q510, the output end of the main path intermediate stage matching network 600 is connected with the gate of the main transistor Q810, the auxiliary path drive stage transistor module 500 is connected with the input end of the auxiliary path intermediate stage matching network 700 respectively, the output end of the auxiliary path intermediate stage matching network 700 is connected with the auxiliary path drive stage transistor module 500, and the input end of the distributed output combining network 900 based on the bandpass T structure is connected with the drain of the main transistor Q810 and the auxiliary transistor module 800 respectively.

[0057] In implementation, the input end of the power divider 100 is connected with a radio frequency input end, non-equal power distribution is performed on a radio frequency input signal, and the main path signal and the auxiliary path signal after non-equal power distribution are output to the input end of the main path input matching network 300 and the delay network 200 in the auxiliary path respectively. The main path input matching network 300 is used for matching the port output impedance of the main path input matching network 300 with the source impedance of the main path drive stage transistor Q510, the delay network 200 is used for adjusting the phase difference between the signal at the input end of the auxiliary path input matching network 400 and the main path input matching network 300, and ensuring that the main auxiliary branch phase relationship is matched. The main path signal after impedance matching flows through the main path drive stage transistor Q510 for signal amplification, and is output to the main path intermediate stage matching network 600 to perform further impedance transformation on the main path signal, and the main path signal after impedance transformation is output to the gate of the main transistor Q810. The main path signal after amplification by the main transistor Q810 is output to the distributed output combining network 900 based on the band-pass T structure. In the auxiliary path branch, the auxiliary path signal after phase difference adjustment by the delay network 200 is input to the auxiliary path input matching network 400, the auxiliary path input matching network 400 is used for matching the port output impedance of the auxiliary path input matching network 400 with the source impedance of the auxiliary path drive stage transistor module 500, and outputting as a plurality of auxiliary path signals. The plurality of auxiliary path signals are input to the auxiliary path drive stage transistor module 500 respectively, and each auxiliary path signal after amplification flows through the auxiliary path intermediate stage matching network 700, the auxiliary path intermediate stage matching network 700 is used for performing impedance transformation on the input auxiliary path signal, and outputting to the distributed output combining network 900 based on the band-pass T structure after amplification by the auxiliary transistor module 800. The distributed output combining network 900 based on the band-pass T structure is used for realizing a wideband traveling wave network, and absorbing the parasitic parameters of the output end of the main transistor Q810 and the auxiliary transistor module 800. By replacing the traditional capacitance-loaded transmission line network with the distributed output combining network 900 based on the band-pass T structure, the parasitic parameters of the transistor itself are absorbed, and the matching bandwidth of the distributed output combining network under the optimal impedance value Qopt of the large transistor is improved.

[0058] Specifically, the power divider 100 is a non-equal Wilkinson power divider 100, and the radio frequency input signal is non-equal power distributed in a ratio of 1:2, and the non-equal power distribution ratio corresponds to the port output impedance ratio of the main path and the auxiliary path.

[0059] In the preferred embodiment, the power distribution ratio (PSR) of the power divider 100 has an important influence on the DEPA linearity. Please refer to Figure 9 、 Figure 10 , Figure 9The gain and power added efficiency of DEPA with different power split ratios are shown, when PSR changes from 2dB to 4dB, the gain gradually changes from compression characteristic to expansion characteristic. Figure 10 The amplitude distortion of the band-pass T structure based distributed output combining network 900 (G R ), the internal current source plane of the main transistor Q810 (G M ), the input network (G V ) and DEPA (G DEPA ) with PSR=3dB is shown, the amplitude distortion of the output network, the main transistor Q810 and each input network can be well cancelled to exhibit a relatively flat overall gain characteristic. In order to build the optimal gain flatness and integrate the implementation difficulty of the actual power divider 100, the application preferably adopts the Wilkinson non-equal power divider with a power split ratio of 3dB. When the application environment changes, the gain compression characteristic of the linear wideband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier can be adjusted by the power split ratio of the power divider 100, and this degree of freedom is used to build the expansion DEPA gain characteristic and to compensate for the gain compression of the main path transistor in the actual design, thereby improving the linearity of the entire DEPA. At the same time, the band-pass T structure based distributed output combining network has gain expansion characteristic, with the increase of input power, the gain of the entire network presents a gradually increasing trend, which is convenient for high linearity DEPA design.

[0060] Please also refer to Figure 1 and Figure 7The delay network 200 comprises a first delay transmission line TL201, a second delay transmission line TL202, a third delay transmission line TL203, a fourth delay transmission line TL204, a fifth delay transmission line TL205, a sixth delay transmission line TL206, a first delay capacitor C201, a second delay capacitor C202, a third delay capacitor C203, a fourth delay capacitor C204, a fifth delay capacitor C205 and a sixth delay capacitor C206. One end of the first delay transmission line TL201 is connected to the auxiliary path output end of the power divider 100, and the other end of the first delay transmission line TL201 is connected to the common connection end of the second delay capacitor C202 and the second delay transmission line TL202 respectively. The other end of the second delay transmission line TL202 is connected to one end of the first delay capacitor C201; the other end of the second delay capacitor C202 is connected to one end of the third delay transmission line TL203, and the other end of the third delay transmission line TL203 is connected to the common connection end of the third delay capacitor C203 and the fourth delay transmission line TL204. The other end of the fourth delay transmission line TL204 is connected to the common connection end of the fourth delay capacitor C204 and the fifth delay transmission line TL205, and the other end of the fifth delay transmission line TL205 is connected to one end of the fifth delay capacitor C205. The other end of the fifth delay capacitor C205 is connected to a signal output end and one end of the sixth delay transmission line TL206 respectively, and the other end of the sixth delay transmission line TL206 is connected to the sixth delay capacitor C206. The other end of the first delay capacitor C201, the other end of the third delay capacitor C203, the other end of the fourth delay capacitor C204 and the other end of the sixth delay capacitor C206 are grounded.

[0061] When the radio frequency input signal flows into the main branch and the auxiliary branch respectively after being divided by the non-equal power signal distribution, the phase difference between the networks is different due to the different network structures of the main branch and the auxiliary branch, and the signals in the main branch and the auxiliary branch to the input distributed output combination network 900 based on the band-pass T structure have a phase difference. Therefore, the delay network 200 is added before the auxiliary path input matching network 400 to compensate for the phase difference between the main branch and the auxiliary branch, so as to ensure that the main branch and the auxiliary branch have appropriate phase relationship.

[0062] Further, the delay network 200 is used to compensate the phase difference between the input terminals of the main path input matching network 300 and the auxiliary path input matching network 400, and the formula of the phase difference is P=P1+P2+P3-P4-P5, wherein P1, P2, P3, P4 and P5 are the phase changes at all the networks except the power divider 100, P1 is the phase difference of the main path input matching network 300, P2 is the phase difference of the main path intermediate stage network, P3 is the phase difference of the distributed output combining network 900 based on the band-pass T structure, P4 is the phase difference of the auxiliary path intermediate stage matching network 700, and P5 is the phase difference of the auxiliary path input matching network 400. When the network is a two-port network, the phase change at the corresponding network is the phase difference between the two ends of the two-port network, i.e. P1, P2 and P4 can be obtained by measuring the phase difference between the ports. When the network is a multi-port network, the phase difference is the phase difference between each first auxiliary branch and the corresponding port in the multi-port network, i.e. P3 is the phase difference between the drain of the main transistor Q810 and the drain of the first auxiliary transistor Q801, and P5 is the phase difference between the input terminal of the auxiliary path input matching network 400 and the gate of the first auxiliary path drive stage transistor Q501. Then, the phase difference between the input terminals of the main path input matching network 300 and the auxiliary path input matching network 400 is calculated, and the phase difference is set as the phase difference inside the delay network 200.

[0063] Further, referring to Figure 6 , the main path input matching network 300 comprises a first main path input transmission line TL301, a second main path input transmission line TL302, a third main path input transmission line TL303, a fourth main path input resistor R304, a fifth main path input transmission line TL305, a sixth main path input resistor R305, a first main path input capacitor C301, a second main path input capacitor C302, a third main path input capacitor C303 and a fourth main path input capacitor C304. One end of the first main path input transmission line TL301 is connected to the main path output terminal of the power divider, the other end of the first main path input transmission line is connected to one end of the first main path input capacitor C301, the other end of the first main path input capacitor C301 is connected to the common terminal of the second main path input capacitor C302 and the second main path input transmission line TL302, the other end of the second main path input capacitor C302 is grounded, and the other end of the second main path input transmission line TL302 is connected to one end of the third main path input transmission line TL303 and the fifth main path input transmission line TL305 respectively; the other end of the third main path input transmission line TL303 is connected to the common terminal of the fourth main path input resistor R304 and the third main path input capacitor C303, the other end of the fourth main path input resistor R304 is connected to the drive voltage V G，M，driveThe other end of the third main path input capacitor C303 is connected to the ground, and the other end of the fifth main path input transmission line TL305 is connected to the common terminal of the sixth main path input resistor R305 and the fourth main path input capacitor C304, and the sixth main path input resistor R305 and the main path input capacitor are connected in parallel to the gate of the main path drive stage transistor Q510. The structure of the main path input matching network 300 is used to realize the impedance transformation from the port output impedance of the main path output end of the power divider 100 to the source impedance of the connected transistor.

[0064] Please refer to Figure 8 , the auxiliary path input matching network 400 can be divided into impedance transformation part IMN A and traveling wave input matching network part DIMN A . The impedance transformation part IMN A includes: a first auxiliary path input capacitor C401, a second auxiliary path input capacitor C402, a first auxiliary path input transmission line TL401, and a traveling wave input matching network part DIMN AThe third auxiliary road input resistance R403, the third auxiliary road input capacitor C403, the second auxiliary road input transmission line TL402, the fourth auxiliary road input capacitor C404, the fourth auxiliary road input transmission line TL404, the fifth auxiliary road input resistance R405, the fifth auxiliary road input capacitor C405, the sixth auxiliary road input transmission line TL406, the sixth auxiliary road input capacitor C406, the seventh auxiliary road input transmission line TL407, the eighth auxiliary road input resistance R408, the seventh auxiliary road input capacitor C407, the ninth auxiliary road input transmission line TL409, the tenth auxiliary road input resistance R410 and the eighth auxiliary road input capacitor C408 are included. One end of the first auxiliary road input capacitor C401 is connected to the output end of the delay network, and the other end is connected to the common connection end of the second auxiliary road input capacitor C402 and the first auxiliary road input transmission line TL401. The other end of the second auxiliary road input capacitor C402 is grounded, and is used for impedance transformation. The other end of the first auxiliary road input transmission line TL401 is connected to the common connection end of the second auxiliary road input transmission line TL402, the third auxiliary road input resistance R403 and the third auxiliary road input capacitor C403 respectively. The third auxiliary road input resistance and the third auxiliary road input capacitor are connected in parallel to the first auxiliary road drive stage transistor Q501. The other end of the second auxiliary road input transmission line TL402 is connected to the common connection end of the fourth auxiliary road input capacitor C404 and the fourth auxiliary road input transmission line TL404. The other end of the fourth auxiliary road input transmission line TL404 is connected to the common connection end of the sixth auxiliary road input transmission line TL406, the fifth auxiliary road input resistance R405 and the fifth auxiliary road input capacitor C405. The fifth auxiliary road input resistance R405 and the fifth auxiliary road input capacitor C405 are connected in parallel to the second auxiliary road drive stage transistor Q502, and are used for outputting a matched traveling wave signal. The other end of the sixth auxiliary road input transmission line TL406 is connected to the common connection end of the sixth auxiliary road input capacitor C406 and the seventh auxiliary road input transmission line TL407. The other end of the seventh auxiliary road input transmission line is connected to the common connection end of the ninth auxiliary road input transmission line TL409, the eighth auxiliary road input resistance R408 and the seventh auxiliary road input capacitor C407 respectively. The eighth auxiliary road input resistance and the seventh auxiliary road input capacitor are connected in parallel to the third auxiliary road drive stage transistor Q503. The other end of the ninth auxiliary road input transmission line TL409 is connected to one end of the tenth auxiliary road input resistance R410. The other end of the tenth auxiliary road input resistance R410 is connected to a drive signal and the eighth auxiliary road input capacitor C408 respectively. The other end of the fourth auxiliary road input capacitor C404, the other end of the sixth auxiliary road input capacitor C406 and the other end of the eighth auxiliary road input capacitor C408 are grounded.

[0065] The main path input matching network 300 and the auxiliary path input matching network 400 are designed to match the port output impedances to the source impedances of the corresponding transistors, respectively. When the power divider 100 performs a non-equal power division with a ratio of 1:2 on the radio frequency input signal, the non-equal power division ratio corresponds to the ratio of the port output impedances of the main path and the auxiliary path of the non-equal Wilkinson power divider 100. For example, according to the designed non-equal Wilkinson power divider 100 performing a non-equal power division with a ratio of 1:2, the port output impedances of the main path and the auxiliary path are 70Ω and 35Ω, respectively. The main path input matching network 300 and the auxiliary path input matching network 400 are designed to match the port output impedances to the source impedances of the corresponding transistors, respectively, so as to realize impedance transformation from the output end of the main path of the power divider 100 to the source impedance of the connected transistor.

[0066] Please refer to Figure 1 The auxiliary path drive stage transistor module 500 includes a first auxiliary path drive stage transistor Q501, a second auxiliary path drive stage transistor Q502, and a third auxiliary path drive stage transistor Q503. The gate of the first auxiliary path drive stage transistor Q501, the gate of the second auxiliary path drive stage transistor Q502, and the gate of the third auxiliary path drive stage transistor Q503 are connected to the output end of the auxiliary path input matching network 400, respectively. The source of the first auxiliary path drive stage transistor Q501, the source of the second auxiliary path drive stage transistor Q502, and the source of the third auxiliary path drive stage transistor Q503 are grounded. The drain of the first auxiliary path drive stage transistor Q501, the drain of the second auxiliary path drive stage transistor Q502, and the drain of the third auxiliary path drive stage transistor Q503 are connected to the auxiliary path intermediate stage matching network 700, respectively.

[0067] Please refer to Figure 1 , Figure 5The main path intermediate stage matching network 600 includes a first intermediate transmission line TL601, a second intermediate transmission line TL602, a third intermediate transmission line TL603, a fourth intermediate transmission line TL604, a fifth intermediate transmission line TL605, a sixth intermediate resistance R606, a seventh intermediate resistance R607, a first intermediate capacitor C601, a second intermediate capacitor C602, a third intermediate capacitor C603, a fourth intermediate capacitor C604, a fifth intermediate capacitor C605, and a sixth intermediate capacitor C606. One end of the first intermediate capacitor C601 is connected to the drain of the main path drive stage transistor Q510, and the other end of the first intermediate capacitor is connected to the common connection end of the second intermediate transmission line TL602, the third intermediate transmission line TL603, and the second intermediate capacitor C602. The other end of the second intermediate transmission line TL602 is connected to one end of the first intermediate capacitor C601, and the other end of the first intermediate capacitor C601 is grounded. The other end of the second intermediate capacitor C602 is connected to the common connection end of the fourth intermediate transmission line TL604 and the fifth intermediate transmission line TL605. The sixth intermediate resistance R606 and the fifth intermediate capacitor C605 are connected in parallel and connected to the gate of the main transistor Q810. The other end of the fifth intermediate transmission line TL605 is connected to the common connection end of the sixth intermediate capacitor C606 and the seventh intermediate resistance R607. The other end of the fourth intermediate transmission line TL604 is connected to one end of the fourth intermediate capacitor C604, the other end of the third intermediate transmission line TL603 is connected to one end of the third intermediate capacitor C603, and the other end of the third intermediate capacitor and the other end of the fourth intermediate capacitor C604 are grounded.

[0068] The auxiliary path intermediate stage matching network 700 includes a first auxiliary path intermediate stage matching network 710, a second auxiliary path intermediate stage matching network 720, and a third auxiliary path intermediate stage matching network 730. The input end of the first auxiliary path intermediate stage matching network 710 is connected to the drain of the first auxiliary path drive stage transistor Q501. The input end of the second auxiliary path intermediate stage matching network 720 is connected to the drain of the second auxiliary path drive stage transistor Q502. The third auxiliary path intermediate stage matching network 730 is connected to the drain of the third auxiliary path drive stage transistor Q503. The first auxiliary path intermediate stage matching network 710, the second auxiliary path intermediate stage matching network 720, and the third auxiliary path intermediate stage matching network 730 are cascaded with each other, so that the three auxiliary paths share the gate bias and the drain bias.

[0069] Further, the circuit structure and size of the first auxiliary path intermediate stage matching network 710, the second auxiliary path intermediate stage matching network 720, the third auxiliary path intermediate stage matching network 730, and the main path intermediate stage matching network 600 are the same, for impedance transformation. The circuit structure is as shown in Figure 5 , and will not be described here.

[0070] The auxiliary transistor module 800 comprises a first auxiliary transistor Q801, a third auxiliary transistor Q802 and a third auxiliary transistor Q803, the gate of the first auxiliary transistor Q801, the gate of the third auxiliary transistor Q802 and the gate of the third auxiliary transistor Q803 are connected with the auxiliary middle stage matching network 700 respectively, the source of the first auxiliary transistor Q801, the source of the third auxiliary transistor Q802 and the source of the third auxiliary transistor Q803 are grounded, and the drain of the first auxiliary transistor Q801, the drain of the third auxiliary transistor Q802 and the drain of the third auxiliary transistor Q803 are connected with the distributed output combining network 900 based on the band-pass T structure respectively.

[0071] The main transistor Q810, the first auxiliary transistor Q801, the third auxiliary transistor Q802 and the third auxiliary transistor Q803 are transistors of the same size, and since the transistors used in the main branch and the auxiliary branch driving stage and the power stage are of the same size, the four middle stage matching networks used in the circuit of the present application all adopt the same circuit structure and size, thereby facilitating industrial design and drawing and reducing material loss in the production process.

[0072] In the present embodiment, the linear wideband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier is divided into a main branch and an auxiliary branch through non-equal power distribution, and the auxiliary branch is divided into three branches after impedance matching and input into the auxiliary branch driving stage transistor module 500 respectively, and then input into the first, second and third auxiliary branch middle stage matching network 730 after amplification. Among them, the first auxiliary branch middle stage matching network 710, the second auxiliary branch middle stage matching network 720 and the third auxiliary branch middle stage matching network 730 are cascaded with each other to form a NDPA-like structure. Through the cascaded structure, the NDPA-like structure can achieve better wideband effect compared with ordinary power amplifiers. On this basis, the DEPA structure based on the present application further divides into a main branch and an auxiliary branch, which can not only achieve the effect of wideband, but also enhance the backoff efficiency through impedance modulation. Further, the auxiliary branch in the present application is not less than 3, and the number of the auxiliary branch is not limited herein.

[0073] Further, please refer to Figure 4The distributed output combiner network 900 based on the band-pass T structure includes a first band-pass T structure unit 901, a second band-pass T structure unit 902, a third band-pass T structure unit 903, a first output capacitor C901, a second output capacitor Cout2, a third output capacitor C903, a fourth output capacitor C904, a first output resistor Rout, and a post matching network 904. One end of the first band-pass T structure unit 901 is connected with the drain of the main transistor Q810 and one end of the first output capacitor C901, and the other end of the first band-pass T structure unit is connected with the drain of the first auxiliary transistor Q801, the second output capacitor Cout2, and the common connection end of the second band-pass T structure unit 902. The other end of the second band-pass T structure unit 902 is connected with the drain of the third auxiliary transistor Q802, one end of the third output capacitor C903, and the common connection end of the third band-pass T structure unit 903. The other end of the third band-pass T structure unit 903 is connected with the drain of the third auxiliary transistor Q803, the fourth output capacitor C904, and the common connection end of the post matching network. The other end of the first output capacitor C901, the other end of the second output capacitor C902, the other end of the third output capacitor C903, and the other end of the fourth output capacitor C904 are grounded, and the other end of the post matching network 904 is connected with the radio frequency output end through the first output resistor Rout.

[0074] Specifically, in a further implementation of the preferred embodiment, the first band-pass T structure unit 901 includes a first transmission line TL1, a second transmission line TL2 and a third transmission line TL3, the second band-pass T structure unit 902 includes a fourth transmission line TL4, a fifth transmission line TL5 and a sixth transmission line TL6, and the third band-pass T structure unit 903 includes a seventh transmission line TL7 and an eighth transmission line TL8; the post matching network 904 includes a ninth transmission line TL9, a tenth transmission line TL10 and a DC blocking capacitor C1. The first band-pass T structure unit 901 applies a band-pass T structure unit circuit, in which the first transmission line TL1 is connected to the drain of the main transistor Q810 and one end of the first output capacitor Cout1, respectively; one end of the second transmission line TL2 is connected to one end of the first transmission line TL1 and one end of the third transmission line TL3, respectively, and the other end of the second transmission line is grounded; the other end of the third transmission line TL3 is connected to the fourth transmission line TL4, the drain of the first auxiliary transistor Q801 and the common terminal of the second output capacitor Cout2. The second band-pass T structure unit 902 has the same structure as the first band-pass T structure unit 901, in which the fourth transmission line TL4, the fifth transmission line TL5 and the sixth transmission line TL6 are connected in a band-pass T structure, and the other end of the fourth transmission line TL4 is connected to one end of the fifth transmission line TL5 and one end of the sixth transmission line TL6, respectively, the other end of the fifth transmission line TL5 is grounded, and the other end of the sixth transmission line TL6 is connected to one end of the seventh transmission line TL7, the third output capacitor Cout3 and the common terminal of the third auxiliary transistor Q802, respectively. In the third band-pass T structure unit 903, the other end of the seventh transmission line TL7 is connected to one end of the eighth transmission line TL8, and the other end of the eighth transmission line TL8 is connected to the drain of the third auxiliary transistor Q803, the fourth output capacitor Cout4 and the common terminal of the ninth transmission line TL9. The post matching network 904 is an L-shaped post matching network, in which the other end of the ninth transmission line TL9 is connected to one end of the DC blocking capacitor C1 and the tenth transmission line TL10, respectively, and the other end of the first output capacitor Cout1, the other end of the second output capacitor Cout2, the other end of the third output capacitor Cout3 and the other end of the fourth output capacitor Cout4 are grounded. In theory, the band-pass T structure unit circuit is a symmetrical network, but in actual design, the transistor capacitances absorbed by the T structure unit networks at different positions may not be consistent, so the T structure unit in the circuit is a non-symmetrical structure in actual application. This structure can better absorb the output parasitic capacitance of the transistor, achieve better matching, and thus significantly improve the matching characteristics of the entire combining network at the back-off point and the saturation point, resulting in better bandwidth and efficiency characteristics.

[0075] Please refer to Figures 2 to 4, Figure 2 The method shown in the prior art is to use a capacitively loaded transmission line to equivalently realize a 90° transmission line of an ideal traveling wave structure, one end of the transmission line is connected to a signal input end and a first output capacitor C901 respectively, and the other end is connected to a signal output end and a second output capacitor Cout2, and the calculation formula of the equivalent process is:

[0076]

[0077] Wherein, Z1a and θ1a are the characteristic impedance and electrical length of the capacitively loaded transmission line corresponding to the 90° transmission line of the ideal traveling wave structure, and Cout is the transistor parasitic capacitance to be absorbed by the unit circuit. The optimal impedance value Qopt (= ωCoutRoptM) of the transistor, i.e. the method of the conventional capacitively loaded transmission line, only has a reasonable solution when Qopt < 2. However, in the millimeter wave frequency band, due to the high bias voltage characteristics of the gallium nitride transistor, the value of Qopt is usually high, usually greater than 2. Therefore, the conventional method cannot be applied to realize the absorption of Cout in the millimeter wave frequency band.

[0078] On the basis of the prior art, the application applies a distributed output combining network based on a bandpass T structure Figure 3 The unit circuit of the bandpass T structure shown in the figure forms a distributed network, wherein Z1b, Z2b, Z3b and θ1a, θ2a, θ3a are the characteristic impedance and electrical length of the corresponding first transmission line, second transmission line and third transmission line TL3, and Cout is the transistor parasitic capacitance to be absorbed by the unit circuit. One end of the first transmission line TL1 is connected to a signal input end and a first output capacitor C901 respectively, and the other end is connected to the common connection end of the second transmission line TL2 and the third transmission line TL3, the other end of the second transmission line TL2 is grounded, the other end of the third transmission line TL3 is connected to a signal output end and a second output capacitor Cout2, and the first, second and third transmission lines TL3 are connected in a bandpass T structure. The equivalent process of the bandpass T structure is not unique, therefore, the unit circuit of the bandpass T structure forms a distributed network with more degrees of freedom, which can realize a better equivalent process in a wider frequency band range. And the unit circuit of the bandpass T structure can provide a drain bias for the power amplifier while absorbing Cout.

[0079] Figure 13 The gain variation of the distributed output combining network 900 based on the bandpass T structure, the internal current source plane of the main transistor Q810, the input network and the DEPA with the increase of the input power is shown in the figure, the gain of the distributed output combining network 900 based on the bandpass T structure is as G RAs shown, with the increase of input power, the gain of the distributed output combiner network based on the band-pass T structure 900 presents a gradually increasing trend after the auxiliary transistor is turned on, and the distributed output combiner network based on the band-pass T structure 900 has certain gain expansion characteristics, laying the foundation for the design of high linearity DEPA. Meanwhile, in the preferred embodiment, the distributed output combiner network based on the band-pass T structure 900 is used to realize a wideband traveling wave network and absorb the parasitic parameters of the output terminals of the main and auxiliary transistors. Because the sizes of the main transistor Q810, the first auxiliary transistor Q801, the third auxiliary transistor Q802 and the third auxiliary transistor Q803 are the same, the transistors have the same output parasitic parameters Cout, and the distributed output combiner network based on the band-pass T structure 900 is used to absorb the parasitic parameters of the transistors, so that the output impedance of the transistors is a pure real number, facilitating the design of the network for impedance matching.

[0080] In the application, the working state of DEPA at the saturation point is close to that of the conventional NDPA, and when the gate bias voltage of the auxiliary transistor is set to -2.2V and all the auxiliary transistors work in the class-C mode, the power amplifier will provide a higher backoff efficiency, which is the high backoff efficiency mode.

[0081] As shown in the drawings, Figure 11 The figure shows the large signal test result of the application in the high backoff efficiency enhancement mode. In the figure, Psat is the saturation output power; PAE@SAT is the power added efficiency at the saturation output power point (0 dB backoff point), that is, the output power of the power amplifier in the saturation state; PAE@6dB-OBO and PAE@7.5dB-OBO are the power added efficiencies at the saturation output power backoff points of 6 dB and 7.5 dB, respectively. As shown in the large signal test result, in the high backoff efficiency mode, the power amplifier can provide a saturation output power of 36.4-37.6 dBm between 24 GHz and 29 GHz, and the PAEs at the backoff points of 7.5 dB, 6 dB and 0 dB are 21.5-30.2%, 24.5-31.1% and 32.1-38.7%, respectively.

[0082] In another preferred embodiment of the application, when the biasing condition of the auxiliary transistor is adjusted from class-C to class-AB, that is, the gate bias voltage of the auxiliary transistor is set to -1.8V, the power amplifier will work in the non-uniform traveling wave power amplifier (NDPA) mode, which can provide a wider bandwidth, and thus is called the bandwidth enhancement mode, thereby improving the compatibility of the linear wideband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier of the application to different application environments. At this time, the linear wideband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier works in the bandwidth enhancement mode. Figure 12The large signal test results of the application in the bandwidth enhancement mode are shown. In the bandwidth enhancement mode, the entire power amplifier can maintain saturated output power and efficiency of 35.8-37.1 dBm and 31.6-38.9% respectively within 24-30.5 GHz.

[0083] In some preferred embodiments, the application provides a linear wideband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier chip, which comprises the above-mentioned linear wideband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier modules and electrical elements, and the chip is manufactured by using a commercial 150 nm GaN-on-SiC HEMT process.

[0084] In some embodiments, the application also provides a radio frequency module comprising the above-mentioned linear wideband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier. Details are described in the embodiment of the linear wideband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier, which will not be repeated here.

[0085] In some embodiments, the application also provides a wireless communication module or a wireless communication device comprising the above-mentioned linear wideband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier. Details are described in the embodiment of the linear wideband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier, which will not be repeated here.

[0086] In summary, the linear wideband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier provided by the application has the following beneficial effects:

[0087] The distributed output combining network based on the bandpass T structure must have certain gain expansion characteristics, which lays the foundation for the design of high-linearity DEPA;

[0088] The gain compression characteristics of the input network can be adjusted by the power distribution ratio of the power divider. This degree of freedom is used to build an expanded DEPA gain characteristic and to compensate for the gain compression of the main transistor in the actual design, thereby improving the linearity of the entire DEPA;

[0089] In the implementation of the distributed output combining network, the distributed unit circuit based on the bandpass T structure is used to replace the traditional capacitively loaded transmission line network, which significantly improves the matching bandwidth of the distributed output combining network at the optimal impedance value Qopt of the large transistor;

[0090] In addition to supporting the high back-off efficiency mode, the amplifier can also be re-modulated into a non-uniform traveling wave amplifier mode by adjusting the auxiliary amplifier gate bias voltage, which supports a more optimal bandwidth, thereby improving the compatibility of the power amplifier for different applications;

[0091] The distributed unit circuit based on the band-pass T structure is used to replace the traditional capacitor-loaded transmission line network, and the matching bandwidth of the distributed output combining network based on the band-pass T structure at the optimal impedance value Qopt of the transistor can be significantly improved.

[0092] It should be understood that the application is not limited to the above examples, and those skilled in the art can make improvements or changes according to the above description, and all these improvements and changes shall belong to the protection scope of the appended claims of the application.

Claims

1. A linear wideband gallium nitride millimeter wave integrated distributed high efficiency power amplifier characterized by, The application relates to a power divider, a delay network, a main path input matching network, an auxiliary path input matching network, a main path drive stage transistor, an auxiliary path drive stage transistor module, a main path intermediate stage matching network, an auxiliary path intermediate stage matching network, a main transistor, an auxiliary transistor module and a distributed output combining network based on a band-pass T structure. An output end of the power divider is connected with an input end of the main path input matching network and an input end of the delay network, and the power divider is used for non-equal power distribution of an accessed radio frequency input signal. An output end of the delay network is connected with an input end of the auxiliary path input matching network, and the delay network is used for adjusting a phase difference between a signal at the input end of the auxiliary path input matching network and a main path signal. An output end of the main path input matching network is connected with a gate of the main path drive stage transistor, and the main path input matching network is used for matching a port output impedance of the main path input matching network to a source impedance of the main path drive stage transistor. An input end of the auxiliary path input matching network is connected with an output end of the delay network, and an output end of the auxiliary path input matching network is connected with the auxiliary path drive stage transistor module, and the auxiliary path input matching network is used for matching a port output impedance of the auxiliary path input matching network to a source impedance of the auxiliary path drive stage transistor module. An input end of the main path intermediate stage matching network is connected with a drain of the main path drive stage transistor, and an output end of the main path intermediate stage matching network is connected with a gate of the main transistor, and the main path intermediate stage matching network is used for impedance conversion of a radio frequency input signal. An input end of the auxiliary path intermediate stage matching network is connected with the auxiliary path drive stage transistor module, and an output end of the auxiliary path intermediate stage matching network is connected with the auxiliary transistor module, and the auxiliary path intermediate stage matching network is used for impedance conversion of a radio frequency input signal. An input end of the distributed output combining network based on the band-pass T structure is connected with a drain of the main transistor and an output end of the auxiliary transistor module, and the distributed output combining network based on the band-pass T structure is used for realizing a wideband traveling wave network and absorbing parasitic parameters of the main transistor and the auxiliary transistor module. The distributed output combining network based on the band-pass T structure comprises a first band-pass T structure unit, a second band-pass T structure unit, a third band-pass T structure unit, a first output capacitor, a second output capacitor, a third output capacitor, a fourth output capacitor, a first output resistor and a post matching network. One end of the first band-pass T structure unit is connected with a drain of the main transistor and one end of the first output capacitor, and the other end of the first band-pass T structure unit is connected with a first output end of the auxiliary transistor module, a first end of the second output capacitor and a common connection end of the second band-pass T structure unit. The other end of the second band-pass T structure unit is connected with a second output end of the auxiliary transistor module, one end of the third output capacitor and a common connection end of the third band-pass T structure unit. The other end of the third band-pass T structure unit is connected with a third output end of the auxiliary transistor module, the fourth output capacitor and a common connection end of the post matching network. ​ Another end of the first output capacitor, another end of the second output capacitor, another end of the third output capacitor and another end of the fourth output capacitor are grounded. Another end of the post matching network is connected with the radio frequency output end through the first output resistor.

2. The linear wideband gallium nitride millimeter wave integrated distributed high efficiency power amplifier of claim 1, wherein, In the distributed output combining network based on the band-pass T structure, the first band-pass T structure unit comprises a first transmission line, a second transmission line and a third transmission line; the second band-pass T structure unit comprises a fourth transmission line, a fifth transmission line and a sixth transmission line; the third band-pass T structure unit comprises a seventh transmission line and an eighth transmission line; and the post matching network comprises a ninth transmission line, a tenth transmission line and a direct current blocking capacitor. One end of the first transmission line is connected with the drain of the main transistor and one end of the first output capacitor respectively; one end of the second transmission line is connected with the other end of the first transmission line and one end of the third transmission line respectively, and the other end of the second transmission line is grounded; the other end of the third transmission line is connected with the fourth transmission line, the first output end of the auxiliary transistor module and the common connection end of the second output capacitor. The other end of the fourth transmission line is connected with one end of the fifth transmission line and one end of the sixth transmission line respectively, the other end of the fifth transmission line is grounded, and the other end of the sixth transmission line is connected with one end of the seventh transmission line and the second output end of the auxiliary transistor module respectively. The other end of the seventh transmission line is connected with one end of the eighth transmission line, and the other end of the eighth transmission line is connected with the common connection end of the third output end of the auxiliary transistor module, the fourth output capacitor and one end of the ninth transmission line. The other end of the ninth transmission line is connected with one end of the direct current blocking capacitor and the tenth transmission line respectively, and the other end of the first output capacitor, the other end of the second output capacitor, the other end of the third output capacitor and the other end of the fourth output capacitor are grounded.

3. The linear wideband gallium nitride millimeter wave integrated distributed high efficiency power amplifier of claim 1, wherein, The auxiliary road drive stage transistor module comprises a first auxiliary road drive stage transistor, a second auxiliary road drive stage transistor and a third auxiliary road drive stage transistor. The gate of the first auxiliary road drive stage transistor, the gate of the second auxiliary road drive stage transistor and the gate of the third auxiliary road drive stage transistor are connected with the output end of the auxiliary road input matching network respectively, the source of the first auxiliary road drive stage transistor, the second auxiliary road drive stage transistor and the third auxiliary road drive stage transistor is grounded, and the drain of the first auxiliary road drive stage transistor, the second auxiliary road drive stage transistor and the third auxiliary road drive stage transistor is connected with the auxiliary road intermediate stage matching network respectively.

4. The linear wideband gallium nitride millimeter-wave integrated distributed high-efficiency power amplifier of claim 1, wherein, The auxiliary transistor module comprises a first auxiliary transistor, a second auxiliary transistor and a third auxiliary transistor; the gate of the first auxiliary transistor, the gate of the second auxiliary transistor and the gate of the third auxiliary transistor are connected with the auxiliary road intermediate stage matching network respectively, the source of the first auxiliary transistor, the source of the second auxiliary transistor and the source of the third auxiliary transistor are grounded, and the drain of the first auxiliary transistor, the drain of the second auxiliary transistor and the drain of the third auxiliary transistor are connected with the distributed output combining network based on the band-pass T structure respectively.

5. The linear wideband gallium nitride millimeter wave integrated distributed high efficiency power amplifier of claim 3, wherein, The auxiliary road intermediate stage matching network includes a first auxiliary road intermediate stage matching network, a second auxiliary road intermediate stage matching network and a third auxiliary road intermediate stage matching network; the input end of the first auxiliary road intermediate stage matching network is connected with the drain of the first auxiliary road driving stage transistor, the input end of the second auxiliary road intermediate stage matching network is connected with the drain of the second auxiliary road driving stage transistor, and the third auxiliary road intermediate stage matching network is connected with the drain of the third auxiliary road driving stage transistor; the first auxiliary road intermediate stage matching network, the second auxiliary road intermediate stage matching network and the third auxiliary road intermediate stage matching network are cascaded with each other, and are used for absorbing the parasitic parameters in the first auxiliary road driving stage transistor, the second auxiliary road driving stage transistor and the third auxiliary road driving stage transistor respectively.

6. The linear wideband gallium nitride millimeter-wave integrated distributed high-efficiency power amplifier of claim 5, wherein, The circuit structure and size of the main road intermediate stage matching network and the first auxiliary road intermediate stage matching network, the second auxiliary road intermediate stage matching network and the third auxiliary road intermediate stage matching network are the same; the main road intermediate stage matching network includes a first intermediate transmission line, a second intermediate transmission line, a third intermediate transmission line, a fourth intermediate transmission line, a fifth intermediate transmission line, a sixth intermediate resistance, a seventh intermediate resistance, a first intermediate capacitor, a second intermediate capacitor, a third intermediate capacitor, a fourth intermediate capacitor, a fifth intermediate capacitor and a sixth intermediate capacitor; wherein, One end of the first intermediate transmission line is connected with the drain of the main road driving stage transistor, the other end of the first intermediate transmission line is connected with one end of the second intermediate transmission line, the third intermediate transmission line and the common connection end of the second intermediate capacitor respectively, the other end of the second intermediate transmission line is connected with one end of the first intermediate capacitor, and the other end of the first intermediate capacitor is grounded; the other end of the second intermediate capacitor is connected with the common connection end of the fourth intermediate transmission line and the fifth intermediate transmission line, the sixth intermediate resistance and the fifth intermediate capacitor are connected in parallel and connected with the gate of the main transistor; the other end of the fifth intermediate transmission line is connected with the common connection end of the sixth intermediate capacitor and the seventh intermediate resistance respectively, the other end of the fourth intermediate transmission line is connected with one end of the fourth intermediate capacitor, the other end of the third intermediate transmission line is connected with one end of the third intermediate capacitor, and the other end of the third intermediate capacitor and the other end of the fourth intermediate capacitor are grounded.

7. The linear wideband gallium nitride millimeter-wave integrated distributed high-efficiency power amplifier of claim 1, wherein, The main road input matching network includes a first main road input transmission line, a second main road input transmission line, a third main road input transmission line, a fourth main road input resistance, a fifth main road input transmission line, a sixth main road input resistance, a first main road input capacitor, a second main road input capacitor, a third main road input capacitor and a fourth main road input capacitor; wherein, One end of the first main input transmission line is connected to the main output end of the power divider, the other end of the first main input transmission line is connected to one end of the first main input capacitor, the other end of the first main input capacitor is connected to the common connection end of the second main input capacitor and the second main input transmission line, the other end of the second main input capacitor is grounded, and the other end of the second main input transmission line is respectively connected to one end of the third main input transmission line and one end of the fifth main input transmission line; the other end of the third main input transmission line is connected to the common connection end of the fourth main input resistor and the third main input capacitor, the other end of the fourth main input resistor is connected to the input end of the driving voltage, the other end of the third main input capacitor is grounded, and the other end of the fifth main input transmission line is connected to the common connection end of the sixth main input resistor and one end of the fourth main input capacitor.

8. The linear wideband gallium nitride millimeter-wave integrated distributed high-efficiency power amplifier of claim 1, wherein, The delay network comprises a first delay transmission line, a second delay transmission line, a third delay transmission line, a fourth delay transmission line, a fifth delay transmission line, a sixth delay transmission line, a first delay capacitor, a second delay capacitor, a third delay capacitor, a fourth delay capacitor, a fifth delay capacitor and a sixth delay capacitor; wherein, One end of the first delay transmission line is connected to the auxiliary output end of the power divider, and the other end of the first delay transmission line is respectively connected to the common connection end of the second delay capacitor and the second delay transmission line; The other end of the second delay transmission line is connected to one end of the first delay capacitor, the other end of the second delay capacitor is connected to one end of the third delay transmission line, the other end of the third delay transmission line is connected to the common connection end of the third delay capacitor and the fourth delay transmission line, the other end of the fourth delay transmission line is connected to the common connection end of the fourth delay capacitor and the fifth delay transmission line, the other end of the fifth delay transmission line is connected to one end of the fifth delay capacitor, the other end of the fifth delay capacitor is respectively connected to the input end of the auxiliary input matching network and one end of the sixth delay transmission line, the other end of the sixth delay transmission line is connected to the sixth delay capacitor, and the other end of the first delay capacitor, the other end of the third delay capacitor, the other end of the fourth delay capacitor and the other end of the sixth delay capacitor are grounded.

9. The linear wideband gallium nitride millimeter-wave integrated distributed high-efficiency power amplifier of claim 3, wherein, The auxiliary input matching network comprises a first auxiliary input capacitor, a second auxiliary input capacitor, a first auxiliary input transmission line, a third auxiliary input resistor, a third auxiliary input capacitor, a second auxiliary input transmission line, a fourth auxiliary input capacitor, a fourth auxiliary input transmission line, a fifth auxiliary input resistor, a fifth auxiliary input capacitor, a sixth auxiliary input transmission line, a sixth auxiliary input capacitor, a seventh auxiliary input transmission line, an eighth auxiliary input resistor, a seventh auxiliary input capacitor, a ninth auxiliary input transmission line, a tenth auxiliary input resistor and an eighth auxiliary input capacitor; wherein, One end of the first auxiliary road input capacitor is connected to the output end of the delay network, the other end of the first auxiliary road input capacitor is connected to the common connection end of the second auxiliary road input capacitor and the first auxiliary road input transmission line, the other end of the second auxiliary road input capacitor is grounded; the other end of the first auxiliary road input transmission line is connected to the common connection end of the second auxiliary road input transmission line, the third auxiliary road input resistor and the third auxiliary road input capacitor respectively; the third auxiliary road input resistor and the third auxiliary road input capacitor are connected in parallel to the first auxiliary road drive stage transistor; the other end of the second auxiliary road input transmission line is connected to the common connection end of the fourth auxiliary road input capacitor, the fourth auxiliary road input transmission line, the other end of the fourth auxiliary road input transmission line is connected to the common connection end of the sixth auxiliary road input transmission line, the fifth auxiliary road input resistor and the fifth auxiliary road input capacitor; the fifth auxiliary road input resistor and the fifth auxiliary road input capacitor are connected in parallel to the second auxiliary road drive stage transistor for outputting the matched traveling wave signal; the other end of the sixth auxiliary road input transmission line is connected to the common connection end of the sixth auxiliary road input capacitor, the seventh auxiliary road input transmission line, the other end of the seventh auxiliary road input transmission line is connected to the common connection end of the ninth auxiliary road input transmission line, the eighth auxiliary road input resistor and the seventh auxiliary road input capacitor respectively; the eighth auxiliary road input resistor and the seventh auxiliary road input capacitor are connected in parallel to the third auxiliary road drive stage transistor; the other end of the ninth auxiliary road input transmission line is connected to one end of the tenth auxiliary road input resistor, the other end of the tenth auxiliary road input resistor is connected to the driving signal and the eighth auxiliary road input capacitor respectively, the other end of the fourth auxiliary road input capacitor, the other end of the sixth auxiliary road input capacitor and the other end of the eighth auxiliary road input capacitor are grounded.

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