A frequency and phase discriminator, phase-locked loop and chip

Abstract

The application discloses a frequency discriminator and phase detector, a phase-locked loop and a chip. The frequency discriminator and phase detector comprises N sub-modules, and each sub-module comprises a first flip-flop, a second flip-flop, a third flip-flop, an AND gate, a first switch unit and a first inverter. In the N sub-modules, the control end of the first switch unit of the first sub-module is connected with a first reset signal, the first end is connected with a first power supply signal, and the second end is connected with the output end of the AND gate in the first sub-module; the control end of the first switch unit in the bth sub-module is connected with a second reset signal, the first end is connected with the output end of the AND gate in the bth sub-module, and the second end is connected with a second power supply signal; the input end of the first inverter in the ith sub-module is connected with the output end of the AND gate in the ith sub-module, and the output end of the first inverter in the ith sub-module is connected with the set end of the second flip-flop in the (i+1)th sub-module. The application can improve the phase discrimination range of the frequency discriminator and phase detector.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, and particularly relates to a phase frequency detector, a phase-locked loop and a chip. BACKGROUND

[0002] The phase-locked loop (PLL) is widely used in clock generation, signal recovery, frequency synthesis and other occasions, and is an indispensable part in high-speed integrated circuits.

[0003] The PLL mainly consists of a phase frequency detector (PFD), a charge pump (CP), a loop filter (LPF), a voltage controlled oscillator (VCO) and a divider (DIV).

[0004] The PFD is used for detecting the frequency and phase of the input reference signal and the feedback signal, and generating a switch control signal of the CP current of the next stage. Under the action of the control signal, the CP charges and discharges the LPF, so that the tuning voltage of the VCO changes accordingly, and in turn the resonant frequency of the VCO changes. The VCO oscillation output signal is divided by the DIV and participates in the phase detection, thereby forming a closed-loop feedback system to realize the phase-locked frequency multiplication function.

[0005] However, the PFD in the prior art has the problem of small phase detection range. SUMMARY

[0006] The present application provides a phase frequency detector, a phase-locked loop and a chip, which can improve the phase detection range of the PFD.

[0007] In a first aspect, the present application provides a frequency and phase discriminator, comprising: N sub-modules, N being an integer greater than or equal to 2; the sub-module comprising a first flip-flop, a second flip-flop, a third flip-flop, an AND gate, a first switch unit and a first inverter; the first flip-flop is used to receive a reference clock signal and output a first trigger signal; the third flip-flop is used to receive a feedback clock signal and output a second trigger signal; the AND gate is used to receive the first trigger signal and the second trigger signal, and generate a first control signal according to the first trigger signal and the second trigger signal, and input the first control signal to the trigger input end of the third flip-flop; the second flip-flop is used to receive the first control signal, and output a second control signal to the reset end of the first flip-flop and the reset end of the second flip-flop; in the N sub-modules, the control end of the first switch unit of the first sub-module is connected to a first reset signal, the first end is connected to a first power supply signal, and the second end is connected to the output end of the AND gate in the first sub-module, and is used to conduct when the first reset signal is a valid level signal; the control end of the first switch unit in the bth sub-module is connected to a second reset signal, the first end is connected to the output end of the AND gate in the bth sub-module, and the second end is connected to a second power supply signal, and is used to conduct when the second reset signal is a valid level signal; b is an integer greater than 1 and less than or equal to N, the set end of the second flip-flop in the first sub-module is connected to the output end of the first inverter in the Nth sub-module, and the input end of the first inverter in the Nth sub-module is connected to the output end of the AND gate in the Nth sub-module; the input end of the first inverter in the ith sub-module is connected to the output end of the AND gate in the ith sub-module, and the output end of the first inverter in the ith sub-module is connected to the set end of the second flip-flop in the ith+1 sub-module; wherein, i is an integer greater than or equal to 1 and less than or equal to N-1.

[0008] Optionally, the sub-module further comprises a first delay control module, the input end of the first delay control module is connected to the output end of the AND gate, and the output end of the first delay control module is connected to the trigger input end of the second flip-flop, which is used to delay the first control signal and control the delay time of the first control signal.

[0009] Optionally, the sub-module further comprises a second inverter and a second delay control module; the second inverter is used to invert the first trigger signal and output a charging current control signal; the second delay control module is used to delay the second trigger signal and output a discharging current control signal.

[0010] Optionally, the sub-module further comprises a charging current control signal output end and a discharging current control signal output end, the charging current control signal output end is configured to output a charging current control signal, and the discharging current control signal output end is configured to output a discharging current control signal; the phase-frequency detector further comprises a charge pump, the charge pump comprises N first branches and N second branches connected to an output node from the N first branches, and the first branch is connected to the charging current control signal output end one by one, and the second branch is connected to the discharging current control signal output end one by one; the first branch is configured to provide a charging current to the output node, and the second branch is configured to provide a discharging current to the output node.

[0011] Optionally, the first branch comprises a first switch tube and a first current source, a gate of the first switch tube is connected to the corresponding charging current control signal, a first pole of the first switch tube is connected to a second power supply signal, a second pole of the first switch tube is connected to a first end of the first current source, a second end of the first current source is connected to the output node, and the first switch tube is configured to selectively conduct according to the charging current control signal; when the first switch is turned on, the first branch is configured to provide a charging current to the output node; and / or, the second branch comprises a second switch tube and a second current source, a gate of the second switch tube is connected to the corresponding discharging current control signal, a first pole of the second switch tube is connected to the first power supply signal, a second pole of the second switch tube is connected to a first end of the second current source, a second end of the second current source is connected to the output node, and the second switch tube is configured to selectively conduct according to the discharging current control signal; when the second switch is turned on, the second branch is configured to provide a discharging current to the output node.

[0012] Optionally, the charge pump further comprises a first capacitor, a first end of the first capacitor is connected to the output node, and a second end of the first capacitor is connected to the first power supply signal.

[0013] Optionally, the feedback clock signal leads or lags the reference clock signal.

[0014] In a second aspect, the present application provides a phase-locked loop, comprising the phase-frequency detector provided by any of the embodiments of the present application, the phase-locked loop further comprising a loop filter, a voltage-controlled oscillator and a frequency divider; an input end of the loop filter is connected to an output end of the phase-frequency detector, and an output end of the loop filter is connected to an input end of the voltage-controlled oscillator; the voltage-controlled oscillator is configured to output a first signal; the loop filter is configured to generate a second signal according to a current signal generated by the phase-frequency detector, and adjust the frequency of the first signal output by the voltage-controlled oscillator through the second signal; an input end of the frequency divider is connected to an output end of the voltage-controlled oscillator, and the frequency divider is configured to divide the first signal output by the voltage-controlled oscillator to generate a feedback clock signal.

[0015] In a third aspect, the embodiment of the present application provides a chip, which comprises the phase-locked loop provided by the embodiment of the present application, and further comprises a control module in communication connection with the phase-locked loop, configured to output an encoded signal, and the encoded signal is used to control the delay time length of the internal loop of the frequency discriminator and phase detector in the phase-locked loop.

[0016] The frequency discriminator and phase detector provided by the embodiment of the present application comprises N sub-modules, the sub-module comprises a first flip-flop, a second flip-flop, a third flip-flop, an AND gate, a first switch unit and a first inverter, the control end of the first switch unit of the first sub-module is connected with a first reset signal, the first end is connected with a first power supply signal, and the second end is connected with the output end of the AND gate in the first sub-module; the control end of the first switch unit in the i-th sub-module is connected with a second reset signal, the first end is connected with the output end of the AND gate in the i-th sub-module, and the second end is connected with a second power supply signal; the setting end of the third flip-flop in the first sub-module is connected with the output end of the first inverter in the Nth sub-module, the input end of the first inverter in the Nth sub-module is connected with the output end of the AND gate in the Nth sub-module; the input end of the first inverter in the i-th sub-module is connected with the output end of the AND gate in the i-th sub-module, and the output end of the first inverter in the i-th sub-module is connected with the setting end of the third flip-flop in the i+1th sub-module, so that the phase discrimination range can be improved, and the clock frequency of the input reference clock signal can be improved. That is, the working frequency of the PFD of the embodiment of the present application is high and the phase discrimination range is large.

[0017] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0019] Figure 1 is a structure diagram of a phase-locked loop provided by the related art;

[0020] Figure 2 is a structure diagram of a frequency discriminator and phase detector provided by the embodiment of the present application;

[0021] Figure 3 is a structure diagram of another frequency discriminator and phase detector provided by the embodiment of the present application;

[0022] Figure 4is a working timing diagram of a PFD provided by an embodiment of the present application;

[0023] Figure 5 is a working timing diagram of a PFD provided by an embodiment of the present application;

[0024] Figure 6 is a structural schematic diagram of a frequency discriminator provided by an embodiment of the present application;

[0025] Figure 7 is a structural schematic diagram of a first delay control module provided by an embodiment of the present application;

[0026] Figure 8 is a structural schematic diagram of a frequency discriminator provided by an embodiment of the present application;

[0027] Figure 9 is a structural schematic diagram of a phase-locked loop provided by an embodiment of the present application;

[0028] Figure 10 is a structural schematic diagram of a chip provided by an embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to make the personnel in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the scope of protection of the present application.

[0030] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion.

[0031] As mentioned in the background art, the existing PFD has the problem of small phase discrimination range, and the inventors have found through careful research that the cause of this technical problem is that:

[0032] Figure 1 is a structural schematic diagram of a phase-locked loop provided by the related art. As Figure 1As shown, the PLL comprises a frequency and phase detector 110, a charge pump 120, a filter 130, a voltage controlled oscillator 140 and a frequency divider 150. The PLL is a negative feedback system. The PFD compares the feedback clock signal outputted by the frequency divider 150 with the reference clock signal REF1 to obtain a phase difference value signal. The phase difference value signal is processed by the charge pump 120 and the filter 130 and then used to control the first signal OUT1 outputted by the voltage controlled oscillator 140. When the phase and frequency of the feedback clock signal and the reference clock signal REF1 are the same, the PLL loop is locked, and the clock frequency of the first signal OUT1 outputted by the voltage controlled oscillator 140 is locked at N times of the clock frequency of the reference clock signal REF1.

[0033] When the frequency division ratio n of the frequency divider 150 is higher, the clock frequency of the first signal outputted by the PLL is higher. However, the noise introduced by the reference clock signal REF1, the frequency and phase detector 110, the charge pump 120 and the frequency divider 150 is proportional to the frequency division ratio n. Therefore, in order to realize a wideband and low-jitter first signal output, the clock frequency of the reference clock signal should be increased and the frequency division ratio n of the frequency divider 150 should be decreased.

[0034] Suppose the time difference corresponding to the phase difference between the reference clock signal REF1 and the feedback clock signal FB1 is ΔT, the fixed delay of the internal loop of the PFD is T D , and the clock period of the reference clock signal is T CLK , if

[0035] ΔT+T D <T CLK (1)

[0036] the PFD is considered to be able to normally detect phase. Therefore, when the clock frequency Fclk of the reference clock signal of the PFD is too high, the clock period T CLK of the reference clock signal is decreased, the phase detection range ΔT of the PFD is compressed, and the PLL can not be locked. And according to formula (1), when the clock period T CLK of the reference clock signal is unchanged, the phase detection range of the frequency and phase detector 11 is limited by the internal loop delay of the PFD. In order to realize a wideband and low-jitter PLL, a PFD with high operating frequency and large phase detection range is needed.

[0037] In order to improve the phase detection range of the PFD, the present application proposes a new PFD structure. Figure 2 is a structural schematic diagram of a frequency and phase detector provided by an embodiment of the present application. Figure 3 is a structural schematic diagram of another frequency and phase detector provided by an embodiment of the present application. In combination with Figure 2 and Figure 3The frequency phase detector comprises N sub-modules 1, N being an integer greater than or equal to 2; the sub-module 1 comprises a first flip-flop T1, a second flip-flop T2, a third flip-flop T3, an AND gate U1, a first switch unit 10 and a first inverter U2. Figure 3 The case where N equals 2 is schematically shown.

[0038] The first flip-flop T1 is configured to receive a reference clock signal CLK_REF and output a first trigger signal.

[0039] The third flip-flop T3 is configured to receive a feedback clock signal CLK_IN and output a second trigger signal.

[0040] The AND gate U1 is configured to receive the first trigger signal and the second trigger signal and generate a first control signal Ctr1 input to a trigger input end CK of the second flip-flop T2 according to the first trigger signal and the second trigger signal.

[0041] The second flip-flop T2 is configured to receive the first control signal Ctr1 and output a second control signal Ctr2 to a reset end RB of the first flip-flop T1 and a reset end RB of the third flip-flop T3.

[0042] In the N sub-modules 1, the control end of the first switch unit 10 of the first sub-module is connected to a first reset signal RST, the first end is connected to a first power supply signal VSS, and the second end is connected to the output end of the AND gate U1 in the first sub-module, for conducting when the first reset signal RST is a valid level signal.

[0043] The control end of the first switch unit 10 in the bth sub-module is connected to a second reset signal RSTN, the first end is connected to the output end of the AND gate U1 in the bth sub-module 12, and the second end is connected to a second power supply signal VDD, for conducting when the second reset signal RSTN is a valid level signal; wherein b is an integer greater than 1 and less than or equal to N;

[0044] The set end SB of the second flip-flop T2 in the first sub-module is connected to the output end of the first inverter U2 in the Nth sub-module, and the input end of the first inverter U2 in the Nth sub-module is connected to the output end of the AND gate U1 in the Nth sub-module.

[0045] The input end of the first inverter U2 in the ith sub-module is connected to the output end of the AND gate U1 in the ith sub-module, and the output end of the first inverter U2 in the ith sub-module is connected to the set end SB of the second flip-flop T2 in the ith+1 sub-module; wherein i is an integer greater than or equal to 1 and less than or equal to N-1.

[0046] Specifically, the first power signal VSS can be a low-level signal, and the second power signal VDD can be a high-level signal. The feedback clock signal CLK_IN leads or lags the reference clock signal CLK_REF.

[0047] The first trigger T1, the second trigger T2, and the third trigger T3 can all be rising edge triggered D flip-flops. When the set end SB of the first trigger T1 and the third trigger T3 is connected to the low-level signal, the first output end Q of the first trigger T1 and the third trigger T3 is set to 1, that is, the set end SB of the first trigger T1 and the third trigger T3 is low-level effective. In the embodiment of the present application, the set end SB of the first trigger T1 and the third trigger T3 is connected to the second power signal VDD, so the set end SB of the first trigger T1 and the third trigger T3 is always ineffective.

[0048] Optionally, the data input end D of the first trigger T1 and the third trigger T3 is connected to the second power signal VDD. The data input end D of the second trigger T2 is connected to the first power signal VSS. The second output end QB of the first trigger T1, the second trigger T2, and the third trigger T3 is suspended.

[0049] Optionally, the first switch unit 10 can include a switching device. By controlling the conduction and turn-off of the switching device, the first power signal VSS or the second power signal VDD is output. The switching device can be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), can also be an Insulated Gate Bipolar Transistor (IGBT), and can also be a Gallium Nitride (GaN) transistor.

[0050] Figure 4 is a working timing diagram of a PFD provided by an embodiment of the present application. The working timing diagram can be applicable to Figure 3 the PFD shown in FIG. 8. In combination with Figure 3 and Figure 4 , the working process of the PFD is as follows:

[0051] At the first time t1, the first reset signal RST flips to 1 and the second reset signal RSTN flips to 0, at this time the trigger input end CK and the set end SB of the second flip-flop T2 in the first sub-module 11 are set to 0, the first output end Q is set to 1, and it is ensured that the second flip-flop T2 in the first sub-module 11 can generate a rising edge when receiving the high-level signal output by the AND gate U1 in the first sub-module instead of being always high. The trigger input end CK and the set end SB of the second flip-flop T2 in the second sub-module 12 are set to 1, the reset end RB is set to 0, and the first output end Q is set to 0. When the second reset signal RSTN returns to 1, the whole PFD ends the reset state and enters the normal working mode. At this time, the first output end Q of the second flip-flop T2 in the second sub-module 12 is always 0, that is, the first node EN<1> is always 0, so that the first flip-flop T1 and the third flip-flop T3 in the second sub-module 12 are in the reset state and continuously output 0, and the second sub-module 12 does not work. Wherein 1 represents high level and 0 represents low level.

[0052] At the second time t2, the rising edge of the reference clock signal CLK_REF comes, and the first flip-flop T1 in the first sub-module 11 outputs a high level to the second node DN<0>.

[0053] At the third time t3, the rising edge of the feedback clock signal CLK_IN comes, the third flip-flop T3 in the first sub-module 11 outputs a high level to the third node UP<0>, at the same time, the AND gate U1 before the trigger input end CK of the second flip-flop T2 in the first sub-module 11 outputs a high level, so that the second flip-flop T2 in the first sub-module 11 receives a rising edge, the first output end Q outputs a low level 0 to the fourth node EN<0>, and the first sub-module 11 stops working, so that the first output end Q of the first flip-flop T1 and the third flip-flop T3 in the first sub-module 11 is reset to 0,

[0054] Wherein the first delay time from "the rising edge of the feedback clock signal CLK_IN comes" to "the first output end Q of the first flip-flop T1 and the third flip-flop T3 in the first sub-module 11 is reset to 0" is Delay_0. At the same time, the high-level signal generated by the AND gate U1 in the first sub-module 11 reaches the set end SB of the second flip-flop T2 in the second sub-module 12 after passing through the first inverter U2 in the first sub-module 11, so that the first output end Q is reset to a high level, that is, the first node EN<1> is high, and the second sub-module 12 starts working. The second delay time from "the rising edge of the feedback clock signal CLK_IN comes" to "the first output end Q of the second flip-flop T2 in the second sub-module 12 is reset to a high level" is Delay_1.

[0055] At the fourth time t4, the second node DN<0> and the third node UP<0> are reset to 0 by the fourth node EN<0>.

[0056] At the fifth time t5, the second rising edge of the reference clock signal CLK_REF makes the third flip-flop T3 in the second sub-module 12 output a high level to the fifth node DN<1>.

[0057] At the sixth time t6, the second rising edge of the feedback clock signal CLK_IN makes the first flip-flop T1 in the second sub-module 12 output a high level to the sixth node UP<1>, and the AND gate U1 connected to the second flip-flop T2 in the second sub-module 12 generates a high level signal, the second flip-flop T2 in the second sub-module 12 receives a rising edge and outputs a low level 0 to the first node EN<1>, which resets the first flip-flop T1 and the third flip-flop T3 in the second sub-module 12 to a low level, at this time, the resetting process of the first sub-module 11 is repeated, and the low level output by the high level generated by the AND gate U1 in the second sub-module 12 after being inverted by the first inverter U2 is output to the set end SB of the second flip-flop T2 in the first sub-module 12, which sets the output of the second flip-flop T2 in the first sub-module 12 to a high level 1, and restarts the first sub-module 11.

[0058] Since the alternative phase detection structure is adopted, the PFD can detect the phase of the reference clock signal CLK_REF with a higher frequency. It can be considered that as long as the following conditions are met:

[0059] ΔT+T D <2T CLK (2)

[0060] Wherein, ΔT is the time difference corresponding to the phase difference between the reference clock signal CLK_REF and the feedback clock signal CLK_IN, T D is the phase detection range, and T CLK is the clock period of the reference clock signal CLK_REF. Therefore, the PFD can normally detect the phase. As can be seen from formula (2), since the right side of the inequality is larger, the phase detection range T D can be larger, that is, the phase detection range of the PFD in the embodiment of the present application is larger than that of the PFD in the related art. If it is necessary to further increase the clock frequency of the reference clock signal CLK_REF of the PFD, more sub-modules 1 can be used for alternative phase detection, such as N sub-modules, and the working principle is similar to that of two sub-modules 1 for alternative phase detection. The clock frequency of the reference clock signal CLK_REF of the PFD can be increased to N times, so as to reduce the frequency division ratio of the DIV, thereby reducing the noise of the entire PLL.

[0061] Figure 5is another working timing diagram of the PFD provided by the embodiment of the present application. The working timing diagram can also be applicable to the PFD shown in Figure 3 in combination with Figure 3 and Figure 5 , the working process of the PFD is as follows:

[0062] At the first time t1, the first reset signal RST flips to 1 and the second reset signal RSTN flips to 0, at this time, the trigger input end CK and the set end SB of the second flip-flop T2 in the first sub-module 11 are set to 0, the first output end Q is set to 1, and it is ensured that the second flip-flop T2 in the first sub-module 11 can generate a rising edge when receiving the high-level signal output by the AND gate U1 in the first sub-module instead of being always high. The trigger input end CK and the set end SB of the second flip-flop T2 in the second sub-module 12 are set to 1, the reset end RB is set to 0, and the first output end Q is set to 0. When the second reset signal RSTN returns to 1, the whole PFD ends the reset state and enters the normal working mode. At this time, the first output end Q of the second flip-flop T2 in the second sub-module 12 is always 0, that is, the first node EN<1> is always 0, so that the first flip-flop T1 and the third flip-flop T3 in the second sub-module 12 are in the reset state and continuously output 0, and the second sub-module 12 does not work. Wherein, 1 represents high level, and 0 represents low level.

[0063] At the second time t2, the rising edge of the feedback clock signal CLK_IN comes, and the third flip-flop T3 in the first sub-module 11 outputs a high level to the third node UP<0>.

[0064] At the third time t3, the rising edge of the reference clock signal CLK_REF comes, the first flip-flop T1 in the first sub-module 11 outputs a high level to the second node DN<0>, and at the same time, the AND gate U1 before the trigger input end CK of the second flip-flop T2 in the first sub-module 11 outputs a high level to make the second flip-flop T2 in the first sub-module 11 receive a rising edge, and the first output end Q outputs a low level 0 to the fourth node EN<0>, and the first sub-module 11 stops working, so that the first output end Q of the first flip-flop T1 and the third flip-flop T3 in the first sub-module 11 is reset to 0,

[0065] The first delay time from "the rising edge of the reference clock signal CLK_REF comes" to "the first output end Q of the first flip-flop Tl and the third flip-flop T3 in the first sub-module 11 outputs reset to 0" is Delay_0. Meanwhile, the high level signal generated by the AND gate U1 in the first sub-module 11 reaches the set end SB of the second flip-flop T2 in the second sub-module 12 after passing through the first inverter U2 in the first sub-module 11, so that the first output end Q of the second flip-flop T2 resets to high level, that is, the first node EN<1> is high level, and the second sub-module 12 starts to work. The second delay time from "the rising edge of the reference clock signal CLK_REF comes" to "the first output end Q of the second flip-flop T2 in the second sub-module 12 resets to high level" is Delay_1.

[0066] At the fourth time t4, the second node DN<0> and the third node UP<0> are reset to 0 by the fourth node EN<0>.

[0067] At the fifth time t5, the second rising edge of the feedback clock signal CLK_IN makes the first flip-flop Tl in the second sub-module 12 output high level to the sixth node UP<1>.

[0068] At the sixth time t6, the second rising edge of the reference clock signal CLK_REF makes the third flip-flop T3 in the second sub-module 12 output high level to the fifth node DN<1>, and the AND gate U1 connected to the second flip-flop T2 in the second sub-module 12 generates high level signal. The second flip-flop T2 in the second sub-module 12 receives the rising edge and outputs low level 0 to the first node EN<1>, which resets the first flip-flop Tl and the third flip-flop T3 in the second sub-module 12 to low level. At this time, the reset process of the first sub-module 11 is repeated, and the low level output by the high level generated by the AND gate U1 in the second sub-module 12 after being inverted by the first inverter U2 is output to the set end SB of the second flip-flop T2 in the first sub-module 12, so that the output of the second flip-flop T2 in the first sub-module 12 is set to high level 1, and the first sub-module 11 is restarted.

[0069] The frequency discriminator and phase discriminator provided by the embodiment of the present application comprises N sub-modules, and each sub-module comprises a first flip-flop, a second flip-flop, a third flip-flop, an AND gate, a first switch unit and a first inverter. The control end of the first switch unit of the first sub-module is connected to a first reset signal, the first end is connected to a first power supply signal, and the second end is connected to the output end of the AND gate in the first sub-module. The control end of the first switch unit in the i-th sub-module is connected to a second reset signal, the first end is connected to the output end of the AND gate in the i-th sub-module, and the second end is connected to a second power supply signal. The set end of the third flip-flop in the first sub-module is connected to the output end of the first inverter in the N-th sub-module, the input end of the first inverter in the N-th sub-module is connected to the output end of the AND gate in the N-th sub-module, the input end of the first inverter in the i-th sub-module is connected to the output end of the AND gate in the i-th sub-module, and the output end of the first inverter in the i-th sub-module is connected to the set end of the third flip-flop in the i+1-th sub-module. The phase discrimination range can be improved, and the clock frequency of the input reference clock signal can be improved. That is, the working frequency of the PFD is high and the phase discrimination range is large.

[0070] Optionally, with reference to Figure 2 and Figure 3 , the first switch unit 10 comprises a third switch tube, the gate of the third switch tube is used as the control end of the first switch unit 10, the first pole of the third switch tube is used as the first end of the first switch unit 10, and the second pole of the third switch tube is used as the second end of the first switch unit 10. Optionally, the third switch tube is an N-channel semiconductor device.

[0071] Figure 6 is a structural schematic diagram of another frequency discriminator and phase discriminator provided by the embodiment of the present application. As shown in Figure 6 , the sub-module 1 further comprises a first delay control module 20, the input end IN of the first delay control module 20 is connected to the output end of the AND gate U1, the output end OUT of the first delay control module 20 is connected to the trigger input end CK of the third flip-flop T3, and the first delay control module 20 is used for delaying the first control signal Ctr1 and controlling the delay time length of the first control signal Ctr1.

[0072] As a preferred embodiment provided by the embodiment of the present application, Figure 7 is a structural schematic diagram of a first delay control module provided by the embodiment of the present application. As shown in Figure 7 , optionally, the first delay control module 20 comprises a delay unit 201 and a second switch unit 202. The delay unit 201 and the second switch unit 202 are connected between the input end IN of the first delay control module 20 and the output end OUT of the first delay control module 20.

[0073] In some embodiments, the on-off state of each second switch unit 202 can be controlled by coding, thereby controlling the delay size of the first delay module 20. If the width of the first delay time Delay_0 is too small, the phase difference between the current switching time of the later stage CP and the two input clock signals (i.e. the reference clock signal CLK_REF and the feedback clock signal CLK_IN) will not be proportional, resulting in an error. At this time, the delay size of the first delay module 20 can be adjusted by coding to make the CP work normally. By adjusting the delay size by coding, the critical delay that makes the CP work normally can be found. Under this delay condition, the internal loop delay of the PFD is minimized and the CP can work normally. This method can further improve the clock frequency of the reference clock signal CLK_REF input to the PFD.

[0074] Optionally, continuing to refer to Figure 7 the control end of each second switch unit 202 can be connected to a different coding signal. Each coding signal controls the on-off state of the corresponding second switch unit 202.

[0075] Figure 8 is another structure diagram of a phase frequency detector provided by an embodiment of the present application. As Figure 8 shown, the sub-module 1 further includes a second inverter U3 and a second delay control module 30.

[0076] The second inverter U3 is used to invert the first trigger signal and output a charging current control signal. The second delay control module 30 is used to delay the second trigger signal and output a discharging current control signal.

[0077] Optionally, the sub-module 1 further includes a charging current control signal output end IN1 and a discharging current control signal output end IN2. The charging current control signal output end IN1 is used to output the charging current control signal, and the discharging current control signal output end IN2 is used to output the discharging current control signal.

[0078] The phase frequency detector further includes a charge pump 2. The charge pump 2 includes N first branches 210 and N second branches 220 connected to an output node out1. The first branch 210 is connected to the charging current control signal output end IN1 one by one, and the second branch 220 is connected to the discharging current control signal output end IN2 one by one. By generating the charging current control signal and the discharging current control signal through the second inverter U3 and the second delay control module 30 respectively, the on-off of the charging and discharging currents in the charge pump 2 can be accurately controlled, and accurate current adjustment of the output node out1 can be realized. By setting multiple first branches 210 and second branches 220, the size and number of the charging and discharging currents can be flexibly adjusted according to actual needs, thereby meeting the requirements of different application scenarios.

[0079] The first branch 210 is configured to provide a charging current to the output node out1, and the second branch 220 is configured to provide a discharging current to the output node out1.

[0080] Optionally, the first branch 210 comprises a first switch tube K1 and a first current source IS1.

[0081] The gate of the first switch tube K1 is connected to a corresponding charging current control signal, the first pole of the first switch tube K1 is connected to the second power supply signal VDD, the second pole of the first switch tube K1 is connected to the first end of the first current source IS1, the second end of the first current source IS1 is connected to the output node out1, and the first switch tube K1 is configured to selectively conduct according to the charging current control signal, and when the first switch tube K1 is conducted, the first branch 210 is configured to provide the charging current to the output node out1.

[0082] And / or, the second branch 220 comprises a second switch tube K2 and a second current source IS2.

[0083] The gate of the second switch tube K2 is connected to a corresponding discharging current control signal, the first pole of the second switch tube K2 is connected to the first power supply signal VSS, the second pole of the second switch tube K2 is connected to the first end of the second current source IS2, the second end of the second current source IS2 is connected to the output node out1, and the second switch tube K2 is configured to selectively conduct according to the discharging current control signal, and when the second switch tube K2 is conducted, the second branch 220 is configured to provide the discharging current to the output node out1. The combination of the switch tube and the current source in the first branch 210 and the second branch 220 can quickly respond to the charging current control signal and the discharging current control signal, realize efficient charging and discharging process, and improve the performance and response speed of the PFD.

[0084] Optionally, the charge pump 2 further comprises a first capacitor C1, the first end of the first capacitor C1 is connected to the output node out1, and the second end of the first capacitor C1 is connected to the first power supply signal VSS. The presence of the first capacitor can smooth the voltage of the output node out1, reduce voltage fluctuation, and improve the stability of the PFD.

[0085] Based on the same inventive concept, the embodiments of the present application also provide a phase-locked loop, Figure 9 is a structural schematic diagram of a phase-locked loop provided by the embodiments of the present application. As shown in the figure, Figure 9 the phase-locked loop comprises the frequency discriminator 101 provided by any of the embodiments of the present application, and further comprises a loop filter 102, a voltage-controlled oscillator 103 and a frequency divider 104.

[0086] An input terminal of the loop filter 102 is connected with an output terminal of the phase frequency detector 101, and an output terminal of the loop filter 102 is connected with an input terminal of the voltage controlled oscillator 103; the voltage controlled oscillator 103 is used for outputting a first signal CLK_OUT; the loop filter 102 is used for generating a second signal according to a current signal generated by the phase frequency detector 101, and adjusting a frequency of the first signal output by the voltage controlled oscillator 103 through the second signal; an input terminal of the frequency divider 104 is connected with an output terminal of the voltage controlled oscillator 103, and the frequency divider 104 is used for frequency dividing the first signal CLK_OUT output by the voltage controlled oscillator 103 to generate a feedback clock signal.

[0087] Optionally, with continuous reference to Figure 9 The phase-locked loop further comprises a serial peripheral interface 105 (SPI), and the serial peripheral interface 105 comprises four connection ports, namely a serial data input terminal SDI, a serial data output terminal SDO, a serial clock terminal SCLK, and a chip selection signal terminal CSN.

[0088] Figure 10 is a structural schematic diagram of a chip provided by an embodiment of the present application, as Figure 10 shown, the chip comprises the phase-locked loop 200 provided by the embodiment of the present application, and further comprises a control module 300, which is in communication connection with the phase-locked loop 200 and is used for outputting an encoding signal ENCODE, the encoding signal ENCODE being used for controlling a delay time length of an internal loop of the phase frequency detector 101 in the phase-locked loop 200.

[0089] Optionally, the control module 300 can exchange data with the phase-locked loop 200 through the serial peripheral interface 105. Optionally, the control module 300 can comprise a single-chip microcomputer, and can further comprise a digital signal processor (DSP) or a field programmable gate array (FPGA).

[0090] The chip can be a radio frequency chip, an analog-to-digital converter (ADC) chip of various sampling rates, an automobile radar chip or a satellite chip.

[0091] The above specific embodiments do not constitute a limitation on the protection scope of the present application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and replacements can be made according to design requirements and other factors. Any modification, equivalent replacement and improvement within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A frequency and phase detector, characterized in that, include: There are N sub-modules, where N is an integer greater than or equal to 2; each sub-module includes a first flip-flop, a second flip-flop, a third flip-flop, an AND gate, a first switching unit, and a first inverter. The first trigger is used to receive a reference clock signal and output a first trigger signal; The third trigger is used to receive the feedback clock signal and output the second trigger signal; The AND gate is used to receive the first trigger signal and the second trigger signal, and generate a first control signal based on the first trigger signal and the second trigger signal, which is then input to the trigger input terminal of the third flip-flop. The second flip-flop is used to receive the first control signal and output a second control signal to the reset terminal of the first flip-flop and the reset terminal of the third flip-flop; In the N sub-modules, the control terminal of the first switch unit of the first sub-module is connected to the first reset signal, the first terminal is connected to the first power signal, and the second terminal is connected to the output terminal of the AND gate in the first sub-module, which is used to turn on when the first reset signal is an effective level signal. The control terminal of the first switch unit in the b-th submodule is connected to a second reset signal, the first terminal is connected to the output terminal of the AND gate in the b-th submodule, and the second terminal is connected to a second power supply signal, which is used to turn on when the second reset signal is a valid level signal; where b is an integer greater than 1 and less than or equal to N; The set terminal of the second flip-flop in the first submodule is connected to the output terminal of the first inverter in the Nth submodule, and the input terminal of the first inverter in the Nth submodule is connected to the output terminal of the AND gate in the Nth submodule. The input terminal of the first inverter in the i-th submodule is connected to the output terminal of the AND gate in the i-th submodule, and the output terminal of the first inverter in the i-th submodule is connected to the set terminal of the second flip-flop in the (i+1)-th submodule; where i is an integer greater than or equal to 1 and less than or equal to N-1.

2. The frequency and phase detector according to claim 1, characterized in that, The submodule further includes a first delay control module, the input of which is connected to the output of the AND gate, and the output of which is connected to the trigger input of the second flip-flop, for delaying the first control signal and controlling the delay duration of the first control signal.

3. The frequency and phase detector according to claim 1, characterized in that, The submodule also includes a second inverter and a second delay control module; The second inverter is used to invert the first trigger signal and output a charging current control signal; The second delay control module is used to delay the second trigger signal and output a discharge current control signal.

4. The frequency and phase detector according to claim 3, characterized in that, The submodule further includes a charging current control signal output terminal and a discharging current control signal output terminal. The charging current control signal output terminal is used to output the charging current control signal, and the discharging current control signal output terminal is used to output the discharging current control signal. The frequency and phase detector further includes a charge pump, which includes N first branches and N second branches connected to the N first branches at the output node. The first branches are connected to the charging current control signal output terminal one by one, and the second branches are connected to the discharging current control signal output terminal one by one. The first branch is used to provide charging current to the output node, and the second branch is used to provide discharging current to the output node.

5. The frequency and phase detector according to claim 4, characterized in that, The first branch includes a first switching transistor and a first current source; The gate of the first switch is connected to the corresponding charging current control signal, the first terminal of the first switch is connected to the second power supply signal, the second terminal of the first switch is connected to the first terminal of the first current source, the second terminal of the first current source is connected to the output node, the first switch is used to selectively turn on according to the charging current control signal, and when the first switch is turned on, the first branch is used to provide charging current to the output node. And / or, the second branch includes a second switching transistor and a second current source; The gate of the second switch is connected to the corresponding discharge current control signal, the first terminal of the second switch is connected to the first power supply signal, the second terminal of the second switch is connected to the first terminal of the second current source, the second terminal of the second current source is connected to the output node, the second switch is used to selectively turn on according to the discharge current control signal, and when the second switch is turned on, the second branch is used to provide discharge current to the output node.

6. The frequency and phase detector according to claim 4, characterized in that, The charge pump also includes a first capacitor, with a first terminal connected to the output node and a second terminal connected to the first power signal.

7. The frequency and phase detector according to claim 1, characterized in that, The feedback clock signal leads or lags behind the reference clock signal.

8. A phase-locked loop, characterized in that, The phase-locked loop includes a frequency and phase detector as described in any one of claims 1-7, and further includes a loop filter, a voltage-controlled oscillator, and a frequency divider; The input terminal of the loop filter is connected to the output terminal of the frequency and phase detector, and the output terminal of the loop filter is connected to the input terminal of the voltage-controlled oscillator. The voltage-controlled oscillator is used to output a first signal; The loop filter is used to generate a second signal based on the current signal generated by the frequency and phase detector, and to adjust the frequency of the first signal output by the voltage-controlled oscillator through the second signal. The input terminal of the frequency divider is connected to the output terminal of the voltage-controlled oscillator. The frequency divider is used to divide the first signal output by the voltage-controlled oscillator to generate a feedback clock signal.

9. A chip, characterized in that, The phase-locked loop including claim 8 further includes a control module, which is communicatively connected to the phase-locked loop and is used to output an encoded signal, which is used to control the delay duration of the internal loop of the phase-frequency detector in the phase-locked loop.

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