High-precision multi-level pipelined SAR ADC based on block LMS calibration

Abstract

The application provides a high-precision multi-stage Pipelined_SAR ADC based on block LMS calibration, which comprises a first-stage ADC subcircuit, a n-stage ADC subcircuit and a dither injection calibration algorithm module. The first-stage ADC subcircuit samples and performs multiple cycle comparison adjustment on an input signal, thereby outputting a 10-bit comparison result digital code. The n-stage ADC subcircuit performs residual amplification resampling on the capacitor upper plate voltage signal after the last adjustment of the previous-stage subcircuit is completed, and performs multiple cycle comparison adjustment on the sampled signal, thereby outputting a 9-bit comparison result digital code. The dither injection calibration algorithm module calibrates all weights according to all comparison result digital codes to obtain correct weights, and then performs normal ADC sampling quantization to obtain a digital code with high linearity. The application selects the first 5 DACs to be split to generate corresponding capacitor selection bits, the inter-stage scaling capacitor relaxes the multiple requirement of the residual amplifier, the calibration weights are processed twice to obtain correct weights, and the linearity can be improved.

Description

Technical Field

[0001] This invention belongs to the field of mixed-signal circuit design technology, specifically relating to a high-precision multi-level pipelined_SAR ADC based on block LMS calibration. Background Technology

[0002] Pipelined SAR ADCs have gained widespread attention in recent years due to their combination of the advantages of both Pipelined ADCs and SAR ADCs. They divide the data quantization process into several parallel stages, effectively balancing accuracy and speed performance requirements. Each stage uses a SAR ADC as a submodule, resulting in a relatively simple structure, high linearity, and applicability to medium-speed, medium-precision applications.

[0003] However, when the accuracy of the Pipelined_SAR ADC exceeds 12 bits, capacitor mismatch limits the linearity of the Pipelined_SAR ADC. Summary of the Invention

[0004] To address the aforementioned problems in the existing technology, this invention provides a high-precision multi-level pipelined_SAR ADC based on block LMS calibration. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] A high-precision multi-stage pipelined SAR ADC based on block LMS calibration includes: an N-stage pipelined ADC sub-circuit and a dither injection calibration algorithm module;

[0006] The first-stage ADC sub-circuit samples the input signal and performs multiple cyclic comparisons and adjustments based on the sampled signal, thereby outputting a 10-bit comparison result digital code to the dither injection calibration algorithm module. The nth-stage ADC sub-circuit performs residual amplification on the upper plate voltage signal of the capacitor after the last adjustment of the previous-stage ADC sub-circuit, and then samples the signal obtained after residual amplification. It performs multiple cyclic comparisons and adjustments based on the sampled signal, thereby outputting a 9-bit comparison result digital code to the dither injection calibration algorithm module. The dither injection calibration algorithm module calibrates all weights based on all comparison result digital codes to obtain the calibrated weights.

[0007] Beneficial effects:

[0008] This invention provides a high-precision multi-stage Pipelined_SAR ADC based on block LMS calibration, comprising: a first-stage ADC subcircuit sampling the input signal and performing multiple cyclic comparisons and adjustments based on the sampled signal, thereby outputting a 10-bit comparison result digital code to the dither injection calibration algorithm module; an nth-stage ADC subcircuit performing residual amplification on the upper plate voltage signal of the capacitor after the last adjustment of the previous stage ADC subcircuit, then sampling the signal obtained after residual amplification, and performing multiple cyclic comparisons and adjustments based on the sampled signal, thereby outputting a 9-bit comparison result digital code to the dither injection calibration algorithm module; the dither injection calibration algorithm module calibrating all weights based on all comparison result digital codes to obtain the calibrated weights. This invention chooses to split the first 5 bits of the DAC into 31 DEM unit capacitors, plus a pseudo-random number generator to generate corresponding capacitor selection bits. The inter-stage scaling capacitor relaxes the requirement for the residual amplifier multiple, reducing it from the original 256 times (stage 1) and 128 times (stage 2) to 32 times. This invention processes the acquired data in two stages during calibration mode. The first stage introduces a dither perturbation component through a dither injection capacitor, while the second stage does not. The difference between the two processing results is used to iteratively correct the weight values ​​using a block-based LMS calibration algorithm. After millions of corrections, the correct weights are obtained. Normal ADC sampling and quantization is then performed using the correct weights, resulting in digital codes with relatively high linearity. Therefore, this invention can improve the linearity of the Pipelined_SAR ADC.

[0009] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the structure of a high-precision multi-level pipelined_SAR ADC based on block LMS calibration provided by the present invention. Detailed Implementation

[0011] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0012] refer to Figure 1 The present invention provides a high-precision multi-stage pipelined SAR ADC based on block LMS calibration, comprising: an ADC sub-circuit connected by an N-stage pipeline and a dither injection calibration algorithm module;

[0013] The first-stage ADC sub-circuit samples the input signal and performs multiple cyclic comparisons and adjustments based on the sampled signal, thereby outputting a 10-bit comparison result digital code to the dither injection calibration algorithm module. The nth-stage ADC sub-circuit performs residual amplification on the upper plate voltage signal of the capacitor after the last adjustment of the previous-stage ADC sub-circuit, and then samples the signal obtained after residual amplification. It performs multiple cyclic comparisons and adjustments based on the sampled signal, thereby outputting a 9-bit comparison result digital code to the dither injection calibration algorithm module. The dither injection calibration algorithm module calibrates all weights based on all comparison result digital codes to obtain the calibrated weights.

[0014] refer to Figure 1 , Figure 1 It is a three-level multi-stage Pipelined_SAR ADC, in Figure 1 The ADC sub-circuits are 10 bits, 9 bits, and 9 bits respectively, with 2 bits of inter-stage redundancy between each stage, resulting in actual bit counts of 10 bits, 7 bits, and 7 bits for each stage. To improve the accuracy of the first few bits without excessively consuming hardware resources, this invention splits the first 5 bits into 31 DEM unit capacitors, adding a pseudo-random number generator to produce the corresponding capacitor selection bits. The inter-stage scaling capacitor relaxes the factor requirement for the residual amplifier, reducing it from 256 times (stage 1) and 128 times (stage 2) to 32 times. In calibration mode, the acquired data is processed twice. The first time, a dither perturbation component is introduced through a dither injection capacitor, while the second time, no dither perturbation component is injected. The difference between the two processing results is iteratively corrected using a block LMS calibration algorithm to adjust the weight value. After millions of corrections, the correct weight is obtained, and then the correct result is derived using the correct weight.

[0015] Continue to refer to Figure 1 The first-stage ADC sub-circuit includes a random number generator, a DEM module, a first-stage DAC module, a first-stage comparator, and a first-stage SAR logic circuit. The output of the random number generator is connected to the input of the DEM module, the output of the DEM module is connected to the first terminal of the first-stage DAC module, the second terminal of the first-stage DAC module is connected to a Vip signal or a Vref signal, the inverting terminal of the first-stage comparator is grounded, and its output is connected to the input of the first-stage SAR logic circuit and the input of the second-stage ADC sub-circuit. The output of the first-stage SAR logic circuit is connected to the control terminal of the first-stage DAC module to control the second terminal of the first-stage DAC module to connect to a Vip signal or a Vref signal. The output of the first-stage SAR logic circuit is also connected to the input of the dither injection calibration algorithm module.

[0016] The random number generator is used to generate pseudo-random numbers;

[0017] The DEM module is used to select capacitors and corresponding switching modes in the first-stage DAC module based on the pseudo-random number.

[0018] The first-stage DAC module is used to sample the input signal according to the connection method of the capacitors in the sampling stage to obtain the sampled signal;

[0019] The first-stage comparator is used to compare the sampled signal with the ground signal and output a digital code of the comparison result.

[0020] The first-level logic circuit is used to generate control logic based on the digital code of the comparison result;

[0021] The first-stage DAC module is also used to switch its own capacitors according to the corresponding switching method in each cycle according to the control logic, and output the voltage signal of the upper plate of the capacitor after the switching is completed.

[0022] The first-stage comparator is also used to compare the voltage signal on the upper plate of the capacitor with the ground signal in each cycle and output a comparison signal to the first-stage logic circuit.

[0023] The first-level logic circuit is also used to output the digital code of the comparison results of 10 comparisons to the dither injection calibration algorithm module.

[0024] The first-stage DAC module of the present invention includes: a dynamic unit matching capacitor and a parallel capacitor bank;

[0025] The dynamic unit matching capacitor includes nine parallel capacitors with a value of 2. 5 The capacitors consist of nine capacitors, with the upper plate of one capacitor serving as the first terminal of the first-stage DAC module, connected to the non-inverting input of the first-stage comparator, and the upper plate of the other capacitor serving as the second terminal of the first-stage DAC module. The parallel capacitor bank comprises six capacitors connected in parallel, with the upper plate of each capacitor connected to the upper plate of the dynamic unit matching capacitor, and the lower plate connected to the lower plate of the dynamic unit matching capacitor. The capacitance of the second capacitor in the six parallel capacitors is 2... 0 Starting with a capacity of 2 1 The capacitance increases proportionally; the capacitance of the first capacitor is 2. 0 .

[0026] like Figure 1 As shown, Figure 1In this invention, the LFSR is a pseudo-random number generator used to generate the serial number of the DEM capacitor; while the DEM module is a module that uses dynamic unit matching (DEM) technology, as shown in the literature (esper Steensgaard-Madsen, "Analog-to-digital converter system and method", United States Patent Number 8,810,443). When performing the first 5 bits of quantization, this invention will randomly select 16, 8, 4, 2, and 1 times the DEM unit capacitance for quantization in sequence. In this way, the product of the first 5 bits of digital code and the weight has characteristics similar to white noise, and will be averaged and suppressed under the limited noise bandwidth.

[0027] Continue to refer to Figure 1 The nth-stage ADC sub-circuit of the present invention includes an nth-stage residual amplifier, an nth-stage scaling capacitor, an nth-stage comparator, an nth-stage DAC module, and an nth-stage SAR logic circuit; n takes values ​​from 2 to N;

[0028] In this circuit, the non-inverting input of the nth-stage residual amplifier is connected to the output of the first-stage ADC sub-circuit, and the inverting input is grounded. The output of the nth-stage residual amplifier is connected to the upper plate of the nth-stage scaling capacitor, the first terminal of the nth-stage DAC module, and the non-inverting input of the nth-stage comparator. The lower plate of the nth-stage scaling capacitor and the second terminal of the nth-stage DAC module are connected to either the Vcm signal or the Vref signal. The inverting input of the nth-stage comparator is grounded, and its output is connected to the input of the nth-stage SAR logic circuit and the input of the (n+1)th-stage ADC sub-circuit. The output of the nth-stage SAR logic circuit is connected to the control terminal of the nth-stage DAC module to control the second terminal of the DAC module to receive either the Vcm signal or the Vref signal. The output of the nth-stage SAR logic circuit is also connected to the input of the dither injection calibration algorithm module.

[0029] The nth stage residual amplifier is used to amplify the voltage signal on the upper plate of the capacitor in the 10th iteration of the previous stage ADC sub-circuit to obtain the residual amplified signal.

[0030] The nth-stage scaling capacitor is used to further amplify the residual amplified signal of the nth stage to obtain the amplified signal.

[0031] The nth stage DAC module is used to sample the amplified signal of the nth stage according to the connection method of the capacitors in the sampling stage to obtain the nth stage sampled signal;

[0032] The nth-stage comparator is used to compare the nth-stage sampled signal with the ground signal and output the nth-stage comparison signal.

[0033] The nth-level logic circuit is used to generate the nth-level control logic based on the nth-level comparison signal;

[0034] The nth-stage DAC module is also used to switch its own capacitors according to the corresponding switching method in each loop according to the control logic, and output the upper plate voltage signal of the capacitor after the switching is completed.

[0035] The nth stage comparator is also used to compare the voltage signal on the upper plate of the capacitor with the ground signal in each feedback and output a comparison signal to the nth stage logic circuit.

[0036] The nth-level logic circuit is also used to output the digital code of the comparison result of the nth-level ADC sub-circuit a total of 9 times to the dither injection calibration algorithm module.

[0037] The nth stage DAC module includes: 9 capacitors connected in parallel, wherein the capacitance of the first capacitor is 2... 0 Starting with a capacity of 2 1 The capacitance increases proportionally until the 9th capacitor has a capacitance of 2. 8 ;

[0038] The upper plate of the nine capacitors is the first terminal of the nth stage DAC module, connected to the non-inverting input of the (n+1)th stage comparator, and the lower plate is the second terminal of the nth stage DAC module.

[0039] Figure 1 The scaling capacitor in the figure is the same as that in the literature (Rao Chenguang, Xiao Rui, Sang Qinghua, et al. Design of high-performance margin amplifier for Piplined-SAR ADC based on g_(m) / I_(d) method [J]. Microelectronics, 2021, 51(3): 8), in Figure 1 Let Catt_b = 7 * Catt_a, and Catt_d = 31 * Catt_c. Figure 1 Taking level 1 and level 2 as an example, the difference between them originally needed to be magnified by 2. 8 =256 times, which is extremely difficult to achieve. A voltage divider is used through capacitors Catt_a, Catt_b, and a second-stage 512C0 capacitor array (where C0 is a unit capacitance). Because 512C0 >> Catt_a + Catt_b, therefore:

[0040]

[0041] Among them, V ref This is the reference voltage for level 1, V. ref2 It is the reference voltage for the second stage, i.e., the reference voltage V for the second stage. ref2 Reduced to the first-level reference voltage V ref1 / 8. Therefore, the actual amplification factor of the residual amplifier between the first and second stages is 256 / 8 = 32.

[0042] Similarly, the second and third stages are divided by a capacitor array consisting of Catt_c, Catt_d, and the 512C0 capacitor in the third stage, thus dividing the reference voltage V of the third stage. ref3 Compressed to the first-level reference voltage V ref 1 / 32, which is the second-stage reference voltage V ref If 1 / 4 of the magnification is used, then the magnification between the second and third levels is 128 / 4 = 32.

[0043] Continue to refer to Figure 1 The dither injection calibration algorithm module calibrates all weights based on the digital codes of all comparison results to obtain the calibrated weights, including:

[0044] Receives the digital codes of all comparison results output from the two outputs of the ADC sub-circuit connected in an N-stage pipeline;

[0045] For the same position in all comparison results of the two outputs, set 0 and 1 respectively according to whether perturbation is added or not;

[0046] Calculate the difference between all comparison results and the unperturbed digital codes;

[0047] The error function is calculated using the difference and the initial weights of the introduced perturbation capacitor;

[0048] The weights are updated and calibrated multiple times using the error function to obtain the updated weights.

[0049] Figure 1 The dither injection calibration algorithm module based on the block LMS algorithm in this invention differs from that in the literature (Hongxing Li, Mark Maddox, Michael CW Coln, et al. A Signal-Independent Background-Calibrating 20b 1MS / s SAR ADC with 0.3ppm INL. ISSCC, 2018) in that the dither injection in this invention is performed on the same circuit.

[0050] In calibration mode, this invention performs two quantizations for each data sample. The first quantization injects a small perturbation (dither) into the input, while the second quantization does not. The difference Δ between the two quantizations represents the perturbation introduced in the analog domain. Ideally, if the circuit has no capacitor mismatch, this perturbation can be subtracted from the digital domain without changing the result. However, in reality, capacitor mismatch introduces nonlinear errors, and Δ contains information about these errors.

[0051] Δ=D A -D B (2)

[0052] In the above formula, Δ represents the difference between the two quantization results in digital code, and D A D represents the quantization result after the first injection of dither. B This indicates the result of the second quantization without dither injection.

[0053] e=Δ×W(3)

[0054] e represents the error function, indicating the degree of deviation between the current weights and the true values.

[0055] W (new) =W (old )-μ×Δ T ×e (4)

[0056] Equation (3) is an iterative equation that continuously updates the weights, where W (new) It is the updated weight, W (old) These are the old weights before the update, μ is the step size coefficient controlling the iteration speed, and Δ... T It is the transpose of matrix Δ.

[0057]

[0058] Through multiple iterations of the block-based LMS algorithm, the computational cost of a million LMS iterations becomes excessive. To reduce this computational burden, the sum of L error functions can be accumulated before a final weight update. By continuously adjusting the initial weights, this error is gradually reduced until it approaches an acceptable range. Finally, the introduced perturbation dither is subtracted from the digital domain to obtain the weights that meet the accuracy requirements. The following example illustrates the specific process of this invention using the block-based LMS algorithm for multiple iterations and weight updates:

[0059] For example, the initial weights W0 = [w1, w2, w3…w 28 ] T A disturbance is introduced into the capacitor C_dither, and the insertion position is w9 and w 10Between w_dither and w9, then W0' = [w1, w2, w3… w9, w_dither, w 10 …w 28 ] T For example, in standard mode, sampling is quantized once:

[0060] The first quantization data introduced for C_dither is:

[0061] D A = [10010101111101011110101100101];

[0062] The second quantization data without introducing C_dither is:

[0063] D B = [01010101011101011110101100101];

[0064] The difference between the two is: Δ = D A -D B = [010000001000000000000000000000];

[0065] The error function is:

[0066] The error update method is expressed as: block_sum(new) = block_sum(old) + Δ T *e;

[0067] After the error block_sum is accumulated 32 times, i.e., L=32, the weight is updated once. The update method is: W(new) = W(old) - u*block_sum, where u is the step size coefficient that controls the iteration speed. A total of 2 calibrations are required. 20 Next, of which, the first 2 14 times, u=2 -5 The iteration speed is relatively fast. (The last two...) 14 times, u=2 -9 The iteration speed is slow because, 2 20 ÷32=2 15 ,2 15 =2 14 +2 14 .

[0068] It is worth noting that the terms "first" and "second" in this invention are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0069] Although this application has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality.

[0070] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A high-precision multi-level pipelined_SAR ADC based on block LMS calibration, characterized in that, include: The N-stage ADC sub-circuit and the dither injection calibration algorithm module are connected in a pipeline manner. The first-stage ADC sub-circuit samples the input signal and performs multiple cyclic comparisons and adjustments based on the sampled signal, thereby outputting a 10-bit comparison result digital code to the dither injection calibration algorithm module. The nth-stage ADC sub-circuit performs residual amplification on the upper plate voltage signal of the capacitor after the last adjustment of the previous-stage ADC sub-circuit, and then samples the signal obtained after residual amplification. It performs multiple cyclic comparisons and adjustments based on the sampled signal, thereby outputting a 9-bit comparison result digital code to the dither injection calibration algorithm module. The dither injection calibration algorithm module calibrates all weights based on all comparison result digital codes to obtain the calibrated weights. The first-stage ADC sub-circuit includes a random number generator, a DEM module, a first-stage DAC module, a first-stage comparator, and a first-stage SAR logic circuit. The output of the random number generator is connected to the input of the DEM module. The output of the DEM module is connected to the first terminal of the first-stage DAC module. The second terminal of the first-stage DAC module is connected to a Vip signal or a Vref signal. The inverting input of the first-stage comparator is grounded, and its output is connected to the input of the first-stage SAR logic circuit and the input of the second-stage ADC sub-circuit. The output of the first-stage SAR logic circuit is connected to the control terminal of the first-stage DAC module to control the second terminal of the first-stage DAC module to connect to a Vip signal or a Vref signal. The output of the first-stage SAR logic circuit is also connected to the input of the dither injection calibration algorithm module. The nth-stage ADC sub-circuit includes an nth-stage residual amplifier, an nth-stage scaling capacitor, an nth-stage comparator, an nth-stage DAC module, and an nth-stage SAR logic circuit; n takes values ​​from 2 to N; In this circuit, the non-inverting input of the nth-stage residual amplifier is connected to the output of the first-stage ADC sub-circuit, and the inverting input is grounded. The output of the nth-stage residual amplifier is connected to the upper plate of the nth-stage scaling capacitor, the first terminal of the nth-stage DAC module, and the non-inverting input of the nth-stage comparator. The lower plate of the nth-stage scaling capacitor and the second terminal of the nth-stage DAC module are connected to either the Vcm signal or the Vref signal. The inverting input of the nth-stage comparator is grounded, and its output is connected to the input of the nth-stage SAR logic circuit and the input of the (n+1)th-stage ADC sub-circuit. The output of the nth-stage SAR logic circuit is connected to the control terminal of the nth-stage DAC module to control the second terminal of the DAC module to receive either the Vcm signal or the Vref signal. The output of the nth-stage SAR logic circuit is also connected to the input of the dither injection calibration algorithm module.

2. The high-precision multi-level pipelined_SAR ADC based on block LMS calibration according to claim 1, characterized in that, The random number generator is used to generate pseudo-random numbers; The DEM module is used to select capacitors and corresponding switching modes in the first-stage DAC module based on the pseudo-random number. The first-stage DAC module is used to sample the input signal according to the connection method of the capacitors in the sampling stage to obtain the sampled signal; The first-stage comparator is used to compare the sampled signal with the ground signal and output a digital code of the comparison result. The first-level logic circuit is used to generate control logic based on the digital code of the comparison result; The first-stage DAC module is also used to switch its own capacitors according to the corresponding switching method in each cycle according to the control logic, and output the voltage signal of the upper plate of the capacitor after the switching is completed. The first-stage comparator is also used to compare the voltage signal on the upper plate of the capacitor with the ground signal in each cycle and output a comparison signal to the first-stage logic circuit. The first-level logic circuit is also used to output the digital code of the comparison results of 10 comparisons to the dither injection calibration algorithm module.

3. The high-precision multi-level pipelined_SAR ADC based on block LMS calibration according to claim 2, characterized in that, The first-stage DAC module includes: a dynamic unit matching capacitor and a parallel capacitor bank; The dynamic unit matching capacitor includes nine parallel capacitors with a value of 2. 5 The capacitors consist of nine capacitors, with the upper plate of one capacitor serving as the first terminal of the first-stage DAC module, connected to the non-inverting input of the first-stage comparator, and the upper plate of the other capacitor serving as the second terminal of the first-stage DAC module. The parallel capacitor bank comprises six capacitors connected in parallel, with the upper plate of each capacitor connected to the upper plate of the dynamic unit matching capacitor, and the lower plate connected to the lower plate of the dynamic unit matching capacitor. The capacitance of the second capacitor in the six parallel capacitors is 2... 0 Starting with a capacity of 2 1 The capacitance increases proportionally; the capacitance of the first capacitor is 2. 0 .

4. The high-precision multi-level pipelined_SAR ADC based on block LMS calibration according to claim 1, characterized in that, The nth stage residual amplifier is used to amplify the voltage signal on the upper plate of the capacitor in the 10th iteration of the previous stage ADC sub-circuit to obtain the residual amplified signal. The nth-stage scaling capacitor is used to further amplify the residual amplified signal of the nth stage to obtain the amplified signal. The nth stage DAC module is used to sample the amplified signal of the nth stage according to the connection method of the capacitors in the sampling stage to obtain the nth stage sampled signal; The nth-stage comparator is used to compare the nth-stage sampled signal with the ground signal and output the nth-stage comparison signal. The nth-level logic circuit is used to generate the nth-level control logic based on the nth-level comparison signal; The nth-stage DAC module is also used to switch its own capacitors according to the corresponding switching method in each loop according to the control logic, and output the upper plate voltage signal of the capacitor after the switching is completed. The nth stage comparator is also used to compare the voltage signal on the upper plate of the capacitor with the ground signal in each feedback and output a comparison signal to the nth stage logic circuit. The nth-level logic circuit is also used to output the digital code of the comparison result of the nth-level ADC sub-circuit a total of 9 times to the dither injection calibration algorithm module.

5. The high-precision multi-level pipelined_SAR ADC based on block LMS calibration according to claim 1, characterized in that, The nth stage DAC module includes: 9 capacitors connected in parallel, wherein the capacitance of the first capacitor is 2... 0 Starting with a capacity of 2 1 The capacitance increases proportionally until the 9th capacitor has a capacitance of 2. 8 ; The upper plate of the nine capacitors is the first terminal of the nth stage DAC module, connected to the non-inverting input of the (n+1)th stage comparator, and the lower plate is the second terminal of the nth stage DAC module.

6. The high-precision multi-level pipelined_SAR ADC based on block LMS calibration according to claim 1, characterized in that, The dither injection calibration algorithm module calibrates all weights based on the digital codes of all comparison results to obtain the calibrated weights, including: Receives the digital codes of all comparison results output from two times by an N-stage ADC sub-circuit connected in a pipeline manner; For the same position in all comparison results of the two outputs, set 0 and 1 respectively according to whether perturbation is added or not; Calculate the difference between all comparison results and the unperturbed digital codes; The error function is calculated using the difference and the initial weights of the introduced perturbation capacitor; The weights are updated and calibrated multiple times using the error function to obtain the updated weights.

7. The high-precision multi-level pipelined_SAR ADC based on block LMS calibration according to claim 6, characterized in that, The step of using the error function to update and calibrate the weights multiple times to obtain the updated weights includes: The error function and the weight for each step are accumulated multiple times, and the weight is updated once using the step size coefficient when the predetermined number of accumulations is reached, so as to obtain the updated weight.

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