Analog-to-digital converter and analog-to-digital conversion chip

Abstract

The embodiment of the invention discloses an analog-to-digital converter and an analog-to-digital conversion chip. The analog-to-digital converter comprises an input interface, a tracking type analog-to-digital conversion module, an oversampling modulator, a digital logic combination module and an output interface, the input interface is used for transmitting input signals; the oversampling modulator is used for generating an initial fine conversion bit stream according to an input signal; the tracking type analog-to-digital conversion module is used for quantizing an input signal and generating a coarse conversion digital code; the digital logic combination module is used for generating a feedback digital code according to the rough conversion digital code and the initial fine conversion bit stream; and the output interface is connected between the digital logic combination module and the oversampling modulator and is used for outputting the feedback digital code. According to the analog-to-digital converter provided by the embodiment, only one minimum clock period is needed in the rough conversion stage, the feedback digital code is generated through the digital logic combination module, the circuit principle is simple, and the performance and overhead of the analog-to-digital converter are effectively improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of analog and mixed analog-digital integrated circuits, and in particular to an analog-to-digital converter and an analog-to-digital conversion chip. Background Art

[0002] In instrumentation applications, such as sensor interfaces, biomedical signal processing, and data readout of industrial instruments, analog-to-digital converters (ADCs) with high absolute accuracy and linearity are required. In recent years, a hybrid architecture zoom ADC (zoom ADC) based on the improved sigma-delta modulator has been proposed to achieve high accuracy.

[0003] Zoom ADC is a type of two-step ADC, which is divided into two categories: static zoom ADC and dynamic zoom ADC. In applications that require higher conversion speeds, dynamic zoom ADC is often used. However, in the existing dynamic zoom ADC architecture, an asynchronous successive approximation ADC is used as a coarse conversion ADC, which has the problem of complex structure of the coarse conversion ADC.

[0004] The existing analog-to-digital converter has the problems of long conversion cycle and complex structure when completing the coarse conversion of ADC signal. Summary of the invention

[0005] The embodiments of the present invention provide an analog-to-digital converter and an analog-to-digital conversion chip to solve the problems of a long conversion cycle and a complex structure when the existing analog-to-digital converter performs coarse conversion of an ADC signal.

[0006] In order to achieve the above technical problems, the present invention adopts the following technical solutions:

[0007] An embodiment of the present invention provides an analog-to-digital converter, comprising:

[0008] Input interface, tracking analog-to-digital conversion module, oversampling modulator, digital logic combination module and output interface;

[0009] The input interface is connected to the tracking analog-to-digital conversion module and the oversampling modulator respectively, and the input interface is used to transmit the input signal Vin; the oversampling modulator is used to convert the input signal Vin into a digital signal according to the input signal V in Generate an initial fine conversion bit stream; the tracking analog-to-digital conversion module is used to convert the input signal V in Quantize and generate a coarse conversion digital code K;

[0010] The digital logic combination module is connected between the tracking analog-to-digital conversion module and the oversampling modulator, and is used to generate a feedback digital code N according to the coarse conversion digital code K and the initial fine conversion bit stream. dac;

[0011] The output interface is connected between the digital logic combination module and the oversampling modulator, and the output interface is used to convert the feedback digital code N dac Output.

[0012] Optionally, the oversampling modulator is further configured to: in and the feedback digital code N dac , generating an adjusted fine conversion bit stream; the adjusted bit stream is used to adjust the feedback digital code N generated by the digital logic combination module dac ;

[0013] The output interface is connected between the digital logic combination module and the oversampling modulator, and the output interface is used to output the adjusted feedback digital code N dac Output.

[0014] Optionally, the digital logic combination module includes:

[0015] A clock unit, a comparison unit, a first configuration unit, a second configuration unit and an output unit;

[0016] The clock unit is connected to the comparison unit, and the clock unit is used to generate a clock signal;

[0017] The comparison unit is connected to the first configuration unit and the second configuration unit, and the output unit is connected to the first configuration unit and the second configuration unit; the comparison unit is used to compare the fine conversion bit stream with a preset parameter value, and when the fine conversion bit stream is equal to the preset parameter value, the first configuration unit configures the feedback digital code as a first parameter; when the fine conversion bit stream is not equal to the preset parameter value, the second configuration unit configures the feedback digital code as a second parameter; the output unit is used to output the first parameter and the second parameter respectively.

[0018] Optionally, the digital logic combination module is specifically used to: when the rising edge of the clock signal clk arrives, determine whether the fine conversion bit stream bs is 1 through the comparison unit, if the fine conversion bit stream bs=1, configure the feedback digital code N through the first configuration unit dac =K+2, and output the feedback digital code N through the output unit dac =K+2; if the fine conversion bit stream bs=0, the feedback digital code N is configured by the second configuration unit dac = K-1, and output the feedback digital code N through the output unit dac=K-1; wherein the clock signal clk is the fastest sampling clock of the analog-to-digital converter, and its sampling period is Ts.

[0019] Optionally, the tracking analog-to-digital conversion module comprises: a first comparator, an up-down counter and a digital-to-analog conversion array;

[0020] The non-inverting input terminal of the first comparator is connected to the input interface, the inverting input terminal of the first comparator is connected to the output terminal of the digital-to-analog conversion array, the output terminal of the first comparator is connected to the first input terminal of the up-down counter, the second input terminal of the up-down counter is used to input the sampling frequency FS, the first output terminal of the up-down counter is connected to the input terminal of the digital-to-analog conversion array, and the second output terminal of the up-down counter is connected to the digital logic combination module;

[0021] The first comparator is used to compare the input signal V in and the digital-to-analog conversion array generates a feedback DAC signal V dac Performing comparison and generating comparison results;

[0022] The up / down counter generates a rough conversion digital code K by increasing by 1 or decreasing by 1 according to the comparison result; the rough conversion digital code K is used to output to the digital logic combination module and control the digital-to-analog conversion array to generate the feedback DAC signal V dac .

[0023] Optionally, the oversampling modulator comprises:

[0024] A loop filter, a second comparator and a feedback DAC unit; the loop filter is connected to the input interface and the feedback DAC unit, and the loop filter is used to generate a feedback signal according to the input signal V in and the feedback DAC unit outputs the feedback signal V fb The difference between the two outputs the corresponding analog voltage V;

[0025] The second comparator is connected to the loop filter, and is used to compare the analog voltage V with a preset reference signal value, and output the fine conversion bit stream bs according to the comparison result;

[0026] The feedback DAC unit is connected to the digital logic combination module, and the feedback DAC unit is used to dac Generate and output feedback signal V fb to the input interface; the feedback signal V fb Follows the input signal V in change.

[0027] Optionally, the feedback digital code Ndac The number of digits is N;

[0028] The number of bits of the feedback DAC unit is related to the feedback digital code N dac The number of digits matches;

[0029] The second comparator is used to receive the output voltage V of the loop filter, and output a 1-bit fine conversion bit stream bs according to the positive or negative condition of the output voltage V of the loop filter; wherein the fine conversion bit stream bs is 0 or 1.

[0030] Optionally, the feedback signal V fb The values ​​include:

[0031] V fb =(K-1)*V LSB Or, V fb =(K+2)*V LSB

[0032] Among them, V LSB is the minimum output step size of the feedback DAC unit, and K is the coarse conversion digital code.

[0033] Optionally, the feedback digital code N dac The coarse conversion digital code K contained in is the (n-1)th period input signal V in The corresponding quantization value, n is a positive integer; when the feedback digital code Ndac acts on the oversampling modulator and performs the conversion of the nth cycle, the input signal V in The following conditions are met:

[0034] K*V LSB <V in <(K+1)*V LSB

[0035]

[0036] Among them, A FS is the input signal V in The full swing, f in is the input signal V in frequency, Fs is the sampling frequency, N is the number of bits of the tracking analog-to-digital conversion module, V refh With V refl They are respectively a high reference level and a low reference level of the analog-to-digital converter.

[0037] Optionally, the analog-to-digital converter further includes: a digital decimation filter;

[0038] The digital decimation filter is connected to the output end of the digital logic combination module;

[0039] The digital decimation filter is used to receive the feedback digital code N dac , and the feedback digital code N dac Perform downsampling and decimation filtering to generate a digital output signal D out ; Wherein, the sampling frequency of the digital extraction filter is FS.

[0040] According to another aspect of the present invention, this embodiment provides an analog-to-digital conversion chip, including: the analog-to-digital converter proposed in any item of the first invention.

[0041] The analog-to-digital converter provided in the embodiment of the present invention uses a tracking analog-to-digital conversion module to generate a coarse conversion digital code K, and uses Tracking ADC as a coarse conversion analog-to-digital conversion unit. Since the output signal of the tracking analog-to-digital conversion module has the characteristic of being available at any time, the analog-to-digital converter provided in this embodiment only needs one minimum clock cycle in the coarse conversion stage, and generates a feedback digital code Ndac through a digital logic combination module, and the feedback digital code Ndac can be transmitted to the output interface for generating a digital signal. The circuit principle is simple, and the performance and overhead of the analog-to-digital converter are effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the contents of the embodiments of the present invention and these drawings without paying any creative work.

[0043] Figure 1 is a structural schematic diagram of an analog-to-digital converter provided by an embodiment of the present invention;

[0044] Figure 2 It is a structural schematic diagram of a digital logic combination module of an analog-to-digital converter provided by an embodiment of the present invention;

[0045] Figure 3 is a waveform diagram of a signal of an analog-to-digital converter provided by an embodiment of the present invention;

[0046] Figure 4 It is a structural schematic diagram of a tracking analog-to-digital conversion module of an analog-to-digital converter provided by an embodiment of the present invention;

[0047] Figure 5 is a schematic structural diagram of another analog-to-digital converter provided by an embodiment of the present invention;

[0048] Figure 6 is a structural schematic diagram of another analog-to-digital converter provided by an embodiment of the present invention;

[0049] Figure 7 is a feedback voltage V of an analog-to-digital converter provided in an embodiment of the present invention fb Schematic diagram of the time domain;

[0050] Figure 8 This is a result diagram comparing the signal to quantization noise ratio of an analog-to-digital converter provided by an embodiment of the present invention and a traditional first-order Sigma-delta modulator with different quantization bits;

[0051] Fig. 9 This is a result diagram comparing the number of comparators required by an analog-to-digital converter provided by an embodiment of the present invention and a traditional first-order Sigma-delta modulator with different quantization bit numbers. DETAILED DESCRIPTION

[0052] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0053] Based on the above technical problems, this embodiment proposes the following solutions:

[0054] Figure 1 is a schematic diagram of the structure of an analog-to-digital converter provided by an embodiment of the present invention. Figure 1 The embodiment of the present invention provides an analog-to-digital converter including: an input interface 10, a tracking analog-to-digital conversion module 1, an oversampling modulator 2, a digital logic combination module 3 and an output interface 20; the input interface 10 is respectively connected to the tracking analog-to-digital conversion module 1 and the oversampling modulator 2, and the input interface 10 is used to transmit an input signal V in ; Oversampling modulator 2 is used to adjust the input signal V in Generate an initial fine conversion bit stream; the tracking analog-to-digital conversion module 1 is used to convert the input signal V in quantization and generate a coarse conversion digital code K; the digital logic combination module 3 is connected between the tracking analog-to-digital conversion module 1 and the oversampling modulator 2, and the digital logic combination module 3 is used to generate a feedback digital code N according to the coarse conversion digital code K and the initial fine conversion bit stream. dac The output interface 20 is connected between the digital logic combination module 3 and the oversampling modulator 2, and the output interface 20 is used to feedback the digital code N dac Output.

[0055] Specifically, the input interface 10 may be a port for signal input. The input interface 10 is used to transmit an input signal V inThe tracking analog-to-digital conversion module 1 may include a tracking analog-to-digital converter (Tracking ADC). The tracking analog-to-digital conversion module 1 receives an input signal V in , and according to the received input signal V in Generate and output an N-bit coarse conversion digital code K.

[0056] The oversampling modulator 2 can be a Sigma-delta modulator. The oversampling modulator 2 is based on the input signal V in An initial fine conversion bit stream is generated and outputted, and the number of bits of the initial fine conversion bit stream may be a 1-bit fine conversion bit stream bs.

[0057] The digital logic combination module 3 receives the coarse conversion digital code K output by the tracking analog-to-digital conversion module 1 and the initial fine conversion bit stream output by the oversampling modulator 2, and generates and outputs the feedback digital code N dac To oversampling modulator 2.

[0058] The output interface 20 is connected to the output end of the digital logic combination module 3. The output interface 20 is used to feedback the digital code N dac Output. Feedback digital code N dac Used to convert to digital signal output.

[0059] Feedback digital code N dac The conversion is performed by the digital logic combination module 3. The feedback digital code N can be generated by using the initial fine conversion bit stream generated by the oversampling modulator 2 in the previous clock cycle and the coarse conversion digital code K output in real time by the tracking analog-to-digital conversion module 1 in the current clock cycle. dac The feedback digital code N dac It can be transmitted to the output interface 20 for generating a digital signal.

[0060] Since the conversion cycle of the coarse conversion digital code K output by the tracking analog-to-digital conversion module 1 is very short, which is only one minimum clock cycle, the digital logic combination module 3 can generate and output the feedback digital code N within one minimum clock cycle. dac The output interface 20 can select the output feedback digital code N as needed. dac frequency, thereby adjusting the frequency of the output signal of the output interface 20.

[0061] Compared with the existing zoom ADC, the conversion period of the coarse conversion stage of the ADC provided in this embodiment is a minimum clock period. The ADC provided in this embodiment can not only ensure that the conversion period of the coarse conversion stage is within a minimum period, but also has the characteristics of simple circuit structure and low complexity.

[0062] The analog-to-digital converter provided in this embodiment uses the tracking analog-to-digital conversion module 1 to generate the coarse conversion digital code K, and uses the Tracking ADC as the coarse conversion analog-to-digital conversion unit. Since the output signal of the tracking analog-to-digital conversion module 1 is available at any time, the analog-to-digital converter provided in this embodiment only needs one minimum clock cycle in the coarse conversion stage, and generates the feedback digital code N through the digital logic combination module 3. dac , the feedback digital code N dac The digital signal can be transmitted to the output interface 20 to generate a digital signal. The circuit principle is simple and effectively improves the performance and cost of the analog-to-digital converter.

[0063] Optionally, based on the above embodiment, continue to refer to Figure 1 The oversampling modulator 2 is also used to adjust the input signal V in and the feedback digital code N dac , generating an adjusted fine conversion bit stream; the adjusted bit stream is used to adjust the feedback digital code N generated by the digital logic combination module 3 dac The output interface 20 is connected between the digital logic combination module 3 and the oversampling modulator 2, and the output interface 20 is used to adjust the feedback digital code N dac Output.

[0064] Specifically, the digital logic combination module 3 receives the coarse conversion digital code K output by the tracking analog-to-digital conversion module 1 and the initial fine conversion bit stream output by the oversampling modulator 2, generates and outputs the feedback digital code N dac To the oversampling modulator 2. The sampling modulator is based on the feedback digital code N dac and input signal V in Generate an adjusted fine conversion bit stream, and feed the adjusted fine conversion bit stream back to the digital logic combination module 3 to form a loop process. The digital logic combination module 3 updates the generated feedback digital code N according to the adjusted fine conversion bit stream. dac .

[0065] The output interface 20 is connected to the output end of the digital logic combination module 3, and the output interface 20 is used to adjust the updated feedback digital code N dac Output. Feedback digital code N dac Used to convert to digital signal output.

[0066] The digital logic combination module 3 can use the adjusted fine conversion bit stream generated by the oversampling modulator 2 in the current clock cycle and the coarse conversion digital code K output by the tracking analog-to-digital conversion module 1 in the current clock cycle to generate an adjusted feedback digital code N dac The adjusted feedback digital code N dacThe digital code K can be transmitted to the output interface 20 for generating a digital signal. Since the conversion cycle of the coarse conversion digital code K output by the tracking analog-to-digital conversion module 1 is very short, which is only one minimum clock cycle, the digital logic combination module 3 can generate and output the feedback digital code N within one minimum clock cycle. dac The output interface 20 can select the output feedback digital code N as needed. dac frequency, thereby achieving the adjustment of the frequency of the output signal of the output interface 20 as needed.

[0067] Optional, Figure 2 FIG. 1 is a schematic diagram of a digital logic combination module of an analog-to-digital converter provided by an embodiment of the present invention. Figure 1 and Figure 2 The digital logic combination module 3 includes: a clock unit 31, a comparison unit 32, a first configuration unit 33, a second configuration unit 34 and an output unit 35; the clock unit 31 is connected to the comparison unit 32, and the clock unit 31 is used to generate a clock signal; the comparison unit 32 is connected to the first configuration unit 33 and the second configuration unit 34, and the output unit 35 is connected to the first configuration unit 33 and the second configuration unit 34; the comparison unit 32 is used to compare the fine conversion bit stream with a preset parameter value, and when the fine conversion bit stream is equal to the preset parameter value, the first configuration unit 33 will feedback the digital code N dac When the fine conversion bit stream is not equal to the preset parameter value, the second configuration unit 34 sets the feedback digital code N dac The output unit 35 is configured as a second parameter; the output unit 35 is used to output the first parameter and the second parameter respectively.

[0068] Figure 3 is a waveform diagram of a signal of an analog-to-digital converter provided by an embodiment of the present invention. Figures 1 to 3 The digital logic combination module 3 is specifically used for: when the rising edge of the clock signal clk arrives, judging whether the fine conversion bit stream bs is 1 through the comparison unit 32, and if the fine conversion bit stream bs=1, configuring the feedback digital code N through the first configuration unit 33 dac =K+2, and outputs the feedback digital code N through the output unit 35 dac =K+2; if the fine conversion bit stream bs=0, the feedback digital code N is configured by the second configuration unit 34 dac =K-1, and outputs the feedback digital code N through the output unit 35 dac =K-1; wherein the clock signal clk is the fastest sampling clock of the analog-to-digital converter, and its sampling period is Ts.

[0069] Specific, combined Figure 2 and Figure 3 Specifically, the first parameter may be K+2, and the second parameter may be K-1. When the rising edge of clk arrives, the digital logic combination module 3 determines whether the fine conversion bit stream bs fed back from the Sigma-delta modulator is 1. If the fine conversion bit stream bs=1, the feedback digital code N is output. dac =K+2; on the contrary, if the fine conversion bit stream bs=0, the output feedback digital code N dac =K-1.

[0070] Optional, Figure 4 FIG. 1 is a schematic diagram of a tracking analog-to-digital conversion module of an analog-to-digital converter provided by an embodiment of the present invention. Figures 1 to 4 The tracking analog-to-digital conversion module 1 includes: a first comparator 11, an up-down counter 12 and a digital-to-analog conversion array 13; the in-phase input end of the first comparator 11 is connected to the input interface 10, the inverting input end of the first comparator 11 is connected to the output end of the digital-to-analog conversion array 13, the output end of the first comparator 11 is connected to the first input end of the up-down counter 12, and the second input end of the up-down counter 12 is used to input the sampling frequency F S The first output end of the up-down counter 12 is connected to the input end of the digital-to-analog conversion array 13, and the second output end of the up-down counter 12 is connected to the digital logic combination module 3; the first comparator 11 is used to compare the input signal V in and the feedback DAC signal V generated by the digital-to-analog conversion array 13 dac The comparison is performed to generate a comparison result; the up-down counter 12 generates a rough conversion digital code K by increasing by 1 or decreasing by 1 according to the comparison result; the rough conversion digital code K is used to output to the digital logic combination module 3 and control the digital-to-analog conversion array 13 to generate the feedback DAC signal V dac .

[0071] Specifically, the input signal V in With the feedback DAC signal V dac The first comparator 11 compares the magnitudes and generates a comparison result. The comparison result is output to the input of the up / down counter 12. The up / down counter 12 increases by +1 or decreases by -1 according to the comparator result and outputs the analog-to-digital conversion result of the Tracking ADC, i.e., the coarse conversion digital code K. The coarse conversion digital code K also controls the digital-to-analog conversion array 13 of the Tracking ADC to generate the feedback DAC signal V dacThe Tracking ADC circuit outputs the coarse conversion digital code K to the digital logic combination module 3 .

[0072] Optional, Figure 5 FIG. 1 is a schematic diagram of the structure of another analog-to-digital converter provided by an embodiment of the present invention. Figure 5 The oversampling modulator 2 comprises: a loop filter 21, a second comparator 22 and a feedback DAC unit 23; the loop filter 21 is connected to the input interface 10 and the feedback DAC unit 23, and the loop filter 21 is used to generate a feedback signal according to the input signal V in The feedback DAC unit 23 outputs a feedback signal V fb The second comparator 22 is connected to the loop filter 21, and the second comparator 22 is used to compare the analog voltage V with the preset reference signal value, and output the fine conversion bit stream bs according to the comparison result; the feedback DAC unit 23 is connected to the digital logic combination module 3, and the feedback DAC unit 23 is used to feedback the digital code N according to the feedback digital code N dac Generate and output feedback signal V fb to the input interface 10; the feedback signal V fb Follows the input signal V in change.

[0073] Specifically, the feedback DAC unit 23 may include an N-bit DAC, that is, an N-bit digital-to-analog conversion unit. The input end of the loop filter 21 receives the input signal Vin and the feedback signal V output by the feedback DAC unit 23. fb The difference between the two values ​​is obtained by the feedback DAC unit 23. The feedback DAC unit 23 outputs the analog voltage V to the input of the second comparator 22 according to the difference. The input of the second comparator 22 receives the analog voltage V output by the loop filter 21, and outputs a 1-bit fine conversion bit stream bs (0 or 1) according to the positive or negative of the analog voltage V output by the loop filter 21. The output of the second comparator 22 is connected to the digital logic combination module 3. The input of the feedback DAC unit 23 receives the N-bit feedback digital code N output by the digital logic combination module 3. dac , and according to the feedback digital code N dac The numerical output feedback reference voltage V fb To the input terminal of the loop filter 21.

[0074] Optionally, based on the above embodiments, Figure 3 and Figure 5 , the feedback digital code N dac The number of bits is N bits; the number of bits of the feedback DAC unit 23 is the same as the feedback digital code N dacThe second comparator 22 is used to receive the output voltage V of the loop filter 21, and output a 1-bit fine conversion bit stream bs according to the positive or negative condition of the output voltage V of the loop filter 21; wherein the fine conversion bit stream bs is 0 or 1.

[0075] Specifically, the input signal V in It is connected to the input of the Tracking ADC and the input of the Sigma-delta modulator. The Tracking ADC only needs one cycle to output the same signal as the input signal V in The corresponding N-bit coarse conversion digital code K. The N-bit coarse conversion digital code K and the 1-bit fine conversion bit stream bs of the Sigma-delta modulator are input to the digital logic combination module 3. The digital logic combination module 3 can generate an N-bit feedback digital code N according to the N-bit coarse conversion digital code K and the 1-bit fine conversion bit stream bs. dac Acts on N-bit DAC. N-bit DAC according to the feedback digital code N dac The feedback signal V fb Follows the input signal V in The change reduces the initial quantization noise floor of the Sigma-Delta modulator and improves the conversion accuracy of the analog-to-digital converter.

[0076] Optional, Figure 6 FIG. 1 is a schematic diagram of the structure of another analog-to-digital converter provided by an embodiment of the present invention. Figure 6 , the analog-to-digital converter further includes: a digital decimation filter 4; the digital decimation filter 4 is connected to the output end of the digital logic combination module 3; the digital decimation filter 4 is used to receive the feedback digital code N dac , and the feedback digital code N dac Perform downsampling and decimation filtering to generate a digital output signal D out ; Wherein, the sampling frequency of the digital extraction filter 4 is FS.

[0077] Specifically, the digital logic combination module 3 has one input end connected to the N-bit coarse conversion digital code K and one input end connected to the 1-bit fine conversion bit stream bs, and outputs the N-bit feedback digital code Ndac to the N-bit DAC and the digital extraction filter 4. The first comparator 11 of the Tracking ADC outputs the N-bit coarse conversion digital code K in each sampling period. The second comparator 22 of the Sigma-delta modulator outputs the 1-bit fine conversion bit stream bs in each sampling period. The digital logic combination module 3 generates the N-bit feedback digital code Ndac in each clock cycle according to the N-bit coarse conversion digital code K and the 1-bit fine conversion bit stream bs. dac The digital decimation filter 4 receives the feedback digital code N dacAnd complete the downsampling extraction filtering, output the ADC digital signal D once every OSR cycle out Output.

[0078] Optionally, based on the above embodiments, Figures 1 to 6 , the feedback signal V fb The values ​​include:

[0079] V fb =(K-1)*V LSB Or, V fb =(K+2)*V LSB

[0080] Among them, V LSB is the minimum output step size of the feedback DAC unit 23, and K is the coarse conversion digital code.

[0081] Optionally, the feedback digital code N dac The coarse conversion digital code K contained in is the (n-1)th period input signal V in The corresponding quantization value, n is a positive integer; in the feedback digital code N dac Acting in the oversampling modulator 2, when the nth cycle conversion is performed, the input signal V in The following conditions are met:

[0082] K*V LSB <V in <(K+1)*V LSB

[0083]

[0084] Among them, A FS is the input signal V in The full swing, f in is the frequency of the input signal Vin, Fs is the sampling frequency, N is the number of bits of the tracking analog-to-digital conversion module 1, V refh With V refl They are respectively a high reference level and a low reference level of the analog-to-digital converter.

[0085] Specifically, when the analog-to-digital converter reaches a stable state, the input signal V in The output of the Tracking ADC is available in each cycle, which is the input signal V inThe correct quantization generates and outputs an N-bit coarse conversion digital code K. The coarse conversion digital code K and the 1-bit fine conversion bit stream bs generated by the second comparator 22 of the Sigma-delta modulator are connected to the digital logic combination module 3. The digital logic combination module 3 generates an N-bit feedback digital code N dac To N-bit DAC. Let the minimum output step size V of feedback DAC unit 23 be LSB is the minimum output step size of the N-bit DAC, then the feedback signal V fb The possible values ​​are: V fb =(K-1)*V LSB Or, V fb =(K+2)*V LSB .

[0086] Feedback signal V fb The two values ​​of correspond to the high reference voltage and low reference voltage of the Sigma-delta modulator in the traditional structure. The N-bit DAC makes the input signal V in With the feedback signal V fb The difference is reduced, which is equivalent to reducing the quantization error of the Sigma-delta modulator. Compared with the traditional Sigma-delta modulator of the same specification, the conversion accuracy is effectively improved. At the same time, considering the conversion error that may be generated by the Tracking ADC, combination redundancy can be added to the digital logic combination module 3 to improve the stability of the entire analog-to-digital converter.

[0087] Among them, the feedback digital code N dac The digital code K contained in is the (n-1)th period input signal V in The corresponding quantized value, therefore, in the feedback digital code N dac In the Sigma-delta modulator, when performing the conversion of the nth cycle, in order to ensure that the loop filter 21 does not overload, the input signal V in Meet the following conditions: K*V LSB <V in <(K+1)*V LSB .

[0088] This requires the input signal V in The change in one clock cycle is less than 1 V of an N-bit DAC. LSB , from which the input signal V can be calculated in The conditions that need to be met are: Among them, A FS is the full swing of the input signal, f in is the input signal frequency, Fs is the sampling frequency, and N is the number of bits of the Tracking ADC. refh With Vrefl They are the high reference level and low reference level of the analog-to-digital converter respectively.

[0089] Since the up / down counter 12 of the Tracking ADC can only complete the operation of up +1 or down -1 in each clock cycle, when the input signal V in The change in one clock cycle exceeds the minimum output step size V of the feedback DAC unit 23. LSB At this time, the counter output result can no longer correctly represent the input signal V in , making the Tracking ADC unable to work properly. Therefore, the input signal V in The overall Zoom ADC architecture is limited by the input signal V in Therefore, in the Zoom ADC system architecture of the analog-to-digital converter provided by the present application, the Tracking ADC is not limited by speed and can efficiently complete the analog-to-digital conversion in each clock cycle.

[0090] Figure 7 is a feedback voltage V of an analog-to-digital converter provided in an embodiment of the present invention fb The time domain diagram of Figure 7 As shown in the figure, the blue dotted line K represents the coarse conversion digital code completed by the Tracking ADC. refh and V refl They are the feedback signals V fb The gray waveform represents the feedback signal V of the feedback DAC. fb The distribution of Figure 7 It can be seen intuitively that at this time the input signal V in With the feedback signal V fb The quantization error caused by the difference is greatly reduced, and considering the possible conversion error of the Tracking ADC, redundancy is added to the digital logic combination module 3 to ensure the stable operation of the Sigma-delta modulator. The analog-to-digital converter provided in this embodiment is a tracking high-precision analog-to-digital converter.

[0091] Figure 8 This is a result diagram comparing the signal to quantization noise ratio of an analog-to-digital converter provided by an embodiment of the present invention and a traditional first-order Sigma-delta modulator with different quantization bits. Figure 8, the pink broken line represents 1-b SDM, which is a traditional first-order Sigma-delta modulator with a quantization bit of 1 bit. The green broken line represents 2-b SDM, which is a traditional first-order Sigma-delta modulator with a quantization bit of 2 bits. The blue broken line represents 3-b SDM, which is a traditional first-order Sigma-delta modulator with a quantization bit of 3 bits. The red broken line represents the 5-b TADC + first-order 1-b SDM of the present application, which is the quantization bit of the analog-to-digital converter provided by the present application, a 5-bit Tracking ADC and a 1-bit Sigma-delta modulator.

[0092] Depend on Figure 8 It can be seen that the signal-to-quantization noise (SQNR) ratio of the traditional first-order Sigma-delta modulator will increase with the increase of the number of quantization bits. Among them, the multi-bit quantized Sigma-delta modulator often involves the design of multiple comparators, resulting in a large overhead in area and power consumption. In general, 3-bit quantization is already a large value, and its SQNR is still lower than the result of the analog-to-digital converter implemented by the 5-bit Tracking ADC proposed in the present application.

[0093] Fig. 9 1 is a graph comparing the number of comparators required by an analog-to-digital converter provided by an embodiment of the present invention and a conventional first-order Sigma-delta modulator with different quantization bit numbers. Fig. 9 Taking the comparator of the Flash ADC structure as an example, the comparators required for the multi-bit quantized Sigma-delta modulator grow exponentially. Seven comparators are required for 3-bit quantization. In contrast, the analog-to-digital converter proposed in this application only requires two comparators, which greatly reduces the area and power consumption.

[0094] This embodiment provides an analog-to-digital conversion chip. The analog-to-digital conversion chip provided by this embodiment includes the analog-to-digital converter provided by any of the above embodiments, and has the beneficial effects of the analog-to-digital converter provided by any of the above embodiments, which will not be described in detail here.

[0095] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. An analog-to-digital converter, characterized in that: include: Input interface, tracking analog-to-digital conversion module, oversampling modulator, digital logic combination module and output interface; The input interface is connected to the tracking analog-to-digital conversion module and the oversampling modulator respectively, and the input interface is used to transmit an input signal; the oversampling modulator is used to generate an initial fine conversion bit stream according to the input signal; the tracking analog-to-digital conversion module is used to quantize the input signal and generate a coarse conversion digital code; The digital logic combination module is connected between the tracking analog-to-digital conversion module and the oversampling modulator, and the digital logic combination module is used to generate a feedback digital code according to the coarse conversion digital code and the initial fine conversion bit stream; The output interface is connected between the digital logic combination module and the oversampling modulator, and the output interface is used to output the feedback digital code.

2. The analog-to-digital converter according to claim 1, characterized in that: The oversampling modulator is further used to generate an adjusted fine conversion bit stream according to the input signal and the feedback digital code; the adjusted bit stream is used to adjust the feedback digital code generated by the digital logic combination module; The output interface is connected between the digital logic combination module and the oversampling modulator, and the output interface is used to output the adjusted feedback digital code.

3. The analog-to-digital converter according to claim 1, characterized in that: The digital logic combination module comprises: A clock unit, a comparison unit, a first configuration unit, a second configuration unit and an output unit; The clock unit is connected to the comparison unit, and the clock unit is used to generate a clock signal; The comparison unit is connected to the first configuration unit and the second configuration unit, and the output unit is connected to the first configuration unit and the second configuration unit; the comparison unit is used to compare the fine conversion bit stream with a preset parameter value, and when the fine conversion bit stream is equal to the preset parameter value, the first configuration unit configures the feedback digital code as a first parameter; when the fine conversion bit stream is not equal to the preset parameter value, the second configuration unit configures the feedback digital code as a second parameter; the output unit is used to output the first parameter and the second parameter respectively; The digital logic combination module is specifically used for: When the rising edge of the clock signal arrives, the comparison unit is used to determine whether the fine conversion bit stream is 1. If the fine conversion bit stream = 1, the feedback digital code = K+2 is configured through the first configuration unit, and the feedback digital code = K+2 is output through the output unit; if the fine conversion bit stream = 0, the feedback digital code = K-1 is configured through the second configuration unit, and the feedback digital code = K-1 is output through the output unit; wherein the clock signal is the fastest sampling clock of the analog-to-digital converter.

4. The analog-to-digital converter according to claim 1, characterized in that: The tracking analog-to-digital conversion module comprises: a first comparator, an up-down counter and a digital-to-analog conversion array; The non-inverting input terminal of the first comparator is connected to the input interface, the inverting input terminal of the first comparator is connected to the output terminal of the digital-to-analog conversion array, the output terminal of the first comparator is connected to the first input terminal of the up-down counter, the second input terminal of the up-down counter is used to input the sampling frequency FS, the first output terminal of the up-down counter is connected to the input terminal of the digital-to-analog conversion array, and the second output terminal of the up-down counter is connected to the digital logic combination module; The first comparator is used to compare the input signal with the feedback DAC signal generated by the digital-to-analog conversion array to generate a comparison result; The up-down counter generates a coarse conversion digital code by increasing by +1 or decreasing by -1 according to the comparison result; the coarse conversion digital code is used to output to the digital logic combination module and control the digital-to-analog conversion array to generate the feedback DAC signal.

5. The analog-to-digital converter according to claim 1, characterized in that: The oversampling modulator comprises: A loop filter, a second comparator and a feedback DAC unit; the loop filter is connected to the input interface and the feedback DAC unit, and the loop filter is used to output a corresponding analog voltage according to the difference between the input signal and the feedback signal output by the feedback DAC unit; The second comparator is connected to the loop filter, and is used to compare the analog voltage with a preset reference signal value, and output the fine conversion bit stream according to the comparison result; The feedback DAC unit is connected to the digital logic combination module, and the feedback DAC unit is used to generate and output a feedback signal to the input interface according to the feedback digital code; the feedback signal changes with the input signal.

6. The analog-to-digital converter according to claim 5, characterized in that: The number of bits of the feedback digital code is N bits; The number of bits of the feedback DAC unit matches the number of bits of the feedback digital code; The second comparator is used to receive the output voltage of the loop filter and output a 1-bit fine conversion bit stream according to the positive or negative condition of the output voltage of the loop filter; wherein the fine conversion bit stream is 0 or 1.

7. The analog-to-digital converter according to claim 6, characterized in that: The feedback signal V fb The values ​​include: V fb =(K-1)*V LSB Or, V fb =(K+2)*V LSB Among them, V LSB is the minimum output step size of the feedback DAC unit, and K is the coarse conversion digital code.

8. The analog-to-digital converter according to claim 1, characterized in that: The coarse conversion digital code included in the feedback digital code is a quantization value corresponding to the (n-1)th period input signal, where n is a positive integer; when the feedback digital code acts on the oversampling modulator to perform the conversion of the nth period, the input signal satisfies the following conditions: K*V LSB <V in <(K+1)*V LSB Among them, A FS is the input signal V in The full swing, f in is the input signal V in frequency, Fs is the sampling frequency, N is the number of bits of the tracking analog-to-digital conversion module, V refh With V refl They are respectively a high reference level and a low reference level of the analog-to-digital converter.

9. The analog-to-digital converter according to claim 1, characterized in that: Also includes: Digital decimation filter; The digital extraction filter is connected to the output end of the digital logic combination module; The digital decimation filter is used to receive the feedback digital code and perform downsampling, decimation and filtering on the feedback digital code to generate a digital output signal; wherein the sampling frequency of the digital decimation filter is F S .

10. An analog-to-digital conversion chip, characterized in that: include: An analog-to-digital converter as claimed in any one of claims 1 to 9.

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