Device and method for detecting performance of RFID chip after salient point processing technology

Abstract

The invention relates to the technical field of RFID chip detection, in particular to a device and method for detecting the performance of an RFID chip after a salient point machining process, and the device comprises an upper computer, an RFID reader, a medium structure array and a motion control system, the plurality of dielectric structures are mounted on the base, and each dielectric structure comprises a microstrip antenna arranged on the outer surface of the dielectric structure; the motion control system comprises a mechanical arm and a driving device, the mechanical arm is used for moving the dielectric structure array, and the driving device is used for moving the dielectric structure relative to the base. And the production cost caused by poor factory leaving of the chip is greatly reduced.

Description

Technical Field

[0001] The present invention relates to the field of RFID chip detection, and in particular to a device and method for detecting the performance of an RFID chip after a bump processing process. Background Art

[0002] In the existing RFID chip production process, the electrical performance test of the chip is mainly carried out through wafer probing (Chip Probing-CP) in the wafer manufacturing stage to confirm the electrical performance of the chip during the manufacturing process. For the packaging stage, after the bump process, optical imaging and other methods are mainly used to check the physical structure changes caused by the bump processing process to the chip, and the chip production yield is confirmed by the change of the physical structure and tolerance control. For mature design solutions and processes, this detection method is highly efficient and cost-controllable, but for exploratory design solutions and process detail optimization stages, due to the high temperature and other environments experienced during the bump processing process, and the process itself is not optimized enough, the chip after packaging may have poor function problems. However, there is currently no method for detecting the electrical performance of the chip after the bump process, and bad chips can only be found during the subsequent product-level packaging verification. At that time, the bad product elimination process will lead to an increase in materials, time, and costs, resulting in a large waste of materials and time. Summary of the invention

[0003] In order to solve the problems in the related art, the present disclosure provides a device and method for detecting the performance of an RFID chip after a bump processing process.

[0004] In a first aspect, an embodiment of the present disclosure provides a device for detecting the performance of an RFID chip after a bump processing process, which is used to detect multiple RFID chips on a wafer to be tested, and is characterized in that it includes: a host computer, an RFID reader, a medium structure array, and a motion control system, wherein:

[0005] The dielectric structure array includes a base and a plurality of dielectric structures, the plurality of dielectric structures are mounted on the base, and the dielectric structure includes a microstrip antenna arranged on an outer surface of the dielectric structure;

[0006] The motion control system includes a mechanical arm and a drive device, the mechanical arm is used to move the medium structure array, and the drive device is used to move the medium structure relative to the base;

[0007] The host computer is used to perform the following operations:

[0008] S1: Control the mechanical arm to move the dielectric structure array and / or control the driving device to move a specified dielectric structure, so that the microstrip antenna of the specified dielectric structure is connected to the bump on the specified RFID chip on the wafer to be tested to form a tag antenna of the specified RFID chip;

[0009] S2: Control the RFID reader to communicate with the designated RFID chip via the tag antenna of the designated RFID chip, obtain designated information from the designated RFID chip, and send the designated information to the host computer;

[0010] S3: Determine whether the area where the designated RFID chip is located is a bad area according to the designated information;

[0011] Among them, when the bad area includes multiple RFID chips, the host computer iteratively performs operations S1-S3 for the bad area, narrows the scope of the bad area by reducing the number of medium structures connected to the RFID chip, until the bad area contains only one RFID chip, and the RFID chip is determined as a bad chip.

[0012] According to an embodiment of the present disclosure, when the wafer to be tested is initially tested, the host computer controls the motion control system so that the microstrip antennas of all dielectric structures in the dielectric structure array are connected to the corresponding RFID chips, and moves the dielectric structure array to traverse the entire wafer to be tested, thereby determining one or more defective areas.

[0013] According to an embodiment of the present disclosure, reducing the range of the bad area by reducing the number of medium structures connected to the RFID chip includes:

[0014] Dividing the bad area into a first sub-area and a second sub-area;

[0015] Connecting a dielectric structure corresponding to the number of RFID chips in the first sub-area to the RFID chips in the first sub-area, thereby determining whether the first sub-area is a bad area;

[0016] A medium structure corresponding to the number of RFID chips in the second sub-area is connected to the RFID chips in the second sub-area, thereby determining whether the second sub-area is a bad area.

[0017] According to an embodiment of the present disclosure, the first sub-area and the second sub-area have the same number of RFID chips.

[0018] According to an embodiment of the present disclosure, the designated information includes: RFID chip TID and / or carrier signal waveform.

[0019] According to an embodiment of the present disclosure, the medium structure has any one or more of the following shapes: a cuboid, a cube, a cylinder, a sphere, an ellipsoid;

[0020] The microstrip antenna is arranged on the bottom surface and the side surface of the dielectric structure;

[0021] The microstrip antenna comprises a first section and a second section disconnected from each other on the bottom surface of the dielectric structure;

[0022] The first section and the second section respectively extend longitudinally upward along the side surface of the dielectric structure and are bent to form an inductor coil structure for matching the capacitive impedance of the RFID chip.

[0023] According to an embodiment of the present disclosure, the width W of the first section and the second section of the microstrip antenna is: 0.2 mm ≤ W ≤ 2 mm;

[0024] The spacing between the first section and the second section on the bottom surface is 10 μm to 30 μm smaller than the spacing between bumps of the RFID chip;

[0025] The first section and the second section are bent at a position 3 mm to 10 mm away from the top surface of the dielectric structure at the side surface.

[0026] According to an embodiment of the present disclosure, the first section and the second section are respectively connected to a metal patch structure to form a radiation dipole arm structure, thereby forming a wide-band tag antenna.

[0027] According to an embodiment of the present disclosure, the material of the microstrip antenna includes any one or more of the following: copper, aluminum, silver paste, and conductive ink.

[0028] According to an embodiment of the present disclosure, the microstrip antenna is any one or more of the following antennas with an operating frequency band covering 920 MHz to 925 MHz: a phased array antenna, a horn antenna, and a waveguide antenna.

[0029] According to an embodiment of the present disclosure, the material of the medium structure includes any one or more of the following: glass, ceramic, and fiberglass reinforced plastic.

[0030] According to an embodiment of the present disclosure, a method for detecting the performance of an RFID chip after a bump processing process is provided, which is used to perform performance detection on multiple RFID chips on a wafer to be tested using a device for detecting the performance of an RFID chip after a bump processing process, wherein the device for detecting the performance of an RFID chip comprises: a host computer, an RFID reader, a medium structure array, and a motion control system, wherein:

[0031] The dielectric structure array includes a base and a plurality of dielectric structures, the plurality of dielectric structures are mounted on the base, and the dielectric structure includes a microstrip antenna arranged on an outer surface of the dielectric structure;

[0032] The motion control system includes a mechanical arm and a drive device, the mechanical arm is used to move the medium structure array, and the drive device is used to move the medium structure relative to the base;

[0033] The method comprises performing the following operations by the host computer:

[0034] S1: Control the mechanical arm to move the dielectric structure array and / or control the driving device to move a specified dielectric structure, so that the microstrip antenna of the specified dielectric structure is connected to the bump on the specified RFID chip on the wafer to be tested to form a tag antenna of the specified RFID chip;

[0035] S2: Control the RFID reader to communicate with the designated RFID chip via the tag antenna of the designated RFID chip, obtain designated information from the designated RFID chip, and send the designated information to the host computer;

[0036] S3: Determine whether the area where the designated RFID chip is located is a bad area according to the designated information;

[0037] Among them, when the bad area includes multiple RFID chips, the host computer iteratively performs operations S1-S3 for the bad area, narrows the scope of the bad area by reducing the number of medium structures connected to the RFID chip, until the bad area contains only one RFID chip, and the RFID chip is determined as a bad chip.

[0038] According to an embodiment of the present disclosure, when the wafer to be tested is initially tested, the host computer controls the motion control system so that the microstrip antennas of all dielectric structures in the dielectric structure array are connected to the corresponding RFID chips, and moves the dielectric structure array to traverse the entire wafer to be tested, thereby determining one or more defective areas.

[0039] According to an embodiment of the present disclosure, reducing the range of the bad area by reducing the number of medium structures connected to the RFID chip includes:

[0040] Dividing the bad area into a first sub-area and a second sub-area;

[0041] Connecting a dielectric structure corresponding to the number of RFID chips in the first sub-area to the RFID chips in the first sub-area, thereby determining whether the first sub-area is a bad area;

[0042] A medium structure corresponding to the number of RFID chips in the second sub-area is connected to the RFID chips in the second sub-area, thereby determining whether the second sub-area is a bad area.

[0043] According to an embodiment of the present disclosure, the first sub-area and the second sub-area have the same number of RFID chips.

[0044] According to an embodiment of the present disclosure, the designated information includes: RFID chip TID and / or carrier signal waveform.

[0045] According to an embodiment of the present disclosure, the medium structure has any one or more of the following shapes: a cuboid, a cube, a cylinder, a sphere, an ellipsoid;

[0046] The microstrip antenna is arranged on the bottom surface and the side surface of the dielectric structure;

[0047] The microstrip antenna includes a first section and a second section disconnected from each other on the bottom surface of the dielectric structure;

[0048] The first section and the second section respectively extend longitudinally upward along the side surface of the dielectric structure and are bent to form an inductor coil structure for matching the capacitive impedance of the RFID chip.

[0049] According to an embodiment of the present disclosure, the width W of the first segment and the second segment of the microstrip antenna is: 0.2 mm ≤ W ≤ 2 mm;

[0050] The spacing between the first section and the second section on the bottom surface is 10 μm to 30 μm smaller than the spacing between bumps of the RFID chip;

[0051] The first section and the second section are bent at a position 3 mm to 10 mm away from the top surface of the dielectric structure at the side surface.

[0052] According to an embodiment of the present disclosure, the first section and the second section are respectively connected to a metal patch structure to form a radiation dipole arm structure, thereby forming a wide-band tag antenna.

[0053] According to an embodiment of the present disclosure, the material of the microstrip antenna includes any one or more of the following: copper, aluminum, silver paste, and conductive ink.

[0054] According to an embodiment of the present disclosure, the microstrip antenna is any one or more of the following antennas with an operating frequency band covering 920 MHz to 925 MHz: a phased array antenna, a horn antenna, and a waveguide antenna.

[0055] According to an embodiment of the present disclosure, the material of the medium structure includes any one or more of the following: glass, ceramic, and fiberglass reinforced plastic.

[0056] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0057] The present invention controls the medium structure to adjust the position through a mechanical arm to connect the miniaturized microstrip antenna port with the radio frequency pin of the RFID wafer chip after the long bump, and uses an RFID reader with an external antenna to simultaneously verify the electrical performance of multiple RFID chips connected to the microstrip antenna, thereby realizing the detection of faults such as TID jump, protocol consistency, and abnormal communication function. The present invention can realize non-destructive, rapid, and low-cost electrical performance detection of RFID chips after the bump process, and simultaneously detect electrical performance defects of multiple RFID chips on the wafer, which complements the physical detection of existing equipment and greatly reduces the production cost caused by defective chips leaving the factory. At the same time, the present invention does not apply local high pressure to the wafer bump, which is different from the current detection method on the market where the probe is close to the wafer structure and easily causes physical damage to the wafer, thus protecting the integrity of the chip structure and reducing the possibility of physical damage to the wafer by the detection equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 The overall schematic diagram of the RFID chip performance detection device after the bump processing process according to the embodiment of the present disclosure is shown;

[0059] Figure 2 A schematic diagram of a dielectric structure array of an RFID chip performance detection device after a bump processing process according to an embodiment of the present disclosure is shown. ;

[0060] Figure 3 A schematic diagram of the medium structure of the RFID chip performance detection device after the bump processing process according to an embodiment of the present disclosure is shown;

[0061] Figure 4 A schematic diagram showing determining one or more bad areas when performing an initial test on a wafer to be tested according to an embodiment of the present disclosure;

[0062] Figure 5 A flow chart is shown for gradually narrowing the scope of a bad area until a bad chip is determined according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0063] Hereinafter, the technical solutions in the embodiments of the present disclosure will be described clearly and completely in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0064] In the present disclosure, it should be understood that terms such as "include" or "have" are intended to indicate the presence of features, numbers, steps, behaviors, components, parts, or a combination thereof disclosed in the present specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, behaviors, components, parts, or a combination thereof exist or are added.

[0065] It should also be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0066] As mentioned above, in the existing RFID chip production process, the electrical performance test of the chip is mainly carried out through wafer testing (ChipProbing-CP) in the wafer manufacturing stage to confirm the electrical performance of the chip during the manufacturing process. For the packaging stage, after the bump process, optical imaging and other methods are mainly used to check the physical structure changes caused by the bump processing process to the chip, and the chip production yield is confirmed by the change of the physical structure and tolerance control. For mature design schemes and processes, this detection method is highly efficient and cost-controllable, but for exploratory design schemes and process detail optimization stages, due to the high temperature and other environments experienced during the bump processing process, and the process itself is not optimized enough, the packaged chip may have poor function problems. However, there is currently no method for detecting the electrical performance of the chip after the bump process, and the bad chips can only be found during the subsequent product-level packaging verification. At that time, the bad product elimination process will lead to an increase in materials, time, and costs, resulting in a large waste of materials and time.

[0067] In order to solve the above technical problems, the present invention discloses a device and method for detecting the performance of an RFID chip after a bump processing process. The device and method for detecting the performance of an RFID chip after a bump processing process include: a host computer, an RFID reader, a medium structure array, and a motion control system, wherein:

[0068] The dielectric structure array includes a base and a plurality of dielectric structures, the plurality of dielectric structures are mounted on the base, and the dielectric structure includes a microstrip antenna arranged on an outer surface of the dielectric structure;

[0069] The motion control system includes a mechanical arm and a drive device, the mechanical arm is used to move the medium structure array, and the drive device is used to move the medium structure relative to the base;

[0070] The host computer is used to perform the following operations:

[0071] S1: Control the mechanical arm to move the dielectric structure array and / or control the driving device to move a specified dielectric structure, so that the microstrip antenna of the specified dielectric structure is connected to the bump on the specified RFID chip on the wafer to be tested to form a tag antenna of the specified RFID chip;

[0072] S2: Control the RFID reader to communicate with the designated RFID chip via the tag antenna of the designated RFID chip, obtain designated information from the designated RFID chip, and send the designated information to the host computer;

[0073] S3: Determine whether the area where the designated RFID chip is located is a bad area according to the designated information;

[0074] Among them, when the bad area includes multiple RFID chips, the host computer iteratively performs operations S1-S3 for the bad area, narrows the scope of the bad area by reducing the number of medium structures connected to the RFID chip, until the bad area contains only one RFID chip, and the RFID chip is determined as a bad chip.

[0075] The present invention controls the medium structure to adjust the position by a mechanical arm to connect the miniaturized microstrip antenna port with the radio frequency pin of the RFID wafer chip after the long bump, and uses the reader of the external antenna to verify the electrical performance of multiple RFID chips connected to the microstrip antenna at the same time, so as to detect faults such as TID jump, protocol consistency, and abnormal communication function. The present invention can realize non-destructive, fast, and low-cost electrical performance detection of RFID chips after the bump process, and simultaneously detect electrical performance defects of multiple RFID chips on the wafer, which complements the physical detection of existing equipment and greatly reduces the production cost caused by defective chips leaving the factory. At the same time, the present invention does not apply local high pressure to the wafer bump, which is different from the current detection method on the market where the probe is close to the wafer structure and easily causes physical damage to the wafer, protecting the integrity of the chip structure and reducing the possibility of physical damage to the wafer by the detection equipment.

[0076] Reference below Figure 1-Figure 3 The device and method for detecting the performance of an RFID chip after a bump processing process according to an embodiment of the present disclosure are specifically described.

[0077] like Figure 1 As shown, the device for detecting the performance of an RFID chip after a bump processing process according to an embodiment of the present disclosure includes: a host computer, an RFID reader, a medium structure array, and a motion control system.

[0078] like Figure 2 As shown, the dielectric structure array includes a base and a plurality of dielectric structures, and the plurality of dielectric structures are mounted on the base.

[0079] like Figure 3 As shown, the dielectric structure includes a microstrip antenna disposed on the outer surface of the dielectric structure. According to an embodiment of the present disclosure, the dielectric structure has any one or more of the following shapes: a cuboid, a cube, a cylinder, a sphere, an ellipsoid, and the material of the dielectric structure includes any one or more of the following: glass, ceramic, and fiberglass.

[0080] like Figure 3 As shown, according to an embodiment of the present disclosure, the microstrip antenna is arranged on the bottom and side surfaces of the dielectric structure; the microstrip antenna includes a first section and a second section disconnected from each other on the bottom surface of the dielectric structure; the first section and the second section respectively ascend longitudinally along the side surface of the dielectric structure and bend to form an inductive coil structure for matching the capacitive impedance of the RFID chip.

[0081] According to an embodiment of the present disclosure, the microstrip antenna includes a first section and a second section disconnected from each other on the bottom surface of the dielectric structure; the first section and the second section respectively ascend longitudinally along the side surface of the dielectric structure and bend to form an inductive coil structure for matching the capacitive impedance of the RFID chip.

[0082] According to an embodiment of the present disclosure, the width W of the first segment and the second segment of the microstrip antenna is: 0.2mm≤W≤2mm; the spacing between the first segment and the second segment on the bottom surface is 10μm to 30μm smaller than the spacing between the bumps of the RFID chip; the first segment and the second segment are bent on the side surface at a distance of 3mm to 10mm from the top surface of the dielectric structure.

[0083] like Figure 3 As shown, the first section and the second section are respectively connected to the metal patch structure to form a radiation dipole arm structure, thereby forming a wide-band tag antenna.

[0084] According to an embodiment of the present disclosure, the material of the microstrip antenna includes any one or more of the following: copper, aluminum, silver paste, and conductive ink.

[0085] According to an embodiment of the present disclosure, the microstrip antenna is any one or more of the following antennas with an operating frequency band covering 920 MHz to 925 MHz: a phased array antenna, a horn antenna, and a waveguide antenna.

[0086] According to an embodiment of the present disclosure, the motion control system includes a mechanical arm and a driving device, wherein the mechanical arm is used to move the medium structure array as a whole, and the driving device is used to move the medium structure relative to the base. Figure 2 As shown, the driving device can drive one or multiple dielectric structures to move perpendicularly to the base. When testing, the motion control system can move the dielectric structure array so that the dielectric structure is aligned with the bumps to be connected, and then the driving device drives the dielectric structure corresponding to the bumps to be connected to make it contact with the bumps and achieve electrical connection.

[0087] According to an embodiment of the present disclosure, the host computer is used to perform the following operations:

[0088] S1: Control the mechanical arm to move the dielectric structure array and / or control the driving device to move a specified dielectric structure, so that the microstrip antenna of the specified dielectric structure is connected to the bump on the specified RFID chip on the wafer to be tested to form a tag antenna of the specified RFID chip;

[0089] S2: Control the RFID reader to communicate with the designated RFID chip via the tag antenna of the designated RFID chip, obtain designated information from the designated RFID chip, and send the designated information to the host computer;

[0090] S3: Determine whether the area where the designated RFID chip is located is a bad area according to the designated information;

[0091] Among them, when the bad area includes multiple RFID chips, the host computer iteratively performs operations S1-S3 for the bad area, narrows the scope of the bad area by reducing the number of medium structures connected to the RFID chip, until the bad area contains only one RFID chip, and the RFID chip is determined as a bad chip.

[0092] According to an embodiment of the present disclosure, when the wafer to be tested is initially tested, the host computer controls the motion control system so that the microstrip antennas of all dielectric structures in the dielectric structure array are connected to the corresponding RFID chips, and moves the dielectric structure array to traverse the entire wafer to be tested, thereby determining one or more defective areas.

[0093] like Figure 4 As shown, the dielectric structure array includes M*N structure arrays, that is, it includes N rows, each row has M dielectric structures, so when the microstrip antennas of all dielectric structures in the dielectric structure array are connected to the bumps of the corresponding RFID chip, M*N tag antennas can be formed at the same time. The wafer to be tested includes N*n rows, each row has M*m RFID chips, which can be divided into m*n areas, each area includes M*N RFID chips. Move the dielectric structure array to align it with one area at a time and connect each dielectric structure array to the bumps of the M*N chips to form a tag antenna. Figure 4 This is a schematic diagram of a 2*2 medium structure array according to an embodiment of the present disclosure.

[0094] The RFID reader obtains the designated information of the corresponding RFID chip through the tag antenna of the M*N RFID chips. According to an embodiment of the present disclosure, the designated information includes the TID and / or carrier signal waveform of the RFID chip to detect faults such as TID jump, protocol consistency, and communication function abnormality. When the designated information received from any area is abnormal, the area is determined as a bad area.

[0095] After determining the bad area, if the bad area includes multiple RFID chips, the host computer iteratively performs operations S1-S3 for the bad area, narrowing the scope of the bad area by reducing the number of medium structures connected to the RFID chip, until the bad area contains only one RFID chip, and the RFID chip is determined as a bad chip.

[0096] According to an embodiment of the present disclosure, reducing the range of the bad area by reducing the number of dielectric structures connected to the RFID chip includes: dividing the bad area into a first sub-area and a second sub-area; connecting dielectric structures corresponding to the number of RFID chips in the first sub-area to the RFID chips in the first sub-area, thereby determining whether the first sub-area is a bad area; connecting dielectric structures corresponding to the number of RFID chips in the second sub-area to the RFID chips in the second sub-area, thereby determining whether the second sub-area is a bad area. According to an embodiment of the present disclosure, the first sub-area and the second sub-area have the same number of RFID chips.

[0097] like Figure 5 As shown, the bad area is first divided into two sub-areas and tested separately. If any of the sub-areas is a bad area, the sub-area is further divided into two sub-areas and tested separately... and so on, until the sub-area determined to be a bad area includes only one chip, then the chip is a bad chip.

[0098] According to the embodiment of the present disclosure, after a bad area is determined in the initial test, the scope of the bad area can be gradually reduced in the above manner until all bad chips in the bad area are determined, and then the next area is moved to test. For example, assuming that the wafer is divided into m*n areas, each area includes M*N RFID chips, the area of ​​the first row and the first column can be tested first. If the area is a bad area, the scope of the bad area is gradually reduced until all bad chips in the bad area are determined, and then the area of ​​the first row and the second column is tested, and so on. The existing chip detection process often divides the wafer into functional detection areas, adds metal structures between chips, does not directly connect the welding points to the chip to complete the electrical connection, and uses the probe and the functional detection area to indirectly connect electrically, and uses an external device to test the chip electrical performance. This method may cause the chip processing technology to change and the defect increase due to the addition of the detection area structure between the wafer chips. The present disclosure does not change the original wafer production process and process, and all detection processes are completely independent, which prevents the problem of chip processing technology change and defect increase due to the addition of the detection area structure between the wafer chips. It is simple and easy to implement, and is easy to promote and apply in the industry.

[0099] Existing chip detection often uses a combination of probes and high-frequency readers and writers. Due to the size limitations of the chip and probe structure, using a probe structure to detect the wafer may cause local damage to the chip welding points due to the concentrated pressure of the probe on the wafer welding points, thereby affecting the detection accuracy and easily causing physical damage to the wafer. The present invention uses a microstrip antenna on the surface of a dielectric structure to electrically connect the chip welding points after the bump process, and together with the RFID chip, forms a tag. The tag is performance tested and verified by an external antenna connected to the dielectric structure and an RFID reader and writer, so as to achieve poor detection and screening of faulty chips such as TID jumps, protocol consistency, and abnormal communication functions. There is no local high-pressure force on the wafer bumps, which makes it easier to protect the integrity of the chip structure, and achieves non-destructive, fast, and low-cost electrical performance detection of ultra-high frequency wafer chips after the bump process, greatly reducing the production cost caused by defective chips leaving the factory.

[0100] The above is only a preferred specific implementation of the present disclosure; however, the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical solutions and improved concepts of the present disclosure within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A device for detecting the performance of RFID chips after bump processing, used for detecting multiple RFID chips on a wafer to be tested, characterized in that: include: Host computer, RFID reader, medium structure array, motion control system, including: The dielectric structure array includes a base and a plurality of dielectric structures, the plurality of dielectric structures are mounted on the base, and the dielectric structure includes a microstrip antenna arranged on an outer surface of the dielectric structure; The motion control system includes a mechanical arm and a drive device, the mechanical arm is used to move the medium structure array, and the drive device is used to move the medium structure relative to the base; The host computer is used to perform the following operations: S1: Control the mechanical arm to move the dielectric structure array and / or control the driving device to move a specified dielectric structure, so that the microstrip antenna of the specified dielectric structure is connected to the bump on the specified RFID chip on the wafer to be tested to form a tag antenna of the specified RFID chip; S2: Control the RFID reader to communicate with the designated RFID chip via the tag antenna of the designated RFID chip, obtain designated information from the designated RFID chip, and send the designated information to the host computer; S3: Determine whether the area where the designated RFID chip is located is a bad area according to the designated information; Among them, when the bad area includes multiple RFID chips, the host computer iteratively performs operations S1-S3 for the bad area, narrows the scope of the bad area by reducing the number of medium structures connected to the RFID chip, until the bad area contains only one RFID chip, and the RFID chip is determined as a bad chip.

2. The device according to claim 1, wherein: When the wafer to be tested is tested for the first time, the host computer controls the motion control system so that the microstrip antennas of all dielectric structures in the dielectric structure array are connected to the corresponding RFID chips, and moves the dielectric structure array to traverse the entire wafer to be tested, thereby determining one or more defective areas.

3. The device according to claim 1, wherein: The method of reducing the scope of the bad area by reducing the number of medium structures connected to the RFID chip includes: Dividing the bad area into a first sub-area and a second sub-area; Connecting a dielectric structure corresponding to the number of RFID chips in the first sub-area to the RFID chips in the first sub-area, thereby determining whether the first sub-area is a bad area; A medium structure corresponding to the number of RFID chips in the second sub-area is connected to the RFID chips in the second sub-area, thereby determining whether the second sub-area is a bad area.

4. The device according to claim 3, wherein: The first sub-area and the second sub-area have the same number of RFID chips.

5. The device according to claim 1, wherein: The specified information includes: RFID chip TID and / or carrier signal waveform.

6. The device according to claim 1, characterized in that: The medium structure has any one or more of the following shapes: cuboid, cube, cylinder, sphere, ellipsoid; The microstrip antenna is arranged on the bottom surface and the side surface of the dielectric structure; The microstrip antenna includes a first section and a second section disconnected from each other on the bottom surface of the dielectric structure; The first section and the second section respectively extend longitudinally upward along the side surface of the dielectric structure and are bent to form an inductor coil structure for matching the capacitive impedance of the RFID chip.

7. The device according to claim 6, characterized in that: The width W of the first section and the second section of the microstrip antenna is: 0.2 mm ≤ W ≤ 2 mm; The spacing between the first section and the second section on the bottom surface is 10 μm to 30 μm smaller than the spacing between bumps of the RFID chip; The first section and the second section are bent at a position 3 mm to 10 mm away from the top surface of the dielectric structure at the side surface.

8. The device according to claim 7, characterized in that The first section and the second section are respectively connected to the metal patch structure to form a radiation dipole arm structure, thereby forming a wide-band tag antenna.

9. The device according to claim 1, characterized in that: The material of the microstrip antenna includes any one or more of the following: copper, aluminum, silver paste, and conductive ink.

10. The device according to claim 1, characterized in that: The microstrip antenna is any one or more of the following antennas with an operating frequency band covering 920 MHz to 925 MHz: a phased array antenna, a horn antenna, and a waveguide antenna.

11. The device according to claim 1, characterized in that: The material of the medium structure includes any one or more of the following: glass, ceramic, and fiberglass reinforced plastic.

12. A method for detecting the performance of an RFID chip after a bump processing process, which is used to perform performance detection on multiple RFID chips on a wafer to be tested using a device for detecting the performance of an RFID chip after a bump processing process, characterized in that: The RFID chip performance detection device includes: a host computer, an RFID reader, a medium structure array, and a motion control system, wherein: The dielectric structure array includes a base and a plurality of dielectric structures, the plurality of dielectric structures are mounted on the base, and the dielectric structure includes a microstrip antenna arranged on an outer surface of the dielectric structure; The motion control system includes a mechanical arm and a drive device, the mechanical arm is used to move the medium structure array, and the drive device is used to move the medium structure relative to the base; The method comprises performing the following operations by the host computer: S1: Control the mechanical arm to move the dielectric structure array and / or control the driving device to move a specified dielectric structure, so that the microstrip antenna of the specified dielectric structure is connected to the bump on the specified RFID chip on the wafer to be tested to form a tag antenna of the specified RFID chip; S2: Control the RFID reader to communicate with the designated RFID chip via the tag antenna of the designated RFID chip, obtain designated information from the designated RFID chip, and send the designated information to the host computer; S3: Determine whether the area where the designated RFID chip is located is a bad area according to the designated information; Among them, when the bad area includes multiple RFID chips, the host computer iteratively performs operations S1-S3 for the bad area, narrows the scope of the bad area by reducing the number of medium structures connected to the RFID chip, until the bad area contains only one RFID chip, and the RFID chip is determined as a bad chip.

13. The method according to claim 12, wherein: When the wafer to be tested is tested for the first time, the host computer controls the motion control system so that the microstrip antennas of all dielectric structures in the dielectric structure array are connected to the corresponding RFID chips, and moves the dielectric structure array to traverse the entire wafer to be tested, thereby determining one or more defective areas.

14. The method according to claim 12, wherein: The method of reducing the scope of the bad area by reducing the number of medium structures connected to the RFID chip includes: Dividing the bad area into a first sub-area and a second sub-area; Connecting a dielectric structure corresponding to the number of RFID chips in the first sub-area to the RFID chips in the first sub-area, thereby determining whether the first sub-area is a bad area; A medium structure corresponding to the number of RFID chips in the second sub-area is connected to the RFID chips in the second sub-area, thereby determining whether the second sub-area is a bad area.

15. The method according to claim 14, wherein: The first sub-area and the second sub-area have the same number of RFID chips.

16. The method according to claim 12, wherein: The specified information includes: RFID chip TID and / or carrier signal waveform.

17. The method according to claim 12, characterized in that: The medium structure has any one or more of the following shapes: cuboid, cube, cylinder, sphere, ellipsoid; The microstrip antenna is arranged on the bottom surface and the side surface of the dielectric structure; The microstrip antenna includes a first section and a second section disconnected from each other on the bottom surface of the dielectric structure; The first section and the second section respectively extend longitudinally upward along the side surface of the dielectric structure and are bent to form an inductor coil structure for matching the capacitive impedance of the RFID chip.

18. The method according to claim 17, characterized in that: The width W of the first section and the second section of the microstrip antenna is: 0.2 mm ≤ W ≤ 2 mm; The spacing between the first section and the second section on the bottom surface is 10 μm to 30 μm smaller than the spacing between bumps of the RFID chip; The first section and the second section are bent at a position 3 mm to 10 mm away from the top surface of the dielectric structure at the side surface.

19. The method according to claim 18, characterized in that The first section and the second section are respectively connected to the metal patch structure to form a radiation dipole arm structure, thereby forming a wide-band tag antenna.

20. The method according to claim 12, characterized in that: The material of the microstrip antenna includes any one or more of the following: copper, aluminum, silver paste, and conductive ink.

21. The method according to claim 12, characterized in that: The microstrip antenna is any one or more of the following antennas with an operating frequency band covering 920 MHz to 925 MHz: a phased array antenna, a horn antenna, and a waveguide antenna.

22. The method according to claim 12, characterized in that: The material of the medium structure includes any one or more of the following: glass, ceramic, and fiberglass reinforced plastic.

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