Apparatus, method and computer program

Abstract

Embodiments of the present disclosure relate to an apparatus, a method, and a computer program. A method, a computer program and a receiver comprising a plurality of decoders are provided for causing the receiver to perform: receiving (901), at each decoder of the plurality of decoders, an encoded input signal y; decoding (902), at each of the plurality of decoders, the input signal by processing the check nodes in a respective order to obtain a plurality of decoded signals x1,..., xL, the respective order being different for the plurality of decoders; determining (903) a plurality of valid codewords from the plurality of decoded signals; and determining (904) an output codeword from the plurality of valid codewords as an estimate of the input signal.

Description

Technical Field

[0001] Examples described herein relate generally to apparatus, methods, and computer programs, and more particularly (but not exclusively) to apparatus, methods for apparatus, and computer programs. Background Art

[0002] A communication system can be viewed as a facility that enables communication sessions between two or more entities (eg, communication devices, base stations, and / or other nodes) by providing carrier waves between the various entities involved in the communication path.

[0003] The communication system may be a communication system. Examples of communication systems include Public Land Mobile Networks (PLMNs) operating based on radio standards such as provided by 3GPP, satellite-based communication systems, and different wired and / or wireless local networks such as Wireless Local Area Networks (WLANs).

[0004] The communication system and associated equipment operate according to a given set of standards or specifications that set out what the various entities associated with the system are allowed to do and how it is achieved. It also usually defines the communication protocols and / or parameters that will be used for the connection. An example of a standard is the so-called 5G standard.

[0005] 3GPP has released multiple versions (Rel) for defining operational communication protocols related to communication networks. Currently, goals and work on Release 18 (Rel. 18) and 19 (Rel. 19) are under development. Summary of the invention

[0006] According to a first aspect, there is provided a receiver comprising a plurality of decoders, the receiver being configured to: receive an encoded input signal y at each of the plurality of decoders; decode the input signal y at each of the plurality of decoders by processing check nodes in a corresponding order to obtain a plurality of decoded signals x1, ..., x L , the corresponding order is different for multiple decoders; determining multiple valid codewords from the multiple decoded signals; and determining an output codeword from the multiple valid codewords as an estimate of the input signal.

[0007] At least part of the decoding at multiple decoders may be performed simultaneously.

[0008] According to a second aspect, a receiver comprising a plurality of decoders is provided, the receiver being configured to: receive an encoded input signal y at a first decoder among the plurality of decoders; decode the input signal at the first decoder by processing check nodes in a first order to obtain a first decoded signal x1; and determine whether to trigger a second decoder among the plurality of decoders to decode the encoded input signal based on a determination of whether the first decoded signal x1 is a valid codeword as an estimate of the input signal.

[0009] The receiver can be further configured to: in response to determining to trigger the second decoder, trigger the second decoder to decode the input signal by processing the check nodes in a second order to obtain a second decoded signal x2, the second order being different from the first order; and determine whether the second decoded signal x2 is a valid codeword as an estimate of the input signal.

[0010] The receiver may be further configured to, when the first decoded signal is determined to be a valid codeword, forgo sending a trigger to the second decoder to decode the encoded input signal by processing the check nodes in the second order.

[0011] The receiver can also be further configured to: in response to determining that the second decoded signal is an invalid codeword, trigger a third decoder to process the check nodes in a third order to decode the input signal to obtain a third decoded signal x3, the third order being different from the first order and the second order; and determine whether the third decoded signal x3 is a valid codeword as an estimate of the input signal.

[0012] In the above first and second aspects, the receiver may be further configured to: generate at least one of the first sequence or the second sequence randomly or pseudo-randomly.

[0013] In the above first and second aspects, the plurality of decoders may include at least one of the following: a flooding belief propagation decoder, a row-layered belief propagation decoder, or a column-layered belief propagation decoder.

[0014] In the above first and second aspects, the receiver may be further configured to: decode the encoded another input signal by processing the check nodes in the first order and / or the second order at at least one of the first decoder or the second decoder to obtain at least one other decoded signal x L '; Determine another valid codeword x from at least one other decoded signal L'; and determining another output codeword from another valid codeword as an estimate of another input signal, wherein the output codeword is based on a first code and the other output codeword is based on a second code. The first code may include a low density parity check code, and the second code may include a polar code.

[0015] According to a third aspect, there is provided a receiver comprising a plurality of decoders, the receiver further comprising: at least one processor; and at least one memory comprising code, which, when executed by the at least one processor, causes the receiver to perform: receiving an encoded input signal y at each of the plurality of decoders; decoding the input signal at each of the plurality of decoders by processing the check nodes in a corresponding order to obtain a plurality of decoded signals x1, ..., x L , the corresponding order is different for multiple decoders; determining multiple valid codewords from the multiple decoded signals; and determining an output codeword from the multiple valid codewords as an estimate of the input signal.

[0016] At least part of the decoding at multiple decoders may be performed simultaneously.

[0017] According to a fourth aspect, a receiver including multiple decoders is provided, which also includes: at least one processor; and at least one memory including codes, which, when executed by the at least one processor, causes the receiver to perform: receiving an encoded input signal y at a first decoder among multiple decoders; at the first decoder, decoding the input signal by processing check nodes in a first order to obtain a first decoded signal x1; and determining whether the first decoded signal x1 is a codeword as an estimate of the input signal, and determining whether to trigger a second decoder among the multiple decoders to decode the encoded input signal.

[0018] The receiver can also perform: in response to determining to trigger the second decoder, trigger the second decoder to decode the input signal by processing the check nodes in a second order to obtain a second decoded signal x2, the second order being different from the first order; and determine whether the second decoded signal x2 is a valid codeword as an estimate of the input signal.

[0019] The receiver may also be caused to perform, when the first decoded signal is determined to be a valid codeword, forgoing sending a trigger to the second decoder to decode the encoded input signal by processing the check nodes in the second order.

[0020] The receiver can also perform: in response to determining that the second decoded signal is an invalid codeword, triggering a third decoder to decode the input signal by processing the check nodes in a third order to obtain a third decoded signal x3, the third order being different from the first order and the second order; and determining whether the third decoded signal x3 is a valid codeword as an estimate of the input signal.

[0021] In the third and fourth aspects above, the receiver may also be caused to execute: generating at least one of the first or second sequences randomly or pseudo-randomly.

[0022] In the third and fourth aspects above, the plurality of decoders may include at least one of the following: a flooding belief propagation decoder, a row-layered belief propagation decoder, or a column-layered belief propagation decoder.

[0023] In the third and fourth aspects above, the receiver may further be caused to perform: at at least one of the first decoder or the second decoder, decoding another encoded input signal by processing the check nodes in the first order and / or the second order to obtain at least one other decoded signal x L '; Determine another valid codeword x from at least one other decoded signal L '; and determining another output codeword from another valid codeword as an estimate of another input signal, wherein the output codeword is based on a first code and the other output codeword is based on a second code. The first code may include a low density parity check code, and the second code may include a polar code.

[0024] According to a fifth aspect, there is provided a method for a receiver comprising a plurality of decoders, the method comprising: receiving an encoded input signal y at each of the plurality of decoders; decoding the input signal y at each of the plurality of decoders by processing check nodes in a corresponding order to obtain a plurality of decoded signals x1, ..., x L , the corresponding order is different for multiple decoders; determining multiple valid codewords from the multiple decoded signals; and determining an output codeword from the multiple valid codewords as an estimate of the input signal.

[0025] At least part of the decoding at multiple decoders may be performed simultaneously.

[0026] According to a sixth aspect, a method for a receiver comprising multiple decoders is provided, the method comprising: receiving an encoded input signal y at a first decoder among the multiple decoders; at the first decoder, decoding the input signal by processing check nodes in a first order to obtain a first decoded signal x1; and determining whether to trigger a second decoder among the multiple decoders to decode the encoded input signal based on a determination of whether the first decoded signal x1 is a valid codeword as an estimate of the input signal.

[0027] The method may further include: in response to determining to trigger the second decoder, triggering the second decoder to decode the input signal by processing the check nodes in a second order to obtain a second decoded signal x2, the second order being different from the first order; and determining whether the second decoded signal x2 is a valid codeword as an estimate of the input signal.

[0028] The method may further include, when the first decoded signal is determined to be a valid codeword, forgoing sending a trigger to the second decoder to decode the encoded input signal by processing the check nodes in the second order.

[0029] The method may further include: in response to determining that the second decoded signal is an invalid codeword, triggering a third decoder to process the check nodes in a third order to decode the input signal to obtain a third decoded signal x3, the third order being different from the first order and the second order; and determining whether the third decoded signal x3 is a valid codeword as an estimate of the input signal.

[0030] In the fifth and sixth aspects above, the method may include: generating at least one of the first order or the second order randomly or pseudo-randomly.

[0031] In the fifth and sixth aspects above, the plurality of decoders may include at least one of: a flooding belief propagation decoder, a row-layered belief propagation decoder, or a column-layered belief propagation decoder.

[0032] In the fifth and sixth aspects above, the method may further comprise: decoding, at at least one of the first decoder or the second decoder, another encoded input signal by processing the check nodes in the first order and / or the second order to obtain at least one other decoded signal x L '; Determine another valid codeword x from at least one other decoded signal L '; and determining another output codeword from another valid codeword as an estimate of another input signal, wherein the output codeword is based on a first code and the other output codeword is based on a second code. The first code may include a low density parity check code, and the second code may include a polar code.

[0033] According to a seventh aspect, there is provided a receiver comprising a plurality of decoders, the receiver comprising: a receiving circuit system for receiving an encoded input signal y at each of the plurality of decoders; a decoding circuit system for decoding the input signal at each of the plurality of decoders by processing the check nodes in a corresponding order to obtain a plurality of decoded signals x1, ..., x L , the corresponding order is different for multiple decoders; a determination circuit system for determining multiple valid codewords from multiple decoded signals; and a determination circuit system for determining an output codeword from the multiple valid codewords as an estimate of the input signal.

[0034] At least part of the decoding at multiple decoders may be performed simultaneously.

[0035] According to an eighth aspect, a receiver including multiple decoders is provided, which includes: a receiving circuit system for receiving an encoded input signal y at a first decoder among the multiple decoders; a decoding circuit system for decoding the input signal at the first decoder by processing check nodes in a first order to obtain a first decoded signal x1; and a determination circuit system for determining whether to trigger a second decoder among the multiple decoders to decode the encoded input signal based on a determination of whether the first decoded signal x1 is a valid codeword as an estimate of the input signal.

[0036] The receiver may further include: a trigger circuit system for triggering a second decoder in response to determining to trigger the second decoder to decode the input signal by processing the check nodes in a second order to obtain a second decoded signal x2, the second order being different from the first order; and a determination circuit system for determining whether the second decoded signal x2 is a valid codeword as an estimate of the input signal.

[0037] The receiver may further include a foregoing circuit system for foregoing sending a trigger to the second decoder to decode the encoded input signal by processing the check nodes in the second order when the first decoded signal is determined to be a valid codeword.

[0038] The receiver may further include: a trigger circuit system for triggering a third decoder to process the check nodes in a third order to decode the input signal to obtain a third decoded signal x3 in response to determining that the second decoded signal is an invalid codeword, the third order being different from the first order and the second order; and determining whether the third decoded signal x3 is a valid codeword as an estimate of the input signal.

[0039] In the seventh and eighth aspects above, the receiver may further include: a generating circuit system for generating at least one of the first sequence or the second sequence randomly or pseudo-randomly.

[0040] In the seventh and eighth aspects above, the plurality of decoders may include at least one of: a flooding belief propagation decoder, a row-layered belief propagation decoder, or a column-layered belief propagation decoder.

[0041] In the seventh and eighth aspects above, the receiver may further include: a decoding circuit system for decoding the encoded another input signal at at least one of the first decoder or the second decoder by processing the check nodes in the first order and / or the second order to obtain at least one other decoded signal x L '; Determine circuit system for determining another valid codeword x based on at least one other decoded signal L '; and determining circuitry for determining another valid codeword x based on at least one other decoded signalL The first code may include a low-density parity-check code, and the second code may include a polar code.

[0042] According to a ninth aspect, there is provided a non-transitory computer-readable medium comprising program instructions for causing a receiver comprising a plurality of decoders to: receive an encoded input signal y at each of the plurality of decoders; decode the input signal at each of the plurality of decoders by processing the check nodes in a corresponding order to obtain a plurality of decoded signals x1, ..., x L , the corresponding order is different for multiple decoders; determining multiple valid codewords from the multiple decoded signals; and determining an output codeword from the multiple valid codewords as an estimate of the input signal.

[0043] At least part of the decoding at multiple decoders may be performed simultaneously.

[0044] According to the tenth aspect, a non-transitory computer-readable medium is provided, comprising program instructions for causing a receiver comprising multiple decoders to perform the following operations: receiving an encoded input signal y at a first decoder among the multiple decoders; at the first decoder, decoding the input signal by processing check nodes in a first order to obtain a first decoded signal x1; and determining whether to trigger a second decoder among the multiple decoders to decode the encoded input signal based on a determination of whether the first decoded signal x1 is a valid codeword as an estimate of the input signal.

[0045] The receiver can also perform: in response to determining to trigger the second decoder, trigger the second decoder to decode the input signal by processing the check nodes in a second order to obtain a second decoded signal x2, the second order being different from the first order; and determine whether the second decoded signal x2 is a valid codeword as an estimate of the input signal.

[0046] The receiver may also be caused to perform, when the first decoded signal is determined to be a valid codeword, forgoing sending a trigger to the second decoder to decode the encoded input signal by processing the check nodes in the second order.

[0047] The receiver can also be caused to perform: in response to determining that the second decoded signal is an invalid codeword, triggering a third decoder to process the check nodes in a third order to decode the input signal to obtain a third decoded signal x3, the third order being different from the first order and the second order; and determining whether the third decoded signal x3 is a valid codeword as an estimate of the input signal.

[0048] In the ninth and tenth aspects above, the receiver may also be caused to execute: generating at least one of the first sequence or the second sequence randomly or pseudo-randomly.

[0049] In the ninth and tenth aspects above, the plurality of decoders may include at least one of: a flooding belief propagation decoder, a row-layered belief propagation decoder, or a column-layered belief propagation decoder.

[0050] In the ninth and tenth aspects above, the receiver may further be caused to perform: at at least one of the first decoder or the second decoder, decoding another encoded input signal by processing the check nodes in the first order and / or the second order to obtain at least one other decoded signal x L '; Determine another valid codeword x from at least one other decoded signal L '; and determining another output codeword from another valid codeword as an estimate of another input signal, wherein the output codeword is based on a first code and the other output codeword is based on a second code. The first code may include a low density parity check code, and the second code may include a polar code.

[0051] In all of the above aspects, the valid codewords may comprise codewords of a linear block code.

[0052] In all the above aspects, the receiver may be comprised in a user equipment, or wherein the receiver is comprised in an access network node.

[0053] According to an eleventh aspect, there is provided a computer program product stored on a medium, which can cause an apparatus to perform any method as described herein.

[0054] According to a twelfth aspect, an electronic device is provided, which may include the apparatus as described herein.

[0055] According to a thirteenth aspect, there is provided a chipset, which may include the apparatus as described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Some examples will now be described, by way of illustration only, using reference to the accompanying drawings, in which:

[0057] Figure 1 A schematic diagram of a 5G system is shown;

[0058] Figure 2 A schematic diagram of a network device is shown;

[0059] Figure 3 A schematic diagram of a user equipment is shown;

[0060] Figure 4A An encoder-decoder architecture is shown;

[0061] Figure 4B and 4C The decoding architecture is shown;

[0062] Figure 5 shows the input and output of the belief propagation list decoder;

[0063] Figures 6 to 8 An example decoder architecture is shown; and

[0064] FIG. 9A to FIG. 10 Example operations that may be performed by the apparatus included herein are shown. DETAILED DESCRIPTION

[0065] A decoder architecture is described below that can be used to determine a codeword associated with any type of coding mechanism. In other words, a first coded signal encoded according to a first coding scheme received at a receiver and a second coded signal encoded according to a second coding scheme received at a receiver can be input to the same decoder. The first coding mechanism and the second coding mechanism can be different. Examples of different coding mechanisms include a low-density parity-check (LDPC) code mechanism and / or a polar code mechanism. It should be understood that the first and / or second coding mechanism may include at least one other coding mechanism in addition to the LDPC code mechanism and / or the polar code mechanism. For example, the mechanism described below can be applied to any type of coding mechanism associated with (multiple) linear block codes.

[0066] The decoder architecture may include hardware and / or software for processing received signals to determine valid codewords. The decoder architecture may be configured to output corresponding candidate codewords using a plurality of different check nodes arranged in sequence. The decoder architecture may include hardware and / or software for identifying valid codewords using corresponding candidate codewords. Examples of how this may be achieved are further provided below.

[0067] In the description of the following examples, some aspects are explained with reference to devices that are generally capable of communicating via wireless cellular systems and mobile communication systems serving such mobile communication devices. For the sake of brevity and clarity, these aspects are described below with reference to 5G wireless communication systems. However, it should be understood that these aspects are not limited to 5G wireless communication systems (or even wireless communication systems), and can be applied, for example, to other wired communication systems and / or wireless communication systems (e.g., current 6G proposals, IEEE 802.11, etc.). It should be understood that the following references to wireless communication systems and devices can also be applied to wired communication systems.

[0068] Before describing the examples in detail, refer to Figure 1 Briefly explain some general principles of 5G wireless communication systems.

[0069] Figure 1A schematic diagram of a 5G system (5GS) 100 is shown. The 5GS may include a user equipment (UE) 102 (which may also be referred to as a communication device or terminal), a 5G access network (AN) 104 (which may be a 5G radio access network (RAN) or any other type of 5G AN, such as a non-3GPP interconnect function (N3IWF) / trusted non-3GPP gateway function (TNGF) for untrusted / trusted non-3GPP access or a wireline access gateway function (WAGF) for wireline access), a 5G core (5GC) 106, one or more application functions (AF) 108, and one or more data networks (DN) 110.

[0070] A 5G RAN may include one or more gNodeB (gNB) distributed unit functions connected to one or more gNodeB (gNB) unit functions. A RAN may include one or more access nodes.

[0071] 5GC 106 may include one or more access and mobility management functions (AMF) 112, one or more session management functions (SMF) 114, one or more authentication server functions (AUSF) 116, one or more unified data management (UDM) functions 118, one or more user plane functions (UPF) 120, one or more unified data repository (UDR) functions 122, one or more network repository functions (NRF) 128 and / or one or more network exposure functions (NEF) 124. The role of NEF is to provide secure network service exposure (e.g., voice, data connection, billing, user data, etc.) to third parties. Although NRF 128 and its interfaces are not described, it should be understood that this is for clarity and that NRF 128 may have multiple interfaces with other network functions.

[0072] 5GC 106 also includes a network data analysis function (NWDAF) 126. NWDAF is responsible for providing network analysis information upon request of one or more network functions or devices within the network. Network functions may also subscribe to NWDAF 126 to receive information therefrom. Thus, NWDAF 126 is also configured to receive and store network information from one or more network functions or devices within the network. Data collection by NWDAF 126 may be performed based on at least one subscription to an event provided by at least one network function.

[0073] Data transmitted between devices, particularly between UE and access point, is usually encoded to prevent interference from destroying the transmitted data. For example, the encoder at the transmitter will encode the data for transmission on the transmission channel by adding redundancy to the data (e.g., by interspersing the code into the data). The encoded signal is then transmitted to the receiver through the transmission channel. The receiver decodes the signal by removing the interspersed code. The receiver can determine whether the signal has been correctly received by extracting words from the encoded signal and determining whether the extracted words are valid code words. When the extracted words are determined to be valid code words, it can be determined that the received encoded signal has been correctly received and decoded. When the extracted words are determined to be invalid code words, it can be determined that the received encoded signal has been received and / or decoded incorrectly. In the case where the extracted words are invalid code words, the received encoded signal can be discarded without further processing.

[0074] Figure 4A , Figure 4B and Figure 4C The process is shown.

[0075] Figure 4A A channel encoder 401 is shown in a transmitter, which receives a signal u for transmission to a receiver. The channel encoder 401 outputs a signal x representing an encoded version of the signal u. The signal x is input to a modulation device 402. The modulation device 402 outputs a signal Channel 403 outputs signal y to channel decoder 404 at the receiver. Channel decoder 404 decodes y to output

[0076] There are various types of codes that can be used to encode data for transmission. The examples of low-density parity-check (LDPC) codes and polar codes are discussed below because these codes are used in a variety of different communication protocols. However, it should be understood that, as mentioned above, the presently described mechanism can be used for any type of linear block code.

[0077] LDPC codes are linear error correction codes for protecting messages on noisy transmission channels. LDPC codes are constructed using sparse Tanner graphs. Tanner graphs are bipartite graphs used to describe constraints or equations for a specified error correction code (e.g., a graph whose vertices can be divided into two independent sets, which are referred to as check nodes and variable nodes hereinafter). The channel code can be fully described by an (M×N) parity check matrix H (referred to as an H matrix), where N represents the number of variable nodes (VN) (e.g., the length of a code block) and M represents the number of check nodes (CN). Check nodes can fill the rows of the H matrix and variable nodes can fill the columns of the H matrix.

[0078] LDPC codes are usually decoded using an iterative message passing decoder, also known as the sum-product algorithm (SPA). This is a modified version of the belief propagation (BP) algorithm introduced in 1962. Soft messages in the form of log-likelihood ratios (LLRs) are exchanged over the code's Tanner graph, a bipartite graph that partitions the nodes into N VNs and M CNs. A hardware-popular approximation method called the minimum sum can be used to reduce the computational cost.

[0079] The belief propagation technique regards each parity check constituting the LDPC as an independent single parity check (SPC) code. Each SPC code is decoded individually using soft input soft output (SISO) technology and other derivative technologies. The soft decision information from each SISO decoding is cross-checked and updated with other redundant SPC decodings of the same information bit. Each SPC code is then decoded again using the updated soft decision information. This process is iterated until a valid codeword is achieved or exhaustive decoding is achieved. This type of decoding is generally referred to as sum-product decoding.

[0080] The decoding of an SPC code is often referred to as a "check node" process, and the cross-checking of variables is often referred to as a "variable node" process.

[0081] The LDPC decoding algorithm can be implemented in different variants: flood decoding and layered decoding.

[0082] Under LDPC flood decoding, assuming a decoding matrix of size M×N, LLR messages are flooded from N VNs to M CNs in parallel, and vice versa.

[0083] Under LDPC layered decoding, CN can be processed sequentially, and the output of the previous CN already in the same iteration is merged. In other words, the decoding algorithm can operate on the rows of the parity check matrix of the LDPC code and process each row, row-by-row decoding (e.g., a top-to-bottom method) separately. This may lead to rapid convergence. Another variant of LDPC layered decoding (also referred to as "column layered" decoding), VN is processed sequentially (e.g., column-by-column decoding, also referred to as a left-to-right method). The LDPC decoder can be implemented based on a row layered BP decoder with a minimum and approximate.

[0084] Polar codes are linear block error correction codes. The code construction of polar codes is based on multiple recursive concatenations of short core codes, which convert physical channels into virtual outer channels. Polar codes can be decoded in a serial manner (e.g., bit by bit). The original decoding method is the successive cancellation (SC) decoder. Current polar code decoding algorithms use a version of list decoding called successive cancellation list (SCL) decoding.

[0085] exist Figure 4AIn the example of , a random bit generator (eg, source) may generate blocks of k bits labeled u, where u represents a vector of information bits. The values ​​of "0" and "1" may be equally probable in the vector u.

[0086] Then, the channel encoder (eg, LDPC or polar encoder) 401 encodes (eg, adds redundancy) the information bit vector u into a codeword x of length N. (ie, x=Enc(u)).

[0087] The modulation means 402 can then transform the codeword bits into symbols. This can be done by the function )express.

[0088] The transmission channel 403 may include any type of transmission channel. For the sake of clarity and simplicity, the transmission channel between the transmitter and the receiver is considered below to include at least one of an additive white Gaussian noise (AWGN) channel and / or a Rayleigh fading channel. However, it should be understood that these are only used as examples, and the transmission channel may include any type of channel.

[0089] The AWGN channel can be regarded as a channel with zero mean and variance σ 2 Gaussian noise of is added to the signal transmitted on the transmission channel 403. In this case, the introduced noise variance in the transmission signal can be directly related to the signal-to-noise ratio (SNR) of the AWGN channel, for example ).

[0090] Rayleigh fading channels can be modeled using a Rayleigh fading model with full channel state information (CSI), which can be understood as a result of orthogonal frequency division multiplexing (OFDM) based transmission in a multipath propagation environment. This can be expressed as, for example Where α>0 is the fading coefficient, and the fading coefficient obeys E[α 2 ]=1, and the coefficient is known by the receiver at each received bit position. Rayleigh fading channels can be modeled using alternative modeling algorithms.

[0091] The transmission channel provides a signal to a channel decoder 404 located at the receiver. Thus, the channel decoder can take as input the output y (or a noise codeword) from the channel and return the estimated codeword (e.g., ).

[0092] In a practical LDPC decoder implementation, a set of SPC codes are decoded in parallel to increase throughput. As mentioned above, this parallel processing is also known as flood decoding, where the check nodes are processed in parallel. This process consists of Figure 4B , where the check nodes are processed in parallel and their outputs are combined to estimate the decoder output.

[0093] exist Figure 4B In the example of , check node 1 (CN1) is connected to VN1, VN4, VN5 and VN7, check node 2 (CN2) is connected to VN2, VN4, VN6 and VN7, and check node 3 (CN3) is connected to VN3, VN5, VN6, VN7. The input signal is shown as y, and the output is shown as exist Figure 4B In the example of , all VNs and CNs are updated in parallel. In other words, all messages are "flooded" from VNs to CNs in parallel (and vice versa).

[0094] Figure 4C An example serial layered BP decoder is shown. Figure 4C In the example of , CN1 is connected to VN1, VN3 and VN4, CN2 is connected to VN2 and VN5, CN3 is connected to VN2 and VN6, and CN4 is connected to VN1, VN4 and VN6. The input signal is shown as y, and the output is shown as exist Figure 4C In the example of , CN is updated in a serial manner (eg, one by one) for each iteration of the algorithm.

[0095] Figure 2 An example of a control device for a communication system is shown, the control device being, for example, coupled to and / or used to control a station of an access system, such as a RAN node, for example a base station gNB, a central unit of a cloud architecture, or a node of a core network, such as a mobility management entity (MME) or a serving gateway (S-GW), a scheduling entity such as a spectrum management entity, or a server or host, such as a device that hosts a network repository function (NRF), a network data analysis function (NWDAF), an access and mobility management function (AMF), a session management function (SMF), a unified data management / unified data repository (UDM / UDR), etc.

[0096] The control device may be integrated with or external to a node or module of a radio access network (RAN) or a core network. In some examples, the base station includes a separate control device unit or module. In other examples, the control device may be another network element, such as a radio network controller or a spectrum controller. The control device 200 may be configured to provide control for communications in a service area of ​​the system. The device 200 includes at least one memory 201, at least one data processing unit 202, 203, and an input / output interface 204. Via the interface, the control device may be coupled to a receiver and a transmitter of the device. The receiver and / or the transmitter may be implemented as a radio front end or a remote radio head. For example, the control device 200 or the processor 201 may be configured to execute appropriate software code to provide control functions. The "code" mentioned here refers to software code, and vice versa.

[0097] Now refer to Figure 3 describing in more detail possible wireless communication devices, Figure 3 A schematic partial cross-sectional view of a communication device 300 is shown. Such a communication device is generally referred to as a user equipment (UE) or a terminal. Suitable mobile communication devices can be provided by any device capable of sending and receiving radio signals. Non-limiting examples include a mobile station (MS) or a mobile device (such as a mobile phone or a so-called "smart phone"), a computer with a wireless interface card or other wireless interface facilities (e.g., a USB dongle), a personal data assistant (PDA) or a tablet computer with wireless communication capabilities, or any combination of these and the like. Mobile communication devices can provide, for example, data communications for carrying communications such as voice, e-mail (email), text messages, multimedia, etc. Therefore, users can obtain and provide many services through their communication devices. Non-limiting examples of these services include two-way or multi-way calls, data communications or multimedia services, or simply access to a data communication network system (e.g., the Internet). Broadcast or multicast data can also be provided to users. Non-limiting examples of content include downloads, television and radio programs, videos, advertisements, various alarms, and other information.

[0098] A wireless communication device may be, for example, a mobile device, i.e., a device that is not fixed to a particular location, or a wireless communication device may be a fixed device. A wireless device may require human interaction to communicate, or may not require human interaction to communicate. As described herein, the term UE or "user" is used to refer to any type of wireless communication device.

[0099] The wireless device 300 may receive signals via the air or radio interface 307 by suitable means for receiving, and may transmit signals via suitable means for transmitting radio signals. Figure 3 In the embodiment of the present invention, the transceiver arrangement is schematically designated by block 306. The transceiver arrangement 306 may be provided, for example, by means of a radio component and an associated antenna arrangement. The antenna arrangement may be arranged internally or externally to the wireless device.

[0100] The wireless device is typically provided with at least one data processing entity 301, at least one memory 302 and possibly other components 303 designed for software code and hardware assistance to perform tasks, including control of access and communication to access systems and other communication devices. Data processing, storage and other related control devices may be provided on appropriate circuit boards and / or in chipsets. This feature is indicated by reference numeral 304. The user of the device may control the operation of the wireless device by means of a suitable user interface such as a keypad 305, voice commands, a touch-sensitive screen or touch-sensitive pad, a combination thereof, etc. A display 308, a speaker and a microphone may also be provided. In addition, the wireless communication device may include appropriate connectors (wired or wireless) to other devices and / or for connecting external accessories, such as hands-free devices.

[0101] In the above example of a decoder, after receiving the noisy sequence of data samples, the receiver then applies different receiver algorithms (e.g., equalization, demapping, and / or decoding algorithms) to extract the originally transmitted information. One of the most energy- and time-consuming steps is the forward error correction (FEC) decoder (e.g., iterative BP decoding for LDPC codes and SCL decoding for polar codes, as described above).

[0102] This application identifies a number of problems associated with current decoders.

[0103] For example, currently, a receiver decodes received encoded signals using different encoding mechanisms by using corresponding decoder hardware for each encoding mechanism (e.g., first decoder hardware for decoding polar codes and second decoder hardware for decoding LDPC codes). Having multiple decoder hardware in the same device can be expensive in terms of chip space and component cost.

[0104] In other words, in channel coding, there is a custom decoder for each channel code, and some communication standards cover multiple channel codes. For example, as mentioned above, the 5G communication protocol currently covers both LDPC codes and polar codes. In this case, an iterative BP decoder (such as the one described above for FIG. 4A to FIG. 4C LDPC codes are decoded using a dual decoder (described in the specification) while polar codes are decoded using an SCL decoder. This dual decoder uses customized decoding hardware (such as a decoder chip) for each channel code, which increases hardware cost and area.

[0105] Another problem involves the problem of decoding short-length LDPC codes. As mentioned above, LDPC codes are usually decoded using an iterative BP decoder. However, for short-length LDPC codes, there is a huge performance gap between the iterative BP decoder and the maximum likelihood (ML) decoder (ML bound). In other words, the performance of conventional decoders for short codes is usually much worse than for longer codes.

[0106] Another problem involves decoding polar codes. As mentioned above, polar codes are decoded using an SC-based decoder, where information bits are decoded bit by bit in a serial manner.

[0107] SC-based decoders typically output a hard decision for each bit without an estimate of the reliability of the bit (e.g., the output is 0 or 1, with no context for the bit value). This is not always useful for iterative receivers using iterative detection and / or decoding loops.

[0108] SC-based decoders are also generally difficult to parallelize, resulting in a serial decoder. Due to the bit-by-bit decoding nature, the use of a serial decoder may result in a high-latency / low-throughput decoder implementation.

[0109] To address at least one of the above problems, a decoder architecture that can be used to decode various types of linear block codes is proposed below. In other words, no matter what code is used to encode the signal, the encoder can feed the received encoded signal into the same decoder chip, which outputs the estimated codeword. The encoded signal can be encoded via any encoding mechanism, such as LDPC and / or polar coding.

[0110] Essentially, we consider below a mechanism for generating different ranges of codeword estimates from L decoders. This can be achieved by changing the order in which the check nodes are updated.

[0111] In more detail, in the current decoding system, the update is adopted from top to bottom (row by row, check node by check node), such as Figure 4C This is because, on average, any check node sequence is as good as any other check node sequence in a row-level BP decoder.

[0112] However, the present application recognizes that a particular check node update order may be better for a particular noise realization experienced by the encoded signal transmitted through the channel. In other words, for a particular noise realization, one CN update schedule may be better than another CN update schedule. The present application proposes to exploit this by changing the order of check node updates across L decoders and using the output from at least one of these decoders to estimate the valid codeword.

[0113] From a slightly different perspective, the performance of the individual CN update schedules for each noise implementation can be different due to the different processing orders in the decoding graph. Therefore, whenever decoding fails using a particular check node update order, another check node update order can be used until a specific stop condition is reached. In this way, a collection of multiple BP decoders can be utilized to improve error correction performance without increasing the worst-case decoding delay.

[0114] It should be understood that the number of permutations of check node updates can be very large. For example, for N check nodes, there can be N! different permutations. However, to make decoding more efficient (in terms of hardware and / or software space and / or processing time), only L of these different permutations can be checked, where L / N! <1. Therefore, in some examples, the number of check node permutations that are checked may be less than all the different permutations. For example, for a code of length N=128 and code dimension k=64, there are Different check node update orders (or schedules). The permutations may be generated and / or represented by a vector π=randperm(M), where randperm(M) is a function that generates a random permutation of the vector {1, 2, 3, ..., M}.

[0115] As described above, there are a large number (M!) of check node permutations (where M! can correspond to (number of rows in the H-matrix)! or (number of check nodes)!), all of which will perform equally well (on average), resulting in the same error rate performance. However, for each noise realization, different check node update orders will perform differently (e.g., have different convergence behaviors: convergence to a valid codeword or not, number of iterations required to converge, correct or incorrect convergence). The currently described mechanism aims to increase the list diversity by implementing different scheduling strategies.

[0116] This can be achieved by combining multiple row-level BP decoders that are arranged to perform the check node update equations row-by-row (eg, check node-by-check node).The order of check node updates may vary between different decoders.

[0117] In more detail, a straightforward way to implement a row-level BP decoder with shuffled check nodes is to arrange the rows of the matrix H according to the generated vector π (i.e., H′=H(π,:)), and then apply a conventional algorithm to update row 1, then row 2, and so on until row M. Using this definition, an almost infinite number of diverse / different BP decoders can be generated based on the same algorithm (e.g., row-level BP decoding). For clarity and brevity, the following example considers L parallel decoders, where L is a user-defined parameter that results in a performance-complexity tradeoff (e.g., increasing L results in better error rate performance but results in higher complexity). Since all L decoders are assumed to run in parallel, the decoding delay remains unchanged.

[0118] To illustrate the presently described technique, the LDPC decoding technique (i.e., row-layered BP decoder) is modified as follows so that the check nodes are processed in various different combinations. This is shown according to the following examples of parallel decoding, serial decoding, and cascade decoding. All three examples involve increasing the diversity of different orders in which the check node updates are performed.

[0119] Furthermore, for simplicity, the basic decoder considered below is a row-layered BP decoder. The decoder can be based on the SPA algorithm, the minimum sum approximation algorithm or any other variant of the belief propagation decoder (e.g., normalization with correction, attenuated minimum sum).

[0120] refer to Figure 5 A decoder example is shown.

[0121] Figure 5 A BP list (BPL) decoder is shown. The BPL decoder receives multiple inputs and outputs codeword estimates. The multiple inputs may include, for example, a received noisy codeword y, a parity check matrix H, a list size L, and a maximum number of iterations (maxIter) for each component decoder. The BPL decoder may use the inputs to determine the outputs, as described below with respect to Figures 6 to 8 shown.

[0122] There may be multiple different decoders employed that differ only in the order of log-likelihood ratio (LLR) schedule updates. The LLR schedule update order can be considered as a change in the order in which messages are passed on the decoding graph. Examples include flooding BP decoders, row-layered BP decoders, and column-layered BP decoders.

[0123] In practice, the row-layered BP decoder can be used to decode LDPC codes and can be efficiently / effectively implemented in hardware (e.g., high throughput, low latency, small area, etc.). Therefore, the decoder proposed below will be based on this row-layered BP decoder. However, it should be understood that any other message update schedule (e.g., column-layered belief propagation decoding) can be used. The purpose here is to increase list diversity, which will enhance the decoder error rate performance.

[0124] It should be understood that any other decoder mentioned herein can be used as component decoder to increase list diversity. However, for simplicity and with a view to reducing component decoders to be implemented in hardware, row-layered SPA BP decoding with different check node update orders is considered below.

[0125] First, consider the parallel decoding example.

[0126] In the parallel decoding mechanism described herein, L parallel independent (e.g., row-layered) BP decoders are run, which can generate corresponding hypotheses. For example, the decoder described herein may include multiple parallel BP decoders (e.g., Figure 4C As described above, each of these parallel BP decoders is configured to update its check nodes in a different order / different arrangement than other BP decoders in the plurality of BP decoders. A single most likely codeword can be selected from the generated valid codewords (e.g., using an "ML-in-the-list" rule).

[0127] The parallel decoder system described herein implements the check node sequence C1, C2, ..., C L For example, a first branch may implement a combination of check nodes in a first arrangement (e.g., C1, C2, C3, C4, C5), a second branch may implement a combination of check nodes in a second arrangement (e.g., C2, C4, C5, C1, C3), and so on.

[0128] Then identify the valid codeword outputs from the L decoders (e.g., by parity checks such as As described further below.) One of the identified valid codewords may then be selected by finding the codeword that is closest in Euclidean distance to the noisy codeword y (e.g., as described below with respect to Figure 6 discussed, and the “ML-in-the-List” decision rule).

[0129] about Figure 6 An example of a parallel decoder according to the present example is shown.

[0130] Figure 6A received encoded signal y is shown input into L parallel branches of the decoder architecture 600 and y is input into the selection function 602. Each parallel branch comprises a row-layered BP decoder 601 configured to process a corresponding check node order (eg, to process a different message schedule).

[0131] For example, the first row hierarchical BP decoder 601 in the first decoding branch may receive the signal y, process the signal y according to the first arrangement of the check node update order (e.g., C1, C2, C3, C4, C5), and output the first signal to the evaluation function 604. Evaluation function determines the first signal Whether it includes a valid codeword. When the evaluation function 604 determines that the signal When a valid codeword is included, evaluation function 604 signals Output to the selection function 602. When the evaluation function 604 in the first decoding branch does not identify a valid codeword, an invalid block error indication 603 is output.

[0132] In addition, the second row hierarchical BP decoder 601 in the second decoding branch can receive the signal y, process the signal y according to the second arrangement of the check node update order (e.g., C2, C4, C5, C1, C3), and output a second signal to the evaluation function 604 included in the second decoding branch. Evaluation function determines the second signal Whether it includes a valid codeword. When the evaluation function 604 determines that the signal When a valid codeword is included, the evaluation function 604 will signal Output to the selection function 602. When the evaluation function 604 in the second decoding branch does not identify a valid codeword, an invalid block error indication 603 is output.

[0133] Operations corresponding to those performed by the first and second decoding branches may be performed by the remaining parallel branches, albeit with respect to corresponding arrangements of the respective check nodes.

[0134] It should be understood that the decoders provided in each branch need not be of the same type. For example, the first decoder branch may include a decoder operating according to a flooded belief propagation algorithm, the second decoder may operate according to a row-level belief propagation algorithm (using a regular order of check node updates), and the remaining decoders may include a row-level belief propagation algorithm (each decoder using a randomly permuted CN update order).

[0135] Since the component decoder Figure 6The examples in are all independent, so they can all run in parallel, which may lead to high throughput with (average and worst-case) decoding delay constraints. Remember that the (average and worst-case) decoding delay in a BP decoder is proportional to the (average and maximum) number of BP iterations.

[0136] The selection function 602 may include functionality (eg, hardware and / or software) for selecting a valid codeword that is determined by the selection function to optimally achieve a combined output.

[0137] For example, in Figure 6 In the example of , L parallel independent decoders are provided that produce (eg, output) L estimated words. In this example, each decoder includes in a corresponding matrix H(π L ), where L denotes the Lth decoder and π L represents a unique order (e.g., permutation) of the check nodes of the parity check matrix H. Thus, assuming that the check nodes are provided as rows in the matrix H, different belief propagation decoders in different decoder branches have different beliefs about H(π L ) differ from each other in the order of the rows of the matrix.

[0138] Each of the L belief propagation decoders converts the corresponding estimated word The output is fed into an evaluation function 604 in the decoder branch that evaluates the validity of the output. This can be done by, for example, multiplying the output with the transpose of the matrix H to determine if the result is equal to zero (e.g., ) to evaluate the validity of the output. When the result is not equal to zero (for example, the word When the result is determined to be invalid, an indication of a block error at 603 is output. is determined to be valid), is output to the decision block (eg, selection function 602).

[0139] The selection function 602 selects an estimated word based on some predefined metrics and declares it as the final output, In this example, the "ML-in-the-list" rule is used. For example, the decision block can output the codeword Determined as:

[0140] If no valid codeword is available (e.g., if no valid codeword is identified by the evaluation function), the decoder may declare decoding failure directly by indicating that a block error has occurred, and optionally select an output according to a predefined metric that aims to reduce the number of bits identified as erroneous.

[0141] Now consider a second example involving a serial decoder.

[0142] In this second example, the first decoder processes the signal using a first order (e.g., arrangement) of check nodes to output a first estimated word. When the first estimated word is determined to be valid, the first estimated word is selected as the output codeword. When the first estimated word is determined to be invalid, the signal is processed by a second decoder, which processes the signal using a second check node order to output a second estimated word. This process can continue until a valid codeword is found or a maximum of L decoders have been used.

[0143] about Figure 7 A second example is shown.

[0144] Figure 7 A signal y is shown which is input to L decoders 701A, 701B and 701L.

[0145] The first decoder 701A uses a first arrangement of the plurality of check nodes to determine a word The word is output to the first validity function 702A. The first validity determination function includes a function for determining Hardware and / or software to determine whether it is a valid codeword. For example, when When is a valid codeword. When it is not equal to zero, a trigger is provided to the second decoder 701B.

[0146] The second decoder 701B uses a second arrangement of the plurality of check nodes to determine the word The second arrangement is different from the first arrangement. is output to the second validity function 702B. The second validity determination function includes a function for determining Hardware and / or software to determine whether it is a valid codeword. For example, when Then confirm is a valid codeword. When is not equal to zero, a trigger is provided to the third decoder 701C (not shown). This process can be repeated at different decoders using different check node update orders until a valid codeword is identified, or until L decoders are reached. As described above, a random generation mechanism can be used to select the check node update order.

[0147] There is a performance-delay-complexity tradeoff between the first example mechanism (parallel BPL) and the second example mechanism (serial BPL).

[0148] For example, the average processing complexity of the serial BPL may be lower than the average processing complexity of the parallel BPL, while both have almost the same worst-case complexity. The error rate performance comparison between the two examples may depend on the stopping criteria (e.g., on determining accuracy) of the system (or the false alarm rate).

[0149] In a third example mechanism, a BP decoder such as that used in current systems (e.g., a row-layered or flooded BP decoder) is provided. When the output of the BP decoder does not produce a valid codeword, then one of the first and second mechanisms described above may be deployed. This is accomplished by Figure 8 Shown.

[0150] Figure 8 The encoded received signal y is shown to be input into a lower complexity decoder 801 (eg, a layered BP decoder or a flooded BP decoder) and input into a higher complexity decoder 803 (eg, as described above with respect to Figure 6 and / or Figure 7 The word from the output of the lower complexity decoder 801 is is input to the validity function 802. The validity function 802 can determine corresponds to a valid codeword. This can be performed as discussed above with respect to any of the previous examples. When it is a valid codeword, the validity function outputs the codeword as When determining When the codeword is invalid, the validity function 802 outputs a trigger to the higher complexity decoder 803. The trigger received at the higher complexity decoder 803 causes the higher complexity decoder to execute Figure 6 and / or Figure 7 mechanism.

[0151] When the transmitting and receiving devices including the encoder and the decoder, respectively, operate in a low error rate region (e.g., when the probability of a data packet error occurring is low), Figure 8 A cascading mechanism may be useful.

[0152] To reduce the complexity of the proposed decoder example, a SNR-dependent lookup table (or a pre-trained neural network) can be used to decide when to activate the above-mentioned Figures 6 to 8 Any decoder in .

[0153] For example, at a predefined (lower) range of SNR values, a row-layered BP decoder may be used, and at a predefined (higher) range of SNR values, a row-layered BP decoder may be used. Figures 6 to 8In other words, the decoder can be adjusted based on the estimated SNR. This means that the decoding parameters can be adjusted dynamically (e.g., in real time) according to the received channel observations y to optimize energy efficiency.

[0154] Furthermore, in the absence of a known explicit decoder, Figures 6 to 8 The above decoder can potentially be used for a channel code when a sparse graph representation of the channel code is found.

[0155] The characteristics of the above examples are as follows FIG. 9A to FIG. 10 Therefore, it should be understood that at least one feature mentioned below can find a functional correspondence with at least one feature mentioned in the above figures. In addition, it should be understood that the above examples can be used to provide an example context for deploying the currently described technology.

[0156] FIG. 9A to FIG. 9B Operations that may be performed by a receiver apparatus including a plurality of decoders are described. The receiver may receive signals wirelessly and / or via a wired connection. The receiving apparatus may be included in a user equipment. The receiver apparatus may be included in an access node (e.g., a gNB). The receiver apparatus may include a network node (e.g., a receiver located within a network).

[0157] Fig. 9A Operations that may be performed by a receiver including multiple decoders are described.

[0158] During 901, a receiver receives an encoded input signal y at each of a plurality of decoders. The encoded input signal y may be a signal received from a transmitter through a channel.

[0159] During 902, the receiver decodes an input signal at each of a plurality of decoders by processing the check nodes in a corresponding order to obtain a plurality of decoded signals x1, . . . , x L , the corresponding order is different for the plurality of decoders. For example, a first decoder among the plurality of decoders may be configured to decode an input signal by processing check nodes in a first order to obtain a first decoded signal, a second decoder among the plurality of decoders may be configured to decode an input signal by processing check nodes in a second order to obtain a second decoded signal, a third decoder among the plurality of decoders may be configured to decode an input signal by processing check nodes in a third order to obtain a third decoded signal, and so on. The first order, the second order, and the third order are different from each other.

[0160] During 903, the receiver determines a plurality of valid codewords from the plurality of decoded signals.

[0161] During 904, the receiver determines an output codeword from a plurality of valid codewords as an estimate of the input signal.

[0162] At least part of the decoding at the plurality of decoders may be performed simultaneously. In other words, the plurality of decoders may be configured to decode the input signal in parallel.

[0163] Fig. 9B Operations that may be performed by a receiver including multiple decoders are shown.

[0164] During 901', the receiver receives an encoded input signal y at a first decoder of a plurality of decoders. The encoded input signal may include a signal transmitted by a transmitter through a channel between the transmitter and the receiver.

[0165] During 902 ′, the receiver, at a first decoder, decodes an input signal by processing check nodes in a first order to obtain a first decoded signal x1.

[0166] During 903 ′, the receiver determines whether to trigger a second decoder of the plurality of decoders to decode the encoded input signal based on the determination of whether the first decoded signal x1 is a valid codeword as an estimate of the input signal.

[0167] The receiver may trigger the second decoder to decode the input signal by processing the check nodes in a second order to obtain a second decoded signal x2 in response to determining that the second decoder is to be triggered (e.g., when it is determined that x1 is not a valid codeword as an estimate of the input signal), the second order being different from the first order. The receiver may determine whether the second decoded signal x2 is a valid codeword as an estimate of the input signal.

[0168] When determining that the first decoded signal is a valid codeword as an input signal estimate, the receiver may forgo sending a trigger to the second decoder to decode the input encoded signal by processing the check nodes in the second order. In this case, the receiver may declare the first decoded signal as an output codeword.

[0169] The receiver may, in response to determining that the second decoded signal is an invalid codeword, trigger a third decoder to decode the input signal by processing the check nodes in a third order to obtain a third decoded signal x3, the third order being different from the first order and the second order. The receiver may determine whether the third decoded signal x3 is a valid codeword as an estimate of the input signal.

[0170] exist FIG. 9A to FIG. 9B In all of the above examples, the receiver may be further configured to: generate at least one of the first order or the second order randomly or pseudo-randomly.

[0171] exist FIG. 9A to FIG. 9BIn all of the above examples, a decoder in the plurality of decoders may include at least one of: a flooding belief propagation decoder, a row-layered belief propagation decoder, or a column-layered belief propagation decoder. For example, the first decoder and / or the second decoder may include at least one of: a flooding belief propagation decoder, a row-layered belief propagation decoder, or a column-layered belief propagation decoder.

[0172] exist FIG. 9A to FIG. 9B In all of the above examples, the receiver may also be configured to: decode the input encoded signal at at least one of the first decoder or the second decoder by processing the check nodes in the first order and / or the second order to obtain at least one other decoded signal x L '; Determine another valid codeword x from at least one other decoded signal L ';Determine another output codeword from another valid codeword as an estimate of another input signal, wherein the output codeword is based on the first code and the other output codeword is based on the second code. In other words, the receiver described herein can be used to decode a received input encoded signal that was encoded using a different code. For example, the first code can include a low-density parity check code and the second code can include a polar code.

[0173] exist FIG. 9A to FIG. 9B In all of the above examples, the valid codewords may include codewords of linear block codes.

[0174] Fig.10 Operations that may be performed by an apparatus are shown. The apparatus may be included in a decoder. The decoder may be included as part of a receiver. The receiver may receive signals wirelessly and / or via a wired connection. The apparatus may be included in a user equipment. The apparatus may be included in an access node (e.g., a gNB). The apparatus may include a network node (e.g., a receiver located within a network).

[0175] During 1001, the apparatus inputs a first received encoded signal into a first decoder and a second decoder, wherein the first decoder is configured to decode the first received encoded signal by processing check nodes in a first order, and the second decoder is configured to decode the first received encoded signal by processing check nodes in a second order.

[0176] The first order may include a first schedule. In other words, the first order may include a first check node update order. The second order may include a second schedule. In other words, the second order may include a second check node update order.

[0177] The first received coded signal may include a signal received by a receiver through a channel. The first received coded signal may include a signal portion (coded by a transmitter of the first received coded signal) and a noise portion (introduced by transmitting the signal portion from the transmitter over the channel).

[0178] It should be understood that "first" and "second" are used above and below to distinguish different devices (e.g., different decoders (and their various signals)). This does not limit the technology currently described below to two such devices, and it should be understood that more than two such devices may be included in the device and perform corresponding features of the first and second devices mentioned throughout the text.

[0179] During 1002, the apparatus outputs a corresponding estimate word from at least one of a first decoder or a second decoder by processing a first received encoded signal at the at least one of the first decoder or the second decoder.

[0180] During 1003, the apparatus determines an output codeword based on the corresponding estimated word.

[0181] During 1004, the apparatus determines whether the first received encoded signal has been correctly decoded by determining whether the determined output codeword is a valid codeword.

[0182] When the device determines that the first received encoded signal has been correctly decoded, the device may output a codeword (eg, the determined output codeword) to continue processing the first received encoded signal.

[0183] When the device determines that the first received encoded signal has been decoded incorrectly, the device can directly declare a decoding failure by indicating that a block error has occurred. In the case of a decoding failure, the device can select an output codeword according to a predetermined metric that is intended to reduce the number of bits identified as errors.

[0184] The first decoder and the second decoder may be arranged in series. For example, the first decoder may determine the first estimated word by processing the check nodes in the first order, determine whether the first estimated word is a valid codeword, and when the first estimated word is determined to be an invalid codeword, send the following trigger to the second decoder: decode the first received encoded signal by processing the check nodes in the second order. When the first estimated word is determined to be a valid codeword, the first decoder may abandon sending the following trigger to the second decoder: decode the first received encoded signal by processing the check nodes in the second order. In the case where the first estimated word is determined to be a valid codeword, the second decoder does not decode the first received encoded signal. The second decoder may discard the first received encoded signal.

[0185] The first decoder and the second decoder may be arranged in parallel. For example, the first decoder and the second decoder may simultaneously process the first received encoded signal at the first decoder and the second decoder. In this case, the first decoder may determine the first estimated word by processing the check nodes in a first order, and the second decoder may determine the second estimated word by processing the check nodes in a second order. Then, the first estimated word and the second estimated word may be used to perform the determination of the output codeword.

[0186] As described above, the device may include a cascade mechanism. For example, the device may input the first received encoded signal into a third decoder, wherein the third decoder is configured to decode the first received encoded signal by processing each check node, output a third estimated word from the third decoder by processing the first received encoded signal at the third decoder, determine whether the first received encoded signal has been correctly decoded by determining whether the third estimated word is a valid codeword, and when determining that the third estimated word is an invalid codeword, trigger the first decoder and / or the second decoder to execute output of the corresponding estimated word. The third decoder may include any type of decoder. As an example, the third decoder may include Figure 4B and / or Figure 4C As an example, only when the third estimated word is an invalid codeword, the first decoder and / or the second decoder can be triggered to perform output.

[0187] The apparatus may generate at least one of the first sequence and the second sequence randomly or pseudo-randomly.

[0188] The first decoder and / or the second decoder may include at least one of: a flooding belief propagation decoder, a row-layered belief propagation decoder, or a column-layered belief propagation decoder.

[0189] The apparatus described herein may be used for a variety of different types of codes (e.g., Reed Muller, polar codes, LDPC codes, etc.). For example, the apparatus may: input a second received encoded signal into a first decoder and a second decoder, output an additional corresponding estimated word from at least one of the first decoder or the second decoder by processing the second received encoded signal at the at least one of the first decoder or the second decoder; determine a second output codeword based on (multiple) additional corresponding estimated words, and determine whether the second received encoded signal has been correctly decoded by determining whether the determined second codeword is a valid codeword, wherein the first codeword is based on the first code and the second codeword is based on the second code. For example, the first code may include a low density parity check code and the second code may include a polar code.

[0190] In all of the above examples, the valid codeword may include a codeword of a linear block code. In other words, the apparatus described above (e.g., Figures 6 to 10 Any of ) can be used to encode signals using any linear block code.

[0191] The above description provides a complete and informative description of some examples by way of non-limiting examples. However, in view of the foregoing description, when read in conjunction with the accompanying drawings and claims, various modifications and adaptations may become apparent to those skilled in the relevant art. However, all such teachings and similar modifications will still fall within the scope of the claims.

[0192] In the above description, different examples are described using radio access architectures based on Long Term Evolution Advanced (LTE Advanced, LTE-A) or New Radio (NR, 5G) as examples of access architectures to which the described techniques can be applied, without limiting the examples to such architectures. These examples can also be applied to other kinds of communication networks with suitable devices by appropriately adjusting parameters and steps. Some examples of other options for suitable systems are Universal Mobile Telecommunications System (UMTS) Radio Access Network (UTRAN), Wireless Local Area Network (WLAN or Wi-Fi), Worldwide Interoperability for Microwave Access (WiMAX), Personal Communications Service (PCS), Wideband Code Division Multiple Access (WCDMA), systems using Ultra-Wideband (UWB) technology, sensor networks, mobile ad hoc networks (MANETs), and Internet Protocol Multimedia Subsystem (IMS), or any combination thereof.

[0193] As provided herein, various aspects are described in the detailed description of the examples and in the claims. Typically, some examples may be implemented in hardware or dedicated circuits, software code, logic, or any combination thereof. For example, some aspects may be implemented by hardware, while other aspects may be implemented in firmware or software code, which may be executed by a controller, microprocessor, or other computing device, but the examples are not limited thereto. Although various examples may be illustrated and described by block diagrams, flow charts, or using some other graphical representations, it should be understood that the boxes, devices, systems, techniques, or methods described herein may be implemented as hardware, software code, firmware code, dedicated circuits or logic, general hardware or controllers or other computing devices, or some combination thereof in non-limiting examples.

[0194] The examples may be implemented by a computer software code stored in a memory and executed by at least one data processor of the entity involved, or by hardware, or by a combination of software code and hardware.

[0195] The memories mentioned herein may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as semiconductor-based memory devices, magnetic memory devices and systems, optical memory devices and systems, fixed memory and removable memory.

[0196] The (data) processors referred to herein may be of any type suitable for the local technical environment, and may include, by way of non-limiting example, one or more of general-purpose computers, special-purpose computers, microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), FPGAs, gate-level circuits, and processors based on multi-core processor architectures.

[0197] Furthermore, in this regard, it should be noted that, for example, Fig. 9A and / or Fig. 9B and / or Fig.10 In and / or in other previously described, any step may represent the operation of a computer program deployed by at least one processor included in the device (where the computer program includes instructions for causing the device to perform at least one action, the instructions being represented as software code stored on at least one memory), or interconnected logic circuits, blocks and functions, or a combination of the operation of a computer program deployed by at least one processor included in the device and logic circuits, blocks and functions. The software code may be stored on a memory, such as a physical medium as a memory chip, or a memory block implemented within a processor, a magnetic medium (such as a hard disk or floppy disk), and an optical medium (e.g., a DVD and its data variants, a CD, etc.).

[0198] The memory may be of any type suitable for the local technical environment and may be implemented using any suitable data storage technology, such as semiconductor-based memory devices, magnetic memory devices and systems, optical memory devices and systems, fixed memory, and removable memory. As non-limiting examples, the data processor may be of any type suitable for the local technical environment and may include one or more of general-purpose computers, special-purpose computers, microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), gate-level circuits, and processors based on multi-core processor architectures.

[0199] Additionally or alternatively, some examples may be implemented using a circuit system. The circuit system may be configured to perform one or more of the previously described functions and / or method steps. The circuit system may be provided in a base station and / or in a communication device and / or in a core network entity.

[0200] As used in this application, the term "circuitry" or "component" may refer to one or more or all of the following: (a) only implemented in hardware circuits (such as implemented only in analog and / or digital circuit systems); (b) Combination of hardware circuits and software codes, such as: (i) a combination of analog and / or digital hardware circuits and software / firmware code and (ii) a hardware processor with software code (including digital signal processor(s)), any portion of the software code and memory(s) that work together to enable an apparatus such as a communication device or base station to perform the various functions previously described; and (c) Hardware circuit(s) and or processor(s), such as microprocessor(s) or portion(s) of microprocessor(s), which requires software code (e.g., firmware) For operation, but the software code may not be present when the operation is not required.

[0201] This definition of circuitry applies to all uses of the term in this application, including in any claims. As another example, as used in this application, the term circuitry also covers an implementation of merely a hardware circuit or processor (or multiple processors) or a portion of a hardware circuit or processor and its accompanying software and / or firmware code. The term circuitry also covers, for example, an integrated device.

[0202] Implementations of the present disclosure can be practiced in various components such as integrated circuit modules. The design of integrated circuits is a highly automated process. Complex and powerful software tools can be used to convert logic level designs into semiconductor circuit designs ready for etching and formation on semiconductor substrates.

[0203] As used herein, similar expressions such as “at least one of: a list of two or more elements” and “at least one of a list of two or more elements” where a list of two or more elements is connected by “and” or “or” refer to at least any one of the elements, or at least any two or more of the elements, or at least all of the elements.

[0204] As used herein, the term "non-transitory" is a limitation of the medium itself (ie, tangible rather than a signal), not a limitation on data storage persistence (eg, RAM versus ROM).

[0205] The scope of protection sought for various examples of the present disclosure is set forth by the independent claims. Examples and features described in this specification that do not belong to the scope of the independent claims are to be construed as examples that help understand the present disclosure.

[0206] The above description provides a complete and informative description of the exemplary implementation of the present disclosure by way of non-limiting example. However, in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims, various modifications and adaptations may become apparent to those skilled in the relevant art. However, all of these teachings and similar modifications of the present disclosure will still fall within the scope of the present invention as defined in the appended claims. In fact, there are further implementations that include a combination of one or more implementations of any other implementation previously discussed.

Claims

1. A receiver comprising a plurality of decoders, the receiver being configured to: receiving (901) an encoded input signal y at each decoder of the plurality of decoders; At each of the plurality of decoders, the input signal is decoded (902) by processing the check nodes in a corresponding order to obtain a plurality of decoded signals x1, ..., x L , the corresponding order is different for the plurality of decoders; determining (903) a plurality of valid codewords from the plurality of decoded signals; as well as An output codeword is determined (904) from the plurality of valid codewords as an estimate of the input signal. 2 . The receiver of claim 1 , wherein at least part of the decoding at the plurality of decoders is performed simultaneously.

3. A receiver comprising a plurality of decoders, the receiver being configured to: Receiving (901') an encoded input signal y at a first decoder of the plurality of decoders; At the first decoder, decoding (902') the input signal by processing the check nodes in a first order to obtain a first decoded signal x1; and Based on the determination of whether the first decoded signal x1 is a valid codeword as an estimate of the input signal, it is determined (903') whether a second decoder of the plurality of decoders is to be triggered to decode the encoded input signal.

4. The receiver according to claim 3, further configured to: In response to determining that the second decoder is to be triggered, triggering the second decoder to decode the input signal by processing check nodes in a second order to obtain a second decoded signal x2, the second order being different from the first order; and It is determined whether the second decoded signal x2 is a valid codeword as an estimate of the input signal.

5. The receiver according to claim 3, further configured to: When the first decoded signal is determined to be a valid codeword, sending a trigger to the second decoder to decode the encoded input signal by processing check nodes in a second order is forgone.

6. The receiver according to any one of claims 4 to 5, wherein the receiver is further configured to: In response to determining that the second decoded signal is an invalid codeword, triggering a third decoder to decode the input signal by processing check nodes in a third order to obtain a third decoded signal x3, the third order being different from the first order and the second order; and It is determined whether the third decoded signal x3 is a valid codeword as an estimate of the input signal.

7. A receiver according to any preceding claim, further configured to generate at least one of the first or second order randomly or pseudo-randomly.

8. A receiver according to any preceding claim, wherein the plurality of decoders comprises at least one of: a flooding belief propagation decoder, a row-layered belief propagation decoder or a column-layered belief propagation decoder.

9. A receiver according to any one of the preceding claims, wherein the receiver is further configured to: At at least one of the first decoder or the second decoder, decoding the encoded further input signal by processing one or more check nodes in the first order and / or the second order to obtain at least one other decoded signal x L '; From the at least one other decoded signal x L 'Determine another valid codeword; as well as determining a further output codeword from the further valid codeword as an estimate of the further input signal, Wherein the output codeword is based on a first code and the another output codeword is based on a second code.

10. The receiver of claim 9, wherein the first code comprises a low density parity check code and the second code comprises a polar code.

11. A receiver according to any preceding claim, wherein the valid codeword comprises a codeword of a linear block code.

12. A receiver according to any preceding claim, wherein the receiver is comprised in a user equipment, or wherein the receiver is comprised in an access network node.

13. A method for decoding an encoded input signal at a receiver comprising a plurality of decoders, the method comprising: receiving (901) an encoded input signal y at each decoder of the plurality of decoders; At each of the plurality of decoders, the input signal is decoded (902) by processing the check nodes in a corresponding order to obtain a plurality of decoded signals x1, ..., x L , the corresponding order is different for the plurality of decoders; determining (903) a plurality of valid codewords from the plurality of decoded signals; as well as An output codeword is determined (904) from the plurality of valid codewords as an estimate of the input signal.

14. A computer program comprising instructions which, when executed by a receiver comprising a plurality of decoders, cause the receiver to: receiving (901) an encoded input signal y at each decoder of the plurality of decoders; At each of the plurality of decoders, the input signal is decoded (902) by processing the check nodes in a corresponding order to obtain a plurality of decoded signals x1, ..., x L , the corresponding order is different for the plurality of decoders; determining (903) a plurality of valid codewords from the plurality of decoded signals; as well as An output codeword is determined (904) from the plurality of valid codewords as an estimate of the input signal.

15. A method for decoding an encoded input signal at a receiver comprising a plurality of decoders, the method comprising: Receiving (901') an encoded input signal y at a first decoder of the plurality of decoders; At the first decoder, decoding (902') the input signal by processing the check nodes in a first order to obtain a first decoded signal x1; and Based on the determination of whether the first decoded signal is a valid codeword as an estimate of the input signal, it is determined (903') whether a second decoder of the plurality of decoders is to be triggered to decode the encoded input signal.

16. A computer program comprising instructions which, when executed by a receiver comprising a plurality of decoders, cause the receiver to: Receiving (901') an encoded input signal y at a first decoder of the plurality of decoders; At the first decoder, decoding (902') the input signal by processing the check nodes in a first order to obtain a first decoded signal x1; and Based on the determination of whether the first decoded signal is a valid codeword as an estimate of the input signal, it is determined (903') whether a second decoder of the plurality of decoders is to be triggered to decode the encoded input signal.

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