Data processing method and device, accelerator card, storage medium and program product

Abstract

The invention discloses a data processing method and device, an accelerator card, a storage medium and a program product, and is applied to the accelerator card deployed with a field programmable gate array, and the method comprises the steps: carrying out the cross-clock domain conversion of received message information, and obtaining the converted message information; the message information is high-clock-domain small-bit data, and the converted message information is low-clock-domain large-bit data; the converted message information is analyzed, the analyzed message information is obtained, and the analyzed message information comprises the data to be processed; performing multi-path splitting on the to-be-processed data to obtain multi-path data; encrypting / decrypting the multiple paths of data in a parallel encryption / decryption mode to obtain multiple paths of encrypted / decrypted data; and splicing the multiple paths of encrypted / decrypted data to obtain encrypted / decrypted data corresponding to the to-be-processed data. By adopting the method, the data encryption / decryption speed can be increased.

Description

Technical Field

[0001] The present application relates to the field of data processing, and in particular to a data processing method, device, accelerator card, storage medium and program product. Background Art

[0002] With the continuous development and popularization of cloud computing technology, encryption algorithms play an important role in cloud computing. They can protect the privacy and security of user data and ensure the security and credibility of cloud services.

[0003] At present, the Blowfish algorithm is generally used in cloud computing technology to encrypt / decrypt data, thereby providing security for data transmission. However, the encryption rate of Blowfish in a 32-bit microprocessor is 26 clock cycles per byte; if 64KB of content is to be processed, 64*1024*26 clock cycles are required; if the computer device has a pre-installed operating system (32-bit home standard version) processor with a processor main frequency of 2.4GHz; the total time required for data encryption / decryption using the Blowfish algorithm is 709.9733us. It can be seen that at present, the speed of data encryption / decryption using the Blowfish algorithm is slow.

[0004] Therefore, how to improve the speed of data encryption / decryption has become an urgent problem to be solved. Summary of the invention

[0005] The embodiments of the present application provide a data processing method, device, acceleration card, storage medium and program product, which can improve the speed of data encryption / decryption.

[0006] In a first aspect, the present application provides a data processing method, which is applied to an accelerator card deployed with a field programmable gate array, and the method includes:

[0007] Performing cross-clock domain conversion on the received message information to obtain converted message information; the message information is small-bit data in the high clock domain, and the converted message information is large-bit data in the low clock domain;

[0008] Parsing the converted message information to obtain parsed message information, wherein the parsed message information includes data to be processed;

[0009] Decompose the data to be processed into multiple channels to obtain multiple channels of data;

[0010] Encrypting / decrypting multiple channels of data by means of parallel encryption / decryption to obtain multiple channels of encrypted / decrypted data;

[0011] The multiple encrypted / decrypted data are concatenated to obtain the encrypted / decrypted data corresponding to the data to be processed.

[0012] In one of the embodiments, the parsed message information also includes a message header, and the method also includes: obtaining the message header, and combining the message header and the encrypted / decrypted data to obtain a combined message; the combined message is low clock domain large bit data; performing cross-clock domain conversion on the combined message to obtain a target message; the target message is high clock domain small bit data; and outputting the target message.

[0013] In one of the embodiments, multiple data are encrypted / decrypted by parallel encryption / decryption to obtain multiple encrypted / decrypted data, including: encrypting / decrypting multiple data by parallel multi-channel Blowfish encryption / decryption algorithm to obtain multiple encrypted / decrypted data.

[0014] In one of the embodiments, before performing cross-clock domain conversion on the received message information to obtain the converted message information, the method also includes: receiving a custom message from a host in the device; the custom message includes multiple sub-keys and multiple initialization parameters; the multiple initialization parameters include multiple P arrays and multiple S boxes; the multiple sub-keys are the same or different; based on the custom message, configuring the parameters in the encryption logic domain and the decryption logic domain; after determining that the encryption logic domain and the decryption logic domain have completed the parameter configuration, sending indication information to the host to indicate that the encryption logic domain and the decryption logic domain have completed the parameter configuration, so that the host uses the acceleration card to perform data encryption / decryption.

[0015] In one of the embodiments, based on a custom message, parameters in an encryption logic domain and a decryption logic domain in an acceleration card are configured, including: parsing the custom message to obtain multiple subkeys and multiple initialization parameters; based on the multiple subkeys and multiple initialization parameters, configuring parameters in the encryption logic domain and the decryption logic domain in the acceleration card.

[0016] In one of the embodiments, parameters in the encryption logic domain and the decryption logic domain in the acceleration card are configured based on multiple subkeys and multiple initialization parameters, including: performing key expansion based on each subkey and each initialization parameter to obtain multiple expanded keys; and configuring parameters in the encryption logic domain and the decryption logic domain in the acceleration card based on the multiple expanded keys.

[0017] In a second aspect, the present application provides a data processing device, which is applied to an accelerator card deployed with a field programmable gate array, and the device includes:

[0018] A data conversion module, used to perform cross-clock domain conversion on the received message information to obtain converted message information; the message information is small-bit data in the high clock domain, and the converted message information is large-bit data in the low clock domain;

[0019] A message parsing module, used for parsing the converted message information to obtain parsed message information, wherein the parsed message information includes data to be processed;

[0020] A data splitting / joining module is used to split the data to be processed into multiple channels to obtain multiple channels of data;

[0021] A data encryption / decryption module is used to encrypt / decrypt multiple channels of data in a parallel encryption / decryption manner to obtain multiple channels of encrypted / decrypted data;

[0022] The data splitting / splicing module is also used to splice multiple encrypted / decrypted data to obtain encrypted / decrypted data corresponding to the data to be processed.

[0023] In a third aspect, the present application provides an accelerator card, the accelerator card includes a memory and a field programmable gate array, the memory stores a computer program, and the field programmable gate array implements the following steps when executing the computer program:

[0024] Performing cross-clock domain conversion on the received message information to obtain converted message information; the message information is small-bit data in the high clock domain, and the converted message information is large-bit data in the low clock domain;

[0025] Parsing the converted message information to obtain parsed message information, wherein the parsed message information includes data to be processed;

[0026] Decompose the data to be processed into multiple channels to obtain multiple channels of data;

[0027] Encrypting / decrypting multiple channels of data by means of parallel encryption / decryption to obtain multiple channels of encrypted / decrypted data;

[0028] The multiple encrypted / decrypted data are concatenated to obtain the encrypted / decrypted data corresponding to the data to be processed.

[0029] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the following steps are implemented:

[0030] Performing cross-clock domain conversion on the received message information to obtain converted message information; the message information is small-bit data in the high clock domain, and the converted message information is large-bit data in the low clock domain;

[0031] Parsing the converted message information to obtain parsed message information, wherein the parsed message information includes data to be processed;

[0032] Decompose the data to be processed into multiple channels to obtain multiple channels of data;

[0033] Encrypting / decrypting multiple channels of data by means of parallel encryption / decryption to obtain multiple channels of encrypted / decrypted data;

[0034] The multiple encrypted / decrypted data are concatenated to obtain the encrypted / decrypted data corresponding to the data to be processed.

[0035] In a fifth aspect, the present application further provides a computer program product, including a computer program, which implements the following steps when executed by a processor:

[0036] Performing cross-clock domain conversion on the received message information to obtain converted message information; the message information is small-bit data in the high clock domain, and the converted message information is large-bit data in the low clock domain;

[0037] Parsing the converted message information to obtain parsed message information, wherein the parsed message information includes data to be processed;

[0038] Decompose the data to be processed into multiple channels to obtain multiple channels of data;

[0039] Encrypting / decrypting multiple channels of data by means of parallel encryption / decryption to obtain multiple channels of encrypted / decrypted data;

[0040] The multiple encrypted / decrypted data are concatenated to obtain the encrypted / decrypted data corresponding to the data to be processed.

[0041] The above-mentioned data processing method, device, acceleration card, storage medium and program product, the acceleration card can perform cross-clock domain conversion on the received message information to obtain the converted message information; the message information is small-bit data in the high clock domain, and the converted message information is large-bit data in the low clock domain; the converted message information is parsed to obtain the parsed message information, and the parsed message information includes the data to be processed; the data to be processed is split into multiple channels to obtain multiple channels of data; the multiple channels of data are encrypted / decrypted by parallel encryption / decryption to obtain multiple channels of encrypted / decrypted data; the multiple channels of encrypted / decrypted data are spliced ​​to obtain the encrypted / decrypted data corresponding to the data to be processed. By adopting this method, the acceleration card converts the small-bit message information in the high-clock domain into the large-bit message information in the low-clock domain (for example, data with a bit width of 1024 bits), and then splits the to-be-processed data in the large-bit message information in the low-clock domain into multiple data channels (for example, 16 channels of 64-bit data), and encrypts / decrypts the multiple data channels using multiple encryption / decryption algorithms in parallel. In this way, the parallelism of the acceleration card is fully utilized, thereby improving the speed of data encryption / decryption. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0043] Figure 1 It is a schematic diagram of the data encryption process;

[0044] Figure 2 It is a logical diagram of the F function;

[0045] Figure 3 It is a schematic diagram of the data decryption process;

[0046] Figure 4 It is a schematic diagram of implementing the Blowfish algorithm using an accelerator card;

[0047] Figure 5 It is a schematic diagram of an application scenario of a data processing method provided in an embodiment of the present application;

[0048] Figure 6 It is a flowchart of a data processing method provided in an embodiment of the present application;

[0049] Figure 7 It is a flowchart of another data processing method provided in an embodiment of the present application;

[0050] Figure 8 It is a schematic diagram of a custom message provided in an embodiment of the present application;

[0051] Fig. 9 This is a schematic diagram of a process of data encryption / decryption using an acceleration card provided in an embodiment of the present application;

[0052] Fig.10 is a structural schematic diagram of a data processing device provided in an embodiment of the present application;

[0053] Fig.11 It is a schematic diagram of the structure of an acceleration card provided in an embodiment of the present application. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0055] In order to facilitate understanding of the embodiments of the present application, some concepts involved in the embodiments of the present application are described below. The description of these concepts includes but is not limited to the following content.

[0056] 1. Field Programmable Gate Array (FPGA)

[0057] FPGA is a product further developed on the basis of programmable array logic (PAL), generic array logic (GAL) and other programmable devices. It emerged as a semi-custom circuit in the field of application specific integrated circuit (ASIC), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable devices.

[0058] 2. Feistel network and Feistel round function

[0059] The Feistel network is a symmetric structure used to construct block ciphers. Its advantage is that the encryption and decryption operations are very similar, and in some cases even identical, and only the key arrangement needs to be reversed. Therefore, the size of the code or circuit required to implement such a cipher can be almost halved. The Feistel network is an iterative cipher in which the internal function is called a round function.

[0060] 3. Blowfish encryption algorithm

[0061] Blowfish encryption and decryption algorithm is a 64-bit symmetric key encryption algorithm. The Blowfish encryption and decryption algorithm is based on the Feistel network. It generates subkeys through key expansion and then uses the subkeys for encryption and decryption. The subkeys include a P array and four S boxes. The S box is a nonlinear structure and plays a key role in obfuscating the relationship between the key and the ciphertext. During the encryption and decryption process, the key and the P box are operated to generate key-box and key-sbox for encryption and decryption operations. The Blowfish algorithm has the characteristics of fast encryption speed, compactness, variable key length, and free use.

[0062] The Blowfish encryption algorithm can be divided into two parts: key expansion and data encryption. The following introduces the key expansion and data encryption parts respectively.

[0063] (1) Key expansion

[0064] The key expansion part may include the following steps:

[0065] Step 1: Initialize the P array and S box.

[0066] The device (such as a computer device or an accelerator card, etc., which is not limited here) can use the decimal part of the constant (in hexadecimal form) to initialize the P array (18) and S box (4), for example:

[0067] P1 = 0x243F6A88, P2 = 0x85A208D3,...;

[0068] S4

[254] =0x578FDFE3, S4

[255] =0x3AC372E6.

[0069] Step 2: Perform an XOR operation on the subkey array and the initialized P array, where the subkey array is K1~K14, K1~K14 is part of the key array K, and K1~K4 needs to be reused later. The specific operations are as follows:

[0070] P1=P1 XOR K1, P2=P2 XOR K2,..., P14=P14 XOR K14;

[0071] Repeated use of K1~K4:

[0072] P15=P15 XOR K1, P16=P16 XOR K2, P17=P17 XOR K3, P18=P18 XOR K4.

[0073] Step 3: Generate encryption keys using the Blowfish algorithm.

[0074] The 64-bit block of all 0s is encrypted using the Blowfish algorithm to obtain a 64-bit ciphertext, which is then divided into two 32-bit blocks, replacing the initial values ​​of P1 and P2 respectively.

[0075] The output of the previous step is encrypted using the Blowfish algorithm and the modified subkey to obtain a 64-bit output, which is then divided into two 32-bit blocks, which are used to replace P3 and P4 respectively.

[0076] Using the Blowfish algorithm and the previous output, replace the rest of the P array (i.e., P5 to P18) and all elements of the four S-boxes in turn. In each step, take the output of the previous step as input and generate the next two 32-bit blocks (e.g., P5 and P6, then P7 and P8, and so on).

[0077] (2) Data encryption

[0078] See also Figure 1 , Figure 1 This is a schematic diagram of the data encryption process. Figure 1 As shown, the data encryption process may include but is not limited to the following steps:

[0079] Step 1: Data processing: Divide the 64-bit plaintext into two parts of equal length, XL and XR.

[0080] Step 2: Iterative encryption: Iteratively encrypt the first 16 rounds. The operations of each round include:

[0081] Divide the 32-bit XL block into four 8-bit sub-blocks, named a, b, c, and d, and calculate the value of the F function (Feistel round function). Figure 2 As shown, Figure 2 It is a logical diagram of the F function. The functions of the F function are:

[0082] F[a, b, c, d] =((S1(a) + S2(b)) XOR S3(c))+S4(d)

[0083] Perform data mixing and transformation operations to obtain encrypted output.

[0084] Step 3, last round of operations: In the last round, cancel the swap of Swap XL, XR in round 16, and then perform the same operation.

[0085] Step 4: Merge to obtain ciphertext: Merge XL and XR obtained after iterative encryption to obtain the final 64-bit ciphertext.

[0086] (3) Data decryption

[0087] See also Figure 3 , Figure 3 This is a schematic diagram of the data decryption process. Figure 3 As shown, the data decryption process is similar to Figure 1 The data encryption process shown is similar, except that the P array is used in reverse order, and the data decryption process is not described here.

[0088] See also Figure 4 , Figure 4 This is a schematic diagram of using an accelerator card to implement the Blowfish algorithm. Figure 4As shown, the accelerator card can split the input data into two 32-bit data, and then implement data encryption based on F function calculation, XOR operation and beat control. Among them, the integration of the Blowfish encryption submodule and the Blowfish decryption submodule is convenient and flexible to call. The accelerator card only needs to change the address sequence of reading the parameter RAM based on the different macro parameters received (parameters pre-determined based on business needs (encryption or decryption)); the P parameters after the extended key are stored in the parameter RAM in the order of (P0, P1, ..., P18). Since the Blowfish decryption submodule needs to use the P parameters in reverse order in the decryption module, it can read the RAM address in reverse order.

[0089] At present, the Blowfish algorithm is generally used in cloud computing technology to encrypt / decrypt data, thereby providing security for data transmission. However, the encryption rate of Blowfish in a 32-bit microprocessor is 26 clock cycles per byte; if 64KB of content is to be processed, 64*1024*26 clock cycles are required; if the computer device has a pre-installed operating system (32-bit home standard version) processor with a processor main frequency of 2.4GHz; the total time required for data encryption / decryption using the Blowfish algorithm is 709.9733us. It can be seen that at present, the speed of data encryption / decryption using the Blowfish algorithm is slow.

[0090] Based on this, the embodiment of the present application provides a data processing method, device, acceleration card, storage medium and program product, which can improve the speed of data encryption / decryption. The method includes: performing cross-clock domain conversion on the received message information to obtain the converted message information; the message information is small-bit data in the high clock domain, and the converted message information is large-bit data in the low clock domain; parsing the converted message information to obtain the parsed message information, and the parsed message information includes the data to be processed; splitting the data to be processed into multiple channels to obtain multiple channels of data; encrypting / decrypting the multiple channels of data by parallel encryption / decryption to obtain multiple channels of encrypted / decrypted data; splicing the multiple channels of encrypted / decrypted data to obtain the encrypted / decrypted data corresponding to the data to be processed. By adopting this method, the acceleration card converts the small-bit message information in the high-clock domain into the large-bit message information in the low-clock domain (for example, data with a bit width of 1024 bits), and then splits the to-be-processed data in the large-bit message information in the low-clock domain into multiple data channels (for example, 16 channels of 64-bit data), and encrypts / decrypts the multiple data channels using multiple encryption / decryption algorithms in parallel. In this way, the parallelism of the acceleration card is fully utilized, thereby improving the speed of data encryption / decryption.

[0091] Combine the following Figure 5 , the application scenarios of the data processing method provided in the embodiments of the present application are introduced.

[0092] See also Figure 5 , Figure 5 Schematic diagram of an application scenario of a data processing method provided in an embodiment of the present application. Figure 5 As shown, it includes a computer device 101 and a network device 102, wherein the computer device 101 includes an accelerator card 1011 deployed with a field programmable gate array and a host 1012.

[0093] The host 1012 in the computer device 101 can send message information to the acceleration card 1011 through the PCIE interface, and correspondingly, the acceleration card 1011 can receive the message information. Then, the acceleration card 1011 can convert the received message information of high clock domain small bit data into message information of low clock domain large bit data, and obtain the data to be processed included in the converted message information; then, the acceleration card 1011 can split the data to be processed into multiple data channels, encrypt / decrypt the multiple data channels by parallel encryption / decryption, and obtain multiple encrypted / decrypted data; then, the acceleration card 1011 can splice the multiple encrypted / decrypted data to obtain the encrypted / decrypted data corresponding to the data to be processed; further, the acceleration card 1011 can also obtain the message header included in the converted message information, and combine the message header and the encrypted / decrypted data to obtain a combined message, wherein the combined message is low clock domain large bit data; then, the acceleration card 1011 also performs cross-clock domain conversion on the combined message to obtain a target message; the target message is high clock domain small bit data; and the target message is sent to the network device 102. By adopting this method, the acceleration card 1011 converts the small-bit message information in the high-clock domain into large-bit message information in the low-clock domain (for example, data with a bit width of 1024 bits), and then splits the to-be-processed data in the large-bit message information in the low-clock domain into multiple data channels (for example, 16 channels of 64-bit data), and encrypts / decrypts the multiple data channels using multiple encryption / decryption algorithms in parallel. In this way, the parallelism of the acceleration card is fully utilized, thereby improving the speed of data encryption / decryption.

[0094] The specific process of the data processing method provided in the embodiment of the present application is described in detail below.

[0095] See also Figure 6 , Figure 6 is a flow chart of a data processing method provided by an embodiment of the present application. The method can be implemented by an accelerator card (e.g., Figure 6 The accelerator card 1011 in the system is executed. Figure 6 As shown, the data processing method may include but is not limited to the following steps:

[0096] S601. Perform cross-clock domain conversion on received message information to obtain converted message information; the message information is small-bit data in the high clock domain, and the converted message information is large-bit data in the low clock domain.

[0097] In an optional implementation, the converted message information may be low clock domain large bit data with a bit width of 1024 bits.

[0098] S602: Parse the converted message information to obtain parsed message information, where the parsed message information includes data to be processed.

[0099] That is to say, after step S601, the acceleration card can parse the message information of the low clock domain large bit data to obtain the parsed message information.

[0100] S603, split the data to be processed into multiple channels to obtain multiple channels of data.

[0101] Exemplarily, assuming that the bit width of the data to be processed is 1024 bits, the acceleration card demultiplexes the data to be processed to obtain multiple data paths. The data to be processed with a bit width of 1024 bits can be demultiplexed into 16 paths according to the bit width to obtain 16 paths of data, where the bit width of each path of data is 64 bits.

[0102] S604: Encrypt / decrypt multiple channels of data in a parallel encryption / decryption manner to obtain multiple channels of encrypted / decrypted data.

[0103] Continuing with the above example, assuming that the multiple data channels are 16 channels of data and the bit width of each channel of data is 64 bits, the accelerator card can encrypt / decrypt the 16 channels of 64-bit data through 16-channel parallel encryption / decryption to obtain 16 channels of encrypted / decrypted data with a bit width of 64 bits.

[0104] S605: splice the multiple encrypted / decrypted data to obtain the encrypted / decrypted data corresponding to the data to be processed.

[0105] Continuing with the above example, assuming that the multi-channel encrypted / decrypted data is 16 channels of encrypted / decrypted data, and the bit width of each channel of encrypted / decrypted data is 64 bits, the acceleration card can splice the 16 channels of encrypted / decrypted data into 1 channel of data with a bit width of 1024 bits, and the 1 channel of data with a bit width of 1024 bits is the encrypted / decrypted data corresponding to the data to be processed.

[0106] In the embodiment of the present application, the acceleration card can perform cross-clock domain conversion on the received message information to obtain the converted message information; the message information is small bit data in the high clock domain, and the converted message information is large bit data in the low clock domain; the converted message information is parsed to obtain the parsed message information, and the parsed message information includes the data to be processed; the data to be processed is split into multiple channels to obtain multiple channels of data; the multiple channels of data are encrypted / decrypted in a parallel encryption / decryption manner to obtain multiple channels of encrypted / decrypted data; the multiple channels of encrypted / decrypted data are spliced ​​to obtain the encrypted / decrypted data corresponding to the data to be processed. Using this method, the acceleration card converts the high clock domain small bit message information into low clock domain large bit message information (for example, bit width 1024 bits (bit) data), and then splits the data to be processed in the low clock domain large bit message information into multiple channels of data (for example, 16 channels of 64bit data), and encrypts / decrypts the multiple channels of data in parallel using multiple encryption / decryption algorithms, so that the parallelism of the acceleration card is fully utilized, thereby improving the speed of data encryption / decryption.

[0107] See also Figure 7 , Figure 7 is a flow chart of another data processing method provided in an embodiment of the present application. Figure 6 The data processing method shown differs in that Figure 7 The data processing method shown also describes how the accelerator card outputs the encrypted / decrypted data to other devices. Figure 7 As shown, the data processing method may include but is not limited to the following steps:

[0108] S701. Perform cross-clock domain conversion on received message information to obtain converted message information; the message information is small-bit data in the high clock domain, and the converted message information is large-bit data in the low clock domain.

[0109] S702: Parse the converted message information to obtain parsed message information, where the parsed message information includes data to be processed.

[0110] In an optional implementation, the parsed message information also includes a message header. In this implementation, the accelerator card can also store the message header for subsequent use in message combination.

[0111] S703, split the data to be processed into multiple channels to obtain multiple channels of data.

[0112] S704, encrypting / decrypting multiple channels of data in a parallel encryption / decryption manner to obtain multiple channels of encrypted / decrypted data.

[0113] S705: splice the multiple encrypted / decrypted data to obtain the encrypted / decrypted data corresponding to the data to be processed.

[0114] In an optional implementation, the relevant descriptions of steps S701 to S705 can refer to the descriptions of the aforementioned steps S501 to S505, and will not be repeated here.

[0115] S706. Obtain a message header, and combine the message header and the encrypted / decrypted data to obtain a combined message; the combined message is low clock domain large-bit data.

[0116] In an optional implementation, before step S706, the accelerator card may obtain a message header from the memory. The message header stored in the memory may be the message header included in the parsed message information obtained by the accelerator card after executing step S702. That is, after step S702, the accelerator card also stores the message header included in the parsed message information in the memory.

[0117] S707 . Perform cross-clock domain conversion on the combined message to obtain a target message; the target message is small-bit data in the high clock domain.

[0118] That is, after executing step S706 and obtaining the combined message of the low clock domain large bit data, the accelerator card can also convert the combined message into a target message of the high clock domain small bit data, so as to facilitate the subsequent output of the target message.

[0119] S708: Output the target message.

[0120] In an optional implementation, if the device where the acceleration card is located is a sending device, the acceleration card may encrypt the message information after receiving the message information. In this case, when executing step S704, the acceleration card specifically encrypts multiple data channels by parallel encryption to obtain multiple encrypted data; when executing step S705, the specific implementation is to splice the multiple encrypted data channels to obtain encrypted data corresponding to the data to be processed; when executing step S706, the specific implementation is to obtain the message header, and combine the message header and the encrypted data to obtain a combined message.

[0121] In this implementation manner, the target message finally obtained by the acceleration card refers to the encrypted message information.

[0122] In this implementation, the accelerator card outputs the target message by outputting the target message to the network device through an optical port.

[0123] In another optional implementation, if the device where the acceleration card is located is a receiving device, the acceleration card can decrypt the message information after receiving the encrypted message information. In this case, when the acceleration card executes step S704, it specifically decrypts multiple data by parallel decryption to obtain multiple decrypted data; when executing step S705, it specifically splices the multiple decrypted data to obtain the decrypted data corresponding to the data to be processed; when executing step S706, it specifically obtains the message header, and combines the message header and the decrypted data to obtain the combined message.

[0124] In this implementation manner, the target message finally obtained by the acceleration card refers to the decrypted message information.

[0125] In this implementation manner, the accelerator card outputs the target message by transmitting the target message to the host of the device through a high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIE) interface.

[0126] In the embodiment of the present application, on the one hand, the acceleration card can convert the high-clock domain small-bit message information into the low-clock domain large-bit message information (for example, 1024-bit (bit) data), and then split the to-be-processed data in the low-clock domain large-bit message information into multiple data channels (for example, 16 channels of 64-bit data), and encrypt / decrypt the multiple data channels through multiple parallel encryption / decryption algorithms. In this way, the parallelism of the acceleration card is fully utilized, thereby improving the speed of data encryption / decryption. On the other hand, the acceleration card can obtain the message header in the low-clock domain large-bit message information, and combine the obtained message header and the encrypted / decrypted data to obtain a combined message; perform cross-clock domain conversion on the combined message to obtain a target message; and output the target message. In this way, it can be ensured that the target message is an encrypted message, so that when the target message is output, the security of data transmission can be improved.

[0127] In addition, taking the example of encrypting / decrypting 16 channels of data in parallel, the clock in the accelerator card runs at 400MHz, and 18 beats process 1024 bits, that is, 128B; therefore, the hardware needs (64KB / 128B)*18 beats = 9213 clock cycles to process 64KB of content, corresponding to 23.04us. It can be seen that compared with Blowfish processing 64KB of content in a 32-bit microprocessor, the encryption / decryption time is greatly shortened and the encryption / decryption speed is improved.

[0128] In an optional implementation, the acceleration card further initializes and configures the encryption logic domain and the decryption logic domain before executing step S601 or S701.

[0129] In this implementation, the acceleration card may perform initialization configuration of the encryption logic domain and the decryption logic domain, including but not limited to the following steps:

[0130] Step 1: receiving a custom message from a host in the device; the custom message includes multiple subkeys and multiple initialization parameters; the multiple initialization parameters include multiple P arrays and multiple S boxes; the multiple subkeys are the same or different.

[0131] See also Figure 8 , Figure 8 Schematic diagram of a custom message provided in an embodiment of the present application. Figure 8 As shown, the custom message includes multiple subkeys ( Figure 8 In the example of two subkeys key) and multiple initialization parameters ( Figure 8 In the figure, two subkeys are used as an example for drawing).

[0132] Among them, the 3-bit control status field in the custom message header is 3'b011, which is sent to the host in the device where the accelerator card is located through the serial port. Optionally, the 3-bit control status field in the custom header may include but is not limited to the following representations: 3'b001 represents writing keys and parameters; 3'b010 represents reading keys and parameters; 3'b011 represents normal completion of initialization; 3'b100 represents initialization exception; 3'b101 represents read return; 3'b000 is invalid; 3'b110; 3'b111 is reserved.

[0133] In an optional implementation, the custom message can carry different keys and parameters for the sending direction and the receiving direction respectively. In this way, the independence of the sending channel and the receiving channel can be guaranteed. Even if the sending channel is cracked, the receiving channel will not be easily cracked because it uses different keys and initialization parameters.

[0134] In another optional implementation, the custom message can carry the same key and parameters for self-test. For example, if there is only one accelerator card, two fiber cards can be looped back and the same key and parameters can be used for self-encryption and self-decryption to perform self-test.

[0135] In an optional implementation, the accelerator card receives the custom message from the host in the device through a serial port. That is, the host in the device where the accelerator card is located can send the custom message to the accelerator card through the serial port.

[0136] Step 2: Based on the custom message, configure the parameters in the encryption logic domain and the decryption logic domain.

[0137] In an optional implementation, the acceleration card configures parameters in the encryption logic domain and the decryption logic domain in the acceleration card based on a custom message, which may include: parsing the custom message to obtain multiple sub-keys and multiple initialization parameters; based on the multiple sub-keys and the multiple initialization parameters, configuring the parameters in the encryption logic domain and the decryption logic domain in the acceleration card.

[0138] In this implementation, the accelerator card configures parameters in the encryption logic domain and the decryption logic domain in the accelerator card based on multiple subkeys and multiple initialization parameters, which may include: performing key expansion based on each subkey and each initialization parameter to obtain multiple expanded keys; and configuring parameters in the encryption logic domain and the decryption logic domain in the accelerator card based on the multiple expanded keys.

[0139] Step three: after determining that both the encryption logic domain and the decryption logic domain have completed parameter configuration, send indication information to the host indicating that both the encryption logic domain and the decryption logic domain have completed parameter configuration, so that the host uses the acceleration card to perform data encryption / decryption.

[0140] With this implementation, after receiving a custom message from the host in the device, the accelerator card can extract the key and the parameters for initializing p_box and s_box in the message, and complete the parameter configuration of the encryption logic domain and the decryption logic domain based on the extracted parameters. In this way, for the accelerator card, by receiving a custom message, all the parameters required for parameter configuration (including key expansion) of the encryption logic domain and the decryption logic domain can be obtained from one message, thereby improving the speed of parameter configuration (including key expansion) for the encryption logic domain and the decryption logic domain; for the host in the device where the accelerator card is located, all the parameters required for configuration can be sent down through one message, thereby avoiding the multiple response processes of traditional register request / response.

[0141] See also Fig. 9 , Fig. 9 Schematic diagram of a process of using an acceleration card to perform data encryption / decryption provided by an embodiment of the present application. Fig. 9 As shown in the figure, when the accelerator card is initialized, the host in the device where the accelerator card is located can send a custom message through the serial port (such as Figure 8The accelerator card can parse the custom message, extract the key and parameters (including initializing the P array and the S box) and send them to the key expansion module. The key expansion module will send the parameters to the encryption logic part and the decryption logic domain. When the parameter configuration of the two domains is completed, they will each send a completion (high level valid) signal. Finally, the key expansion module will AND these two completion signals to 1 to form an initialization completion message (that is, the key expansion module will determine the completion of the parameter configuration of the encryption logic domain and the decryption logic domain based on the completion information sent by the encryption logic domain and the decryption logic domain, that is, the completion of the initialization configuration).

[0142] Among them, when the accelerator card works normally, according to the different devices where the accelerator card is located, it can be divided into two parts: the data processing process in the sending direction and the data processing process in the receiving direction. Among them, if the device where the accelerator card is located is a sending device that sends message information, the host in the sending device where the accelerator card is located can pass the message information to the accelerator card through the PCIE interface, and then the accelerator card can perform cross-clock domain conversion on the received message information, and output a message with a bit width of 1024 bits (that is, the converted message information); after that, the accelerator card can parse the message with a bit width of 1024 bits, put the parsed message header into the message header cache, align the remaining part of the message payload (that is, the data to be processed) by 64 bits, and then split the 1024 bits into 16 * 64 according to the bit width. bit; then, the acceleration card can pass the 16-channel data to the 16-channel parallel Blowfish encryption module (after receiving the data and the key, the data encryption module uses the Blowfish algorithm to encrypt the data), and re-splice the output 16-channel encrypted data into 1024 bits (that is, the encrypted data); further, the acceleration card can take out the message header from the message header cache, and splice the message header and the encrypted data; finally, by performing cross-clock conversion on the spliced ​​message (combined message), the target message (that is, the encrypted message corresponding to the message information) is obtained, and the target message is output through the optical port.

[0143] If the device where the accelerator card is located is a receiving device for receiving message information, the accelerator card can first receive the message information from the optical fiber port 1, perform cross-clock domain conversion on the received message information, and output a message with a bit width of 1024 bits (i.e., the converted message information); secondly, the accelerator card can parse the message with a bit width of 1024 bits, put the parsed message header into the message header cache, align the remaining message payload (i.e., the data to be processed) with 64 bits, and then split the 1024 bits into 16 channels * 64 bits according to the bit width; then, the accelerator card can send the 16 channels of ciphertext to the 16 The accelerator card can further extract the message header from the message header cache and perform message splicing on the message header and the decrypted data; finally, the target message (the decrypted message corresponding to the message information) is obtained by performing cross-clock conversion on the spliced ​​message (the combined message), and the target message is transmitted to the host in the device through the PCIE interface.

[0144] It should be understood that although Figure 6 and Figure 7 The steps in the flowchart shown are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 6 and Figure 7 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0145] See also Fig.10 , Fig.10 Schematic diagram of a data processing device provided in an embodiment of the present application. Fig.10 As shown, the device includes but is not limited to the following modules:

[0146] The data conversion module 1001 is used to perform cross-clock domain conversion on the received message information to obtain the converted message information; the message information is small-bit data in the high clock domain, and the converted message information is large-bit data in the low clock domain;

[0147] The message parsing module 1002 is used to parse the converted message information to obtain parsed message information, wherein the parsed message information includes data to be processed;

[0148] The data splitting / joining module 1003 is used to split the data to be processed into multiple channels to obtain multiple channels of data;

[0149] The data encryption / decryption module 1004 is used to encrypt / decrypt multiple channels of data in a parallel encryption / decryption manner to obtain multiple channels of encrypted / decrypted data;

[0150] The data splitting / splicing module 1003 is also used to splice multiple encrypted / decrypted data to obtain encrypted / decrypted data corresponding to the data to be processed.

[0151] In one embodiment, the parsed message information also includes a message header, and the device also includes an acquisition module, a message combination module, and an output module. The acquisition module is used to acquire the message header; the message combination module is used to combine the message header and the encrypted / decrypted data to obtain a combined message; the combined message is low clock domain large bit data; the data conversion module 1001 is also used to perform cross-clock domain conversion on the combined message to obtain a target message; the target message is high clock domain small bit data; the output module is used to output the target message.

[0152] In one embodiment, the data encryption / decryption module 1004 is used to encrypt / decrypt multiple data channels by means of parallel encryption / decryption to obtain multiple encrypted / decrypted data. Specifically, it is used to encrypt / decrypt multiple data channels by means of parallel multi-channel Blowfish encryption / decryption algorithm to obtain multiple encrypted / decrypted data.

[0153] In one embodiment, the device further includes a receiving module, a configuration module, and a sending module. Among them, before the data conversion module 1001 is used to perform cross-clock domain conversion on the received message information and obtain the converted message information, the receiving module is used to receive a custom message from the host in the device; the custom message includes multiple subkeys and multiple initialization parameters; the multiple initialization parameters include multiple P arrays and multiple S boxes; the multiple subkeys are the same or different; the configuration module is used to configure the parameters in the encryption logic domain and the decryption logic domain based on the custom message; the sending module is used to send an indication information to the host to indicate that the encryption logic domain and the decryption logic domain have completed the parameter configuration after determining that the encryption logic domain and the decryption logic domain have completed the parameter configuration, so that the host uses the acceleration card to perform data encryption / decryption.

[0154] In one embodiment, when the configuration module is used to configure the parameters in the encryption logic domain and the decryption logic domain in the acceleration card based on the custom message, it is specifically used to: parse the custom message to obtain multiple sub-keys and multiple initialization parameters; based on the multiple sub-keys and multiple initialization parameters, configure the parameters in the encryption logic domain and the decryption logic domain in the acceleration card.

[0155] In one embodiment, when the configuration module is used to configure the parameters in the encryption logic domain and the decryption logic domain in the acceleration card based on multiple subkeys and multiple initialization parameters, it is specifically used to: perform key expansion based on each subkey and each initialization parameter to obtain multiple expanded keys; based on the multiple expanded keys, configure the parameters in the encryption logic domain and the decryption logic domain in the acceleration card.

[0156] For the specific definition of the data processing device, please refer to the definition of the data processing method above, which will not be repeated here. Each module in the above data processing device can be implemented in whole or in part by software, hardware and a combination thereof. The above modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0157] In an exemplary embodiment, the present application provides an accelerator card, whose internal structure diagram can be as follows: Fig.11 As shown. The acceleration card includes a field programmable gate array, a memory, and an input / output interface. The field programmable gate array, the memory, and the input / output interface are connected via a system bus. The field programmable gate array in the acceleration card is used to provide computing and control capabilities. The memory of the acceleration card includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the acceleration card is used to exchange information between the field programmable gate array and an external device. When the computer program is executed by the field programmable gate array, a data processing method is implemented.

[0158] Those skilled in the art will understand that Fig.11 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0159] In an exemplary embodiment, the present application provides an accelerator card, including a memory and a field programmable gate array, wherein the memory stores a computer program, and the field programmable gate array implements the following steps when executing the computer program:

[0160] Performing cross-clock domain conversion on the received message information to obtain converted message information; the message information is small-bit data in the high clock domain, and the converted message information is large-bit data in the low clock domain;

[0161] Parsing the converted message information to obtain parsed message information, wherein the parsed message information includes data to be processed;

[0162] Decompose the data to be processed into multiple channels to obtain multiple channels of data;

[0163] Encrypting / decrypting multiple channels of data by means of parallel encryption / decryption to obtain multiple channels of encrypted / decrypted data;

[0164] The multiple encrypted / decrypted data are concatenated to obtain the encrypted / decrypted data corresponding to the data to be processed.

[0165] In one embodiment, the parsed message information also includes a message header, and the field programmable gate array executing the computer program further implements the following steps: obtaining the message header, and combining the message header and the encrypted / decrypted data to obtain a combined message; the combined message is low clock domain large bit data; the combined message is converted across clock domains to obtain a target message; the target message is high clock domain small bit data; and the target message is output.

[0166] In one embodiment, a field programmable gate array executes a computer program to encrypt / decrypt multiple channels of data by means of parallel encryption / decryption to obtain multiple channels of encrypted / decrypted data, and specifically implements the following steps: encrypt / decrypt multiple channels of data by means of a parallel multi-channel Blowfish encryption / decryption algorithm to obtain multiple channels of encrypted / decrypted data.

[0167] In one embodiment, a field programmable gate array executes a computer program to implement cross-clock domain conversion of received message information, and before obtaining the converted message information, the following steps are also implemented: receiving a custom message from a host in the device; the custom message includes multiple subkeys and multiple initialization parameters; the multiple initialization parameters include multiple P arrays and multiple S boxes; the multiple subkeys are the same or different; based on the custom message, configuring parameters in the encryption logic domain and the decryption logic domain; after determining that the encryption logic domain and the decryption logic domain have completed parameter configuration, sending indication information to the host to indicate that the encryption logic domain and the decryption logic domain have completed parameter configuration, so that the host uses the acceleration card to perform data encryption / decryption.

[0168] In one embodiment, when a field programmable gate array executes a computer program to configure parameters in an encryption logic domain and a decryption logic domain in an accelerator card based on a custom message, the following steps are specifically implemented: parsing the custom message to obtain multiple subkeys and multiple initialization parameters; and configuring parameters in the encryption logic domain and the decryption logic domain in the accelerator card based on the multiple subkeys and the multiple initialization parameters.

[0169] In one embodiment, when a field programmable gate array executes a computer program to configure parameters in an encryption logic domain and a decryption logic domain in an accelerator card based on multiple subkeys and multiple initialization parameters, the following steps are specifically implemented: key expansion is performed based on each subkey and each initialization parameter to obtain multiple expanded keys; based on the multiple expanded keys, the parameters in the encryption logic domain and the decryption logic domain in the accelerator card are configured.

[0170] In an exemplary embodiment, the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the following steps are implemented:

[0171] Performing cross-clock domain conversion on the received message information to obtain converted message information; the message information is small-bit data in the high clock domain, and the converted message information is large-bit data in the low clock domain;

[0172] Parsing the converted message information to obtain parsed message information, wherein the parsed message information includes data to be processed;

[0173] Decompose the data to be processed into multiple channels to obtain multiple channels of data;

[0174] Encrypting / decrypting multiple channels of data by means of parallel encryption / decryption to obtain multiple channels of encrypted / decrypted data;

[0175] The multiple encrypted / decrypted data are concatenated to obtain the encrypted / decrypted data corresponding to the data to be processed.

[0176] In one embodiment, the parsed message information also includes a message header, and the computer program executed by the processor also implements the following steps: obtaining the message header, and combining the message header and the encrypted / decrypted data to obtain a combined message; the combined message is low clock domain large bit data; the combined message is converted across clock domains to obtain a target message; the target message is high clock domain small bit data; and the target message is output.

[0177] In one embodiment, when a computer program is executed by a processor to encrypt / decrypt multiple data channels by means of parallel encryption / decryption and obtain multiple encrypted / decrypted data, the following steps are specifically implemented: encrypt / decrypt multiple data channels by means of a parallel multi-channel Blowfish encryption / decryption algorithm and obtain multiple encrypted / decrypted data.

[0178] In one embodiment, a computer program is executed by a processor to implement cross-clock domain conversion of received message information, and before obtaining the converted message information, the following steps are also implemented: receiving a custom message from a host in the device; the custom message includes multiple sub-keys and multiple initialization parameters; the multiple initialization parameters include multiple P arrays and multiple S boxes; the multiple sub-keys are the same or different; based on the custom message, the parameters in the encryption logic domain and the decryption logic domain are configured; after determining that the encryption logic domain and the decryption logic domain have completed the parameter configuration, sending an indication information to the host to indicate that the encryption logic domain and the decryption logic domain have completed the parameter configuration, so that the host uses the acceleration card to perform data encryption / decryption.

[0179] In one embodiment, when a computer program is executed by a processor to configure parameters in an encryption logic domain and a decryption logic domain in an accelerator card based on a custom message, the following steps are specifically implemented: parsing the custom message to obtain multiple subkeys and multiple initialization parameters; and configuring parameters in the encryption logic domain and the decryption logic domain in the accelerator card based on the multiple subkeys and the multiple initialization parameters.

[0180] In one embodiment, when a computer program is executed by a processor to configure parameters in an encryption logic domain and a decryption logic domain in an accelerator card based on multiple subkeys and multiple initialization parameters, the following steps are specifically implemented: key expansion is performed based on each subkey and each initialization parameter to obtain multiple expanded keys; based on the multiple expanded keys, the parameters in the encryption logic domain and the decryption logic domain in the accelerator card are configured.

[0181] In an exemplary embodiment, the present application provides a computer program product, including a computer program, which implements the following steps when executed by a processor:

[0182] Performing cross-clock domain conversion on the received message information to obtain converted message information; the message information is small-bit data in the high clock domain, and the converted message information is large-bit data in the low clock domain;

[0183] Parsing the converted message information to obtain parsed message information, wherein the parsed message information includes data to be processed;

[0184] Decompose the data to be processed into multiple channels to obtain multiple channels of data;

[0185] Encrypting / decrypting multiple channels of data by means of parallel encryption / decryption to obtain multiple channels of encrypted / decrypted data;

[0186] The multiple encrypted / decrypted data are concatenated to obtain the encrypted / decrypted data corresponding to the data to be processed.

[0187] In one embodiment, the parsed message information also includes a message header, and the computer program executed by the processor also implements the following steps: obtaining the message header, and combining the message header and the encrypted / decrypted data to obtain a combined message; the combined message is low clock domain large bit data; the combined message is converted across clock domains to obtain a target message; the target message is high clock domain small bit data; and the target message is output.

[0188] In one embodiment, when a computer program is executed by a processor to encrypt / decrypt multiple data channels by means of parallel encryption / decryption and obtain multiple encrypted / decrypted data, the following steps are specifically implemented: encrypt / decrypt multiple data channels by means of a parallel multi-channel Blowfish encryption / decryption algorithm and obtain multiple encrypted / decrypted data.

[0189] In one embodiment, a computer program is executed by a processor to implement cross-clock domain conversion of received message information, and before obtaining the converted message information, the following steps are also implemented: receiving a custom message from a host in the device; the custom message includes multiple sub-keys and multiple initialization parameters; the multiple initialization parameters include multiple P arrays and multiple S boxes; the multiple sub-keys are the same or different; based on the custom message, the parameters in the encryption logic domain and the decryption logic domain are configured; after determining that the encryption logic domain and the decryption logic domain have completed the parameter configuration, sending an indication information to the host to indicate that the encryption logic domain and the decryption logic domain have completed the parameter configuration, so that the host uses the acceleration card to perform data encryption / decryption.

[0190] In one embodiment, when a computer program is executed by a processor to configure parameters in an encryption logic domain and a decryption logic domain in an accelerator card based on a custom message, the following steps are specifically implemented: parsing the custom message to obtain multiple subkeys and multiple initialization parameters; and configuring parameters in the encryption logic domain and the decryption logic domain in the accelerator card based on the multiple subkeys and the multiple initialization parameters.

[0191] In one embodiment, when a computer program is executed by a processor to configure parameters in an encryption logic domain and a decryption logic domain in an accelerator card based on multiple subkeys and multiple initialization parameters, the following steps are specifically implemented: key expansion is performed based on each subkey and each initialization parameter to obtain multiple expanded keys; based on the multiple expanded keys, the parameters in the encryption logic domain and the decryption logic domain in the accelerator card are configured.

[0192] It should be noted that the data involved in this application (including but not limited to message information, converted message information, parsed message information, data to be processed, multi-channel data, encrypted / decrypted data, combined messages, target messages, etc.) are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with relevant regulations.

[0193] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0194] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0195] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the present application. It should be noted that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A data processing method, characterized in that: Applied to an accelerator card deployed with a field programmable gate array, the method comprises: Performing cross-clock domain conversion on the received message information to obtain converted message information; the message information is small-bit data in the high clock domain, and the converted message information is large-bit data in the low clock domain; Parsing the converted message information to obtain parsed message information, wherein the parsed message information includes data to be processed; Decomposing the data to be processed into multiple channels to obtain multiple channels of data; Encrypting / decrypting the multiple channels of data in a parallel encryption / decryption manner to obtain multiple channels of encrypted / decrypted data; The encrypted / decrypted data of multiple channels are concatenated to obtain the encrypted / decrypted data corresponding to the data to be processed.

2. The method according to claim 1, characterized in that: The parsed message information also includes a message header, and the method further includes: Acquire the message header, and combine the message header and the encrypted / decrypted data to obtain a combined message; the combined message is the low clock domain large bit data; Performing cross-clock domain conversion on the combined message to obtain a target message; the target message is the high clock domain small bit data; Output the target message.

3. The method according to claim 1, characterized in that The method of encrypting / decrypting the multiple channels of data in a parallel encryption / decryption manner to obtain the multiple channels of encrypted / decrypted data includes: The multiple-channel data are encrypted / decrypted by a parallel multi-channel Blowfish encryption / decryption algorithm to obtain the multiple-channel encrypted / decrypted data.

4. The method according to claim 1, characterized in that: Before performing cross-clock domain conversion on the received message information to obtain the converted message information, the method further includes: Receiving a custom message from a host in the device; the custom message includes multiple subkeys and multiple initialization parameters; the multiple initialization parameters include multiple P arrays and multiple S boxes; the multiple subkeys are the same or different; Based on the custom message, configure parameters in the encryption logic domain and the decryption logic domain in the acceleration card; After determining that the encryption logic domain and the decryption logic domain have completed parameter configuration, indication information for indicating that the encryption logic domain and the decryption logic domain have completed parameter configuration is sent to the host, so that the host uses the acceleration card to perform data encryption / decryption.

5. The method according to claim 4, characterized in that The configuring parameters in the encryption logic domain and the decryption logic domain in the acceleration card based on the custom message includes: Parsing the custom message to obtain multiple subkeys and multiple initialization parameters; Based on the multiple subkeys and the multiple initialization parameters, the parameters in the encryption logic domain and the decryption logic domain in the acceleration card are configured.

6. The method according to claim 5, characterized in that The configuring of parameters in the encryption logic domain and the decryption logic domain in the acceleration card based on the multiple subkeys and the multiple initialization parameters includes: Performing key expansion based on each of the subkeys and each of the initialization parameters to obtain a plurality of expanded keys; Based on the multiple extended keys, parameters in the encryption logic domain and the decryption logic domain in the acceleration card are configured.

7. A data processing device, characterized in that: Applied to an accelerator card deployed with a field programmable gate array, the device comprises: A data conversion module, used for performing cross-clock domain conversion on the received message information to obtain converted message information; the message information is small-bit data in the high clock domain, and the converted message information is large-bit data in the low clock domain; A message parsing module, used for parsing the converted message information to obtain parsed message information, wherein the parsed message information includes data to be processed; A data splitting / joining module is used to split the data to be processed into multiple channels to obtain multiple channels of data; A data encryption / decryption module, used to encrypt / decrypt multiple channels of data in a parallel encryption / decryption manner to obtain multiple channels of encrypted / decrypted data; The data splitting / splicing module is also used to splice multiple channels of encrypted / decrypted data to obtain encrypted / decrypted data corresponding to the data to be processed.

8. An accelerator card, characterized in that: The acceleration card comprises a memory and a field programmable gate array, the memory stores a computer program, and the field programmable gate array implements the steps of any one of the methods of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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