Semiconductor memory device

Abstract

There is provided a semiconductor memory device including: a bit line on a substrate; a protruding insulating pattern on the bit line and in the channel trench; a first channel pattern and a second channel pattern extending along sidewalls of the channel trench and spaced apart from each other in the first direction; a channel interface layer extending along sidewalls of the channel trench and in contact with the first channel pattern and the second channel pattern; a first word line between the first channel pattern and the second channel pattern; a second word line between the first channel pattern and the second channel pattern, and spaced apart from the first word line in the first direction; and first and second capacitors electrically connected to the first and second channel patterns, respectively.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a vertical channel transistor (VCT). Background Art

[0002] It has been proposed to increase the integration of semiconductor memory devices to meet the excellent performance and low cost expected by consumers. In the case of semiconductor memory devices, since the integration is an important factor determining the price of the product, it is particularly necessary to increase the integration.

[0003] In the case of a two-dimensional or planar semiconductor memory device, since the integration degree is mainly determined by the area occupied by the unit memory cell, it is greatly affected by the technical level used to form fine patterns. However, since fine patterns require ultra-high-priced equipment, the integration degree of two-dimensional semiconductor memory devices is increasing, but may be limited. Therefore, a semiconductor memory device including a vertical channel transistor whose channel extends in the vertical direction has been proposed. Summary of the invention

[0004] An object of the present disclosure is to provide a semiconductor memory device having improved integration and electrical characteristics.

[0005] According to some aspects of the present inventive concept, a semiconductor memory device is provided, which includes: a bit line extending along a first direction on a substrate; a protruding insulating pattern on the bit line and in a channel trench; a first channel pattern extending along a first sidewall of the channel trench and including a first metal oxide; a second channel pattern extending along a second sidewall of the channel trench and including a first metal oxide and spaced apart from the first channel pattern in the first direction; a channel interface layer extending along a first sidewall and a second sidewall of the channel trench and contacting the first channel pattern and the second channel pattern; a first word line between the first channel pattern and the second channel pattern and extending in the second direction; a second word line between the first channel pattern and the second channel pattern, extending in the second direction and spaced apart from the first word line in the first direction; and a first capacitor and a second capacitor electrically connected to the first channel pattern and the second channel pattern, respectively, and on the first channel pattern and the second channel pattern.

[0006] According to some aspects of the present invention, a semiconductor memory device is provided, which includes: a peripheral gate structure on a substrate; a bit line on the peripheral gate structure and extending in a first direction; a protruding insulating pattern on the bit line and in a channel trench; a channel structure on the bit line and including a horizontal portion located inside the channel trench and a first vertical portion and a second vertical portion, the first vertical portion and the second vertical portion protruding from the horizontal portion, and the horizontal portion of the channel structure contacts the bit line; a channel interface layer between the protruding insulating pattern and the channel structure; a first word line on the channel structure, and the first word line extends in a second direction intersecting the first direction; a second word line on the channel structure, the second word line extends in the second direction and is spaced apart from the first word line in the first direction; a gate isolation pattern on the horizontal portion of the channel structure, the gate isolation pattern separating the first word line and the second word line from each other; and a first capacitor and a second capacitor, which are electrically connected to the first vertical portion of the channel structure and the second vertical portion of the channel structure, respectively.

[0007] According to some aspects of the present invention, a semiconductor memory device is provided, which includes: a peripheral gate structure on a substrate; a bit line on the peripheral gate structure, and the bit line extends in a first direction; a protruding insulating pattern on the bit line and in a channel trench; a channel structure on the bit line, the channel structure including a horizontal portion located inside the channel trench and a first vertical portion and a second vertical portion, the first vertical portion and the second vertical portion protruding from the horizontal portion, and the horizontal portion of the channel structure is separated from the bit line; a channel interface layer between the protruding insulating pattern and the channel structure, and between the bit line and the channel structure; a first word line on the channel structure, and the first word line extends in a second direction intersecting the first direction; a second word line on the channel structure, the second word line extends in the second direction and is spaced apart from the first word line in the first direction; a gate isolation pattern on the horizontal portion of the channel structure, the gate isolation pattern separating the first word line and the second word line from each other; and a first capacitor and a second capacitor, which are electrically connected to the first vertical portion of the channel structure and the second vertical portion of the channel structure, respectively.

[0008] However, the various aspects of the present disclosure are not limited to those set forth herein. For those skilled in the art to which the present disclosure pertains, the above and other aspects of the present disclosure will become more apparent by referring to the detailed description of the present disclosure given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects and features of the present disclosure will become more apparent by describing in detail illustrative embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0010] Figure 1 is a layout diagram illustrating a semiconductor memory device according to some embodiments.

[0011] Figure 2 is along Figure 1 A cross-sectional view taken along lines AA and BB.

[0012] Figure 3 is along Figure 1 A cross-sectional view taken along lines CC and DD.

[0013] Figures 4 to 6 It is shown Figure 2 An enlarged view of part P.

[0014] Figure 7 is a diagram illustrating a semiconductor memory device according to some embodiments.

[0015] Figure 8 is a diagram illustrating a semiconductor memory device according to some embodiments.

[0016] Fig. 9 is a diagram illustrating a semiconductor memory device according to some embodiments.

[0017] Fig.10 is a diagram illustrating a semiconductor memory device according to some embodiments.

[0018] Figures 11 to 13 is a diagram illustrating a semiconductor memory device according to some embodiments.

[0019] Figures 14 to 17 is a diagram illustrating a semiconductor memory device according to some embodiments.

[0020] Figures 18 to 21 is a diagram illustrating a semiconductor memory device according to some embodiments.

[0021] Figures 22 to 32 is a diagram illustrating a method for manufacturing a semiconductor memory device according to some embodiments.

[0022] Fig.33 and Fig.34 is a diagram illustrating a method for manufacturing a semiconductor memory device according to some embodiments. DETAILED DESCRIPTION

[0023] It will be understood that, although the terms "first", "second", etc. may be used herein to describe various elements or components, these elements or components should not be limited by these terms. These terms are only used to distinguish one element or component from another element or component. Therefore, without departing from the disclosed technical spirit, the first element or component discussed below may be referred to as the second element or component.

[0024] Figure 1 is a layout diagram illustrating a semiconductor memory device according to some embodiments. Figure 2 is along Figure 1 A cross-sectional view taken along lines AA and BB. Figure 3 is along Figure 1 A cross-sectional view taken along lines CC and DD. Figures 4 to 6 It is shown Figure 2 An enlarged view of part P.

[0025] A semiconductor memory device according to an embodiment of the present disclosure may include a memory cell including a vertical channel transistor (VCT).

[0026] Reference Figures 1 to 6 , a semiconductor memory device according to some embodiments may include a peripheral gate structure PG, a bit line BL, word lines WL1 and WL2 , a channel gate structure AP_ST, a protruding insulating pattern 175 , a channel interface layer CH_IF, and a data storage pattern DSP.

[0027] The substrate 100 may be a silicon substrate, or may include other materials such as silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0028] The peripheral gate structure PG may be disposed on the substrate 100. The substrate 100 may include a cell array region and a peripheral circuit region. The peripheral gate structure PG may be disposed above the cell array region and the peripheral circuit region. In other words, a portion of the peripheral gate structure PG may be disposed in the cell array region of the substrate 100, and the rest of the peripheral gate structure PG except the portion may be disposed in the peripheral circuit region of the substrate 100.

[0029] The peripheral gate structure PG may be included in a sensing transistor, a transfer transistor, a driving transistor, etc. The types of transistors disposed in the cell array region and the peripheral circuit region may vary according to the design layout of the semiconductor memory device.

[0030] The peripheral gate structure PG may include a peripheral gate insulating layer 215, a peripheral lower conductive pattern 223, and a peripheral upper conductive pattern 225. The peripheral gate insulating layer 215 may include a silicon oxide layer, a silicon oxynitride layer, a high dielectric constant insulating layer having a dielectric constant higher than that of the silicon oxide layer, or a combination thereof. The high dielectric constant insulating layer may include, for example, at least one of a metal oxide, a metal oxynitride, a metal silicon oxide, and a metal silicon oxynitride, but is not limited thereto.

[0031] Each of the peripheral lower conductive pattern 223 and the peripheral upper conductive pattern 225 may include a conductive material. For example, each of the peripheral lower conductive pattern 223 and the peripheral upper conductive pattern 225 may include at least one of a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbon nitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional (2D) material, a metal, and a metal alloy. The peripheral gate structure PG is shown as including a plurality of conductive patterns, but is not limited thereto.

[0032] In the semiconductor memory device according to some embodiments, the two-dimensional material may be a metal material and / or a semiconductor material. The two-dimensional (2D) material may include a two-dimensional allotrope or a two-dimensional compound, and may include, for example, graphene, molybdenum disulfide (MoS 2 ), Molybdenum diselenide (MoSe 2 ), tungsten diselenide (WSe 2 ) and tungsten disulfide (WS 2 ) at least one of, but not limited to. That is, since the above-mentioned two-dimensional materials are examples, the two-dimensional materials that can be included in the semiconductor memory device of the present disclosure are not limited to the above-mentioned materials.

[0033] The first and second peripheral lower insulating layers 227 and 228 are disposed on the substrate 100. Each of the first and second peripheral lower insulating layers 227 and 228 may be made of an insulating material.

[0034] The first peripheral wiring line 241a and the peripheral contact plug 241b may be disposed in the first peripheral lower insulating layer 227 and the second peripheral lower insulating layer 228. Although the first peripheral wiring line 241a and the peripheral contact plug 241b are shown as different films from each other, the present disclosure is not limited thereto. The boundary between the first peripheral wiring line 241a and the peripheral contact plug 241b may not be distinguished. Each of the first peripheral wiring line 241a and the peripheral contact plug 241b includes a conductive material.

[0035] The first peripheral upper insulating layer 261 and the second peripheral upper insulating layer 262 may be disposed on the first peripheral wiring line 241a and the peripheral contact plug 241b. Each of the first peripheral upper insulating layer 261 and the second peripheral upper insulating layer 262 may be made of an insulating material.

[0036] The second peripheral wiring line 243 and the peripheral via plug 242 are disposed on the first peripheral wiring line 241 a. The peripheral via plug 242 may be disposed in the first peripheral upper insulating layer 261. The second peripheral wiring line 243 may be disposed in the second peripheral upper insulating layer 262.

[0037] The second peripheral wiring line 243 and the peripheral via plug 242 may be connected to the first peripheral wiring line 241a. The peripheral via plug 242 may connect the first peripheral wiring line 241a to the second peripheral wiring line 243. Each of the second peripheral wiring line 243 and the peripheral via plug 242 includes a conductive material. The second peripheral wiring line 243 and the peripheral via plug 242 are shown as different films from each other, but are not limited thereto. The boundary between the second peripheral wiring line 243 and the peripheral via plug 242 may not be distinguished.

[0038] The third, fourth, and fifth peripheral upper insulating layers 263, 264, and 265 may be sequentially disposed on the second peripheral wiring line 243. Each of the third, fourth, and fifth peripheral upper insulating layers 263, 264, and 265 may be made of an insulating material.

[0039] The fourth peripheral upper insulating layer 264 may be made of an insulating material different from the insulating materials of the third peripheral upper insulating layer 263 and the fifth peripheral upper insulating layer 265. For example, the fourth peripheral upper insulating layer 264 may be made of an oxide-based insulating material including silicon. The third peripheral upper insulating layer 263 and the fifth peripheral upper insulating layer 265 may be made of a nitride-based insulating material including silicon, but are not limited thereto.

[0040] The cell connection plug 244 may be disposed in the third peripheral upper insulating layer 263, the fourth peripheral upper insulating layer 264, and the fifth peripheral upper insulating layer 265. The cell connection plug 244 may be connected to the second peripheral wiring line 243. The cell connection plug 244 includes a conductive material. Unlike the illustrated example, the peripheral upper insulating layer made of a single layer may be disposed on the second peripheral wiring line 243. In this case, the cell connection plug 244 may be disposed in the peripheral upper insulating layer made of a single layer.

[0041] The bit line BL is disposed on the peripheral gate structure PG. In more detail, the bit line BL may be disposed on the fifth peripheral upper insulating layer 265. For example, the bit line BL may contact the fifth peripheral upper insulating layer 265.

[0042] The bit lines BL may extend longitudinally in the second direction D2. The bit lines BL adjacent to each other may be spaced apart from each other in the first direction D1. The bit lines BL include long sidewalls extending in the second direction D2 and short sidewalls extending in the first direction D1.

[0043] Although not shown, each bit line BL may extend from the cell array region to the peripheral circuit region. An end portion of each bit line BL may be disposed on the peripheral circuit region of the substrate 100.

[0044] Each bit line BL may be disposed on the cell connection plug 244. Each bit line BL may be electrically and / or physically connected to the cell connection plug 244. Each bit line BL may include, for example, at least one of a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbon nitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material, and a metal. Each bit line BL is shown as a single layer, but is not limited thereto.

[0045] The cell lower insulating layer 171 may be disposed on the fifth peripheral upper insulating layer 265. The cell lower insulating layer 171 is disposed between the bit lines BL spaced apart from each other in the first direction D1. The cell lower insulating layer 171 may be made of an insulating material.

[0046] The protruding insulating pattern 175 may be disposed on the bit line BL and the cell lower insulating layer 171. The cell lower etch stop layer 173 may be disposed between the protruding insulating pattern 175 and the cell lower insulating layer 171.

[0047] The protruding insulating pattern 175 may include an upper protruding insulating pattern 175U and a lower protruding insulating pattern 175B. The lower protruding insulating pattern 175B may be disposed between the upper protruding insulating pattern 175U and the bit line BL and between the upper protruding insulating pattern 175U and the cell lower insulating layer 171. The lower protruding insulating pattern 175B may be disposed between the upper protruding insulating pattern 175U and the cell lower etch stop layer 173. The upper protruding insulating pattern 175U includes an upper surface of the protruding insulating pattern 175.

[0048] Each of the upper protruding insulating pattern 175U and the lower protruding insulating pattern 175B may be made of an insulating material. The upper protruding insulating pattern 175U and the lower protruding insulating pattern 175B may include their respective insulating materials different from each other. In a semiconductor memory device according to some embodiments, the upper protruding insulating pattern 175U may include silicon nitride, and the lower protruding insulating pattern 175B may include silicon oxide.

[0049] The cell lower etch stop layer 173 may be made of an insulating material. The cell lower etch stop layer 173 may include a material having an etching selectivity relative to the lower protruding insulating pattern 175B. Unlike the illustrated example, the cell lower etch stop layer 173 may not be disposed between the lower protruding insulating pattern 175B and the cell lower insulating layer 171.

[0050] The protruding insulating pattern 175 may include a plurality of channel trenches CH_T. Each of the channel trenches CH_T may extend longitudinally in the first direction D1. Adjacent channel trenches CH_T may be spaced apart from each other in the second direction D2.

[0051] Each channel trench CH_T crosses, overlaps, or intersects the bit line BL. One channel trench CH_T may expose a plurality of bit lines BL adjacent to each other in the first direction D1.

[0052] The bottom surface of each of the channel trenches CH_T may be defined by the bit line BL and the cell lower insulating layer 171. For example, a portion of the bottom surface of the channel trench CH_T may be the upper surface BL_US of the bit line. The sidewall of each channel trench CH_T may be defined by the lower protruding insulating pattern 175B, the upper protruding insulating pattern 175U, and the cell lower etch stop layer 173. At least a portion of the sidewall of the channel trench CH_T may be the sidewall 175SW of the protruding insulating pattern. When the cell lower etch stop layer 173 is not provided, the sidewall of each of the channel trenches CH_T may be defined by the lower protruding insulating pattern 175B and the upper protruding insulating pattern 175U.

[0053] The channel structure AP_ST may be disposed on each bit line BL. A plurality of channel structures AP_ST may be connected to one bit line BL. The plurality of channel structures AP_ST disposed on one bit line BL are spaced apart from each other in the second direction D2.

[0054] The channel structure AP_ST may be disposed inside a channel trench CH_T extending in the first direction D1. A plurality of channel structures AP_ST may be disposed inside one channel trench CH_T. The plurality of channel structures AP_ST disposed inside the channel trench CH_T are spaced apart from each other in the first direction D1.

[0055] For example, the channel structure AP_ST may be two-dimensionally disposed along a first direction D1 and a second direction D2 that cross or intersect each other.

[0056] The channel structure AP_ST may extend along the sidewall and the bottom surface of the channel trench CH_T. In a cross section cut along the second direction D2, the channel structure AP_ST may have a 'U' shape.

[0057] The channel structure AP_ST may include a horizontal portion AP_STH, a first vertical portion AP_STV1, and a second vertical portion AP_STV2. The first vertical portion AP_STV1 and the second vertical portion AP_STV2 of the channel structure may protrude from the horizontal portion AP_STH of the channel structure in a third direction D3.

[0058] The horizontal portion AP_STH of the channel structure may extend along a bottom surface of the channel trench CH_T. In a cross section cut along the second direction D2, the horizontal portion AP_STH of the channel structure may extend along an upper surface BL_US of the bit line.

[0059] The horizontal portion AP_STH of the channel structure is connected to the bit line BL. In the semiconductor memory device according to some embodiments, the channel structure AP_ST may be in contact with the bit line BL. For example, the horizontal portion AP_STH of the channel structure may be in contact with the bit line BL.

[0060] The first and second vertical portions AP_STV1 and AP_STV2 of the channel structure may extend along sidewalls of the channel trench CH_T. In a cross section cut along the second direction D2, the first and second vertical portions AP_STV1 and AP_STV2 of the channel structure may extend along sidewalls 175SW of the protruding insulating pattern 175, respectively.

[0061] The channel structure AP_ST may include an oxide semiconductor material. The channel structure AP_ST may include, for example, a first metal oxide. The first metal oxide is a semiconductor material. For example, the channel structure AP_ST may be an amorphous metal oxide layer. For another example, the channel structure AP_ST may be a polycrystalline metal oxide layer. For another example, the channel structure AP_ST may be a combination of an amorphous metal oxide layer and a polycrystalline metal oxide layer. For another example, the channel structure AP_ST may be a c-axis oriented crystal (CAAC) metal oxide layer.

[0062] The channel structure AP_ST may include, for example, indium oxide, tin oxide, zinc oxide, In-Zn-based oxide (IZO), Sn-Zn-based oxide, Al-Zn-based oxide, Zn-Mg-based oxide, Sn-Mg-based oxide, In-Mg-based oxide, In-Ga-based oxide (IGO), In-Ga-Zn-based oxide (IGZO), In-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-N At least one of In-D-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, In-Sn-Ga-Zn-based oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide and In-Hf-Al-Zn-based oxide, but not limited to these.

[0063] In this case, the In-Ga-Zn-based oxide refers to an oxide having In, Ga, and Zn as main components, but does not refer to the ratio of In, Ga, and Zn. That is, the channel structure AP_ST may include indium gallium zinc oxide (IGZO, In) as an example of indium gallium zinc oxide (IGZO). x Ga y Zn z O). IGZO (In:Ga:Zn=1:1:1) in which indium, gallium, and zinc are included in the same proportion may be an In-Ga-Zn based oxide. Ga-rich IGZO may have a gallium ratio higher than the gallium ratio of IGZO (In:Ga:Zn=1:1:1), and an indium ratio lower than the indium ratio of IGZO (In:Ga:Zn=1:1:1). Ga-rich IGZO may also be an In-Ga-Zn based oxide. In addition, In-rich IGZO may have an indium ratio higher than the indium ratio of IGZO (In:Ga:Zn=1:1:1), and a gallium ratio lower than the gallium ratio of IGZO (In:Ga:Zn=1:1:1). In-rich IGZO may also be an In-Ga-Zn based oxide.

[0064] The above description is made using IGZO, but is not limited thereto. When each of the channel structures AP_ST includes three or more metal oxides, the above description can be applied thereto. In addition, when the channel structure AP_ST includes an In-Ga-Zn-based oxide, the channel structure AP_ST may also include doped metal elements in addition to In, Ga, and Zn.

[0065] The channel structure AP_ST may include a first channel pattern AP1, a second channel pattern AP2, and a connection channel pattern AP_CP. The connection channel pattern AP_CP connects the first channel pattern AP1 with the second channel pattern AP2. The first channel pattern AP1 and the second channel pattern AP2 are spaced apart from each other in the second direction D2.

[0066] First channel pattern AP1, second channel pattern AP2, and connection channel pattern AP_CP are disposed on bit line BL. First channel pattern AP1 and second channel pattern AP2 are connected to bit line BL. In a semiconductor memory device according to some embodiments, first channel pattern AP1 and second channel pattern AP2 may contact upper surface BL_US of the bit line.

[0067] The first channel pattern AP1 may extend along the sidewall of the channel trench CH_T. The first channel pattern AP1 may include a portion of the horizontal portion AP_STH of the channel structure and a first vertical portion AP_STV1 of the channel structure. A portion of the horizontal portion AP_STH of the channel structure may be a horizontal portion of the first channel pattern AP1. The first vertical portion AP_STV1 of the channel structure may be a vertical portion of the first channel pattern AP1.

[0068] The second channel pattern AP2 may extend along the sidewall of the channel trench CH_T. The second channel pattern AP2 may include another portion of the horizontal portion AP_STH of the channel structure and a second vertical portion AP_STV2 of the channel structure. Another portion of the horizontal portion AP_STH of the channel structure may be a horizontal portion of the second channel pattern AP2. The second vertical portion AP_STV2 of the channel structure may be a vertical portion of the second channel pattern AP2.

[0069] The connection channel pattern AP_CP includes the remaining portion of the horizontal portion AP_STH of the channel structure.

[0070] The first channel pattern AP1, the second channel pattern AP2, and the connection channel pattern AP_CP may be distinguished based on the first word line WL1 and the second word line WL2 which will be described later. Figure 4 , the first word line WL1 will be described as an example. The first word line WL1 may include an inner sidewall facing the sidewall 175SW of the protruding insulating pattern and an outer sidewall opposite to the inner sidewall in the second direction D2. The boundary between the first channel pattern AP1 and the connection channel pattern AP_CP may be an extension line of the outer sidewall of the first word line WL1 extending in the third direction D3.

[0071] Each of the first channel pattern AP1 , the second channel pattern AP2 , and the connection channel pattern AP_CP includes a first metal oxide contained in a channel structure AP_ST.

[0072] The channel interface layer CH_IF may be disposed between the channel structure AP_ST and the protruding insulating pattern 175 . The channel interface layer CH_IF may be disposed between the first channel pattern AP1 and the protruding insulating pattern 175 . The channel interface layer CH_IF may be disposed between the second channel pattern AP2 and the protruding insulating pattern 175 .

[0073] The channel interface layer CH_IF may be in contact with the channel structure AP_ST. The channel interface layer CH_IF may be in contact with the first channel pattern AP1 and the second channel pattern AP2. In the semiconductor memory device according to some embodiments, the channel interface layer CH_IF may be in contact with the protruding insulating pattern 175. For example, the channel interface layer CH_IF may be in contact with the upper protruding insulating pattern 175U and / or the lower protruding insulating pattern 175B.

[0074] The channel interface layer CH_IF may extend along the sidewall of the channel trench CH_T. In the semiconductor memory device according to some embodiments, the channel interface layer CH_IF may not extend along the upper surface BL_US of the bit line. In other words, the channel interface layer CH_IF may not extend along the bottom surface of the channel trench CH_T. That is, the channel interface layer CH_IF may include only the vertical portion CH_IFV of the channel interface layer.

[0075] The channel interface layer CH_IF may extend to the bit line BL. The channel interface layer CH_IF may contact the bit line BL. For example, the channel interface layer CH_IF may contact the upper surface BL_US of the bit line.

[0076] The channel interface layer CH_IF may include at least one of silicon oxide, silicon oxynitride, silicon nitride, and metal oxide. When the channel interface layer CH_IF includes metal oxide, the channel interface layer CH_IF may include a second metal oxide different from the first metal oxide included in the channel structure AP_ST. Unlike the first metal oxide, the second metal oxide may be an insulating material. The second metal oxide may include, for example, at least one of aluminum oxide and hafnium oxide, but the technical spirit of the present disclosure is not limited thereto. That is, the channel interface layer CH_IF may include a metal oxide as an insulating material.

[0077] For example, when the channel interface layer CH_IF includes the same material as the upper protruding insulating pattern 175U, the boundary between the channel interface layer CH_IF and the upper protruding insulating pattern 175U may not be distinguished. The boundary between the channel interface layer CH_IF and the lower protruding insulating pattern 175B may be used to identify the boundary between the channel interface layer CH_IF and the upper protruding insulating pattern 175U.

[0078] Furthermore, when the boundary between the channel interface layer CH_IF and the cell lower etch stop layer 173 is not distinguished, the boundary between the channel interface layer CH_IF and the lower protruding insulating pattern 175B may also be used to identify the boundary between the channel interface layer CH_IF and the cell lower etch stop layer 173 .

[0079] For another example, when the channel interface layer CH_IF includes the same material as the lower protruding insulating pattern 175B, the boundary between the channel interface layer CH_IF and the lower protruding insulating pattern 175B may not be distinguished. The boundary between the channel interface layer CH_IF and the upper protruding insulating pattern 175U may be used to identify the boundary between the channel interface layer CH_IF and the lower protruding insulating pattern 175B.

[0080] When the channel structure AP_ST and the protruding insulating pattern 175 contact each other, the electrical characteristics of the semiconductor memory device may be deteriorated. Since the channel interface layer CH_IF is inserted between the channel structure AP_ST and the protruding insulating pattern 175, the interface characteristics of the channel structure AP_ST can be improved. As a result, the subthreshold swing (SS) and current characteristics of the semiconductor memory device can be improved.

[0081] In addition, the boundary traps may be distributed in the protruding insulating pattern 175. Due to the boundary traps, a threshold voltage V of a random noise telegram may be generated. th The channel interface layer CH_IF is interposed between the channel structure AP_ST and the protruding insulating pattern 175, so that the threshold voltage fluctuation of the semiconductor memory device may be improved.

[0082] The first word line WL1 and the second word line WL2 may be disposed on the channel structure AP_ST. The first word line WL1 and the second word line WL2 may be disposed inside the channel trench CH_T.

[0083] Each of the first word line WL1 and the second word line WL2 may extend in the first direction D1. The first word line WL1 and the second word line WL2 may be alternately arranged in the second direction D2. The first word line WL1 is spaced apart from the second word line WL2 in the second direction D2.

[0084] The first word line WL1 and the second word line WL2 are spaced apart from the bit line BL in the third direction D3. The first word line WL1 and the second word line WL2 cross the bit line BL.

[0085] The first word line WL1 and the second word line WL2 are disposed on the horizontal portion AP_STH of the channel structure. The first word line WL1 and the second word line WL2 are disposed between the first vertical portion AP_STV1 and the second vertical portion AP_STV2 of the channel structure.

[0086] The first word line WL1 is disposed on the first channel pattern AP1. The second word line WL2 is disposed on the second channel pattern AP2. The first word line WL1 and the second word line WL2 are disposed between the first channel pattern AP1 and the second channel pattern AP2. The first channel pattern AP1 is closer to the first word line WL1 than the second word line WL2. The second channel pattern AP2 is closer to the second word line WL2 than the first word line WL1.

[0087] Each of the first word line WL1 and the second word line WL2 may have a width in the second direction D2. The width of the first word line WL1 in a portion overlapping with the channel structure AP_ST along the third direction D3 may be different from the width of the first word line WL1 in a portion not overlapping with the channel structure AP_ST. The width of the second word line WL2 in a portion overlapping with the channel structure AP_ST along the third direction D3 may be different from the width of the second word line WL2 in a portion not overlapping with the channel structure AP_ST.

[0088] For example, each of the first word line WL1 and the second word line WL2 may include a first portion WLa of the word line and a second portion WLb of the word line. The width of the first portion WLa of the word line in the second direction D2 may be smaller than the width of the second portion WLb of the word line in the second direction D2. For example, the first portion WLa of the word line may be disposed on the channel structure AP_ST. The first portion WLa of the word line may be disposed on the first channel pattern AP1 and the second channel pattern AP2.

[0089] Each of the first word line WL1 and the second word line WL2 may include a first portion WLa of the word line and a second portion WLb of the word line alternately disposed along the first direction D1. Each of the channel structures AP_ST may be disposed between the second portions WLb of the word lines adjacent to each other along the first direction D1. In the first word line WL1, each of the first channel patterns AP1 may be disposed between the second portions WLb of the word lines adjacent to each other along the first direction D1. In the second word line WL2, each of the second channel patterns AP2 may be disposed between the second portions WLb of the word lines adjacent to each other along the first direction D1.

[0090] The channel structure AP_ST is not disposed below the second portion WLb of the word line. The height of the first portion WLa of the word line is less than the height of the second portion WLb of the word line. For example, the height difference between the first portion WLa of the word line and the second portion WLb of the word line may be the same as the thickness of the channel structure AP_ST.

[0091] The first word line WL1 and the second word line WL2 include a conductive material, and may include, for example, at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, a two-dimensional material, a metal, and a metal alloy.

[0092] Each of the first and second word lines WL1 and WL2 may include an upper surface WL_US and a bottom surface WL_BS opposite to each other in the third direction D3. The bottom surfaces of the first and second word lines WL1 and WL2 face (ie, are parallel to) the upper surface BL_US of the bit line.

[0093] exist Figure 4 In the embodiment, the upper surfaces WL_US of the first word line WL1 and the second word line WL2 may be planar. Figure 5 In the embodiment, the upper surfaces WL_US of the first word line WL1 and the second word line WL2 may be convex. Figure 6 In the embodiment, upper surfaces WL_US of the first word line WL1 and the second word line WL2 may be concave.

[0094] Based on the upper surface BL_US of the bit line, the upper surface WL_US of the first word line WL1 and the second word line WL2 may be higher than the uppermost portion AP_UUS of the vertical portions AP_STV1 and AP_STV2 of the channel structure. The uppermost portions of the channel patterns AP1 and AP2 may be the uppermost portion AP_UUS of the vertical portions AP_STV1 and AP_STV2 of the channel structure. A height H1 from the upper surface BL_US of the bit line to the uppermost portion AP_UUS of the vertical portions AP_STV1 and AP_STV2 of the channel structure may be less than a height H2 from the upper surface BL_US of the bit line to the upper surface WL_US of the first word line WL1 and the second word line WL2.

[0095] The uppermost portion AP_UUS of the channel structure is lower than the upper surface of the protruding insulating pattern 175 based on the upper surface BL_US of the bit line.

[0096] The gate insulating layer GOX may be disposed between the first word line WL1 and the channel structure AP_ST and between the second word line WL2 and the channel structure AP_ST. The gate insulating layer GOX may be disposed between the first word line WL1 and the first channel pattern AP1 and between the second word line WL2 and the second channel pattern AP2. The gate insulating layer GOX may extend in parallel with the first word line WL1 and the second word line WL2 in the first direction D1.

[0097] The gate insulating layer GOX may extend along the first vertical portion AP_STV1 of the channel structure. The gate insulating layer GOX may extend along the second vertical portion AP_STV2 of the channel structure. In the semiconductor memory device according to some embodiments, the gate insulating layer GOX may not be disposed on a horizontal portion AP_STH of the channel structure that does not overlap with the first word line WL1 and the second word line WL2 in the third direction D3. In a cross-sectional view, the gate insulating layer GOX between the first word line WL1 and the channel structure AP_ST may be separated from the gate insulating layer GOX between the second word line WL2 and the channel structure AP_ST.

[0098] The gate insulating layer GOX may include a silicon oxide layer, a silicon oxynitride layer, a high dielectric constant insulating layer having a dielectric constant higher than that of the silicon oxide layer, or a combination thereof.

[0099] A portion of the gate insulating layer GOX may protrude further than upper surfaces WL_US of the first and second word lines WL1 and WL2 in the third direction D3. A portion of the gate insulating layer GOX may protrude further than uppermost portions AP_UUS of the vertical portions AP_STV1 and AP_STV2 of the channel structures in the third direction D3.

[0100] A height H4 from the upper surface BL_US of the bit line to the uppermost portion GOX_UUS of the gate insulating layer may be greater than a height H1 from the upper surface BL_US of the bit line to the uppermost portion AP_UUS of the vertical portions AP_STV1 and AP_STV2 of the channel structure. A height H4 from the upper surface BL_US of the bit line to the uppermost portion GOX_UUS of the gate insulating layer may be greater than a height H2 from the upper surface of the bit line BL to the upper surfaces WL_US of the word lines WL1 and WL2.

[0101] The gate isolation pattern GSS may be disposed on the bit line BL and the cell lower insulating layer 171. The gate isolation pattern GSS may be disposed inside the channel trench CH_T. The gate isolation pattern GSS may be disposed on the channel structure AP_ST, the first word line WL1, and the second word line WL2.

[0102] In a semiconductor memory device according to some embodiments, a gate isolation pattern GSS may be in contact with a channel structure AP_ST. The gate isolation pattern GSS may be disposed on the connection channel pattern AP_CP. The gate isolation pattern GSS may be in contact with a horizontal portion AP_STH of the channel structure. The gate isolation pattern GSS may be spaced apart from a bit line BL in a third direction D3.

[0103] The gate isolation pattern GSS may be disposed between the first and second word lines WL1 and WL2 adjacent to each other in the second direction D2. The first and second word lines WL1 and WL2 may be separated from each other by the gate isolation pattern GSS. The gate isolation pattern GSS may extend in the first direction D1 between the first and second word lines WL1 and WL2.

[0104] The first word line WL1 may be disposed between the gate isolation pattern GSS and the channel structure AP_ST. The second word line WL2 may be disposed between the gate isolation pattern GSS and the channel structure AP_ST. The first word line WL1 may be disposed between the gate isolation pattern GSS and the first channel pattern AP1. The second word line WL2 may be disposed between the gate isolation pattern GSS and the second channel pattern AP2.

[0105] The gate isolation pattern GSS may include a horizontal portion and a protruding portion. The protruding portion of the gate isolation pattern GSS may protrude from the horizontal portion of the gate isolation pattern GSS toward the bit line BL in the third direction D3. The protruding portion of the gate isolation pattern GSS may be closer to the bit line BL than the horizontal portion of the gate isolation pattern GSS. The horizontal portion of the gate isolation pattern GSS may be disposed on the upper surface WL_US of the first word line WL1 and the second word line WL2. From a cross-sectional view, the gate isolation pattern may have a "T" shape.

[0106] The gate isolation pattern GSS may include a gate isolation liner 151, a gate isolation filling layer 153, and a gate isolation capping layer 155. The gate isolation liner 151 may extend along the upper surface WL_US of the first word line WL1 and the second word line WL2 and the outer sidewalls of the first word line WL1 and the second word line WL2. The gate isolation liner 151 may extend along the horizontal portion AP_STH of the channel structure. The gate isolation liner 151 may contact the connection channel pattern AP_CP. The gate isolation liner 151 may extend along the gate insulation layer GOX protruding more than the upper surface WL_US of the first word line WL1 and the second word line WL2. The gate isolation liner 151 may contact the side of the gate insulation layer GOX. Unlike the example shown, in some embodiments, the gate isolation liner 151 may not extend along the gate insulation layer GOX protruding more than the upper surface WL_US of the first word line WL1 and the second word line WL2.

[0107] The gate isolation filling layer 153 may be disposed on the gate isolation liner 151. The gate isolation capping layer 155 may be disposed on the gate isolation filling layer 153. Each of the gate isolation liner 151, the gate isolation filling layer 153, and the gate isolation capping layer 155 may be made of an insulating material. For example, the gate isolation liner 151 and the gate isolation capping layer 155 may be made of a nitride-based insulating material containing silicon, and the gate isolation filling layer 153 may be made of an oxide-based insulating material containing silicon, but is not limited thereto. Unlike the illustrated example, the gate isolation pattern GSS may be a single layer.

[0108] The upper surface GSS_US of the gate isolation pattern may be disposed at the same height as the upper surface of the protrusion insulating pattern 175 based on the upper surface BL_US of the bit line, but is not limited thereto.

[0109] A height H3 from the upper surface BL_US of the bit line to the upper surface GSS_US of the gate isolation pattern may be greater than a height H1 from the upper surface BL_US of the bit line to the uppermost portion AP_UUS of the vertical portions AP_STV1 and AP_STV2 of the channel structure. A height H3 from the upper surface BL_US of the bit line to the upper surface GSS_US of the gate isolation pattern may be greater than a height H2 from the upper surface BL_US of the bit line to the upper surfaces WL_US of the word lines WL1 and WL2.

[0110] A height H3 from the upper surface BL_US of the bit line to the upper surface GSS_US of the gate isolation pattern is shown to be equal to a height H4 from the upper surface BL_US of the bit line to the uppermost portion GOX_UUS of the gate insulation layer, but is not limited thereto.

[0111] The landing pad LP may be disposed on the channel structure AP_ST. The landing pad LP is connected to the first vertical portion AP_STV1 of the channel structure and the second vertical portion AP_STV2 of the channel structure.

[0112] The landing pad LP may be disposed on the first and second channel patterns AP1 and AP2. The landing pad LP is connected to the first and second channel patterns AP1 and AP2.

[0113] When viewed in a plan view, the landing pad LP may have various shapes such as a circle, an oval, a rectangle, a square, a diamond, and a hexagon.

[0114] The landing pad LP may include a horizontal portion LP_H and a protruding portion LP_P. The horizontal portion LP_H of the landing pad may be disposed on an upper surface of the protruding insulating pattern 175 and an upper surface GSS_US of the gate isolation pattern. The protruding portion LP_P of the landing pad may protrude from the horizontal portion LP_H of the landing pad toward the bit line BL in the third direction D3.

[0115] Based on the upper surface BL_US of the bit line, the lowermost portion of the landing pad LP may be lower than the upper surface GSS_US of the gate isolation pattern. In other words, the protruding portion LP_P of the landing pad is disposed between the protruding insulating pattern 175 and the gate isolation pattern GSS. The height from the upper surface BL_US of the bit line to the lowermost portion of the landing pad LP may be less than the height H4 from the upper surface BL_US of the bit line BL to the uppermost portion GOX_US of the gate insulation layer.

[0116] The pad isolation insulating pattern 235 may be disposed between the landing pads LP. When viewed in a plan view, the landing pads LP may be arranged in a matrix along the first direction D1 and the second direction D2. The upper surface of the landing pad LP may be disposed on the same plane as the upper surface of the pad isolation insulating pattern 235, but is not limited thereto.

[0117] The landing pad LP includes a conductive material. The landing pad LP may include, for example, at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, metal, and metal alloy.

[0118] Data storage patterns DSP may be disposed on the landing pads LP, respectively. The data storage patterns DSP may be connected to the first vertical portion AP_STV1 and the second vertical portion AP_STV2 of the channel structure. The data storage patterns DSP may be connected to the first channel pattern AP1 and the second channel pattern AP2, respectively.

[0119] like Figure 1 As shown, the data storage pattern DSP may be arranged in a matrix along the first direction D1 and the second direction D2. The data storage pattern DSP may completely or partially overlap the landing pad LP in the third direction D3. The data storage pattern DSP may contact the entire upper surface of the landing pad LP or some of the upper surface of the landing pad LP.

[0120] For example, the data storage pattern DSP may be a capacitor. The first channel pattern AP1 may be connected to the first capacitor. The second channel pattern AP2 may be connected to the second capacitor.

[0121] The data storage pattern DSP may include a capacitor dielectric layer 253 inserted between the storage electrode 251 and the plate electrode 255. In this case, the storage electrode 251 may be in contact with the landing pad LP. When viewed in a plan view, the storage electrode 251 may have various shapes such as a circle, an oval, a rectangle, a square, a diamond, or a hexagon. The data storage pattern DSP may overlap the landing pad LP completely or partially. The data storage pattern DSP may be in contact with the entire upper surface of the landing pad LP or some of the upper surface of the landing pad LP. The storage electrode 251 may pass through, penetrate, or extend into the upper cell etch stop layer 247. The upper cell etch stop layer 247 may be made of an insulating material.

[0122] Each of the storage electrode 251 and the plate electrode 255 may include, for example, at least one of a conductive semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, and a metal. The capacitor dielectric layer 253 may include at least one of a ferroelectric material, an antiferroelectric material, and a paraelectric material. For example, the capacitor dielectric layer 253 may include one of a ferroelectric material, an antiferroelectric material, a paraelectric material, a combination of a ferroelectric material and an antiferroelectric material, a combination of a ferroelectric material and a paraelectric material, a combination of a paraelectric material and an antiferroelectric material, and a combination of a ferroelectric material, an antiferroelectric material, and / or a paraelectric material.

[0123] In some embodiments, the data storage pattern DSP may be a variable resistance pattern that can be switched between two resistance states by an electric pulse applied to the memory element. For example, the data storage pattern DSP may include a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material whose crystal state changes according to the amount of current.

[0124] Figure 7 is a diagram illustrating a semiconductor memory device according to some embodiments. Figure 8 is a diagram showing a semiconductor memory device according to some embodiments. For ease of description, the following description will be based on the reference Figures 1 to 6 For reference, Figure 7 and Figure 8 It is shown Figure 2 An enlarged view of part P.

[0125] Reference Figure 7 , in the semiconductor memory device according to some embodiments, the gate isolation pattern GSS does not contact the channel structure AP_ST.

[0126] A portion of the gate insulating layer GOX may be disposed between the gate isolation pattern GSS and the channel structure AP_ST. In a cross-sectional view, the gate insulating layer GOX between the first word line WL1 and the channel structure AP_ST may be connected to the gate insulating layer GOX between the second word line WL2 and the channel structure AP_ST.

[0127] Reference Figure 8 , in the semiconductor memory device according to some embodiments, a portion of the gate isolation pattern GSS may be recessed into the channel structure AP_ST.

[0128] The thickness of the connection channel pattern AP_CP is smaller than the thickness of the horizontal portion AP_STH of the channel structure included in the channel patterns AP1 and AP2 .

[0129] Fig. 9 is a diagram illustrating a semiconductor memory device according to some embodiments. Fig.10 is a diagram showing a semiconductor memory device according to some embodiments. For ease of description, the following description will be based on the reference Figures 1 to 6 For reference, Fig. 9 and Fig.10 It is shown Figure 2 An enlarged view of part P.

[0130] Reference Fig. 9 , in the semiconductor memory device according to some embodiments, the upper surface BL_US of the bit line may include a first region BL_US1 and a second region BL_US2 .

[0131] The protruding insulating pattern 175 may be disposed on the first region BL_US1 of the upper surface of the bit line. The protruding insulating pattern 175 may overlap the first region BL_US1 of the upper surface of the bit line in the third direction D3. The channel interface layer CH_IF may be disposed on the first region BL_US1 of the upper surface of the bit line. The channel interface layer CH_IF may contact the first region BL_US1 of the upper surface of the bit line.

[0132] The channel structure AP_ST may be disposed on the second region BL_US2 of the upper surface of the bit line. The first channel pattern AP1 and the second channel pattern AP2 may be disposed on the second region BL_US2 of the upper surface of the bit line. The second region BL_US2 of the upper surface of the bit line may be the bottom surface of the channel trench CH_T. For example, the channel structure AP_ST may contact the second region BL_US2 of the upper surface of the bit line.

[0133] The height of the first region BL_US1 of the upper surface of the bit line may be different from the height of the second region BL_US2 of the upper surface of the bit line. Figure 2The upper surface of the bit line 100), the second area BL_US2 of the upper surface of the bit line may be lower than the first area BL_US1 of the upper surface of the bit line.

[0134] Reference Fig.10 , the semiconductor memory device according to some embodiments may further include an interface insertion layer CH_IFR disposed between the protruding insulating pattern 175 and the channel interface layer CH_IF.

[0135] The interface insertion layer CH_IFR may extend along the channel interface layer CH_IF. The interface insertion layer CH_IFR may contact the upper surface BL_US of the bit line. The interface insertion layer CH_IFR may be a material layer remaining without being oxidized when the channel interface layer CH_IF is formed.

[0136] The interface insertion layer CH_IFR may include, for example, a semiconductor material. When the interface insertion layer CH_IFR is provided, the channel interface layer CH_IF may include at least one of silicon oxide, silicon oxynitride, and silicon nitride.

[0137] Figures 11 to 13 is a diagram showing a semiconductor memory device according to some embodiments. For ease of description, the following description will be based on the reference Figures 1 to 6 The differences in the descriptions performed.

[0138] For reference, Fig.11 is along Figure 1 A cross-sectional view taken along lines AA and BB. Fig.12 is along Figure 1 A cross-sectional view taken along lines CC and DD. Fig.13 It is shown Fig.11 An enlarged view of part P.

[0139] Reference Figures 11 to 13 , in the semiconductor memory device according to some embodiments, the channel interface layer CH_IF may extend along the sidewalls and the bottom surface of the channel trench CH_T.

[0140] The channel interface layer CH_IF may be disposed between the channel structure AP_ST and the protruding insulating pattern 175 and between the channel structure AP_ST and the bit line BL. The channel interface layer CH_IF may be disposed between the channel structure AP_ST and the cell under insulating layer 171 .

[0141] The channel interface layer CH_IF may include a vertical portion CH_IFV extending along a sidewall of the channel trench CH_T and a horizontal portion CH_IFH extending along a bottom surface of the channel trench CH_T. The vertical portion CH_IFV of the channel interface layer may protrude from the horizontal portion CH_IFH of the channel interface layer in the third direction D3.

[0142] A vertical portion CH_IFV of the channel interface layer may be disposed between the channel structure AP_ST and the protruding insulating pattern 175. A horizontal portion CH_IFH of the channel interface layer may be disposed between the channel structure AP_ST and the bit line BL and between the channel structure AP_ST and the cell under insulating layer 171.

[0143] The horizontal portion CH_IFH of the channel interface layer may contact the bit line BL. Since the channel interface layer CH_IF is disposed between the channel structure AP_ST and the bit line BL, the channel structure AP_ST may not contact the bit line BL.

[0144] The horizontal portion CH_IFH of the channel interface layer may include a first portion CH_IFH1 and a second portion CH_IFH2. The first portion CH_IFH1 of the horizontal portion of the channel interface layer may contact the bit line BL. The second portion CH_IFH2 of the horizontal portion of the channel interface layer may contact the under-cell insulating layer 171.

[0145] The horizontal portion CH_IFH of the channel interface layer may include a material different from that of the vertical portion CH_IFV of the channel interface layer. The vertical portion CH_IFV of the channel interface layer may include, for example, at least one of silicon oxynitride and silicon nitride.

[0146] The first portion CH_IFH1 of the horizontal portion of the channel interface layer may include a material different from that of the second portion CH_IFH2 of the horizontal portion of the channel interface layer. The second portion CH_IFH2 of the horizontal portion of the channel interface layer may include, for example, at least one of silicon oxynitride and silicon nitride. The first portion CH_IFH1 of the horizontal portion of the channel interface layer may include, for example, a metal nitride. When the bit line BL includes a first metal, the metal nitride included in the first portion CH_IFH1 of the horizontal portion of the channel interface layer may be a nitride of the first metal included in the bit line BL. When it is assumed that the bit line BL includes tungsten (W), the first portion CH_IFH1 of the horizontal portion of the channel interface layer may include tungsten nitride.

[0147] For example, when the second portion CH_IFH2 of the horizontal portion of the channel interface layer includes the same material as that of the cell lower insulating layer 171, the second portion CH_IFH2 of the horizontal portion of the channel interface layer may not be distinguished from the cell lower insulating layer 171. The boundary between the cell lower insulating layer 171 and the second portion CH_IFH2 of the horizontal portion of the channel interface layer may be identified using the boundary between the bit line BL and the first portion CH_IFH1 of the horizontal portion of the channel interface layer.

[0148] The upper surface BL_US of the bit line may include a first region BL_US1 and a second region BL_US2. The protruding insulating pattern 175 may be disposed on the first region BL_US1 of the upper surface of the bit line. The channel interface layer CH_IF may be disposed on the second region BL_US2 of the upper surface of the bit line. The channel interface layer CH_IF may extend along the second region BL_US2 of the upper surface of the bit line.

[0149] Based on substrate ( Figure 2 The upper surface of the bit line 100), the second area BL_US2 of the upper surface of the bit line may be lower than the first area BL_US1 of the upper surface of the bit line.

[0150] Figures 14 to 17 is a diagram showing a semiconductor memory device according to some embodiments. For ease of description, the following description will be based on the reference Figures 1 to 6 The differences in the descriptions performed.

[0151] For reference, Fig.14 is a layout diagram illustrating a semiconductor memory device according to some embodiments. Fig.15 is along Fig.14 A cross-sectional view taken along lines AA and BB. Fig.16 is along Fig.14 A cross-sectional view taken along lines CC and DD. Fig.17 It is shown Fig.15 An enlarged view of part P.

[0152] Reference Figures 14 to 17 , in the semiconductor memory device according to some embodiments, the first channel pattern AP1 and the second channel pattern AP2 spaced apart from each other in the second direction D2 are not connected to each other inside the channel trench CH_T.

[0153] The first channel pattern AP1 may include a horizontal portion AP1_H extending along the upper surface BL_US of the bit line and a vertical portion AP1_V extending along the sidewall 175SW of the protruding insulating pattern. The vertical portion AP1_V of the first channel pattern may protrude from the horizontal portion AP1_H of the first channel pattern in the third direction D3.

[0154] The second channel pattern AP2 may include a horizontal portion AP2_H extending along the upper surface BL_US of the bit line and a vertical portion AP2_V extending along the sidewall 175SW of the protruding insulating pattern. The vertical portion AP2_V of the second channel pattern may protrude from the horizontal portion AP2_H of the second channel pattern in the third direction D3.

[0155] The gate isolation pattern GSS may contact the bit line BL. The horizontal portion AP1_H of the first channel pattern and the horizontal portion AP2_H of the second channel pattern may be spatially separated from each other by the gate isolation pattern GSS. The gate isolation liner 151 may contact the bit line BL.

[0156] Figures 18 to 21 is a diagram showing a semiconductor memory device according to some embodiments. For ease of description, the following description will be based on the reference Figures 1 to 6 The differences in the descriptions performed.

[0157] Reference Fig.18 In the semiconductor memory device according to some embodiments, the first channel pattern AP1 and the second channel pattern AP2 may be alternately arranged in a diagonal direction relative to the first direction D1 and the second direction D2. In this case, the diagonal direction may be aligned with the substrate ( Figure 2 The upper surface of 100) is parallel.

[0158] The channel structure AP_ST may be formed to be twisted in a diagonal direction. When viewed in a plan view, each of the first channel pattern AP1, the second channel pattern AP2, and the connection channel pattern AP_CP may have a parallelogram shape or a rhombus shape.

[0159] Reference Fig.19 , in the semiconductor memory device according to some embodiments, when viewed in a plan view, the landing pads LP and the data storage patterns DSP may be arranged in a zigzag or honeycomb shape.

[0160] Reference Fig. 20 , in the semiconductor memory device according to some embodiments, the data storage pattern DSP may be disposed to be misaligned with the landing pad LP when viewed in a plan view.

[0161] Each of the data storage patterns DSP may make contact with a portion of the landing pad LP.

[0162] Reference Fig.21 , in the semiconductor memory device according to some embodiments, each of the landing pads LP disposed on the first and second channel patterns AP1 and AP2 may have a semicircular shape or a semi-elliptical shape when viewed in a plan view.

[0163] The landing pads LP may be disposed symmetrically to each other when viewed in a plan view.

[0164] Figures 22 to 32 is a diagram illustrating a method for manufacturing a semiconductor memory device according to some embodiments.

[0165] Reference Figure 22 to Figure 24, a peripheral gate structure PG may be formed on the substrate 100 .

[0166] A first peripheral wiring line 241 a and a peripheral contact plug 241 b may be formed on the substrate 100 .

[0167] First to fifth peripheral upper insulating layers 261, 262, 263, 264, and 265 may be sequentially formed on the first peripheral wiring line 241a and the peripheral contact plug 241b. Second peripheral wiring lines 243, peripheral via plugs 242, and cell connection plugs 244 may be formed in the first to fifth peripheral upper insulating layers 261, 262, 263, 264, and 265.

[0168] Then, a bit line BL may be formed on the fifth peripheral upper insulating layer 265. The bit line BL may extend longitudinally along the second direction D2 on the substrate. A cell lower insulating layer 171 may be formed on the fifth peripheral upper insulating layer 265. The cell lower insulating layer 171 may expose an upper surface of the bit line BL.

[0169] Reference Figure 25 to Figure 27 , a protruding insulating pattern 175 may be formed on the substrate 100 . In more detail, the protruding insulating pattern 175 may be formed on the bit line BL and the cell lower insulating layer 171 .

[0170] The protruding insulating pattern 175 may include an upper protruding insulating pattern 175U and a lower protruding insulating pattern 175B. A cell lower etch stop layer 173 may be formed between the protruding insulating pattern 175 and the cell lower insulating layer 171, but is not limited thereto.

[0171] The protruding insulating pattern 175 may include a plurality of channel trenches CH_T extending in the first direction D1. The channel trenches CH_T may cross the bit lines BL. The channel trenches CH_T may expose the bit lines BL.

[0172] Reference Fig.28 , a channel interface layer CH_IF may be formed on the sidewall of the channel trench CH_T.

[0173] The channel interface layer CH_IF may extend along the sidewalls of the channel trench CH_T. The channel interface layer CH_IF does not extend along the bottom surface of the channel trench CH_T.

[0174] In more detail, for example, a semiconductor liner layer may be formed along the sidewalls and bottom surface of the channel trench CH_T. The semiconductor liner layer may be anisotropically etched so that the semiconductor liner layer on the bottom surface of the channel trench CH_T may be removed. Then, the semiconductor liner layer on the sidewalls of the channel trench CH_T may be oxidized so that a channel interface layer CH_IF may be formed on the sidewalls of the channel trench CH_T. When the semiconductor liner layer is not completely oxidized, an interface insertion layer ( Fig.10 of CH_IFR).

[0175] For another example, a metal oxide layer as an insulating material may be formed along the sidewall and bottom surface of the channel trench CH_T. The metal oxide layer may be formed using, for example, an atomic layer deposition (ALD) method, but is not limited thereto. Subsequently, the metal oxide layer may be anisotropically etched so that the metal oxide layer on the bottom surface of the channel trench CH_T may be removed. As a result, a channel interface layer CH_IF including a second metal oxide may be formed on the sidewall of the channel trench CH_T.

[0176] For another example, a portion of the exposed protruding insulating pattern 175 may be nitrided using a plasma nitridation process. A channel interface layer CH_IF may be formed on the sidewall of the channel trench CH_T. An exposed portion of the lower cell etch stop layer 173 may be nitrided so that a portion of the channel interface layer CH_IF may be formed. When the plasma nitridation process is performed, the exposed bit line BL may also be nitrided. When the bit line BL includes a metal nitride, the channel interface layer CH_IF may not be formed on the bit line BL. The exposed lower cell insulating layer 171 may be nitrided. In this case, although not shown, a structure such as Fig.11 and Fig.12 A second portion CH_IFH2 of the horizontal portion of the channel interface layer is shown.

[0177] Reference Fig.29 and Fig.30 , a channel structure AP_ST may be formed along the sidewalls and the bottom surface of the channel trench CH_T.

[0178] A gate insulating layer GOX may be formed on the channel structure AP_ST. The gate insulating layer GOX may be formed along the outline of the channel structure AP_ST. In a portion where the channel structure AP_ST is not formed, a gate insulating layer GOX may be formed along the sidewall of the protruding insulating pattern 175. The gate insulating layer GOX may be formed using at least one of physical vapor deposition (PVD), thermal chemical vapor deposition (thermal CVD), low pressure chemical vapor deposition (LP-CVD), plasma enhanced chemical vapor deposition (PE-CVD), and atomic layer deposition (ALD), but is not limited thereto.

[0179] The first word line WL1 and the second word line WL2 may be formed on the gate insulating layer GOX. The first word line WL1 and the second word line WL2 may be formed along the sidewall of the channel trench CH_T.

[0180] Forming the first word line WL1 and the second word line WL2 may include depositing a gate conductive layer on the gate insulating layer GOX, and then performing an anisotropic etching process on the gate conductive layer.

[0181] During the anisotropic etching process of the gate conductive layer, a portion of the gate insulating layer GOX may be etched. As a result, the gate insulating layer GOX between the first word line WL1 and the channel structure AP_ST may be separated from the gate insulating layer GOX between the second word line WL2 and the channel structure AP_ST. Unlike the illustrated example, during the anisotropic etching process of the gate conductive layer, the gate insulating layer GOX may be used as an etching stop layer.

[0182] An upper surface of the first word line WL1 and an upper surface of the second word line WL2 may be located at a level lower than that of an upper surface of the protruding insulating pattern 175 .

[0183] Reference Fig.31 and Fig.32 , a gate isolation pattern GSS may be formed on the first word line WL1 and the second word line WL2. The gate isolation pattern GSS may fill the channel trench CH_T.

[0184] In more detail, the gate isolation liner 151 may be formed along the profile of the first word line WL1 and the profile of the second word line WL2 . The gate isolation liner 151 may also be formed on the upper surface of the protruding insulating pattern 175 .

[0185] A prefill layer may be formed on the gate isolation liner 151 . The prefill layer may also be formed on the upper surface of the protruding insulating pattern 175 . A portion of the prefill layer may be removed so that a gate isolation filling layer 153 may be formed on the gate isolation liner 151 .

[0186] A pre-capping layer may be formed on the gate isolation filling layer 153. A pre-capping layer may also be formed on the upper surface of the protruding insulating pattern 175. A portion of the pre-capping layer may be removed so that the gate isolation capping layer 155 may be formed. When the gate isolation capping layer 155 is formed, the gate isolation liner 151 and the pre-capping layer formed on the upper surface of the protruding insulating pattern 175 may be removed.

[0187] Reference Figure 2 and Figure 3, a portion of the channel structure AP_ST may be removed so that the uppermost surface of the channel structure AP_ST may be lower than the upper surface of the protruding insulating pattern 175. Then, a pre-landing pad layer may be formed on the protruding insulating pattern 175, the gate isolation pattern GSS, and the channel structure AP_ST. The pre-landing pad layer may be patterned so that a landing pad LP may be formed on the channel structure AP_ST.

[0188] Subsequently, a data storage pattern DSP may be formed on the landing pad LP. The data storage pattern DSP may be connected to the channel structure AP_ST and may be formed on the gate isolation pattern GSS.

[0189] Fig.33 and Fig.34 is a diagram illustrating a method for manufacturing a semiconductor memory device according to some embodiments. Fig.33 and Fig.34 It can be in Figure 25 to Figure 27 The process to be performed afterwards.

[0190] Reference Fig.33 and Fig.34 , a channel interface layer CH_IF may be formed along the sidewalls and the bottom surface of the channel trench CH_T.

[0191] For example, a portion of the exposed protruding insulating pattern 175 may be nitrided using a plasma nitridation process. A portion of the exposed bit line BL and a portion of the exposed under-cell insulating layer 171 may be nitrided. As a result, a channel interface layer CH_IF may be formed.

[0192] You can then execute the Figure 29 to Figure 32 Describe the manufacturing process.

[0193] At the end of the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the described embodiments without departing substantially from the principles of the inventive concept. Therefore, the disclosed embodiments of the present disclosure are used in a general and descriptive sense only, and not for the purpose of limitation.

Claims

1. A semiconductor memory device, comprising: A bit line extending along a first direction on the substrate; a protruding insulating pattern on the bit line and in the channel trench; a first channel pattern extending along a sidewall of the channel trench and comprising a first metal oxide; a second channel pattern extending along a sidewall of the channel trench, including the first metal oxide, and spaced apart from the first channel pattern in the first direction; a channel interface layer extending along a sidewall of the channel trench and contacting the first channel pattern and the second channel pattern; a first word line between the first channel pattern and the second channel pattern and extending in a second direction intersecting the first direction; a second word line extending in the second direction between the first channel pattern and the second channel pattern and spaced apart from the first word line in the first direction; as well as A first capacitor and a second capacitor are electrically connected to the first channel pattern and the second channel pattern, respectively.

2. The semiconductor memory device according to claim 1, wherein The first channel pattern and the second channel pattern contact an upper surface of the bit line.

3. The semiconductor memory device according to claim 2, wherein: The channel interface layer includes at least one of silicon oxide, silicon oxynitride, silicon nitride and a second metal oxide, and Wherein, the second metal oxide comprises an insulating material.

4. The semiconductor memory device according to claim 1, wherein: The channel interface layer extends along the bottom surface of the channel trench, and The channel interface layer includes a horizontal portion and a vertical portion, wherein the horizontal portion extends along a bottom surface of the channel trench, and the vertical portion extends along a sidewall of the channel trench.

5. The semiconductor memory device according to claim 4, wherein: The horizontal portion of the channel interface layer includes a material different from a material of the vertical portion of the channel interface layer.

6. The semiconductor memory device according to claim 5, wherein: The horizontal portion of the channel interface layer includes a metal nitride, and Wherein, the vertical portion of the channel interface layer includes one of silicon nitride and silicon nitride oxide.

7. The semiconductor memory device according to claim 1, wherein: The protruding insulating pattern includes a lower protruding insulating pattern and an upper protruding insulating pattern, and The lower protruding insulating pattern is between the bit line and the upper protruding insulating pattern.

8. The semiconductor memory device according to claim 1, wherein: The first word line includes a first portion and a second portion, and The width of the first portion of the first word line in the first direction is smaller than the width of the second portion of the first word line in the first direction.

9. The semiconductor memory device according to claim 1, further comprising: a gate isolation pattern on the bit line, wherein the gate isolation pattern separates the first word line and the second word line from each other, wherein the first channel pattern and the second channel pattern are connected to each other through a connecting channel pattern, and Wherein, the gate isolation pattern is on the connection channel pattern.

10. The semiconductor memory device according to claim 1, further comprising: a gate insulating layer between the first channel pattern and the first word line, Wherein, a height from an upper surface of the bit line to an uppermost portion of the gate insulating layer is greater than a height from an upper surface of the bit line to an uppermost portion of the first channel pattern.

11. A semiconductor memory device comprising: a peripheral gate structure on the substrate; A bit line on the peripheral gate structure, wherein the bit line extends in a first direction; a protruding insulating pattern on the bit line and in the channel trench; a channel structure on the bit line, wherein the channel structure includes a horizontal portion located inside the channel trench and a first vertical portion and a second vertical portion, wherein the first vertical portion and the second vertical portion protrude from the horizontal portion, and wherein the horizontal portion of the channel structure contacts the bit line; a channel interface layer between the protruding insulating pattern and the channel structure; a first word line on the channel structure, wherein the first word line extends in a second direction intersecting the first direction; a second word line on the channel structure, wherein the second word line extends in the second direction and is spaced apart from the first word line in the first direction; a gate isolation pattern on a horizontal portion of the channel structure, wherein the gate isolation pattern separates the first word line and the second word line from each other; and A first capacitor and a second capacitor are electrically connected to the first vertical portion of the channel structure and the second vertical portion of the channel structure, respectively.

12. The semiconductor memory device according to claim 11, wherein The channel interface layer includes at least one of silicon oxide, silicon oxynitride, silicon nitride and metal oxide.

13. The semiconductor memory device according to claim 12, wherein the metal oxide is an insulating material.

14. The semiconductor memory device according to claim 11, wherein: A height from an upper surface of the bit line to an upper surface of the gate isolation pattern is greater than a height from an upper surface of the bit line to an uppermost portion of the first vertical portion of the channel structure.

15. The semiconductor memory device according to claim 11, wherein The protruding insulating pattern includes a lower protruding insulating pattern and an upper protruding insulating pattern, wherein the lower protruding insulating pattern is between the bit line and the upper protruding insulating pattern, wherein the lower protruding insulating pattern comprises silicon oxide, and Wherein, the upper protruding insulating pattern comprises silicon nitride.

16. A semiconductor memory device comprising: a peripheral gate structure on the substrate; A bit line on the peripheral gate structure, wherein The bit lines extend in a first direction; a protruding insulating pattern on the bit line and in the channel trench; a channel structure on the bit line, wherein the channel structure includes a horizontal portion located inside the channel trench and a first vertical portion and a second vertical portion, wherein the first vertical portion and the second vertical portion protrude from the horizontal portion, and wherein the horizontal portion of the channel structure is separated from the bit line; a channel interface layer between the protruding insulating pattern and the channel structure, and between the bit line and the channel structure; a first word line on the channel structure, wherein the first word line extends in a second direction intersecting the first direction; a second word line on the channel structure, wherein the second word line extends in the second direction and is spaced apart from the first word line in the first direction; a gate isolation pattern on a horizontal portion of the channel structure, wherein the gate isolation pattern separates the first word line and the second word line from each other; and A first capacitor and a second capacitor are electrically connected to the first vertical portion of the channel structure and the second vertical portion of the channel structure, respectively.

17. The semiconductor memory device according to claim 16, wherein: The channel interface layer includes a horizontal portion and a vertical portion, the horizontal portion extending along a bottom surface of the channel trench and contacting the bit line, the vertical portion extending along a sidewall of the channel trench, and The horizontal portion of the channel interface layer includes a material different from a material of the vertical portion of the channel interface layer.

18. The semiconductor memory device according to claim 17, wherein: The horizontal portion of the channel interface layer includes a metal nitride, and Wherein, the vertical portion of the channel interface layer includes one of silicon nitride and silicon nitride oxide.

19. The semiconductor memory device according to claim 18, wherein: The bit line includes a first metal, and Wherein, the metal nitride is the nitride of the first metal.

20. The semiconductor memory device according to claim 16, further comprising: a gate insulating layer between the channel structure and the first word line, Wherein, a height from an upper surface of the bit line to an uppermost portion of the gate insulating layer is greater than a height from an upper surface of the bit line to an uppermost portion of the first vertical portion of the channel structure.

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