Manufacturing method of memory device and memory device

Abstract

The invention discloses a manufacturing method of a memory device and the memory device, and the manufacturing method comprises the steps: providing a semiconductor substrate which comprises a substrate and a hard mask layer on the substrate; a plurality of first grooves are formed in the active area of the substrate from the hard mask layer, one part of the first grooves are located in the storage area, the other part of the first grooves are located in the leading-out area, and the parts, in the substrate, of the first grooves are defined as base body grooves; forming a gate insulating layer and a semi-floating gate at the bottom of the groove of the substrate; one part of the semi-floating gate is in contact with the substrate, and the other part of the semi-floating gate is isolated from the substrate through a gate insulating layer; and forming an inter-gate dielectric layer and a first gate layer in the first groove, forming a control gate of the memory unit in the first groove of the memory region, and forming a lead-out wire of the memory unit in the first groove of the lead-out region, namely, enabling the lead-out region to be in contact with the outside, and solving the problem of voltage drop caused by large buried gate resistance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a manufacturing method of a memory device and a memory device. Background Art

[0002] In the application process of integrated circuits, the performance of various devices will be affected by the contact area between the layers of materials, especially memory devices, because the contact area between the layers of materials affects the power consumption of the device.

[0003] During actual operation, the researchers of this application discovered that in current semiconductor device manufacturing schemes, especially in the manufacture of memory devices, the buried gate structure formed often leads to insufficient coupling between the control gate and the semi-floating gate, which makes the operating voltage of the memory device relatively large and the power consumption is also relatively large, affecting the performance of the memory device. Summary of the invention

[0004] The main technical problem solved by the present invention is to provide a manufacturing method of a memory device and a memory device, which can effectively improve the coupling between the control gate and the semi-floating gate of the memory device, reduce the operating voltage, and thus reduce power consumption.

[0005] In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a method for manufacturing a memory device, comprising: providing a semiconductor substrate, the semiconductor substrate comprising a substrate and a hard mask layer on the substrate; opening a plurality of first grooves in the active area of ​​the substrate from the hard mask layer, a part of the plurality of first grooves being located in the storage area, and another part being located in the lead-out area, wherein the part of the first groove in the substrate is defined as a base groove; forming a gate insulating layer and a semi-floating gate at the bottom of the base groove, a part of the semi-floating gate being in contact with the substrate, and another part being isolated from the substrate by the gate insulating layer; forming an inter-gate dielectric layer and a first gate layer in the plurality of first grooves, respectively, wherein a part of the first gate layer in the first groove in the storage area is removed to form a control gate of a memory cell, and the first gate layer in the first groove in the lead-out area is retained as a lead-out line of the memory cell, and the lead-out line connects the control gates of a plurality of the memory cells in the same row.

[0006] In an embodiment of the present application, the height of the control gate is not higher than the height of the substrate groove.

[0007] In one embodiment of the present application, providing a semiconductor substrate includes: providing a substrate, and sequentially forming a first dielectric layer and a second dielectric layer on the substrate; opening a second groove from the second dielectric layer toward the substrate, wherein the second groove is arranged at intervals along the first direction and extends along the second direction; filling the second groove with an isolation material to form the shallow trench isolation structure, and performing ion implantation on the substrate to form a first well region in the substrate; removing the second dielectric layer and exposing a portion of the shallow trench isolation structure; performing ion implantation on the substrate using the first dielectric layer as a barrier layer to form a second well region on one side of the substrate; wherein the second well region is located on the first well region, and the doping type is different from the doping type of the first well region; forming a filling covering layer on the first dielectric layer, and using the first dielectric layer and the filling covering layer as hard mask layers, wherein the filling covering layer is filled between two adjacent shallow trench isolation structures and covers the shallow trench isolation structure.

[0008] In one embodiment of the present application, forming a gate insulating layer and a semi-floating gate at the bottom of the substrate groove includes: forming a first insulating layer on the inner wall of the substrate groove, forming a sacrificial material on the first insulating layer, and the sacrificial material filling the first groove; removing part of the sacrificial material and the first insulating layer to form a contact window; removing the remaining sacrificial material, and filling the first groove with gate material; removing part of the gate material and the first insulating layer to form a semi-floating gate and a gate insulating layer at the bottom of the substrate groove; wherein the remaining gate material is the semi-floating gate, the remaining first insulating layer is the gate insulating layer, a part of the semi-floating gate is in contact with the substrate through the contact window, and the other part is isolated from the substrate by the gate insulating layer.

[0009] In one embodiment of the present application, the gate insulation layer and the semi-floating gate are formed at the bottom of the substrate groove, including: forming a gate insulation layer, a second gate and a third gate at the bottom of the substrate groove, wherein the second gate is isolated from the substrate by the gate insulation layer, the third gate is in direct contact with the substrate, and the second gate and the third gate cooperate to constitute a semi-floating gate of the storage unit in the storage device.

[0010] In one embodiment of the present application, the gate insulation layer, the first gate and the second gate are formed at the bottom of the substrate groove, including: forming a first insulation layer on the inner wall of the substrate groove, and filling the first groove with a second gate material; removing part of the second gate material and part of the first insulation layer to form a contact window, and forming a third gate material above the contact window; removing part of the second gate material, the third gate material and the first insulation layer, and retaining the second gate material, the third gate material and the first insulation layer in the first groove section of the substrate groove; wherein the remaining second gate material, the third gate material and the first insulation layer serve as the second gate, the third gate and the gate insulation layer, respectively.

[0011] In an embodiment of the present application, at least the contact portion between the third gate and the substrate is made of single crystal material.

[0012] In one embodiment of the present application, a shallow trench isolation structure is provided in the substrate, wherein a portion of the shallow trench isolation structure is provided in the substrate and a portion protrudes from the substrate, and the shallow trench isolation structure is spaced apart along the first direction and extends along the second direction; after a gate insulation layer and a semi-floating gate are formed at the bottom of the substrate groove, a portion of the shallow trench isolation structure is removed to form a first isolation portion, wherein a height of the shallow trench isolation structure remaining in the first isolation portion is not higher than a height of the semi-floating gate.

[0013] In one embodiment of the present application, the inter-gate dielectric layer and the first gate layer are formed in the plurality of first grooves, respectively, including: forming the inter-gate dielectric layer, wherein the inter-gate dielectric layer covers at least a half-floating gate; covering the inter-gate dielectric layer with a first gate material, wherein the first gate material is flush with the highest point of the first groove; removing part of the first gate material in the first groove of the storage area until the remaining first gate material is not higher than the highest point of the base groove, and retaining the first gate material in the first groove of the lead-out area as the first gate layer of the lead-out area to form a lead-out line of the storage unit, wherein the remaining first gate material serves as the first gate layer of the storage area to form a control gate of the storage unit.

[0014] In one embodiment of the present application, in a first direction, at least one of the first grooves in the lead-out area after every preset number of the first grooves is shielded, and a portion of the first gate material in the first grooves in the lead-out area is retained, wherein, in the first direction, the first gate material retained in the first grooves in the same row serves as a connection point for all control gates in the storage unit in the row, and is used to realize the connection between the first gate layer in the same row and the outside world.

[0015] In one embodiment of the present application, it also includes: forming a second insulating layer in the vacant area of ​​the first groove in the storage area; removing the hard mask layer; forming isolation barriers on both sides of the second insulating layer and / or the first gate material; forming an interlayer dielectric layer; forming connecting pillars in the interlayer dielectric layer, wherein the connecting pillars are connected to the first gate material of the lead-out area.

[0016] In order to solve the above technical problems, another technical solution adopted by the present application is: a memory device is provided, comprising a substrate, a substrate groove, a semi-floating gate, an inter-gate dielectric layer and a first gate layer; the substrate groove extends from a side surface of the substrate to the substrate, a part of the plurality of substrate grooves is located in a storage area, and another part is located in a lead-out area, wherein a gate insulating layer is arranged on the inner wall of the bottom of the substrate groove; a semi-floating gate is filled in the bottom of the substrate groove, wherein a part of the semi-floating gate is isolated from the substrate by the gate insulating layer, and another part of the semi-floating gate is in contact with the substrate; an inter-gate dielectric layer covers the semi-floating gate; a first gate layer is arranged on the inter-gate dielectric layer, wherein the first gate layer in the storage area constitutes a control gate of a storage unit in the memory device; the first gate layer in the lead-out area serves as a lead-out line, and the lead-out line connects the control gates of multiple storage units in the same row.

[0017] In one embodiment of the present application, the semi-floating gate includes a second gate and a third gate, the second gate is isolated from the substrate by the gate insulating layer, and the third gate is in contact with the substrate.

[0018] In an embodiment of the present application, at least the contact portion between the third gate and the substrate is made of single crystal material.

[0019] In one embodiment of the present application, a shallow trench isolation structure is formed in the substrate, and the shallow trench isolation structure is arranged at intervals along a first direction and extends along a second direction; wherein the shallow trench isolation structure includes a first isolation part and a second isolation part arranged at intervals, the first isolation part is arranged in the substrate, and the second isolation part protrudes from the substrate.

[0020] In an embodiment of the present application, the control gate and the lead line are connected through the first gate layer on the first isolation portion.

[0021] In one embodiment of the present application, the height of the control gate is not higher than the height of the substrate groove, the height of the first gate layer in the substrate groove of the lead-out area is higher than the height of the substrate groove, and serves as a connection point to realize the connection between the first gate layer and the outside world.

[0022] In an embodiment of the present application, in the first direction, at least one corresponding lead wire is provided for every preset number of control gates, and the lead wire serves as a connection point for realizing the connection between the control gates in the same row and the outside world.

[0023] In one embodiment of the present application, it also includes a second insulating layer, an isolation barrier, an interlayer dielectric layer and a connecting column; wherein the second insulating layer covers the first gate layer of the substrate groove in the storage area, and the isolation barrier is located on both sides of the second insulating layer and / or the first gate material remaining on the substrate groove; the interlayer dielectric layer covers the substrate, the second insulating layer and / or the first gate layer remaining on the substrate groove; the connecting column is located in the interlayer dielectric layer, wherein the connecting column connects the third gate layer on the substrate groove in the lead-out area.

[0024] Different from the prior art, the manufacturing method of the memory device provided by the present application includes: providing a manufacturing method of the memory device, including: providing a semiconductor substrate, the semiconductor substrate including a substrate and a hard mask layer on the substrate; opening a plurality of first grooves in the active area of ​​the substrate from the hard mask layer, a part of the plurality of first grooves is located in the storage area, and another part is located in the lead-out area, wherein the part of the first groove in the substrate is defined as a base groove; forming a gate insulating layer and a semi-floating gate at the bottom of the base groove, a part of the semi-floating gate is in contact with the substrate, and the other part is isolated from the substrate by the gate insulating layer; forming an inter-gate dielectric layer and a first gate layer in the plurality of first grooves respectively, removing a part of the first gate layer in the first groove in the storage area to form a control gate of the memory cell, and retaining the first gate layer in the first groove in the lead-out area as a lead-out line of the memory cell, wherein the height of the control gate is not higher than the height of the base groove, and the lead-out line connects the control gates of a plurality of the memory cells in the same row. That is, in the present application, the lead-out wires in the lead-out area can be in contact with the outside world, thereby solving the voltage drop problem caused by the large buried gate resistance of the control gate, and at the same time reducing the operating voltage of the memory device to reduce power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0026] Figure 1 is a flow chart of an embodiment of a method for manufacturing a memory device in the present application;

[0027] Figure 2aIt is a schematic structural diagram of a first direction of an embodiment of a semiconductor substrate in the present application; Figure 2b It is a schematic structural diagram of a second direction of an embodiment of a semiconductor substrate in the present application;

[0028] Figure 3a This is a schematic diagram of the first direction structure of an embodiment of opening a second groove in the substrate in the present application; Figure 3b This is a schematic diagram of the structure in the second direction of an embodiment of opening a second groove in the substrate in the present application;

[0029] Figure 4a It is a schematic diagram of the structure in the first direction of an embodiment of forming a shallow trench isolation structure in the present application; Figure 4b It is a schematic diagram of the structure in the second direction of an embodiment of forming a shallow trench isolation structure in the present application;

[0030] Figure 5a It is a schematic diagram of the structure in the first direction of an embodiment of forming a second well region in the present application; Figure 5b It is a schematic diagram of the structure in the second direction of an embodiment of forming a second well region in the present application;

[0031] Figure 6a It is a schematic diagram of the structure in the first direction of an embodiment of forming a filling covering layer in the present application; Figure 6b It is a schematic diagram of the structure in the second direction of an embodiment of forming a filling covering layer in the present application;

[0032] Figure 7a This is a schematic diagram of the first direction structure of an embodiment of a first groove in the present application; Figure 7b This is a schematic diagram of the structure in the second direction of an embodiment of the present application in which a first groove is provided;

[0033] Figure 8a This is a schematic diagram of the first direction structure of an embodiment of filling the second gate material in the present application; Figure 8b This is a schematic diagram of the structure in the second direction of an embodiment of filling the second gate material in the present application;

[0034] Figure 9a It is a schematic diagram of the structure in the first direction of an embodiment of forming a contact window in the present application; Figure 9b It is a schematic diagram of the structure in the second direction of an embodiment of forming a contact window in the present application;

[0035] Fig.10a This is a schematic diagram of the structure in the first direction of an embodiment of filling the third gate material in the present application; Fig.10b This is a schematic diagram of the structure in the second direction of an embodiment of filling the third gate material in the present application;

[0036] Fig.11aIt is a schematic diagram of the structure in the first direction of an embodiment of the present application in which a portion of the second gate material, the third gate material and the first insulating layer in the first groove are removed; Fig.11b It is a schematic diagram of the structure in the second direction of an embodiment of the present application in which a portion of the second gate material, the third gate material and the first insulating layer in the first groove are removed;

[0037] Fig.12a It is a schematic diagram of the structure in the first direction of an embodiment of forming the first isolation part in the present application; Figure 12b It is a schematic diagram of the structure in the second direction of an embodiment of forming the first isolation part in the present application;

[0038] Fig.13a It is a schematic diagram of the structure in the first direction of another embodiment of the present application in which the shallow trench isolation structure is further lowered to form the first isolation portion; Fig.13b It is a schematic diagram of the structure in the second direction of another embodiment of the present application in which the shallow trench isolation structure is further lowered to form the first isolation portion;

[0039] Fig.14a It is a schematic diagram of the structure in the first direction of an embodiment of forming an inter-gate dielectric layer in the present application; Fig.14b It is a schematic diagram of the structure in the second direction of an embodiment of forming an inter-gate dielectric layer in the present application;

[0040] Fig.15a It is a schematic diagram of the first direction structure of an embodiment covering the first gate material in the present application; Fig.15b It is a schematic diagram of the second direction structure of an embodiment of covering the first gate material in the present application;

[0041] Fig.16a This is a schematic diagram of the structure in the first direction of an embodiment of the present application in which part of the first gate material is removed; Fig.16b This is a schematic diagram of the structure in the second direction of an embodiment of the present application in which part of the first gate material is removed;

[0042] Fig.17a It is a schematic diagram of the structure in the first direction of an embodiment of forming a second insulating layer in the present application; Fig.17b It is a schematic diagram of the structure in the second direction of an embodiment of forming a first groove of a second insulating layer in the present application;

[0043] Fig.18a It is a schematic diagram of the structure in the first direction of an embodiment of the present application in which a portion of the first insulating layer and the filling cover layer are removed; Fig.18b It is a schematic diagram of the structure in the second direction of an embodiment of the present application in which a portion of the first insulating layer and the filling covering layer are removed;

[0044] Fig.19 is a top view of the storage device in the present application;

[0045] Fig.20aIt is a schematic diagram of the structure in the first direction of an embodiment of forming an isolation retaining wall in the present application; Fig.20b It is a schematic diagram of the structure in the second direction of an embodiment of forming an isolation retaining wall in the present application;

[0046] Fig.21a It is a schematic structural diagram of the first direction of an embodiment of forming a connecting column in an interlayer dielectric layer in the present application; Figure 21b It is a schematic diagram of the second direction structure of an embodiment of forming a connecting column in an interlayer dielectric layer in the present application.

[0047] In the accompanying drawings, there are a substrate 100, a second groove 101, a shallow trench isolation structure 102, a first groove 103, a first groove section 1031, a second groove section 1032, a vacant area 1033, a first insulating layer 104, a gate insulating layer 1041, a second gate material 105, a second gate 1051, a third gate material 106, a third gate 1061, a first dielectric layer 200, a metal silicide layer 210, a second dielectric layer 300, a filling cover layer 400, a filling layer 410, a first protective layer 420, an inter-gate dielectric layer 500, a first gate material 600, a first gate layer 610, an idle area 620, a second insulating layer 700, an isolation retaining wall 800, an interlayer dielectric layer 900, and a connecting column 910. DETAILED DESCRIPTION

[0048] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0049] In the current memory device manufacturing process, especially the memory device manufacturing, the buried gate structure formed by the semi-floating gate in the manufacturing process brings about a voltage drop problem due to the large buried gate resistance, and often leads to insufficient coupling between the control gate and the semi-floating gate, which makes the operating voltage of the memory device relatively large, and the power consumption is also relatively large, affecting the performance of the memory device.

[0050] Therefore, a method for manufacturing a memory device is provided, so that the lead wires of the lead area can contact the outside world, solving the voltage drop problem caused by the large buried gate resistance of the control gate, and reducing the operating voltage of the memory device to reduce power consumption.

[0051] See also Figure 1 , Figure 1 It is a flow chart of an embodiment of a method for manufacturing a memory device in the present application.

[0052] like Figure 1 The manufacturing method of the memory device of the present application comprises:

[0053] S11. Provide a semiconductor substrate, wherein the semiconductor substrate includes a substrate and a hard mask layer on the substrate.

[0054] The semiconductor substrate in step S11 is as follows Figure 6a , 6b As shown, the operation flow of step S11 in the embodiment is as follows:

[0055] A substrate is provided, and a first dielectric layer and a second dielectric layer are sequentially formed on the substrate.

[0056] The substrate may be any suitable base material known in the art, for example, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI).

[0057] See also Figure 2a and Figure 2b , Figure 2a It is a schematic structural diagram of a first direction of an embodiment of a semiconductor substrate in the present application; Figure 2b It is a structural schematic diagram of the second direction of an embodiment of a semiconductor substrate in the present application.

[0058] Specifically, a substrate 100 is provided, and a first dielectric layer 200 and a second dielectric layer 300 are sequentially formed on the substrate 100 .

[0059] In some embodiments, the first dielectric layer 200 may be an oxide layer, such as a silicon oxide layer, and the second dielectric layer 300 may be a nitride layer, such as a silicon nitride layer.

[0060] Second grooves are opened from the second dielectric layer toward the substrate, wherein the second grooves are arranged at intervals along the first direction and extend along the second direction.

[0061] The first direction is the wordline extension direction (wordline, WL), which is also the X direction, and the second direction is the bitline extension direction (bitline, BL), which is also the Y direction. That is, the first direction and the second direction are perpendicular to the same horizontal plane.

[0062] See also Figure 3a and Figure 3b , Figure 3a This is a schematic diagram of the first direction structure of an embodiment of opening a second groove in the substrate in the present application; Figure 3b It is a schematic diagram of the second direction structure of an embodiment of opening a second groove into the substrate in the present application.

[0063] like Figure 3a As shown, in the first direction, a second groove 101 is opened from the second dielectric layer 300 to the substrate 100. In the second direction, a first dielectric layer 200 and a second dielectric layer 300 are sequentially formed on the substrate 100.

[0064] In some embodiments, a plurality of second grooves 101 are sequentially spaced apart along the first direction (X direction), and the bottom of the second groove is higher than the bottom of the substrate 100 , that is, the second groove 101 extends to a portion of the substrate 100 .

[0065] An isolation material is filled in the second groove to form a shallow trench isolation structure; and ion implantation is performed to form a first well region in the substrate.

[0066] See also Figure 4a and Figure 4b , Figure 4a It is a schematic diagram of the structure in the first direction of an embodiment of forming a shallow trench isolation structure in the present application; Figure 4b It is a schematic diagram of the second direction structure of an embodiment of forming a shallow trench isolation structure in the present application.

[0067] like Figure 4a As shown, in the first direction, an isolation material is filled in the second groove 101 to form a shallow trench isolation structure 102, and then ion implantation is performed on the substrate 100 to form a first well region 110 in the substrate 100; wherein the shallow trench isolation structure 102 penetrates into the first well region 110, and the bottom of the shallow trench isolation structure 102 is higher than the bottom of the first well region 110 and lower than the top of the first well region 110; as shown in FIG. Figure 4b As shown, in the second direction, ion implantation is performed on the substrate 100 to form a first well region 110 in the substrate 100 .

[0068] In some embodiments, the lowest point of the first well region 110 is higher than the lowest point of the substrate 100 , and the highest point of the first well region 110 is lower than the highest point of the substrate 100 , that is, the first well region 110 is located in the substrate 100 .

[0069] In some embodiments, a portion of the shallow trench isolation structure 102 is disposed in the substrate 100 and a portion protrudes from the substrate 100 to define a plurality of active areas (AA) in the substrate. The shallow trench isolation structure 102 extends along the second direction and is spaced apart in the first direction.

[0070] After the shallow trench isolation structure 102 is formed, the second dielectric layer 300 is removed to expose a portion of the shallow trench isolation structure 102 .

[0071] The first dielectric layer 200 is used as a barrier layer to perform ion implantation on the substrate 100 to form a second well region 120 on a side of the substrate 100 close to the first dielectric layer 200 ; wherein the doping type of the second well region 120 is different from the doping type of the first well region 110 .

[0072] See also Figure 5a and Figure 5b , Figure 5a It is a schematic diagram of the structure in the first direction of an embodiment of forming a second well region in the present application; Figure 5b It is a schematic diagram of the second direction structure of an embodiment of forming a second well region in the present application.

[0073] like Figure 5a As shown, in the first direction, the second dielectric layer 300 is removed to expose part of the shallow trench isolation structure 102, and the first dielectric layer 200 is used as a barrier layer to perform ion implantation on the substrate 100 to form a second well region 120 on a side of the substrate 100 close to the first dielectric layer 200; Figure 5b As shown, in the second direction, the second dielectric layer 300 is removed to expose the first dielectric layer 200, and ion implantation is performed on the substrate 100 using the first dielectric layer 200 as a barrier layer to form a second well region 120 on a side of the substrate 100 close to the first dielectric layer 200, wherein the second well region 120 is above the first well region 110.

[0074] In some embodiments, the doping types of the first well region 110 and the second well region 120 are different, that is, the doping types of the first well region 110 and the second well region 120 are opposite; for example, the first well region 110 is an N-type doped well region, and the second well region 120 is a P-type doped well region; conversely, the first well region 110 is a P-type doped well region, and the second well region is an N-type doped well region.

[0075] A filling covering layer is formed on the first dielectric layer, and the first dielectric layer and the filling covering layer are used as a hard mask layer 400, wherein the filling covering layer fills between two adjacent shallow trench isolation structures 102 and covers the shallow trench isolation structures 102, and can be a multi-layer structure or a single-layer structure.

[0076] In the case of a multi-layer structure, the filling cover layer may include a filling layer 410 and a first protective layer 420, and then: a filling layer 410 is formed on the first dielectric layer 200, wherein the filling layer 410 is filled between two adjacent shallow trench isolation structures 102; and a first protective layer 420 is formed on the filling layer 410 and the shallow trench isolation structure 102. Alternatively, the filling cover layer is a single-layer structure, such as a silicon nitride layer, which is filled between two shallow trench isolation structures 102 and formed on the shallow trench isolation structure 102, and the first dielectric layer 200 also serves as a part of the hard mask layer 400.

[0077] See also Figure 6a and Figure 6b , Figure 6a It is a schematic diagram of the structure in the first direction of an embodiment of forming a hard mask layer in the present application; Figure 6b It is a schematic diagram of the second direction structure of an embodiment of forming a hard mask layer in the present application.

[0078] like Figure 6a As shown, in the first direction, a filling layer 410 is formed on the first dielectric layer 200, and the filling layer 410 is filled between two adjacent shallow trench isolation structures 102, and then a first protection layer 420 is formed on the filling layer 410 and the shallow trench isolation structure 102, wherein the filling layer 410 and the first protection layer 420 constitute a filling cover layer, and the first dielectric layer 200, the filling layer 410 and the first protection layer 420 are used as a hard mask layer 400. Figure 6b As shown, in the second direction, a filling layer 410 is formed on the first dielectric layer 200 , and then a first protection layer 420 is formed on the filling layer 410 .

[0079] In some embodiments, the filling layer 410 may be a polycrystalline material filling layer, and the first protective layer may be an ON structure composed of a nitride layer and an oxide layer, such as an ON structure protective layer composed of a silicon nitride layer and a silicon oxide layer.

[0080] S12, opening a plurality of first grooves in the active area of ​​the substrate from the hard mask layer, wherein a portion of the plurality of first grooves is located in the storage area and a portion is located in the lead-out area, wherein a portion of the first groove in the substrate is defined as a base groove. Figure 7a and 7b shown.

[0081] Wherein, the first grooves are arranged at intervals in the second direction.

[0082] See also Figure 7a and Figure 7b , Figure 7a This is a schematic diagram of the first direction structure of an embodiment of a first groove in the present application; Figure 7b It is a schematic diagram of the second direction structure of an embodiment of a first groove in the present application.

[0083] A plurality of first grooves 103 are opened from the hard mask layer 400 toward the active area of ​​the substrate 100, a portion of the first grooves 103 are located in the storage area, and another portion of the first grooves 103 are located in the lead-out area. In the first direction, the first grooves 103 are separated by shallow trench isolation structures 102, and in the second direction, a plurality of first grooves 103 are spaced apart.

[0084] like Figure 7aAs shown, in the first direction, a portion of the hard mask layer 400 on the shallow trench isolation structure 102 between two adjacent first grooves 103 is removed to expose a portion of the shallow trench isolation structure 102, and then a first groove 103 is opened in the active area between the shallow trench isolation structures 102; Figure 7b As shown, in the second direction, a plurality of first grooves 103 arranged at intervals are opened from the hard mask layer 400 to the active area of ​​the substrate 100 .

[0085] In some embodiments, the first groove 103 sequentially penetrates the first protective layer 420, the filling layer 410, the first dielectric layer 200 and the second well region 120, that is, penetrates the hard mask layer 400 and the second well region 120, that is, the bottom of the first groove 103 contacts the first well region 110, so that the first well region 110 is exposed through the first groove 103.

[0086] S13, forming a gate insulating layer and a semi-floating gate at the bottom of the substrate groove, wherein a portion of the semi-floating gate contacts the substrate, and the other portion is isolated from the substrate by the gate insulating layer. Fig.13a and 13b shown.

[0087] The bottom of the substrate groove is the first groove section 1031 , that is, the first groove section 1031 is the bottom portion of the substrate groove where the half floating gate is formed.

[0088] An embodiment of step S13 includes: forming a gate insulating layer, a second gate and a third gate at the bottom of the substrate groove, wherein the second gate is isolated from the substrate by the gate insulating layer, the third gate is in direct contact with the substrate, and the second gate and the third gate cooperate to form a semi-floating gate of a storage unit in the storage device. The specific operation process is as follows, including:

[0089] A first insulating layer is formed on the inner wall of the substrate groove, and a second gate material is filled in the first groove. A portion of the second gate material and a portion of the first insulating layer are removed to form a contact window, and a third gate material is formed above the contact window.

[0090] See also Figure 8a and Figure 8b , Figure 8a This is a schematic diagram of the first direction structure of an embodiment of filling the second gate material in the present application; Figure 8b It is a schematic diagram of the second direction structure of an embodiment of filling the second gate material in the present application.

[0091] like Figure 8a As shown, in the first direction, a first insulating layer 104 is formed on the inner wall of the substrate groove, and the first insulating layer 104 can be formed on the exposed substrate by a thermal oxidation process, and a second gate material 105 is filled in the first groove 103, and the second gate material 105 covers the first groove 103; Figure 8b As shown, in the second direction, a first insulating layer 104 is formed on the inner wall of the substrate groove, and a second gate material 105 is filled in the first groove 103 , so that the second gate material 105 is flush with the hard mask layer 400 , that is, flush with the first protection layer 420 .

[0092] In some embodiments, the second gate material 105 may be a polycrystalline material, such as polysilicon. After the second gate material 105 is filled, the second gate material 105 is chemically mechanically polished so that the second gate material 105 is flush with the first protection layer 420 .

[0093] In some embodiments, when the first insulating layer 104 is formed on the inner wall of the first groove 103 and the second gate material 105 is filled in the first groove 103, the second gate material 105 also covers the shallow trench isolation structure 102. Figure 8a .

[0094] A portion of the second gate material 105 and a corresponding portion of the first insulating layer 104 in the first groove 103 are removed to form a contact window; wherein at least a portion of the first insulating layer in the first groove section is removed.

[0095] See also Figure 9a and Figure 9b , Figure 9a It is a schematic diagram of the structure in the first direction of an embodiment of forming a contact window in the present application; Figure 9b It is a schematic diagram of the second direction structure of an embodiment of forming a contact window in the present application.

[0096] like Figure 9b As shown, in the second direction, a portion of the second gate material 105 and a corresponding portion of the first insulating layer 104 in the first groove 103 are removed, and a portion of the second gate material 105 and a portion of the first insulating layer 104 in the first groove section 1031 in the base groove are removed to form a contact window with the substrate 100; Figure 9a As shown, in the first direction, keep Figure 8a The structure shown.

[0097] The base groove includes a first groove section 1031 and a second groove section 1032, wherein the second groove section 1032 is above the first groove section 1031, that is, the first groove section 1031 is the bottom part of the first groove 103, the first groove section 1031 is used to place the second gate and the third gate, and the second groove section 1032 is used to place the first gate layer.

[0098] In some embodiments, the removal method may be photolithography or etching.

[0099] The third gate material is filled in the idle area of ​​the first groove 103 , that is, the third gate material is formed above the contact window; wherein the third gate material in the first groove section 1031 contacts the substrate through the contact window.

[0100] See also Fig.10a and Fig.10b , Fig.10a This is a schematic diagram of the structure in the first direction of an embodiment of filling the third gate material in the present application; Fig.10b It is a schematic diagram of the second direction structure of an embodiment of filling the third gate material in the present application.

[0101] like Fig.10a As shown, in the first direction, keep Figure 9a The structure shown; Fig.10b As shown, in the second direction, after removing part of the second gate material 105 and the corresponding part of the first insulating layer 104 in the first groove 103, an idle area of ​​the first groove 103 is formed, and the third gate material 106 is filled in the idle area of ​​the first groove 103, that is, the third gate material 106 is formed above the contact window, and chemical mechanical polishing is performed after filling to make the surface after filling smooth; and because at least part of the first insulating layer 104 in the first groove section 1031 is removed to form a contact window, the third gate material 106 in the first groove section 1031 can contact the substrate 100 through the contact window, such as contacting the second well region 120.

[0102] The third gate material may be formed by epitaxy or deposition process. In one embodiment, the third gate material is formed by epitaxy process so that at least the third gate material is made of single crystal material at the contact point with the substrate.

[0103] After filling the third gate material 106, the second gate material 105, the third gate material 106 and the first insulating layer 104 in the first groove 103 are removed, and the second gate material 105, the third gate material 106 and the first insulating layer 104 in the bottom of the substrate groove (i.e., in the first groove section 1031) are retained; wherein the second gate material 105, the third gate material 106 and the first insulating layer 104 remaining in the first groove section 1031 are used as the second gate 1051, the third gate 1061 and the gate insulating layer, respectively. Fig.11a and Fig.11b , Fig.11a It is a schematic diagram of the structure in the first direction of an embodiment of the present application in which a portion of the second gate material, the third gate material and the first insulating layer in the first groove are removed; Fig.11b It is a schematic diagram of the second direction structure of an embodiment of the present application in which a portion of the second gate material, the third gate material and the first insulating layer in the first groove are removed.

[0104] like Fig.11b As shown, in the second direction, part of the second gate material 105, the third gate material 106 and the first insulating layer 104 in the first groove 103 are removed, and the second gate material 105, the third gate material 106 and the first insulating layer 104 in the first groove section 1031 are retained, and the second gate material 105 in the retained first groove section 1031 is used as the second gate 1051, the third gate material 106 in the retained first groove section 1031 is used as the third gate 1061, and the first insulating layer 104 in the retained first groove section 1031 is used as the gate insulating layer 1041. The bottom of the substrate groove where the second gate 1051, the third gate 1061 and the gate insulating layer 1041 are retained is the first groove section 1031.

[0105] In some embodiments, when performing the step of removing a portion of the second gate material 105, the third gate material 106 and the first insulating layer 104 in the first groove 103, a portion of the second gate material 105 covering the shallow trench isolation structure 102 is removed at the same time, thereby continuing to expose a portion of the shallow trench isolation structure 102.

[0106] like Fig.11a As shown, in the first direction, the portion of the second gate material 105 covering the shallow trench isolation structure 102 is removed simultaneously, so that the shallow trench isolation structure 102 continues to be exposed.

[0107] The height of the shallow trench isolation structure is reduced to form a first isolation portion.

[0108] In another embodiment, a first insulating layer 104 is formed on the inner wall of the substrate groove, and a sacrificial material is formed on the first insulating layer 104, and the sacrificial material fills the first groove 103; a portion of the sacrificial material and the first insulating layer 104 are removed to form a contact window on the side wall of the first groove section 1031 of the substrate groove; the remaining sacrificial material is removed and the gate material is filled; a portion of the gate material and the first insulating layer 104 in the first groove 103 are removed to form a semi-floating gate and a gate insulating layer in the first groove section 1031.

[0109] The remaining gate material is a semi-floating gate, the remaining first insulating layer is a gate insulating layer, a part of the semi-floating gate is in contact with the substrate through a contact window, and the other part is isolated from the substrate by the gate insulating layer.

[0110] The sacrificial material is, for example, a silicon-rich composite material or other suitable dielectric material, wherein the gate material remaining in the first trench section 1031 is a semi-floating gate, and the first insulating layer 104 remaining in the first trench section 1031 is a gate insulating layer.

[0111] In the following process, a semi-floating gate including a second gate and a third gate is taken as an example.

[0112] See also Fig.12a and Figure 12b , Fig.12a It is a schematic diagram of the structure in the first direction of an embodiment of forming the first isolation part in the present application; Figure 12b It is a schematic diagram of the second direction structure of an embodiment of forming the first isolation part in the present application.

[0113] like Fig.12a As shown, in the first direction, based on Fig.11a , removing the exposed portion of the shallow trench isolation structure 102, that is, lowering the height of the shallow trench isolation structure 102 so that the height of the shallow trench isolation structure 102 is not higher than the height of the half-floating gate, so as to form a first isolation portion; Figure 12b As shown, in the second direction, it is possible to maintain Fig.11b structure.

[0114] In some embodiments, when the height of the shallow trench isolation structure 102 is reduced to form the first isolation portion, the remaining shallow trench isolation structure 102 may be flush with the half-floating gate to serve as the first isolation portion.

[0115] See also Fig.13a and Fig.13b , Fig.13a It is a schematic diagram of the structure in the first direction of another embodiment of the present application in which the shallow trench isolation structure is further lowered to form the first isolation portion; Fig.13b It is a schematic diagram of the second direction structure of another embodiment of the present application in which the shallow trench isolation structure is further lowered to form the first isolation part.

[0116] like Fig.13a As shown, in the first direction, based on Fig.12a , removing a portion of the shallow trench isolation structure 102 so that the height of the shallow trench isolation structure 102 is lower than the height of the half-floating gate, and using the remaining portion of the shallow trench isolation structure 102 as the first isolation portion; Fig.13b As shown, in the second direction, the first protection layer 420 may be removed.

[0117] In some embodiments, the removal process may be performed by first wet etching and then dry etching.

[0118] S14, forming an inter-gate dielectric layer and a first gate layer in the plurality of first grooves, removing part of the first gate layer in the first groove in the storage area to form a control gate of the storage unit, retaining the first gate layer in the first groove in the lead-out area as a lead-out line of the storage unit, and connecting the control gates of the plurality of storage units in the same row. Fig.16a and 16b shown.

[0119] The operation flow of the embodiment of step S14 is as follows, including:

[0120] An inter-gate dielectric layer is formed, wherein the inter-gate dielectric layer at least covers a half floating gate.

[0121] See also Fig.14a and Fig.14b , Fig.14a It is a schematic diagram of the structure in the first direction of an embodiment of forming an inter-gate dielectric layer in the present application; Fig.14b It is a schematic diagram of the second direction structure of an embodiment of forming an inter-gate dielectric layer in the present application.

[0122] like Fig.14a As shown, in the first direction, based on Fig.13a , forming an inter-gate dielectric layer 500, so that the inter-gate dielectric layer 500 covers the first isolation portion and the semi-floating gate in the first trench section 1031, forming a tooth structure, thereby increasing the coupling area between the semi-floating gate and the control gate; Fig.14b As shown, in the second direction, an inter-gate dielectric layer 500 is formed so that the inter-gate dielectric layer 500 covers the first groove 103 portion above the semi-floating gate composed of the second gate 1051 and the third gate 1061, and covers the residual hard mask layer 400 on the area between two adjacent first grooves.

[0123] The first gate material is covered on the inter-gate dielectric layer, and the excess first gate material is removed until it is flush with the highest point of the first groove, that is, the first gate material is flush with the highest point of the first groove.

[0124] See also Fig.15a and Fig.15b , Fig.15a It is a schematic diagram of the first direction structure of an embodiment covering the first gate material in the present application; Fig.15b It is a schematic diagram of the second direction structure of an embodiment of covering the first gate material in the present application.

[0125] like Fig.15a As shown, in the first direction, based on Fig.14a , covering the first gate material 600 on the inter-gate dielectric layer 500, and removing the excess first gate material 600, so that the first gate material 600 is flush with the highest point of the first groove 103; Fig.15b As shown, in the second direction, based on Fig.14b , covering the inter-gate dielectric layer 500 with the first gate material 600 , and removing excess first gate material 600 , so that the first gate material 600 is flush with the highest point of the first groove 103 .

[0126] Part of the first gate material in the first groove 103 of the storage area and the first gate material on the first isolation portion are removed until the remaining first gate material is no higher than the highest point of the substrate groove, and the first gate material in the first groove 103 of the lead-out area is retained as the first gate layer of the lead-out area and as the lead-out line of the storage unit, wherein the remaining first gate material serves as the first gate layer of the storage area to form a control gate of the storage unit.

[0127] See also Fig.16a and Fig.16b , Fig.16a This is a schematic diagram of the structure in the first direction of an embodiment of the present application in which part of the first gate material is removed; Fig.16b It is a schematic diagram of the second direction structure of an embodiment of the present application in which part of the first gate material is removed.

[0128] like Fig.16b As shown, in the second direction, based on Fig.15b , remove part of the first gate material 600 in the first groove 103 of the storage area to form a vacant area 1033. In one embodiment, the remaining first gate material 600 is not higher than the highest point of the substrate groove, and the remaining first gate material 600 is used as the first gate layer 610, that is, the height of the control gate of the storage area is not higher than the height of the substrate groove.

[0129] In order to more completely represent the structure of the device, Fig.16b The left side of the dotted line is a cross-sectional view of a vacant area 1033 formed in the second direction, as shown below Fig.19 A cross-sectional view of the storage area in the Y1 direction; Fig.16b The right side of the dotted line is a cross-sectional view of the first gate material 600 retained in the first groove 103 in the second direction, and the retained first gate material 600 is used as the control gate contact region, that is, the lead-out region, as follows Fig.19 The cross-sectional view of the region Y2 is shown in FIG. Fig.16b As shown, the first gate material 600 above the substrate groove in the storage area is removed to form a first gate layer 610. Fig.16a As shown, viewed from the first direction, an idle area 620 is formed.

[0130] A second insulating layer 700 is formed on the remaining first gate material on the vacant area 1033 of the first groove 103 and the first isolation portion.

[0131] See also Fig.17a and Fig.17b , Fig.17a It is a schematic diagram of the structure in the first direction of an embodiment of forming a second insulating layer in the present application; Fig.17b It is a schematic diagram of the second direction structure of an embodiment of forming a first groove of a second insulating layer in the present application.

[0132] like Fig.17a As shown, in the first direction, based on Fig.16a , forming a second insulating layer 700 in the idle area 620 of the first gate material 600; Fig.17b As shown, in the second direction, based on Fig.16b A second insulating layer 700 is formed in the vacant area 1033 of the first groove 103, and chemical mechanical polishing is performed to make the surface flat. The material of the second insulating layer 700 is, for example, silicon oxide.

[0133] In some embodiments, in the second direction (as described below) Fig.19 The first gate material 600 retained in the first groove 103 in the lead-out region is used as a connection point of the control gate in the storage unit to realize the connection between the first gate layer 610 in the storage area and the outside world.

[0134] In some embodiments, in the first direction, at least one first groove of the lead-out region after every preset number of first grooves is shielded, and part of the first gate material 600 in the first groove 103 of the lead-out region is retained, wherein, in the first direction, the first gate material 600 retained in the first grooves of the same row serves as a connection point for all control gates in the storage cells of the row, and is used to realize the connection between the first gate layer 610 in the storage area of ​​the same row and the outside world; a gate contact area, i.e., a lead-out area, can be made at a fixed distance BL, such as every 32 columns BL, so that the first gate layer 610 is connected to the outside world through the gate contact area.

[0135] In some embodiments, the method further includes removing all hard mask layers on the memory device, wherein the second isolation portion is a portion of the shallow trench isolation structure 102 other than the exposed first isolation portion.

[0136] See also Fig.18a , Fig.18b and Fig.19 , Fig.18a It is a schematic diagram of the structure in the first direction of an embodiment of removing the hard mask layer in the present application; Fig.18b It is a schematic diagram of the structure in the second direction of an embodiment of removing the hard mask layer in the present application; Fig.19 is a top view of the storage device in this application.

[0137] like Fig.19As shown, in the first direction, it can be divided into two types of regions, wherein X1 is the first type of region in the first direction, and the aforementioned xa figures are all cross-sectional views of the first type of region in the first direction, and the first isolation portion is located in the first type of region X1 in the first direction; X2 is the second type of region in the first direction, and the second isolation portion is located in the second type of region X2 in the first direction; in the second direction, it can be divided into three types of regions, wherein Y1 is the first type of region in the second direction, i.e., the storage area, and the left side of the dotted line of the aforementioned xb figure is the cross-sectional view of the first type of region in the second direction, and Y2 is the second type of region in the second direction, and the right side of the dotted line of the aforementioned xb figure is the cross-sectional view of the second type of region in the second direction, i.e., the lead-out area, and the third gate material in the second type of region in the second direction can be used as a contact area to connect to the outside world, and Y3 is the cross-sectional view of the third type of region in the second direction, i.e., the cross-sectional view of STI, which also belongs to the storage area.

[0138] In the first direction, the first insulating layer 104 and the hard mask layer 400 on the second isolation portion of the shallow trench isolation structure in the second type region in the first direction are removed. Fig.18a is a cross-sectional view of the first type of region in the first direction, that is, on the first isolation portion and without the first insulating layer 104 and the hard mask layer 400; Fig.18b As shown, in the second direction, the first insulating layer 104 and the hard mask layer 400 in the area between two adjacent substrate grooves and on the second isolation portion of the shallow trench isolation structure 102 in the second direction are removed.

[0139] In some embodiments, in the Y3 direction, the first isolation portion and the second isolation portion are alternately arranged; the second insulating layer remaining on the substrate groove and the third gate material remaining on the substrate groove are located in the second direction of different X-axis coordinates.

[0140] Form an isolation retaining wall.

[0141] See also Fig.20a and Fig.20b , Fig.20a It is a schematic diagram of the structure in the first direction of an embodiment of forming an isolation retaining wall in the present application; Fig.20b It is a schematic diagram of the second direction structure of an embodiment of forming an isolation retaining wall in the present application.

[0142] like Fig.20a As shown, in the first direction, the structure is as Fig.18a ;like Fig.20b As shown in FIG. 1 , in the second direction, an isolation barrier 800 is formed on both sides of the second insulating layer 700 and / or the first gate material 600 remaining on the substrate groove, that is, an isolation barrier 800 is formed on both sides of the second insulating layer 700 remaining on the substrate groove of the storage region, as shown in FIG. Fig.20b On the left side of the dotted line; on both sides of the first gate 610 on the substrate groove of the lead-out region, an isolation barrier 800 is formed, such as Fig.20b To the right of the dotted line.

[0143] See also Fig.21a and Figure 21b , Fig.21a It is a schematic structural diagram of the first direction of an embodiment of forming a connecting column in an interlayer dielectric layer in the present application; Figure 21b It is a schematic diagram of the second direction structure of an embodiment of forming a connecting column in an interlayer dielectric layer in the present application.

[0144] like Fig.21a and 21b As shown, an interlayer dielectric layer 900 is formed on the entire top view plane of the memory device, the interlayer dielectric layer 900 covers the above structure, and a connecting column 910 is formed in the interlayer dielectric layer 900 so that the connecting column 910 can connect all control gates of the same row of memory cells.

[0145] In some embodiments, ion implantation is performed to form source and drain regions in the substrate on both sides of the first groove 103; the first dielectric layer 200 is removed, and a metal silicide layer 210 is formed on the source region, the drain region and the control gate; corresponding connection columns may also be provided in the source region and the drain region to connect to the outside world.

[0146] The present application also relates to a storage device, such as Fig.21a , Figure 21b and Fig.19 As shown, the cross-sectional view of the first type region X1 in the first direction is the cross-sectional view of the storage device in the first direction, and the cross-sectional view of the first type region Y1 in the second direction and the cross-sectional view of the second type region Y2 in the second direction are the cross-sectional view of the storage device in the second direction, wherein the cross-sectional view of the first type region Y1 in the second direction is on the left side of the dotted line, and the cross-sectional view of the second type region Y2 in the second direction is on the right side of the dotted line.

[0147] The memory device comprises a substrate, a base groove, a semi-floating gate, an inter-gate dielectric layer and a first gate layer.

[0148] The base groove extends from one side surface of the substrate 100 to the substrate 100. There are multiple base grooves, one of which is located in the storage area and the other is located in the lead-out area. A gate insulating layer 1041 is provided on the inner wall of the bottom of the base groove. Figure 21b shown.

[0149] The semi-floating gate is filled at the bottom of the substrate groove, a portion of the semi-floating gate is isolated from the substrate 100 by the gate insulating layer 1041 , and another portion of the semi-floating gate is in contact with the substrate 100 .

[0150] The substrate groove includes a first groove section and a second groove section, the bottom of the substrate groove where the second gate 1051, the third gate 1061 and the gate insulation layer 1041 are retained is the first groove section, and the second groove section is above the first groove section.

[0151] An inter-gate dielectric layer 500 covering the semi-floating gate;

[0152] The first gate layer 610 is disposed on the inter-gate dielectric layer 500, wherein the first gate layer in the storage area constitutes the control gate of the storage unit in the storage device, and the first gate layer in the lead-out area serves as a lead-out line, which connects the control gates of multiple storage units in the same row.

[0153] In some embodiments, a shallow trench isolation structure 102 is formed on the substrate 100, and the shallow trench isolation structure is arranged at intervals along the first direction and extends along the second direction; wherein the shallow trench isolation structure includes a first isolation portion and a second isolation portion arranged at intervals, the first isolation portion is arranged in the substrate, and the second isolation portion protrudes from the substrate. Fig.21a As shown, in the first type of region X1 in the first direction, a shallow trench isolation structure 102 is formed in the substrate, that is, the height of the shallow trench isolation structure is lower than the height of the substrate, and in the second type of region X2 in the first direction, the height of the shallow trench isolation structure is higher than the height of the substrate to isolate the storage units in the storage device; the shallow trench isolation structures 102 are arranged at intervals along the first direction and extend along the second direction, as shown in FIG. Fig.19 As shown. In the first type of region X1 in the first direction, the shallow trench isolation structure 102 includes a first isolation portion, which is formed between two adjacent substrate grooves in the first direction, and the highest point of the first isolation portion in the third direction is lower than the highest point of the substrate groove in the third direction; in the second type of region X2 in the first direction, the shallow trench isolation structure 102 includes a second isolation portion, and the highest point of the second isolation portion in the third direction is higher than the highest point of the substrate groove in the third direction; that is, the first isolation portion and the second isolation portion are arranged at intervals, the first isolation portion is arranged in the substrate, and the second isolation portion protrudes from the substrate; the third direction is a vertical direction.

[0154] In some embodiments, the semi-floating gate includes a second gate 1051 and a third gate 1061 , the second gate 1051 is isolated from the substrate 100 by the gate insulation layer 1041 , and the third gate 1061 is in direct contact with the substrate 100 ; the inter-gate dielectric layer 500 covers the second gate 1051 and the third gate 1061 .

[0155] In some embodiments, the inter-gate dielectric layer 500 also covers the first isolation portion.

[0156] In some embodiments, at least the third gate in contact with the substrate is made of single crystal material.

[0157] In some embodiments, the first gate layer 610 includes a first gate first portion filled in the substrate groove, and a first gate second portion located on the first isolation portion; in the second direction, the first gate first portions in two adjacent substrate grooves are isolated from each other, that is, the control gates in two adjacent substrate grooves are isolated from each other; in the first direction, the control gates in two adjacent substrate grooves are connected to each other through the first gate layer on the first isolation portion therebetween.

[0158] In some embodiments, the height of the control gate is not higher than the height of the substrate groove, and the first gate layer further includes at least one first gate third portion, i.e., a lead wire, as a connection point, i.e., the height of the first gate layer in the substrate groove of the lead-out region is higher than the height of the substrate groove and serves as a connection point for connecting the control gate to the outside world. The control gate is connected to the lead wire through the first gate layer on the first isolation portion.

[0159] In the first direction, at least one corresponding lead wire is provided for every preset number of control grids, and the lead wire serves as a connection point for realizing the connection between the control grids in the same row and the outside world.

[0160] In some embodiments, the storage device further includes: a second insulating layer, an isolation retaining wall 800, an interlayer dielectric layer 900 and a connecting pillar 910; the second insulating layer covers the first gate layer of the substrate groove in the storage area, and the isolation retaining wall 800 is located on both sides of the second insulating layer 700 and / or the first gate layer remaining on the substrate groove, that is, isolation retaining walls are provided on both sides of the second insulating layer in the storage area, and isolation retaining walls are formed on both sides of the first gate layer in the lead-out area; the interlayer dielectric layer 900 covers the substrate 100, the second insulating layer 700 and / or the first gate layer remaining on the substrate groove; the connecting pillar 910 is located in the interlayer dielectric layer 900, wherein the connecting pillar 910 connects the first gate layer on the substrate groove in the lead-out area.

[0161] In some embodiments, the connection pillar 910 may also connect the source and drain regions divided by the substrate groove.

[0162] In the present application, a method for manufacturing a memory device includes: providing a semiconductor substrate, the semiconductor substrate including a substrate and a hard mask layer on the substrate; opening a plurality of first grooves from the hard mask layer to the active area of ​​the substrate, a portion of the plurality of first grooves being located in the storage area and another portion being located in the lead-out area, wherein the portion of the first groove in the substrate is defined as a base groove; forming a gate insulating layer and a semi-floating gate at the bottom of the base groove, a portion of the semi-floating gate being in contact with the substrate, and the other portion being isolated from the substrate by the gate insulating layer; forming an inter-gate dielectric layer and a first gate layer in the plurality of first grooves, removing a portion of the first gate layer in the first groove in the storage area to form a control gate of a memory cell, retaining the first gate layer in the first groove in the lead-out area as a lead-out line of the memory cell, and the lead-out line connecting the control gates of a plurality of memory cells in the same row. Through the above method, the lead-out line in the lead-out area can be in contact with the outside world, solving the voltage drop problem caused by the large buried gate resistance of the control gate, and reducing the operating voltage of the memory device to reduce power consumption.

[0163] The above description is only an implementation mode of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for manufacturing a memory device, characterized in that: include: Providing a semiconductor substrate, the semiconductor substrate comprising a substrate, and a hard mask layer on the substrate; Opening a plurality of first grooves in the active area of ​​the substrate from the hard mask layer, wherein a portion of the plurality of first grooves is located in the storage area and a portion of the plurality of first grooves is located in the lead-out area, wherein a portion of the first groove in the substrate is defined as a base groove; forming a gate insulating layer and a semi-floating gate at the bottom of the substrate groove, wherein a portion of the semi-floating gate is in contact with the substrate, and another portion of the semi-floating gate is isolated from the substrate by the gate insulating layer; An inter-gate dielectric layer and a first gate layer are respectively formed in the multiple first grooves, a portion of the first gate layer in the first groove of the storage area is removed to form a control gate of the storage unit, and the first gate layer in the first groove of the lead-out area is retained as a lead-out line of the storage unit, and the lead-out line connects the control gates of the multiple storage units in the same row.

2. The method according to claim 1, characterized in that The height of the control gate is not higher than the height of the substrate groove.

3. The method according to claim 1, characterized in that The semiconductor substrate is provided, comprising: Providing a substrate, and forming a first dielectric layer and a second dielectric layer on the substrate; Opening second grooves from the second dielectric layer toward the substrate, wherein the second grooves are arranged at intervals along the first direction and extend along the second direction; Filling the second groove with an isolation material to form a shallow trench isolation structure, and performing ion implantation on the substrate to form a first well region in the substrate; removing the second dielectric layer to expose a portion of the shallow trench isolation structure; Performing ion implantation on the substrate using the first dielectric layer as a barrier layer to form a second well region on one side of the substrate; wherein the second well region is located on the first well region and has a doping type different from that of the first well region; A filling covering layer is formed on the first dielectric layer, and the first dielectric layer and the filling covering layer are used as the hard mask layer, wherein the filling covering layer is filled between two adjacent shallow trench isolation structures and covers the shallow trench isolation structures.

4. The method according to claim 1, characterized in that: The step of forming a gate insulating layer and a semi-floating gate at the bottom of the substrate groove comprises: forming a first insulating layer on the inner wall of the substrate groove, and forming a sacrificial material on the first insulating layer, wherein the sacrificial material fills the first groove; removing a portion of the sacrificial material and the first insulating layer to form a contact window; removing the remaining sacrificial material and filling the first groove with a gate material; Part of the gate material and the first insulating layer is removed to form a semi-floating gate and a gate insulating layer at the bottom of the substrate groove; wherein the remaining gate material is the semi-floating gate, the remaining first insulating layer is the gate insulating layer, a part of the semi-floating gate is in contact with the substrate through the contact window, and the other part is isolated from the substrate by the gate insulating layer.

5. The method according to claim 1, characterized in that The step of forming a gate insulating layer and a semi-floating gate at the bottom of the substrate groove comprises: A gate insulating layer, a second gate and a third gate are formed at the bottom of the base groove, wherein the second gate is isolated from the substrate by the gate insulating layer, the third gate is in direct contact with the substrate, and the second gate and the third gate cooperate to form a semi-floating gate of a storage unit in the storage device.

6. The method according to claim 5, characterized in that The method of forming a gate insulating layer, a second gate and a third gate at the bottom of the substrate groove comprises: Forming a first insulating layer on the inner wall of the substrate groove, and filling the first groove with a second gate material; removing a portion of the second gate material and a portion of the first insulating layer to form a contact window, and forming a third gate material above the contact window; Part of the second gate material, the third gate material and the first insulating layer is removed, and the second gate material, the third gate material and the first insulating layer in the first groove section of the substrate groove are retained; wherein the remaining second gate material, the third gate material and the first insulating layer serve as the second gate, the third gate and the gate insulating layer, respectively.

7. The method according to claim 5, characterized in that At least the contact portion between the third gate and the substrate is made of single crystal material.

8. The method according to claim 1, characterized in that A shallow trench isolation structure is disposed in the substrate, wherein a portion of the shallow trench isolation structure is disposed in the substrate and a portion is exposed from the substrate, and the shallow trench isolation structure is disposed at intervals along a first direction and extends along a second direction; After forming a gate insulation layer and a semi-floating gate at the bottom of the substrate groove, part of the shallow trench isolation structure is removed to form a first isolation part, wherein the height of the shallow trench isolation structure remaining in the first isolation part is not higher than the height of the semi-floating gate.

9. The method according to claim 1, characterized in that: The method comprises forming an inter-gate dielectric layer and a first gate layer in the plurality of first grooves respectively, removing a portion of the first gate layer in the first groove of the storage area to form a control gate of the storage unit, and retaining the first gate layer in the first groove of the lead-out area as a lead-out line of the storage unit, comprising: forming the inter-gate dielectric layer, wherein the inter-gate dielectric layer at least covers the semi-floating gate; Covering the inter-gate dielectric layer with a first gate material, wherein the first gate material is flush with the highest point of the first groove; A portion of the first gate material in the first groove of the storage area is removed until the remaining first gate material is no higher than the highest point of the substrate groove, and the first gate material in the first groove of the lead-out area is retained as a lead-out line of the storage unit, wherein the remaining first gate material serves as the first gate layer of the storage area to form a control gate of the storage unit.

10. The method according to claim 9, characterized in that In the first direction, at least one of the first grooves in the lead-out area after a preset number of the first grooves is shielded, and a portion of the first gate material in the first grooves in the lead-out area is retained, wherein in the first direction, the first gate material retained in the first grooves in the same row serves as a connection point for all control gates in the storage unit in the row, and is used to realize the connection between the first gate layer in the storage area in the same row and the outside world.

11. The method according to claim 9, characterized in that Also includes: forming a second insulating layer in a vacant area of ​​the first groove in the storage area; removing the hard mask layer; Forming isolation barriers on both sides of the second insulating layer and / or the first gate material; forming an interlayer dielectric layer; A connection column is formed in the interlayer dielectric layer, wherein the connection column is connected to the first gate material of the lead-out region.

12. A storage device, characterized in that: include: substrate; A base groove extending from a side surface of the substrate toward the substrate, a portion of the base grooves being located in the storage area and another portion being located in the lead-out area, wherein a gate insulating layer is disposed on an inner wall of a bottom of the base groove; A semi-floating gate filled at the bottom of the substrate groove, wherein a portion of the semi-floating gate is isolated from the substrate by the gate insulating layer, and another portion of the semi-floating gate is in contact with the substrate; An inter-gate dielectric layer covering the semi-floating gate; A first gate layer is arranged on the inter-gate dielectric layer, wherein the first gate layer in the storage area constitutes a control gate of a storage unit in the storage device; and the first gate layer in the lead-out area serves as a lead-out line, and the lead-out line connects the control gates of multiple storage units in the same row.

13. The memory device according to claim 12, wherein: The semi-floating gate includes a second gate and a third gate, the second gate is isolated from the substrate by the gate insulating layer, and the third gate is in contact with the substrate.

14. The memory device according to claim 13, wherein: At least the contact portion between the third gate and the substrate is made of single crystal material.

15. The memory device according to claim 12, wherein: A shallow trench isolation structure is formed in the substrate, and the shallow trench isolation structure is arranged at intervals along a first direction and extends along a second direction; wherein the shallow trench isolation structure includes a first isolation part and a second isolation part arranged at intervals, the first isolation part is arranged in the substrate, and the second isolation part protrudes from the substrate.

16. The memory device according to claim 15, wherein: The control gate and the lead line are connected through the first gate layer on the first isolation portion.

17. The memory device according to claim 12, wherein: The height of the control gate is not higher than that of the substrate groove. The height of the first gate layer in the substrate groove of the lead-out area is higher than that of the substrate groove and serves as a connection point to realize the connection between the first gate layer and the outside world.

18. The memory device according to claim 12, wherein: In the first direction, at least one corresponding lead wire is provided for every preset number of control grids, and the lead wire serves as a connection point for realizing the connection between the control grids in the same row and the outside world.

19. The memory device according to claim 12, wherein: Also includes: a second insulating layer covering the first gate layer of the substrate groove in the storage region; Isolation retaining walls, located on both sides of the second insulating layer and / or the first gate layer remaining on the substrate groove; an interlayer dielectric layer, covering the substrate, the second insulating layer remaining on the base groove and / or the first gate layer; A connecting column is located in the interlayer dielectric layer, wherein the connecting column is connected to the first gate layer of the lead-out region.

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