Ultra-fast flash memory floating gate TiN film manufacturing method

Abstract

The present invention discloses a method for manufacturing a floating gate TiN film of an ultra-fast flash memory, comprising: completing the preceding process according to the prior art until the groove etching is completed; depositing TiN; depositing a wrapping layer to wrap the TiN; photolithography to define a protection area and a non-protection area, forming a protective layer to protect the protection area, and exposing the non-protection area; etching to remove the wrapping layer of the non-protection area, exposing the TiN of the non-protection area; removing the protective layer of the protection area; etching to remove the TiN of the non-protection area; depositing a wrapping layer to wrap the TiN of the protection area; etching to remove the wrapping layer at the top of the protection area and the bottom of the groove, forming a wrapping layer sidewall; etching to remove the TiN at the top of the protection area and the bottom of the groove and the wrapping layer sidewall, and retaining the TiN of the groove sidewall. The present invention can effectively retain the ultra-fast flash memory sidewall floating gate TiN film, and improve the device performance and uniformity.

Description

Technical Field

[0001] The invention relates to the field of integrated circuit manufacturing, and in particular to a method for manufacturing an ultra-fast flash memory floating gate TiN film. Background Art

[0002] Compared with the third generation Nor flash in the industry, 38SF (ultra-fast flash memory at 38nm technology node) has higher erase efficiency, higher erase and write durability, higher write efficiency, faster write speed, lower erase and write voltage, lower power consumption, no read and write interference, the storage unit size is only half of SF1.0, the process is simple, the test time is short, and the cost is greatly reduced. High speed, low power consumption and low voltage are the highlights of 38SF technology. The new ultra-fast flash memory 2.0 is a new generation of Nor flash that uses horizontal electric field write operation and cutting-edge TiN voltage-free coupling erase operation, which can greatly improve erase efficiency and reduce operating voltage. The growth and etching of each subsidiary layer in the ALD TiN floating gate process has extremely high requirements for uniformity and stability. In the process, multiple heat treatments are used to make TiN easily agglomerated, resulting in discontinuous TiN film, which seriously affects product performance. Summary of the invention

[0003] A series of simplified concepts are introduced in the Summary of the Invention, which are all simplifications of the prior art in the field, and will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention of the present invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0004] The technical problem to be solved by the present invention is to provide a method for manufacturing a super flash memory floating gate TiN film which can effectively retain the super flash memory sidewall floating gate TiN film to improve device performance and uniformity.

[0005] In order to solve the above technical problems, the present invention provides a method for manufacturing a floating gate TiN film of an ultra-fast flash memory, comprising the following steps:

[0006] S2, depositing an isolation layer;

[0007] S3, TiN deposition;

[0008] S4, depositing a wrapping layer, wrapping TiN;

[0009] S5, photolithography defines the protection area and the non-protection area, and forms a protection layer to protect the protection area and expose the non-protection area;

[0010] S6, etching to remove the encapsulation layer in the non-protected area, exposing the TiN in the non-protected area;

[0011] S7, removing the protective layer of the protected area;

[0012] S8, etching to remove TiN in non-protected areas;

[0013] S9, depositing a wrapping layer to wrap the TiN in the protection area;

[0014] S10, etching and removing the wrapping layer at the top of the protection zone and the bottom of the trench to form a wrapping layer sidewall;

[0015] S11, etching and removing the TiN on the top of the protection zone and the bottom of the trench as well as the sidewall of the encapsulation layer, and retaining the TiN on the sidewall of the trench.

[0016] Optionally, the ultra-fast flash memory floating gate TiN film manufacturing method is further improved, and the encapsulation layer is an oxide layer.

[0017] Optionally, the method for manufacturing the ultra-fast flash memory floating gate TiN film is further improved, and the oxide layer is formed by a low-temperature atomic layer deposition process.

[0018] Optionally, the ultra-fast flash memory floating gate TiN film manufacturing method is further improved, wherein the protection area is an active area, and the non-protection area is an isolation area.

[0019] Optionally, the ultra-fast flash memory floating gate TiN film manufacturing method is further improved, and the protective layer is a photoresist.

[0020] Optionally, the method for manufacturing the ultra-fast flash memory floating gate TiN thin film is further improved by performing step S5 to remove the oxide layer by dry isotropic etching.

[0021] Optionally, the method for manufacturing the ultra-fast flash memory floating gate TiN film is further improved, and step S7 is implemented to remove the TiN in the non-protected area by using dry and wet etching.

[0022] Optionally, the method for manufacturing the ultra-fast flash memory floating gate TiN thin film is further improved by performing step S9 to remove the oxide layer at the top of the active area and the bottom of the trench by dry anisotropic etching.

[0023] Optionally, the method for manufacturing the ultra-fast flash memory floating gate TiN film is further improved by performing step S10 to remove the TiN at the top of the protection zone and the bottom of the trench as well as the sidewall of the oxide layer by dry and wet etching.

[0024] After the groove is completed by the prior art, the present invention deposits a wrapping layer to wrap TiN to avoid TiN on the wafer surface, and then photolithography defines the protection area and non-protection area, forms a shielding layer to protect the protection area, exposes the non-protection area, etches to remove the wrapping layer of the non-protection area, and exposes the TiN in the non-protection area; removes the shielding layer of the protection area; etches to remove the TiN in the non-protection area; deposits a wrapping layer to wrap the TiN in the protection area to avoid the TiN on the wafer surface from being exposed and contaminated; etches to remove the wrapping layer at the top of the protection area and the bottom of the groove to form the side wall of the wrapping layer; etches to remove the TiN at the top of the protection area and the bottom of the groove and the side wall of the wrapping layer, and retains the TiN on the side wall of the groove. It is applied to 38SF to utilize the write operation of the horizontal electric field and the erase operation of the tip TiN without voltage coupling, which greatly improves the erase efficiency and reduces the operating voltage. The present invention can increase the nesting window of EG to FG and better tip control, and the Endurance performance is better. The cell area is only 60% of the same generation SF, and the number of embedded new masks is only half of SF, which can be reduced to <20nm. It can cover 4Mb~4Gb capacity and has NOR and NOVRAM functions (Internet of Things, AI, automotive electronics, etc.). The present invention can effectively retain the floating gate TiN film of the ultra-fast flash memory sidewall, improving device performance and uniformity. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings of the present invention are intended to illustrate the general characteristics of the methods, structures and / or materials used in specific exemplary embodiments of the present invention, and to supplement the description in the specification. However, the drawings of the present invention are schematic diagrams not drawn to scale, and thus may not accurately reflect the precise structure or performance characteristics of any given embodiment, and the drawings of the present invention should not be interpreted as limiting or restricting the range of values ​​or properties covered by the exemplary embodiments of the present invention. The present invention is further described in detail below in conjunction with the drawings and specific embodiments:

[0026] Figure 1 The intermediate structure of the present invention is shown in FIG. Figure 1 .

[0027] Figure 2 The intermediate structure of the present invention is shown in FIG. Figure 2 .

[0028] Figure 3 The intermediate structure of the present invention is shown in FIG. Figure 3 .

[0029] Figure 4 The intermediate structure of the present invention is shown in FIG. Figure 4 .

[0030] Figure 5 The intermediate structure of the present invention is shown in FIG. Figure 5 .

[0031] Figure 6 The intermediate structure of the present invention is shown in FIG. Figure 6 . DETAILED DESCRIPTION

[0032] The following describes the implementation methods of the present invention through specific specific embodiments, and those skilled in the art can fully understand other advantages and technical effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through different specific implementation methods, and the details in this specification can also be applied based on different viewpoints, and various modifications or changes can be made without deviating from the overall design concept of the invention. It should be noted that the following embodiments and the features in the embodiments can be combined with each other in the absence of conflict. The following exemplary embodiments of the present invention can be implemented in a variety of different forms and should not be interpreted as being limited to the specific embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary specific embodiments to those skilled in the art.

[0033] First embodiment;

[0034] The present invention provides a method for manufacturing an ultra-fast flash memory floating gate TiN film, comprising the following steps:

[0035] S1, completing the previous process according to the prior art until the trench etching is completed;

[0036] S2, depositing an isolation layer;

[0037] S3, TiN deposition;

[0038] S4, depositing a wrapping layer, wrapping TiN;

[0039] S5, photolithography defines the protection area and the non-protection area, and forms a protection layer to protect the protection area and expose the non-protection area;

[0040] S6, etching to remove the encapsulation layer in the non-protected area, exposing the TiN in the non-protected area;

[0041] S7, removing the protective layer of the protected area;

[0042] S8, etching to remove TiN in non-protected areas;

[0043] S9, depositing a wrapping layer to wrap the TiN in the protection area;

[0044] S10, etching and removing the wrapping layer at the top of the protection zone and the bottom of the trench to form a wrapping layer sidewall;

[0045] S11, etching and removing the TiN on the top of the protection zone and the bottom of the trench as well as the sidewall of the encapsulation layer, and retaining the TiN on the sidewall of the trench.

[0046] Second embodiment;

[0047] The present invention provides a method for manufacturing an ultra-fast flash memory floating gate TiN film, comprising the following steps:

[0048] S1, completing the previous process according to the prior art until the trench etching is completed;

[0049] S2, depositing an isolation layer;

[0050] S3, deposition of TiN;

[0051] S4, using low-temperature atomic layer deposition process to deposit an oxide layer to encapsulate TiN;

[0052] S5, photolithography defines the active area and the isolation area, and the photoresist shields and protects the active area, exposing the isolation area;

[0053] S6, etching and removing the oxide layer of the isolation region to expose the TiN in the isolation region;

[0054] S7, removing the photoresist in the active area;

[0055] S8, etching and removing TiN in the isolation area;

[0056] S9, using low temperature atomic layer deposition process to deposit an oxide layer to cover the TiN in the active area;

[0057] S10, etching and removing the oxide layer at the top of the active area and the bottom of the trench to form an oxide layer sidewall;

[0058] S11, etching and removing the TiN on the top of the protection zone and the bottom of the trench and the sidewall of the oxide layer, and retaining the TiN on the sidewall of the trench.

[0059] Exemplarily, the oxide layer may be made of hafnium dioxide.

[0060] In all the accompanying drawings, the same reference numerals represent the same elements all the time. In addition, it should also be understood that, although the terms "first", "second" etc. can be used here to describe different elements, parameters, components, regions, layers and / or parts, these elements, parameters, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, parameter, component, region, layer or part from another element, parameter, component, region, layer or part. Therefore, without departing from the teaching according to exemplary embodiments of the present invention, the first element, parameter, component, region, layer or part discussed below may also be referred to as the second element, parameter, component, region, layer or part.

[0061] Third embodiment;

[0062] The present invention provides a method for manufacturing an ultra-fast flash memory floating gate TiN film, comprising the following steps:

[0063] S1, completing the previous process according to the prior art until the trench etching is completed;

[0064] S2, depositing an isolation layer;

[0065] S3, transfer to HK FOUP and deposit TiN;

[0066] S4, using low temperature atomic layer deposition process to deposit hafnium dioxide, encapsulating TiN, such as Figure 1 As shown; the optional backside cleaning is transferred to HL FOU and then the subsequent step S4 is performed;

[0067] S5, photolithography defines the active area and isolation area, photoresist shields and protects the active area, exposing the isolation area, such as Figure 2 As shown;

[0068] S6, transfer to HK FOUP, use dry isotropic etching to remove the hafnium dioxide in the isolation area, and expose the TiN in the isolation area;

[0069] S7, removing the photoresist in the active area, such as Figure 3 As shown;

[0070] S8, etching to remove the TiN in the isolation region, such as Figure 4 As shown;

[0071] S9, using low temperature atomic layer deposition process to deposit hafnium dioxide to encapsulate the TiN in the active area;

[0072] S10, using dry anisotropic etching to remove the hafnium dioxide on the top of the active area and the bottom of the trench to form a hafnium dioxide sidewall, such as Figure 5 As shown;

[0073] S11, using dry and wet etching to remove TiN at the top of the protection zone and the bottom of the trench and the sidewall of hafnium dioxide, and retaining TiN on the sidewall of the trench, such as Figure 6 shown.

[0074] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. It will also be understood that, unless expressly defined herein, terms such as those defined in general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not interpreted in an ideal or overly formal sense.

[0075] The present invention has been described in detail above through specific implementation modes and embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may also make many variations and improvements, which should also be regarded as the protection scope of the present invention.

Claims

1. A method for manufacturing a TiN film on the sidewall of a floating gate trench, which is used in an ultra-fast flash memory, characterized in that: The following steps are involved: S1, completing the previous process according to the prior art until the trench etching is completed; S2, TiN deposition; S3, depositing a wrapping layer, wrapping TiN; S4, photolithography defines the protection area and the non-protection area, and forms a protection layer to protect the protection area and expose the non-protection area; S5, etching to remove the encapsulation layer in the non-protected area, exposing the TiN in the non-protected area; S6, remove the protective layer of the protected area; S7, etching to remove TiN in non-protected areas; S8, depositing a wrapping layer to wrap the TiN in the protection area; S9, etching and removing the wrapping layer at the top of the protection zone and the bottom of the trench to form a wrapping layer sidewall; S10, etching and removing the TiN on the top of the protection area and the bottom of the trench and the side wall of the wrapping layer, and retaining the TiN on the side wall of the trench, wherein the protection area is an active area, and the non-protection area is an isolation area.

2. The method for manufacturing a floating gate TiN thin film for an ultra-fast flash memory according to claim 1, wherein: The encapsulating layer is an oxide layer.

3. The method for manufacturing a floating gate TiN thin film for an ultra-fast flash memory as claimed in claim 2, characterized in that: The oxide layer is formed by a low-temperature atomic layer deposition process.

4. The method for manufacturing a floating gate TiN thin film for an ultra-fast flash memory as claimed in claim 1, characterized in that: The protective layer is photoresist.

5. The method for manufacturing a floating gate TiN thin film for an ultra-fast flash memory as claimed in claim 1, characterized in that: In step S5, dry isotropic etching is used to remove the oxide layer.

6. The method for manufacturing a floating gate TiN thin film for an ultra-fast flash memory as claimed in claim 1, characterized in that: In step S7, dry and wet etching are used to remove TiN in the non-protected area.

7. The method for manufacturing a floating gate TiN thin film for an ultra-fast flash memory as claimed in claim 1, characterized in that: Step S9 is implemented to remove the oxide layer on the top of the active area and the bottom of the trench by dry anisotropic etching.

8. The method for manufacturing a floating gate TiN thin film for an ultra-fast flash memory as claimed in claim 1, characterized in that: Step S10 is implemented to remove the TiN on the top of the protection area and the bottom of the trench as well as the sidewall of the oxide layer by dry and wet etching.

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