Semiconductor structure and method of forming the same

Abstract

The present application provides a semiconductor structure and a forming method thereof. The forming method comprises: providing a substrate having adjacent word line regions and a select gate region; sequentially forming a stack layer and a hard mask layer on the substrate; and forming a patterned mandrel on the hard mask layer. Further comprising forming a sidewall spacer on opposite sidewalls of the patterned mandrel, forming a patterned photoresist above the select gate region, and using the sidewall spacer and the patterned photoresist as a mask, sequentially patterning the hard mask layer and the stack layer to form word lines in the word line regions and a select gate in the select gate region, respectively, wherein the word lines have a first pitch, a first word line closest to the select gate has a second pitch with the select gate, and the second pitch is greater than the first pitch.

Description

Technical Field

[0001] This invention relates to semiconductor technology, and in particular to semiconductor structures formed by a self-aligned multiple patterning manufacturing process and methods thereof. Background Technology

[0002] With the advancement of technology, various electronic products are trending towards being lighter, thinner, shorter, and smaller. However, as component dimensions continue to shrink, many challenges arise. In conventional photolithography manufacturing processes, methods for reducing critical dimensions include using optical elements with larger numerical apertures (NA), shorter exposure wavelengths (e.g., extreme ultraviolet (EUV)), or using interface media other than air (e.g., water). As the resolution of conventional photolithography manufacturing processes gradually approaches its theoretical limit, manufacturers have begun to turn to methods such as double-patterning (DP) and quadruple-patterning (QP) to overcome optical limitations and thereby increase the density of memory components.

[0003] In current patterning methods, the pattern transfer manufacturing process for the select gate can affect the linewidth of the word line closest to the select gate, causing structural damage or breakage of the word line, thereby impacting the isolation and electrical performance of the memory array regions. Therefore, the industry still needs to improve memory manufacturing processes to increase memory yield. Summary of the Invention

[0004] This invention provides a method for forming a semiconductor structure, including providing a substrate having adjacent word line regions and select gate regions; sequentially forming a stacked layer and a hard mask layer on the substrate; forming a plurality of patterned mandrels on the hard mask layer, wherein the distance between the two closest patterned mandrels at the boundary between the word line region and the select gate region is smaller than the distance between patterned mandrels in the word line region; forming a plurality of sidewall spacers on a plurality of opposite sidewalls of the patterned mandrels; forming patterned photoresist above the select gate region; and using the sidewall spacers and patterned photoresist as masks, sequentially patterning the hard mask layer and the stacked layer to form a plurality of word lines in the word line region and select gates in the select gate region, wherein the word lines have a first spacing, and the first word line closest to the select gate has a second spacing with the select gate, and the second spacing is greater than the first spacing.

[0005] This invention provides a semiconductor structure including a substrate; a plurality of word lines disposed on the substrate, wherein the word lines extend along a first direction and are arranged along a second direction, and the first direction intersects the second direction; and a select gate disposed on the substrate, adjacent to and separated from the word lines in the second direction, wherein the word lines have a first spacing, and the first word line closest to the select gate has a second spacing with the select gate, and the second spacing is greater than the first spacing. Attached Figure Description

[0006] This application can be more fully understood through the following detailed description of the embodiments in conjunction with the accompanying drawings, in which:

[0007] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 as well as Figure 6 This is a cross-sectional schematic diagram of a semiconductor structure according to an embodiment of this application at various manufacturing stages;

[0008] Figure 7 This is a partial top view of a semiconductor structure according to an embodiment of this application;

[0009] Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 as well as Figure 14 This is a cross-sectional schematic diagram of a semiconductor structure according to another embodiment of this application at various manufacturing stages.

[0010] [Symbol Explanation]

[0011] 10, 20: Semiconductor Structure

[0012] 100:Substrate

[0013] 101: Character Line Area

[0014] 102: Select gate region

[0015] 105: Stacked Layers

[0016] 110: Sacrifice Layer

[0017] 115: Hard mask layer

[0018] 120: Patterned mandrel

[0019] 125, 125': First spacer

[0020] 127: First conjoined spacer

[0021] 130: Patterned photoresist

[0022] 133: Plasma Ions

[0023] 135: Second spacer

[0024] 137: Second Connecting Spacer

[0025] 200: Word Line

[0026] 300: Select Gate

[0027] 400: Virtual Structure

[0028] 500: Landing mat

[0029] d1, d2, d3, d4: Distance

[0030] S1: First spacing

[0031] S2: Second spacing

[0032] S3: Third spacing

[0033] S4: Fourth spacing

[0034] W1, W2: Width

[0035] X, Y, Z: Direction Detailed Implementation

[0036] In the optical lithography manufacturing process of flash memory, the cell structure is typically defined using self-aligned multiple patterning processes, such as self-aligned double-patterning (SADP) or self-aligned quadruple-patterning (SAQP). The select gate adjacent to the cell structure is usually formed directly using photoresist. However, because the select gate and the cell structure have different patterns, the photoresist defining the select gate may affect the pattern of the first word line closest to the select gate in subsequent pattern transfer processes. This causes the pattern of the first word line to be susceptible to additional plasma re-sputtering from the select gate photoresist during the pattern transfer etching process. In other words, ions in the plasma are reflected by the sidewalls of the select gate photoresist and subjected to secondary bombardment of the first word line pattern. Although the first word line is usually used as a dummy word line, damage to its pattern (e.g., line width) can still affect the integrity of the memory cell structure, and consequently affect the electrical performance of other word line arrays.

[0037] To address the aforementioned issues, embodiments of the present invention modify the pattern of the self-aligned multiple patterning and utilize interconnected spacers to enable the subsequently formed first word line to have a larger linewidth and a larger gap between the first word line and the select gate. This reduces the impact of the pattern transfer manufacturing process on the first word line and maintains the stability of the semiconductor structure and the performance of the memory device.

[0038] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 as well as Figure 6 This is a schematic cross-sectional view of the semiconductor structure 10 at various manufacturing stages, based on the first embodiment provided by the present invention. First see... Figure 1 In some embodiments, a substrate 100 is provided. In some embodiments, the substrate 100 has an adjacent word line region 101 and a select gate region 102.

[0039] refer to Figure 1 A stacked layer 105, a sacrificial layer 110, and a hard mask layer 115 are sequentially formed on a substrate 100. First, the stacked layer 105 is formed on the substrate 100. In some embodiments, the stacked layer 105 is a film layer stacked in the Z direction, where Z is the normal direction perpendicular to the main surface of the substrate 100. In some embodiments, the stacked layer 105 may sequentially include, from bottom to top in the Z direction, a tunneling dielectric layer, a floating gate layer, an inter-gate dielectric layer, a control gate layer, a metal layer, and a capping layer. For the sake of simplicity, the above layers are not shown in detail, and only the stacked layer 105 is schematically shown. In some embodiments, the material of the tunneling dielectric layer may be silicon oxide. In some embodiments, the material of the patterned floating gate layer may be a conductive material, such as doped polysilicon, undoped polysilicon, or a combination thereof. In some embodiments, the inter-gate dielectric layer may be a composite layer such as that composed of oxide / nitride / oxide (ONO), but the invention is not limited thereto, and the composite layer may also be a film layer with five or more layers. In some embodiments, the material of the control gate layer may be a conductive material, such as doped polysilicon, undoped polysilicon, or a combination thereof. In some embodiments, the material of the metal layer may be such as W, TiN, or a combination thereof. In some embodiments, the material of the capping layer may be a dielectric material, such as silicon nitride, silicon oxynitride, or a combination thereof.

[0040] Next, a sacrificial layer 110 and a hard mask layer 115 are sequentially formed on the stacked layer 105. The sacrificial layer 110 can protect the stacked layer 105 from the etching process during the subsequent fabrication steps of patterning the hard mask layer 115. The hard mask layer 115 can serve as a patterning mask for the stacked layer 105 in subsequent fabrication steps to form word lines 200 and select gates 300, as will be described in detail below. In some embodiments, the material of the sacrificial layer 110 comprises silicon oxide. In some embodiments, the hard mask layer 115 may be a single-layer or multi-layer structure. In some embodiments, the material of the hard mask layer 115 comprises polysilicon (poly-Si).

[0041] See Figure 2 In the first embodiment, a plurality of patterned mandrels 120 are formed on the hard mask layer 115. In some embodiments, the distance d1 between the two closest patterned mandrels 120 at the boundary between the word line region 101 and the select gate region 102 is smaller than the distance d2 between the patterned mandrels 120 in the word line region 101, such as... Figure 2 As illustrated. Generally, in the patterning manufacturing process for forming word lines and select gates, patterned mandrels with a fixed spacing are typically formed. After the mandrel pattern transfer manufacturing process, another patterning manufacturing process is used to separate the pattern into word line patterns and select gate patterns. Therefore, during the pattern transfer manufacturing process, the pattern of the first word line closest to the select gate pattern is susceptible to additional plasma damage, leading to structural instability or breakage issues in the subsequently formed first word line. Compared to conventional techniques, in the step of forming the patterned mandrel 120, the present invention first forms the patterned mandrel 120 in the select gate region 102 to a larger width (e.g., forming the patterned mandrel 120 in the select gate region 102 to a width W1) so that the pattern of the first word line can have a larger distance from the pattern of the select gate. In addition, patterned mandrels 120 with different spacings (e.g., d1 < d2) are formed in the word line region 101 and the select gate region 102, thereby forming a larger merged spacer (i.e., corresponding to the pattern of the first word line) in the subsequent manufacturing process. This reduces the additional damage to the pattern of the first word line by the plasma in the pattern transfer manufacturing process and effectively improves the problem of instability or breakage of the first word line structure.

[0042] In this embodiment of the invention, the patterned mandrel 120 can be used in subsequent manufacturing processes for self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP) processes. The following description will use self-aligned double patterning as an example. In some embodiments, the patterned mandrel 120 is formed by first forming a mandrel layer (not shown) on a hard mask layer 115, and then forming a photoresist pattern on the mandrel layer via photolithography and etching processes. Next, an etching process is performed to transfer the photoresist pattern to the mandrel layer, thereby forming the patterned mandrel 120. In some embodiments, the material of the patterned mandrel 120 may include carbon, silicon oxynitride (SiON), a bottom anti-reflective coating (BARC), or a combination thereof.

[0043] See Figure 3 After the patterned mandrel 120 is formed, a self-aligned double patterning (SADP) fabrication process is performed to form a plurality of first spacers 125 on a plurality of opposing sidewalls of the patterned mandrel 120, and to form a first integral spacer 127 between two adjacent patterned mandrels 120 in the word line region 101 and the select gate region 102. In some embodiments, the self-aligned double patterning fabrication process includes compliantly forming a first spacer material layer (not shown) on the hard mask layer 115 and the patterned mandrel 120. In some embodiments, the material of the first spacer material layer may be an oxide such as silicon oxide (SiOx). In some embodiments, after forming the first spacer material layer, an etching-back process is performed on the first spacer material layer until the top surface of the patterned mandrel 120 and a portion of the top surface of the hard mask layer 115 are exposed, thereby forming the first spacer 125 on the opposite sidewalls of the patterned mandrel 120, and forming a first connected spacer 127 between two adjacent patterned mandrels 120 in the word line region 101 and the select gate region 102. In some embodiments, the ratio of the width of the first connected spacer 127 to the width of the first spacer 125 is greater than 1 and not greater than 2. It is worth noting that if the ratio of the width of the first connected spacer 127 to the width of the first spacer 125 is greater than 2, it may increase the difficulty of forming the first connected spacer 127.

[0044] See Figure 4The patterned mandrel 120 is removed, leaving the first spacer 125 and the first interconnected spacer 127 on the hard mask layer 115. In the first embodiment, after removing the patterned mandrel 120, the patterns of the first spacer 125 and the first interconnected spacer 127 can be sequentially transferred to the hard mask layer 115 and the stacked layer 105 to form word lines 200 and the first word line 200' closest to the select gate 300. In the second embodiment, after removing the patterned mandrel 120, the self-aligned quadruple patterning (SAQP) manufacturing process can continue, as detailed below. In the first embodiment, after the patterned mandrel 120 is removed, the first spacers 125 remaining on the hard mask layer 115 in the word line region 101 have a first spacing S1, which is essentially the first spacing S1 between the word lines 200 subsequently formed in the word line region 101, and the first integral spacer 127 and the first spacers 125 in the select gate region 102 have a second spacing S2, which is essentially the second spacing S2 between the subsequently formed first word lines 200' and the select gate 300. In some embodiments, the patterned mandrel 120 can be removed using the previously described etching process, stripping process, ashing process, or a combination thereof.

[0045] See Figure 5 A patterned photoresist 130 is formed over the select gate region 102. The patterned photoresist 130 can be used to define a pattern 300 of the subsequently formed select gate in the select gate region 102. In some embodiments, the patterned photoresist 130 may partially cover the first spacer 125 closest to the word line region on the select gate region 102, exposing a portion of the first spacer 125. This helps to improve alignment misalignment that may occur between the patterned photoresist 130 and the first spacer 125 on the select gate region 102 due to pattern overlap, thereby ensuring that the select gate 300 can be formed to the desired width. In some embodiments, the distance between the patterned photoresist 130 and the first integral spacer 127 may be substantially equal to the second pitch S2. In some embodiments, the height of the patterned photoresist 130 is greater than the height of the first spacer 125 and the first integral spacer 127. This helps to reduce etching damage to the first spacer 125 and the first integral spacer 127 during the formation of the patterned photoresist 130.

[0046] See also Figure 5In subsequent pattern transfer manufacturing processes, plasma ions 133 may be reflected by the sidewalls of the patterned photoresist 130 and bombard the first interconnected spacer 127, causing the first interconnected spacer 127 (i.e., the pattern corresponding to the subsequent formation of the first word line 200') to be subjected to additional ion bombardment. However, in this embodiment of the invention, by reducing the distance d1 between the two closest patterned mandrels 120 at the junction of the word line region 101 and the select gate region 102, a first interconnected spacer 127 with a larger width is formed (i.e., two adjacent first spacers 125 are adjacent to each other and merged), the manufacturing process margin of the first interconnected spacer 127 being bombarded by plasma ions 133 can be increased, and the integrity of the pattern of the first word line 200' can be maintained. It is worth noting that, in the first embodiment, the distance between the first interconnecting spacer 127 and the patterned photoresist 130 is also increased by increasing the width W1 of the patterned mandrel 120 located in the select gate region 102 (that is, equivalent to increasing the second spacing S2 between the first word line 200' and the select gate 300). This helps to reduce the possibility of plasma ions 133 bombarding the first interconnecting spacer 127, thereby maintaining the pattern integrity of the first word line 200'.

[0047] See Figure 5 as well as Figure 6 Using the first spacer 125, the first interconnected spacer 127, and the patterned photoresist 130 as masks, the patterns of the first spacer 125 and the first interconnected spacer 127 are sequentially transferred to the hard mask layer 115 and the stacked layer 105 to form word lines 200 and first word lines 200'. Simultaneously, the pattern of the patterned photoresist 130 is sequentially transferred to the hard mask layer 115 and the stacked layer 105 to form the select gate 300. The first word line 200' is the first word line of word line 200 closest to the select gate 300. In other words, the portion of the stacked layer 105 in the word line region 101 corresponding to the first spacer 125 and the first interconnected spacer 127 is formed as word lines 200 and first word lines 200', respectively, and the portion of the stacked layer 105 in the select gate region 102 corresponding to the patterned photoresist 130 is formed as the select gate 300. In some embodiments, a first spacing S1 is provided between word lines 200. The first spacing S1 may correspond to the spacing between first spacers 125 in word line region 101, or it may correspond to the width of patterned mandrels 120 in word line region 101. A second spacing S2 is provided between the first word line 200' closest to the select gate 300 and the select gate 300. The second spacing S2 may correspond to the width W1 of patterned mandrels 120 in select gate region 102. In some embodiments, the second spacing S2 is greater than the first spacing S1. In some embodiments, the width of the first word line 200' is greater than the width of any other word line 200. In some embodiments, the width of the first word line 200' may be equal to the second spacing S2.

[0048] Figure 7 This is a partial top view schematic diagram of a semiconductor structure 10 according to a first embodiment provided in this application. In some embodiments, the semiconductor structure 10 further includes a dummy structure 400 and a plurality of landing pads 500. The formation of the dummy structure 400 can prevent the end portions of the word lines 200 from being affected by the etching load effect and producing uneven widths. The landing pads 500 can serve as pick-ups for the word lines 200 and are respectively connected to another plurality of word lines 200 (not shown). In some embodiments, the word lines 200 extend along a first direction (e.g., direction X) and are arranged along a second direction (e.g., direction Y), and the first direction intersects the second direction. In some embodiments, the select gate 300 is adjacent to and spaced apart from the word lines 200 in the second direction (e.g., direction Y), and the select gate 300 is disposed on both sides of the word lines 200 in the second direction. As previously described, word lines 200 have a first spacing S1, and the first word line 200' closest to the select gate 300 has a second spacing S2 with the select gate. In some embodiments, the second spacing S2 is greater than the first spacing S1. Figure 7 As illustrated. In some embodiments, the ratio of the width of the first word line 200' to the width of any other word line 200 is greater than 1 and not greater than 2. In some embodiments, the ratio of the second spacing S2 to the width of any other word line 200 besides the first word line 200' is greater than 1 and not greater than 2. In some embodiments, the ratio of the second spacing S2 to the first spacing S1 is greater than 1 and not greater than 2. In some embodiments, the ratio of the width of the first word line 200' to the first spacing S1 is greater than 1 and not greater than 2. After forming the word line 200, the first word line 200', the select gate 300, the dummy structure 400, and the landing pad 500, various semiconductor manufacturing processes such as deposition, photolithography, and etching can be performed to form other related components of the memory device, such as capacitor contact windows and bit lines, which will not be further described here.

[0049] Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 as well as Figure 14 This is a cross-sectional schematic diagram of the semiconductor structure 20 at various manufacturing stages, according to a second embodiment of this application. Similar to the first embodiment, Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 as well as Figure 6This is an example of a self-aligned double patterning (SADP) manufacturing process. Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 as well as Figure 14 This is an example of a self-aligned quadruple patterning (SAQP) manufacturing process. See also Figure 8 Similar to the first embodiment, a stacked layer 105, a sacrificial layer 110, and a hard mask layer 115 are sequentially formed on the substrate 100, and a plurality of patterned mandrels 120 are formed on the hard mask layer 115. The stacked layer 105, sacrificial layer 110, hard mask layer 115, and patterned mandrels 120 in the second embodiment are similar to those in the first embodiment and will not be described again here. In some embodiments, the two closest patterned mandrels 120 at the boundary between the word line region 101 and the select gate region 102 have a distance d3 between them, and the patterned mandrels 120 in the word line region 101 have a distance d4 between them, and the distance d3 is less than the distance d4, such as... Figure 8 As illustrated. In the second embodiment, the distance between the subsequently formed first word line 200' and the select gate 300 is also controlled by changing the spacing (i.e., distance d3) of the patterned mandrel 120 in the word line region 101 and the select gate region 102, as will be described in detail later. It is worth noting that in the second embodiment, the width of the subsequently formed first word line 200' is controlled by controlling the width W2 of the patterned mandrel 120 closest to the select gate region 102 in the word line region 101, as will be described in detail later. In some embodiments, the material of the patterned mandrel 120 may include carbon, silicon oxynitride (SiON), bottom anti-reflective coating (BARC), or a combination thereof.

[0050] See Figure 9Similar to the first embodiment, after forming the patterned mandrel 120, a plurality of first spacers 125 are first formed on a plurality of opposing sidewalls of the patterned mandrel 120, and a first contiguous spacer 127 is formed between two adjacent patterned mandrels 120 in the word line region 101 and the select gate region 102. Similar to the first embodiment, the formation of the first spacers 125 and the first contiguous spacers 127 may include compliantly forming a first spacer material layer (not shown) on the hard mask layer 115 and the patterned mandrel 120. In some embodiments, the first spacer material layer may be formed by methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or a combination thereof. In some embodiments, after forming the first spacer material layer, the first spacer material layer is etched back until the top surface of the patterned mandrel 120 and a portion of the top surface of the hard mask layer 115 are exposed, thereby forming the first spacer 125 on the opposite sidewalls of the patterned mandrel 120, and forming a first connected spacer 127 between two adjacent patterned mandrels 120 in the word line region 101 and the select gate region 102. In some embodiments, the ratio of the width of the first connected spacer 127 to the width of the first spacer 125 is greater than 1 and not greater than 2. It is worth noting that if the ratio of the width of the first connected spacer 127 to the width of the first spacer 125 is greater than 2, it may increase the difficulty of forming the first connected spacer 127.

[0051] It is worth noting that in the second embodiment, the width of the first interconnected spacer 127 is changed by controlling the distance d3 between the two closest patterned spindles 120 at the junction of the word line region 101 and the select gate region 102. That is, the two closest first spacers 125 are adjacent to each other and merged to form the first interconnected spacer 127, so as to increase the distance between the subsequently formed first word line 200' and the select gate 300 (e.g., the fourth spacing S4).

[0052] See Figure 10 The patterned mandrel 120 is removed, leaving the first spacer 125 and the first integral spacer 127 on the hard mask layer 115. In some embodiments, the patterned mandrel 120 may be removed using the previously described etching process, stripping process, ashing process, or a combination thereof. Unlike the first embodiment, after removing the patterned mandrel 120, the second embodiment continues the self-aligned quadruple patterning (SAQP) process. In the second embodiment, after removing the patterned mandrel 120, the distance between the first integral spacer 127 and the closest first spacer 125 in the word line region 101 is substantially the width W2 of the patterned mandrel 120 closest to the select gate region 102 in the aforementioned word line region 101.

[0053] See Figure 11After removing the patterned mandrel 120, a plurality of second spacers 135 are formed on the plurality of opposite sidewalls of the first spacer 125 and the first connected spacer 127, using the first spacer 125 and the first connected spacer 127 as mandrels. A second connected spacer 137 is formed between the first connected spacer 127 and the first spacer 125' closest to the word line area. In other words, two second spacers 135 are adjacent to each other and merged to form a second connected spacer 137. In some embodiments, the second spacer 135 and the second integrated spacer 137 can be formed using a method similar to that used to form the first spacer 125 and the first integrated spacer 127, but with the difference that the second spacer 135 and the second integrated spacer 137 use materials with different etching selectivity than the first spacer 125 and the first integrated spacer 127, so that the first spacer 125 and the first integrated spacer 127 can be selectively removed in subsequent manufacturing processes without removing the second spacer 135 and the second integrated spacer 137. In some embodiments, the width of the first integrated spacer 127 is equal to the width of the second integrated spacer 137. In a second embodiment, the materials of the first spacer 125 and the first integrated spacer 127 may include silicon oxide, silicon nitride, and polysilicon, while the materials of the second spacer 135 and the second integrated spacer 137 may include silicon oxide, silicon nitride, and polysilicon. It is worth noting that in some embodiments, the first spacer 125 and the first interconnected spacer 127 are made of different materials than the second spacer 135 and the second interconnected spacer 137, but the materials can be interchanged. For example, if the first spacer 125 and the first interconnected spacer 127 are made of polysilicon, then the second spacer 135 and the second interconnected spacer 137 are made of silicon oxide or silicon nitride; and if the first spacer 125 and the first interconnected spacer 127 are made of silicon oxide or silicon nitride, then the second spacer 135 and the second interconnected spacer 137 are made of polysilicon. In a second embodiment, the width of the second interconnected spacer 137 corresponds to the width W2 of the patterned spindle 120 closest to the select gate region 102 in the aforementioned word line region 101.

[0054] See Figure 12The first spacer 125 and the first connected spacer 127 are selectively removed to leave the second spacer 135 and the second connected spacer 137 on the hard mask layer 115. The second spacer 135 and the second connected spacer 137 in the word line region 101 correspond to the subsequently formed word lines 200 and first word lines 200', respectively. In some embodiments, the first spacer 125 and the first connected spacer 127 can be removed using the previously described etching process, stripping process, ashing process, or a combination thereof. Compared with the first embodiment, the second embodiment using the self-aligned quadruple patterning (SAQP) process can form a spacer pattern with a smaller pitch, thereby subsequently forming word lines 200 with smaller line widths and line spacings. In the second embodiment, after selectively removing the first spacer 125 and the first interconnected spacer 127, a third spacing S3 is formed between the second spacers 135 remaining on the hard mask layer 115 in the word line region 101. This third spacing S3 is essentially the third spacing S3 between the word lines 200 subsequently formed in the word line region 101. A fourth spacing S4 is formed between the second interconnected spacer 137 and the second spacer 135 closest to the boundary between the word line region 101 and the select gate region 102 in the select gate region 102. This fourth spacing S4 is essentially the second spacing S2 between the subsequently formed first word line 200' and the select gate 300. In some embodiments, the ratio of the width of the second interconnected spacer 137 to the width of the second spacer 135 is greater than 1 and not greater than 2.

[0055] See Figure 13 A patterned photoresist 130 is formed over the select gate region 102. The patterned photoresist 130 can be used to define a pattern 300 of the subsequently formed select gate in the select gate region 102. In some embodiments, the patterned photoresist 130 may partially cover the second spacer 135 closest to the word line region on the select gate region 102, exposing a portion of the second spacer 135. This helps to improve alignment misalignment that may occur between the patterned photoresist 130 and the second spacer 135 due to pattern overlap, thereby ensuring that the select gate 300 can be formed to the desired width. In some embodiments, the distance between the patterned photoresist 130 and the second integral spacer 137 may be substantially equal to the fourth pitch S4. In some embodiments, the height of the patterned photoresist 130 is greater than the height of the second spacer 135 and the second integral spacer 137. This helps to reduce etching damage to the second spacer 135 and the second integral spacer 137 during the formation of the patterned photoresist 130.

[0056] Furthermore, as mentioned above, in the subsequent pattern transfer manufacturing process, plasma ions 133 may be reflected by the sidewalls of the patterned photoresist 130 and bombard the second interconnected spacer 137, causing the second interconnected spacer 137 (i.e., the pattern corresponding to the subsequent formation of the first word line 200') to be subjected to additional ion bombardment. However, in this embodiment of the invention, by controlling the distance between the first spacer 125' and the first interconnected spacer 127 (i.e., the width W2 corresponding to the width of the patterned mandrel 120 closest to the select gate region 102 in the word line region 101), a second interconnected spacer 137 with a larger width can be formed, which can increase the manufacturing process margin of the second interconnected spacer 137 being bombarded by plasma ions 133 and maintain the integrity of the pattern of the first word line 200'. Furthermore, in the second embodiment, by increasing the width of the first interconnecting spacer 127 (i.e., the distance d3 between the two closest patterned spindles 120 at the junction of the word line region 101 and the select gate region 102), the distance between the second interconnecting spacer 137 and the patterned photoresist 130 is increased (e.g., a fourth spacing S4). This helps to reduce the possibility of plasma ions 133 bombarding the second interconnecting spacer 137, thereby maintaining the pattern integrity of the first word line 200'.

[0057] See Figure 13 as well as Figure 14Using the second spacer 135, the second interconnected spacer 137, and the patterned photoresist 130 as masks, the patterns of the second spacer 135 and the second interconnected spacer 137 are sequentially transferred to the hard mask layer 115 and the stacked layer 105 to form word lines 200 and first word lines 200', and the pattern of the patterned photoresist 130 is sequentially transferred to the hard mask layer 115 and the stacked layer 105 to form the select gate 300, where the first word line 200' is the first word line of word line 200 closest to the select gate 300. In other words, the portion of the stacked layer 105 in the word line region 101 corresponding to the second spacer 135 and the second interconnected spacer 137 is formed as word lines 200 and first word lines 200', respectively, and the portion of the stacked layer 105 in the select gate region 102 corresponding to the patterned photoresist 130 is formed as the select gate 300. In some embodiments, a third spacing S3 is provided between word lines 200. The third spacing S3 may correspond to the spacing between second spacers 135 in word line region 101, or to the width of first spacers 125 in word line region 101. A fourth spacing S4 is provided between the first word line 200' closest to the select gate 300 and the select gate 300. The fourth spacing S4 may correspond to the width of the first interconnected spacer 127, or to the distance d3 between the two closest patterned spindles 120 at the junction of word line region 101 and select gate region 102. In some embodiments, the fourth spacing S4 is greater than the third spacing S3. In some embodiments, the width of the first word line 200' is greater than the width of any other word line 200. In some embodiments, the width of the first word line 200' is equal to the fourth spacing S4. In some embodiments, the first word line 200' is separated from the select gate 300 by the width of the first interconnected spacer 127.

[0058] See the description of the first embodiment above. Figure 7 As mentioned above, similar to semiconductor structure 10, semiconductor structure 20 can continue to undergo semiconductor manufacturing processes such as various deposition, photolithography, and etching to form other related components of the memory device, such as capacitor contact windows and bit lines, which will not be further described here.

[0059] In summary, compared to conventional patterning manufacturing processes, this invention, by altering the spacing of the patterned mandrels, further controls the formation of the interconnected spacers, thereby increasing the width of the first word line closest to the select gate. Furthermore, by changing the width of the patterned mandrels or the width of the interconnected spacers, the distance between the word line and the select gate is increased, preventing potential breakage or other damage to the first word line. It should be understood that not all advantages are necessarily discussed herein, nor are all embodiments required to possess specific advantages, and other embodiments may offer different advantages.

[0060] Those skilled in the art will understand that such equivalent structures do not depart from the spirit and scope of the invention, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of the invention. Therefore, the scope of protection of the invention shall be determined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate having an adjacent word line region and a select gate region; A stacked layer and a hard mask layer are sequentially formed on the substrate; Multiple patterned mandrels are formed on the hard mask layer, wherein the distance between the two closest patterned mandrels at the junction of the word line region and the selected gate region is smaller than the distance between the patterned mandrels in the word line region; Multiple sidewall spacers are formed on multiple opposing sidewalls of the patterned mandrel, and a first integral spacer is provided between two adjacent patterned mandrels in the word line region and the select gate region; A patterned photoresist is formed over the selected gate region; as well as Using the plurality of sidewall spacers and the patterned photoresist as masks, the hard mask layer and the stacked layer are patterned sequentially to form a plurality of word lines in the word line region and a selection gate in the selection gate region, respectively. The plurality of word lines have a first spacing between them, and the first word line closest to the select gate has a second spacing with the select gate, and the second spacing is greater than the first spacing.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The steps of forming the plurality of sidewall spacers include: A plurality of first spacers are formed on the plurality of opposite sidewalls of the patterned mandrels, and the first integral spacers are formed between two adjacent patterned mandrels in the word line region and the select gate region; Remove the patterned mandrel to leave the plurality of first spacers and the first integral spacer on the hard mask layer; and The patterns of the plurality of first spacers and the first connected spacers are sequentially transferred to the hard mask layer and the stacked layer to form the word line and the select gate, wherein the portion of the stacked layer in the word line region corresponding to the plurality of first spacers and the first connected spacers is formed as the word line and the first word line, respectively, and the portion of the stacked layer in the select gate region corresponding to the patterned photoresist is formed as the select gate.

3. The method for forming a semiconductor structure according to claim 2, characterized in that, The ratio of the width of the first interconnected spacer to the width of the plurality of first spacers is greater than 1 and not greater than 2.

4. The method for forming a semiconductor structure according to claim 2, characterized in that, The height of the patterned photoresist is greater than the height of the plurality of first spacers and the first conjoined spacer.

5. The method for forming a semiconductor structure according to claim 2, characterized in that, The width of the first character line is greater than the width of any other character line.

6. The method for forming a semiconductor structure according to claim 1, characterized in that, The steps of forming the plurality of sidewall spacers include: A plurality of first spacers are formed on the plurality of opposite sidewalls of the patterned mandrels, and the first integral spacers are formed between two adjacent patterned mandrels in the word line region and the select gate region; Remove the patterned mandrel to leave the plurality of first spacers and the first integral spacer on the hard mask layer; Multiple second spacers are formed on multiple opposite sidewalls of the multiple first spacers and the first connected spacers, and a second connected spacer is formed between the first connected spacer and the closest first spacer in the word line area; Remove the plurality of first spacers and the first interconnected spacers to leave the plurality of second spacers and the second interconnected spacers on the hard mask layer; and The patterns of the plurality of second spacers and the second interconnected spacers are sequentially transferred to the hard mask layer and the stacked layer to form the word line and the select gate, wherein the portion of the stacked layer in the word line region corresponding to the plurality of second spacers and the second interconnected spacers is formed as the word line and the first word line, respectively, and the portion of the stacked layer in the select gate region corresponding to the patterned photoresist is formed as the select gate.

7. The method for forming a semiconductor structure according to claim 6, characterized in that, Before forming the hard mask layer on the stacked layers, the method further includes: A sacrificial layer is formed on the stacked layer, the sacrificial layer protecting the stacked layer from etching during the step of transferring the pattern of the plurality of second spacers and the second interconnected spacers to the hard mask layer, wherein the hard mask layer comprises polysilicon and the sacrificial layer comprises silicon oxide.

8. A semiconductor structure, characterized in that, include: One substrate; Multiple character lines are disposed on the substrate, wherein the character lines extend along a first direction and are arranged along a second direction, and the first direction intersects the second direction; as well as A select gate is disposed on the substrate and is adjacent to and separated from the word lines in the second direction. The word lines have a first spacing, and the first word line closest to the select gate has a second spacing with the select gate. The second spacing is greater than the first spacing, and the width of the first word line is greater than the first spacing.

9. The semiconductor structure according to claim 8, characterized in that, The width of the first character line is greater than the width of any other character line.

10. The semiconductor structure according to claim 8, characterized in that, The width of the first character line is equal to the second spacing.

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