Memory device and method of manufacturing the same

Abstract

The invention relates to a memory device and a manufacturing method of the memory device. A memory device includes: a first stacked structure including conductive layers stacked in a first direction, the first stacked structure having a step structure defined by ends of the conductive layers; contact plugs connected to the conductive layers, respectively, the contact plugs extending in a first direction, the contact plugs extending into the first stack structure; and a dummy layer between the contact plugs.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0110420 filed in the Korean Intellectual Property Office on August 23, 2023, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to a memory device and a method of manufacturing the memory device, and more particularly, to a memory device including a memory block having a three-dimensional structure and a method of manufacturing the memory device. Background Art

[0004] The memory device may include a nonvolatile memory device in which data stored remains intact even when power is interrupted. According to the structure in which the memory cells are arranged, the nonvolatile memory device may be divided into a two-dimensional structure and a three-dimensional structure. The memory cells of the nonvolatile memory device having a two-dimensional structure may be arranged in a single layer above a substrate, and the memory cells of the nonvolatile memory device having a three-dimensional structure may be stacked above the substrate in a vertical direction. Because the integration level of the nonvolatile memory device having a three-dimensional structure is higher than that of the nonvolatile memory device having a two-dimensional structure, electronic devices using the nonvolatile memory device having a three-dimensional structure have recently been increasingly used. Summary of the invention

[0005] According to one embodiment of the present disclosure, a memory device is provided, which includes: a first stacking structure, which includes conductive layers stacked along a first direction, the first stacking structure has a step structure defined by ends of the conductive layers; contact plugs respectively connected to the conductive layers, the contact plugs extending along the first direction, the contact plugs extending to the interior of the first stacking structure; and a dummy layer located between the contact plugs.

[0006] According to one embodiment of the present disclosure, a method for manufacturing a memory device is provided, the method comprising: forming a first preliminary stacking structure, the first preliminary stacking structure comprising a first material layer and a second material layer stacked alternately, the first preliminary stacking structure having a step structure defined by an end of the second material layer; forming a covering pattern on a top surface of the end of the second material layer; forming a second preliminary stacking structure by alternately stacking a first dummy material layer and a second dummy material layer, the first dummy material layer and the second dummy material layer respectively extending along the end on the step structure; forming a first opening, the first opening penetrating the first preliminary stacking structure and the second preliminary stacking structure; forming a recess by removing a portion of each of the second material layer and the second dummy material layer exposed by the first opening; forming a spacer layer in the first opening and the recess; forming a second opening penetrating the spacer layer; forming a third opening by removing the covering pattern through the second opening; and forming a contact plug by filling a conductive material in the second opening and the third opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein.

[0008] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. Like reference numerals refer to like elements throughout.

[0009] Figure 1 is a diagram illustrating a memory device according to one embodiment of the present disclosure.

[0010] Figure 2 is a view schematically illustrating a memory device according to an embodiment of the present disclosure.

[0011] Figure 3 is a view illustrating a cell region and a contact region of a memory device according to an embodiment of the present disclosure.

[0012] Figure 4A , Figure 4B and Figure 4C is a view illustrating a structure of a memory device according to an embodiment of the present disclosure.

[0013] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Fig. 5F , Figure 5G , Figure 5H , Fig.5I, Figure 5J , Figure 5K , Figure 5L and Figure 5M is a view illustrating a method of manufacturing a memory device according to an embodiment of the present disclosure.

[0014] Figure 6 is a diagram illustrating a memory card system to which the memory device of the present disclosure is applied.

[0015] Figure 7 is a diagram illustrating a solid-state drive (SSD) system to which the memory device of the present disclosure is applied. DETAILED DESCRIPTION

[0016] The specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concepts of the present disclosure. Embodiments according to the concepts of the present disclosure may be implemented in various forms and should not be interpreted as being limited to the embodiments set forth herein.

[0017] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical spirit of the present disclosure. It will be understood that when an element or layer, etc. is referred to as being "on", "connected to" or "coupled to" another element or layer, etc., it may be directly on, directly connected to or directly coupled to the other element or layer, etc., or there may be an intermediate element or layer, etc. In contrast, when an element or layer, etc. is referred to as being "directly" "on", "directly connected to" or "directly coupled to" another element or layer, etc., there are no intermediate elements or layers, etc.

[0018] Various embodiments provide a memory device and a method of manufacturing the memory device, which can minimize shape distortion of a contact plug.

[0019] Figure 1 is a diagram illustrating a memory device according to one embodiment of the present disclosure.

[0020] refer to Figure 1 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 170 , and a control circuit 180 .

[0021] The memory cell array 110 may include first to i-th memory blocks BLK1 to BLKi. Each of the first to i-th memory blocks BLK1 to BLKi may include a memory cell capable of storing data. A drain select line DSL, a word line WL, a source select line SSL, and a source line SL may be connected to each of the first to i-th memory blocks BLK1 to BLKi, and a bit line BL may be commonly connected to the first to i-th memory blocks BLK1 to BLKi.

[0022] The first to i-th memory blocks BLK1 to BLKi may be formed in a three-dimensional structure. The memory block having the three-dimensional structure may include memory cells stacked in a vertical direction over a substrate.

[0023] According to the programming method, the memory cell can store one bit or two or more bits of data. For example, the method of storing one bit of data in one memory cell is called a single-level cell (SLC) method, and the method of storing two bits of data in one memory cell is called a multi-level cell (MLC) method. The method of storing three bits of data in one memory cell is called a three-level cell (TLC) method, and the method of storing four bits of data in one memory cell is called a quad-level cell (QLC) method. In addition, five or more bits of data can be stored in one memory cell.

[0024] The peripheral circuit 170 may be configured to perform a program operation for storing data, a read operation for outputting data stored in the memory cell array 110, and an erase operation for erasing data stored in the memory cell array 110. For example, the peripheral circuit 170 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, and an input / output circuit 160.

[0025] The voltage generator 120 may generate various operation voltages Vop for a programming operation, a reading operation, or an erasing operation in response to the operation code OPCD. For example, the voltage generator 120 is configured to generate a programming voltage, a turn-on voltage, a turn-off voltage, a negative voltage, a precharge voltage, a verification voltage, a read voltage, a pass voltage, or an erase voltage in response to the operation code OPCD. The operation voltage Vop generated by the voltage generator 120 may be applied to the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL of the selected memory block through the row decoder 130.

[0026] The programming voltage is a voltage applied to a selected word line among word lines WL in a programming operation, and can be used to increase the threshold voltage of a memory cell connected to the selected word line. The turn-on voltage can be applied to a drain select line DSL or a source select line SSL, and is used to turn on a drain select transistor or a source select transistor. The turn-off voltage can be applied to a drain select line DSL or a source select line SSL, and is used to turn off a drain select transistor or a source select transistor. For example, the turn-off voltage can be set to 0V. The precharge voltage is a voltage higher than 0V, and can be applied to a bit line in a read operation. The verification voltage can be used in a verification operation to determine whether the threshold voltage of the selected memory cell has increased to a target level. The verification voltage can be set to various levels according to the target level and is applied to the selected word line.

[0027] The read voltage may be applied to the selected word line in the read operation of the selected memory cell. For example, the read voltage may be set to various levels according to the programming mode of the selected memory cell. The pass voltage is a voltage applied to the unselected word lines among the word lines WL in the programming or reading operation, and may be used to turn on the memory cells connected to the unselected word lines. The erase voltage may be used to erase the memory cells included in the selected memory block in the erase operation, and is applied to the source line SL.

[0028] The row decoder 130 may be configured to transmit the operation voltage Vop to the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL connected to the selected memory block according to the row address RADD. For example, the row decoder 130 may be connected to the voltage generator 120 through the global line, and may be connected to the first memory block BLK1 to the i-th memory block BLKi through the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL.

[0029] The page buffer group 140 may include a page buffer (not shown) connected to each of the first to i-th memory blocks BLK1 to BLKi. The page buffer (not shown) may be connected to the first to i-th memory blocks BLK1 to BLKi, respectively, through the bit lines BL. In a read operation, in response to a page buffer control signal PBSIG, the page buffer (not shown) may sense a current or voltage of the bit line BL (which varies according to a threshold voltage of a selected memory cell) and store the sensed data.

[0030] The column decoder 150 may be configured to transmit data between the page buffer group 140 and the input / output circuit 160 in response to the column address CADD. For example, the column decoder 150 may be connected to the page buffer group 140 through the column line CL and transmit an enable signal through the column line. A page buffer (not shown) included in the page buffer group 140 may receive or output data through the data line DL in response to the enable signal.

[0031] The input / output circuit 160 may be configured to receive or output a command CMD, an address ADD, or data through an input / output line I / O. For example, the input / output circuit 160 may transmit a command CMD and an address ADD received from an external controller through the input / output line I / O to the control circuit 180, and transmit data received from the external controller through the input / output line I / O to the page buffer group 140. Alternatively, the input / output circuit 160 may output data transmitted from the page buffer group 140 to the external controller through the input / output line I / O.

[0032] The control circuit 180 may output at least one of an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to a command CMD and an address ADD. For example, when the command CMD input to the control circuit 180 is a command corresponding to a program operation, the control circuit 180 may control the peripheral circuit 170 to perform a program operation of a memory block selected by the address ADD. When the command CMD input to the control circuit 180 is a command corresponding to a read operation, the control circuit 180 may control the peripheral circuit 170 to perform a read operation of the selected memory block and output the read data. When the command CMD input to the control circuit 180 is a command corresponding to an erase operation, the control circuit 180 may control the peripheral circuit 170 to perform an erase operation of the selected memory block.

[0033] Figure 2 is a view schematically illustrating a memory device according to an embodiment of the present disclosure.

[0034] refer to Figure 2 , the memory device 100 may include a peripheral circuit structure PC and memory blocks BLK1 to BLKi disposed on a substrate SUB. The memory blocks BLK1 to BLKi may overlap with the peripheral circuit structure PC.

[0035] The substrate SUB may be a single crystal semiconductor layer. For example, the substrate SUB may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin film formed by a selective epitaxial growth process.

[0036] The peripheral circuit structure PC may include a row decoder ( Figure 1 130 shown in), column decoder ( Figure 1 150 shown in FIG), a page buffer group ( Figure 1 140 shown in), control circuit ( Figure 1 180) etc., which constitute a circuit for controlling the operation of the memory blocks BLK1 to BLKi. For example, the peripheral circuit structure PC may include: NMOS transistors, PMOS transistors, resistors, capacitors, etc. electrically connected to the memory blocks BLK1 to BLKi. The peripheral circuit structure PC may be disposed between the substrate SUB and the memory blocks BLK1 to BLKi.

[0037] Each memory block in the memory blocks BLK1 to BLKi may include: a source structure, a bit line, a cell string electrically connected to the source structure and the bit line, a word line electrically connected to the cell string, and a selection line electrically connected to the cell string. Each cell string in the cell string may include a memory cell and a selection transistor connected in series through a cell plug. Each selection line in the selection line may be used as a gate electrode of a selection transistor corresponding thereto, and each word line in the word line may be used as a gate electrode of a memory cell corresponding thereto.

[0038] In another embodiment, the substrate SUB, the peripheral circuit structure PC, and the memory blocks BLK1 to BLKi may be connected in a manner similar to Figure 2 For example, the peripheral circuit structure PC may be disposed on the memory blocks BLK1 to BLKi.

[0039] In another embodiment, Figure 2 Unlike shown, the peripheral circuit structure PC may be disposed on a partial region of the substrate SUB that does not overlap with the memory blocks BLK1 to BLKi. For example, the peripheral circuit structure PC and the memory blocks BLK1 to BLKi may be disposed on regions of the substrate SUB that do not overlap with each other.

[0040] Figure 3 is a view illustrating a cell region and a contact region of a memory device according to an embodiment of the present disclosure. Figure 3 is a plan view illustrating the layout of the cell region CR and the contact region CTR of the memory device 100 .

[0041] refer to Figure 3 , the memory device may include a cell region CR and a contact region CTR. For example, the contact region CTR may extend from the cell region CR in the X direction. Figure 3Unlike the illustration of FIG. 1 , the contact region CTR may extend from the cell region CR in the Y direction, or extend in the X direction and the Y direction. In addition, the cell region CR and the contact region CTR may be variously arranged.

[0042] The cell plug CPL may be located in the cell region CR. The cell plug CPL may be formed in the cell region CR. The cell plug CPL may be arranged in the cell region CR in the X direction and the Y direction. Each of the cell plugs CPL may extend in the Z direction. Each of the cell plugs CPL may include a barrier layer BX, a charge trapping layer CTL formed along the inner wall of the barrier layer BX, a tunnel insulating layer TX formed along the inner wall of the charge trapping layer CTL, a channel layer CH formed along the inner wall of the tunnel insulating layer TX, or a core column CO inside the channel layer CH, or a combination of at least two thereof. The barrier layer BX and the tunnel insulating layer TX may be formed of an oxide layer. For example, the barrier layer BX and the tunnel insulating layer TX may be formed of a silicon oxide layer or a silicon nitride layer, or a combination thereof. The charge trapping layer CTL may be formed of a nitride layer or a variable resistance material. The channel layer CH may be formed of a conductive layer (e.g., a doped silicon layer). The channel layer CH may be replaced by an electrode structure. The core column CO may be formed of an insulating layer or a conductive layer. Each of the blocking layer BX, the charge trapping layer CTL, the tunnel insulating layer TX, the channel layer CH, and the pillar CO included in the cell plug CPL may extend in the Z direction. In one embodiment, a capping layer for improving electrical characteristics of a selection transistor included in each cell string may be further formed on top of the pillar CO.

[0043] The contact plug CT may be located in the contact region CTR. The contact plug CT may be formed in the contact region CTR. The contact plug CT may be arranged in the contact region CTR along the X direction. Figure 3 In addition to the illustration of FIG. 1 , the contact plugs CT may be arranged in the contact region CTR along the Y direction. Alternatively, some of the contact plugs may be arranged along the X direction, and other of the contact plugs CT may be arranged along the Y direction. Each of the contact plugs CT may extend in the Z direction.

[0044] The number of cell plugs CPL and contact plugs CT is not affected by Figure 3 For example, the number of contact plugs CT may vary according to the number of stacked layers included in the memory device 100. In addition, the positions of the cell plugs CPL and the contact plugs CT are not limited by Figure 3 The illustrated limitations of FIG. 1 and the cell plug CPL and the contact plug CT may be located at various positions as long as the cell plug CPL and the contact plug CT include FIG. 4A to FIG. 4C Features described in .

[0045] The memory device 100 may include a slit S1. The slit S1 may extend in the Z direction and in the X direction. The slit S1 may divide the memory device 100 into a plurality of regions, each of which includes a cell region CR and a contact region CTR. For example, the slit S1 may Figure 2 The first to i-th memory blocks BLK1 to BLKi shown in FIG. 5 are isolated from each other.

[0046] FIG. 4A to FIG. 4C is a view illustrating a structure of a memory device according to an embodiment of the present disclosure. Figure 4A The diagram is along Figure 3 A cross-sectional view of a cross section taken along line AA' is shown. Figure 4B It is a graphic Figure 4A 00 is a perspective view of a portion of a memory device 100 shown in FIG. Figure 4C The diagram is along Figure 4A A cross-sectional view of a cross section taken along line BB' is shown in FIG.

[0047] refer to Figure 4A , the memory device 100 may include a first stacked structure STK1. The first stacked structure STK1 may include conductive layers CD stacked along the Z direction. The interlayer insulating layer IL may be located between the conductive layers CD. The conductive layers CD and the interlayer insulating layers IL may be alternately stacked along the Z direction. The first stacked structure STK1 may extend in the X direction and the Y direction. The conductive layer CD may be formed of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si) or polycrystalline silicon (poly-Si), or a combination of at least two thereof. The interlayer insulating layer IL may be formed of an oxide layer (e.g., a silicon oxide layer).

[0048] Each of the conductive layers CD may include an interposition portion P1 and an end portion P2 extending from the interposition portion P1. The interposition portion P1 of each of the conductive layers CD may be disposed between interlayer insulating layers IL adjacent to each other in the Z direction. The end portion P2 of each of the conductive layers CD may extend from the interposition portion P1 in the X direction. For example, an area of ​​any one conductive layer CDa that overlaps with the interlayer insulating layer IL at its top end may correspond to the interposition portion P1, and other areas of the one conductive layer CDa may correspond to the end portion P2. In another example, an area of ​​any one conductive layer CDb that overlaps with another conductive layer CDa may correspond to the interposition portion P1, and an area of ​​the one conductive layer CDb that does not overlap with the other conductive layer CDa may correspond to the end portion P2. However, for ease of description, the interposition portion P1 and the end portion P2 are described in a manner distinct from each other, and may be physically extended to each other.

[0049] The first stacked structure STK1 may have a step structure defined by the end P2 of the conductive layer CD. For example, the step structure defined by the end P2 of the conductive layer CD may be formed in the contact region CTR of the memory device 100. The end P2 of the conductive layer CD may correspond to a corresponding step of the step structure. The top surface of the end P2 may correspond to the top surface of the step structure of the first stacked structure STK1. Figure 4A and Figure 4B , because the lengths of the conductive layers CD in the X direction are different from each other, a stepped structure may be defined by the end portions P2 of the conductive layers CD.

[0050] The cover pattern CP may be disposed on a portion of the top surface of the first stacked structure STK1. The cover pattern CP may cover the portion of the top surface of the first stacked structure STK1. For example, the cover pattern CP may cover the top surface of the cell region CR of the first stacked structure STK1.

[0051] The connection structure CS may be formed on the top surface of the end portion P2 of the conductive layer CD. The connection structure CS may be in contact with the top surface of the end portion P2 of the conductive layer CD, respectively. The connection structure CS may be electrically connected to the conductive layer CD. For example, referring to Figure 4A and 4B Any one of the connection structures CSa may cover a portion of the top surface of any one of the conductive layers CDa. The connection structure CS may be formed of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si) or polycrystalline silicon (poly-Si), or a combination of at least two thereof.

[0052] The connection structures CS may be formed to be spaced apart from each other. For example, any one connection structure CSa may be spaced apart from another connection structure CSb. The connection structures CS may be formed to not overlap each other. For example, the connection structures CSa and CSb may not overlap each other. The connection structure CS may be formed on a corresponding step in the step structure included in the first stack structure STK1.

[0053] Each of the connection structures CS may include a concave surface CSF recessed from the side surface of the first stack structure STK1. Each of the connection structures CS may include a concave surface CSF such that the concave surface CSF contacts the top surface of each of the steps of the first stack structure STK1 and does not contact the side surface of each of the steps. The concave surface CSF of the connection structure CS may be formed at a side surface located in the opposite direction of the X direction among the side surfaces of the connection structure CS. Through the concave surface CSF, the connection structure CS may prevent or reduce the conductive layers CD from being connected to each other. For example, any one connection structure CSb is connected to any one conductive layer CDb, but may not be connected to another conductive layer CDa. Because the connection structure CSb includes the concave surface CSF, the connection structure CSb may be prevented from or reduced from contacting the side surface of another conductive layer CDa. Figure 4A , it is illustrated that the cross section of the concave surface CSF has an arc shape (or the cross section of the concave portion has a fan shape). However, the present disclosure is not limited thereto. For example, the cross section of the concave surface CFS may have a line shape or a curve shape, and the cross section of the concave portion may have a triangular shape or a quadrilateral shape, as long as the connection structure CS does not contact the side surface of the conductive layer CD. In the present disclosure, the concave portion may mean an area between the concave surface CSF and the side surface of the first stacked structure STK1.

[0054] The memory device 100 may include a second stack structure STK2. The second stack structure STK2 may be disposed on the step structure of the first stack structure STK1. The second stack structure STK2 may overlap at least a portion of the first stack structure STK1. The second stack structure STK2 may cover the step structure of the first stack structure STK1.

[0055] The second stacked structure STK2 may include a dummy layer DL located on the step structure of the first stacked structure STK1. The first spacer SP1 may be located between the dummy layers DL. The dummy layers DL and the first spacers SP1 may be alternately stacked along the Z direction. The second stacked structure STK2 may extend along the X direction and the Y direction. The dummy layer DL may include a conductive material. The dummy layer DL may be formed of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si) or polycrystalline silicon (poly-Si), or a combination of at least two thereof. For example, the dummy layer DL may be formed of the same material as the conductive layer CD. In addition, the first spacer SP1 may be formed of an oxide layer (e.g., a silicon oxide layer).

[0056] The dummy layer DL and the first spacer SP1 may be formed along the step structure of the first stacked structure STK1. For example, the dummy layer DL and the first spacer SP1 may extend along the end portion P2 of the conductive layer CD, respectively. Figure 4A and Figure 4B , at least one dummy layer DL may have a stepped shape corresponding to the stepped structure of the first stacked structure STK1. For example, unlike the stepped structure of the first stacked structure STK1 in which the ends P2 of different conductive layers CD constitute different steps, each of the dummy layer DL and the first spacer SP1 may extend while forming a step in the second stacked structure STK2.

[0057] The first spacer SP1 at the lowermost end among the first spacers SP1 may contact the first stacked structure STK1 and the connection structure CS. The first spacer SP1 may contact the side surface of the cell region CR of the first stacked structure STK1. Moreover, the first spacer SP1 may be formed on the contact region CTR of the first stacked structure STK1. The first spacer SP1 may be formed along the top surface and the side surface of the connection structure CS. The first spacer SP1 may fill the recess included in the connection structure CS. Therefore, the first spacer SP1 may contact the concave surface CSF of the connection structure CS.

[0058] The memory device 100 may include contact plugs CT electrically connected to the conductive layers CD, respectively. Since the contact plugs CT are spaced apart from the conductive layers CD, respectively, but are in contact with the connection structures CS, the contact plugs CT may be electrically connected to the conductive layers CD through the connection structures CS. Figure 4A and 4B , the contact plug CTa contacts the connection structure CSa but may not contact the conductive layer CDa. The contact plug CTa may be connected to the conductive layer CDa through the connection structure CSa. The contact plug CT may be formed integrally with the connection structure CS. Figure 4A and Figure 4B , for convenience of description, the contact plug CT and the connection structure CS are illustrated as if they are isolated from each other. However, the contact plug CT and the connection structure CS may be formed to extend to each other.

[0059] The contact plug CT may extend in the Z direction. For example, the contact plug CT may extend from the connection structure CS in the Z direction. Also, the contact plug CT may extend from the connection structure CS to the inside of the first stack structure STK1 .

[0060] The contact plug CT may be formed of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), or polysilicon (poly-Si), or a combination of at least two thereof.

[0061] The contact plug CT may be located in the first stack structure STK1. The contact plug CT may penetrate the contact region CTR of the first stack structure STK1. The contact plug CT extends to the inside of the first stack structure STK1, but may be spaced apart from the conductive layer CD by the second spacer SP2.

[0062] The second spacer SP2 may be disposed between the contact plug CT and the conductive layer CD. FIG. 4A to FIG. 4C , the second spacer SP2 may surround the side surface of the contact plug CT. Moreover, the second spacer SP2 may be formed on the inner wall of the conductive layer CD. For example, the second spacer SP2 may have a columnar shape surrounding the contact plug CT. Alternatively, the second spacer SP2 may have a columnar shape with a portion removed therefrom, the columnar shape having a side surface extending from the side surface of the end portion P2 of the conductive layer CD.

[0063] Furthermore, the second spacer SP2 surrounding any one of the contact plugs CTa may be formed in the conductive layer CDb which is not electrically connected to the contact plug CTa, and further, the second spacer SP2 surrounding the contact plug CTa may even be formed in the conductive layer CDa which is electrically connected to the contact plug CTa. Therefore, the contact plug CTa may be connected to the conductive layer CDa through the connection structure CSa without being in direct contact with the conductive layer CDa.

[0064] The second spacer SP2 may insulate the contact plug CT and the conductive layer CD from each other. For example, the second spacer SP2 may be formed of an oxide layer (e.g., a silicon oxide layer). Therefore, through the second spacer SP2, it is possible to prevent or mitigate the two or more conductive layers CD included in the first stacked structure STK1 from being electrically connected to any one of the contact plugs CT.

[0065] The contact plug CT may be located in the second stacked structure STK2. The contact plug CT may penetrate the second stacked structure STK2. The contact plug CT extends to the inside of the second stacked structure STK2, but may be spaced apart from the dummy layer DL by the third spacer SP3. The dummy layer DL may float between the contact plugs CT by the third spacer SP3. For example, each of the dummy layers DL located between the contact plugs CT does not contact any conductive layer.

[0066] The third spacer SP3 may be disposed between the contact plug CT and the dummy layer DL. Figure 4A and Figure 4B , the third spacer SP3 may surround the side surface of the contact plug CT. Also, the third spacer SP3 may be formed on the inner wall of the dummy layer DL. For example, the third spacer SP3 may have a columnar shape surrounding the contact plug CT.

[0067] The third spacer SP3 can insulate the contact plug CT and the dummy layer DL from each other. For example, the third spacer SP3 can be formed of an oxide layer (e.g., a silicon oxide layer). Therefore, by the third spacer SP3, the dummy layer DL included in the second stacked structure STK2 can be prevented or alleviated from being electrically connected to the contact plug CT.

[0068] Because the memory device 100 includes the dummy layer DL floating between the contact plugs CT, the shape distortion of the contact plug CT can be prevented or mitigated. For example, when the volume of the insulating layer (e.g., the first spacer SP1) is reduced by forming the dummy layer DL on the contact region CTR of the first stacked structure STK1, the shape of the contact plug CT is not distorted, or the degree of shape distortion of the contact plug CT can be reduced, compared with the case where only a bulk-shaped upper insulating layer is formed without any dummy layer DL.

[0069] FIG. 5A to FIG. 5M is a view illustrating a method of manufacturing a memory device according to an embodiment of the present disclosure. FIG. 5A to FIG. 5M Each figure in the figure shows the Figure 3 The cross section taken along the line AA' is shown in FIG.

[0070] refer to Figure 5A , the first material layer IL and the second material layer SF may be alternately stacked. The first material layer IL may be formed of an insulating material. For example, the first material layer IL may be formed of an oxide layer (e.g., a silicon oxide layer). The second material layer SF may be formed of a material having an etching selectivity different from that of the first material layer IL. For example, the second material layer SF may be formed of a nitride layer.

[0071] Portions of the alternately stacked first material layers IL and second material layers SF may be etched to form a first preliminary stacked structure pSTK1 having a step structure. For example, portions of the first material layers IL and second material layers SF may be defined as a cell region CR, and other portions of the first material layers IL and second material layers SF may be defined as a contact region CTR. The step structure may be formed in the contact region CTR. Some of the first material layers IL in the first material layer IL and some of the second material layers SF in the second material layer SF may be cut in the Z direction at the boundary between the cell region CR and the contact region CTR.

[0072] The first preliminary stacked structure pSTK1 may have a step structure including a first material layer IL and a second material layer SF, each of the first material layer IL and the second material layer SF forming a pair. The step structure may be defined by the end of the second material layer SF. For example, the second material layer SF may be exposed through the steps of the step structure, respectively. For example, the step structure may be included in the example Figure 5A In the contact area CTR shown.

[0073] refer to Figure 5B , a cover layer CVL may be formed on the first preliminary stacked structure pSTK1. The cover layer CVL may be formed on the top surface and the side surface of the first preliminary stacked structure pSTK1. The cover layer CVL may be formed along the top surface and the side surface of the first preliminary stacked structure pSTK1. The cover layer CVL may have a thickness that varies depending on its position. For example, the thickness of the cover layer CVL formed on the top surface of the first preliminary stacked structure pSTK1 may be thicker than the thickness of the cover layer CVL formed on the side surface of the first preliminary stacked structure pSTK1. The cover layer CVL may be formed of a nitride layer.

[0074] refer to Figure 5C , part of the covering layer CVL may be etched to form a covering pattern CP. The covering layer CVL on the side surface of the first preliminary stacked structure pSTK1 may be removed from the entire covering layer CVL. For example, the covering layer CVL formed on the side surface of the first preliminary stacked structure pSTK1 may be etched from the entire covering layer CVL to form a covering pattern CP. At the same time, the covering layer CVL formed on the top surface of the first preliminary stacked structure pSTK1 may also be etched to a certain thickness. Therefore, the thickness of the covering pattern CP may be thinner than the thickness of the covering layer CVL formed on the top surface of the first preliminary stacked structure pSTK1.

[0075] The cover pattern CP may be disposed on the top surface of the first preliminary stacked structure pSTK1. The cover pattern CP may be formed on the top surface of the end of the second material layer SF. For example, the cover pattern CP may be disposed along the top surface of each of the steps included in the first preliminary stacked structure pSTK1. In addition, the cover pattern CP may be disposed on a region of the first preliminary stacked structure pSTK1 corresponding to the cell region CR.

[0076] Each of the covering patterns CP may include a concave surface CSF recessed from the side surface of the first preliminary stacked structure pSTK1. Each of the covering patterns CP may include the concave surface CSF such that the concave surface CSF contacts the top surface of the first preliminary stacked structure pSTK1 and does not contact the side surface of the first preliminary stacked structure pSTK1. The concave surface CSF of each of the covering patterns CP may be formed on a side surface located in the opposite direction of the X direction among the side surfaces of the covering pattern CP. While removing the covering layer CVL formed on the side surface of the first preliminary stacked structure pSTK1 in the entire covering layer CVL, a portion of the covering layer CVL formed on the top surface of the first preliminary stacked structure pSTK1 in the entire covering layer CVL may be removed together, so that each of the covering patterns CP includes a recess. Figure 5C , it is illustrated that the cross section of the concave surface CSF has an arc shape (or the cross section of the concave portion has a fan shape). However, the present disclosure is not limited thereto. For example, the cross section of the concave surface CFS may have a line shape or a curve shape, and the cross section of the concave portion may have a triangular shape or a quadrilateral shape, as long as the cover pattern CP does not contact the side surface of the second material layer SF.

[0077] refer to Figure 5D , a first dummy material layer DM1 may be formed, which covers the first preliminary stacked structure pSTK1 and the cover pattern CP. The first dummy material layer DM1 may cover the step structure of the first preliminary stacked structure pSTK1. The first dummy material layer DM1 may extend on the step structure of the first preliminary stacked structure pSTK1 along the end of the second material layer SF. Moreover, the first dummy material layer DM1 may cover the cover pattern CP. The first dummy material layer DM1 may fill the recessed portion of the cover pattern CP. The first dummy material layer DM1 may be formed of an insulating material. For example, the first dummy material layer DM1 may be formed of an oxide layer (e.g., a silicon oxide layer).

[0078] refer to Figure 5E The second dummy material layer DM2 and the first dummy material layer DM1 may be alternately stacked on Figure 5D For example, in forming the first dummy material layer DM1 Figure 5DAfter forming the first dummy material layer DM1 in the process, a second dummy material layer DM2 covering the first dummy material layer DM1 may be formed. The second dummy material layer DM2 may be conformally formed on the first dummy material layer DM1. Subsequently, the first dummy material layer DM1 and the second dummy material layer DM2 may be alternately deposited. The second dummy material layer DM2 may be formed of a material that may be selectively removed in a subsequent process. The second dummy material layer DM2 may be formed of a material having an etching selectivity different from that of the first dummy material layer DM1. For example, the second dummy material layer DM2 may be formed of a nitride layer.

[0079] Each of the first and second dummy material layers DM1 and DM2 may extend on the stepped structure of the first preliminary stacked structure pSTK1 along an end of the second material layer SF. For example, each of the first and second dummy material layers DM1 and DM2 may have a stepped shape corresponding to the stepped structure of the first preliminary stacked structure pSTK1.

[0080] refer to Fig. 5F , portions of the first dummy material layer DM1 and the second dummy material layer DM2 formed on the first preliminary stack structure pSTK1 may be removed, thereby forming a second preliminary stack structure pSTK2. Figure 5E In the first dummy material layer DM1 and the second dummy material layer DM2 formed in the embodiment, a region formed at a level higher than a specific level is formed. Figure 5E After the deposition process performed in , a chemical mechanical polishing (CMP) process may be performed until the capping pattern CP (eg, the capping pattern CP on the top of the first material layer IL) is exposed.

[0081] refer to Figure 5G , the first opening OP1 may be formed in the entire structure including the first preliminary stacked structure pSTK1 and the second preliminary stacked structure pSTK2. For example, the first opening OP1 penetrating the first preliminary stacked structure pSTK1 and the second preliminary stacked structure pSTK2 may be formed. The first opening OP1 may penetrate the first preliminary stacked structure pSTK1 and the second preliminary stacked structure pSTK2 and the covering pattern CP. For example, the first opening OP1 may penetrate the covering pattern CP on the step structure, respectively. The inner wall of the first preliminary stacked structure pSTK1 and the inner wall of the second preliminary stacked structure pSTK2 and the inner wall of the covering pattern CP may be exposed through the first opening OP1. That is, the first material layer IL and the second material layer SF and the first dummy material layer DM1 and the second dummy material layer DM2 may be exposed through the first opening OP1. The first opening OP1 may have substantially the same depth. An anisotropic dry etching process may be performed to form the first opening OP1 at a designated position.

[0082] refer to Figure 5H , portions of the second material layer SF and the second dummy material layer DM2 exposed through the first opening OP1 may be removed. Among the first material layer IL and the second material layer SL, the first dummy material layer DM1 and the second dummy material layer DM2 exposed through the first opening OP1, and the cover pattern CP, the second material layer SF and the second dummy material layer DM2 may be selectively etched. For example, a portion of each of the second material layers SF exposed through the first opening OP1 may be removed to form a first recess RC1. In addition, a portion of each of the second dummy material layers DM2 exposed through the first opening OP1 may be removed to form a second recess RC2.

[0083] refer to Fig.5I , a spacer layer SPL may be formed in the first opening OP1 and the recesses RC1 and RC2. A spacer layer SPL filling the first opening OP1, the first recess RC1, and the second recess RC2 may be formed. The spacer layer SPL may be formed of an insulating material. For example, the spacer layer SPL may be formed of an oxide layer (eg, a silicon oxide layer).

[0084] refer to Figure 5J , the second material layer SF of the first preliminary stacked structure pSTK1 may be replaced with the third material layer CD, and the second dummy material layer DM2 of the second preliminary stacked structure pSTK2 may be replaced with the third dummy material layer DL. In a state where the spacer layer SPL is filled in the first opening OP1, the first recess RC1, and the second recess RC2, some of the material layers of the first preliminary stacked structure pSTK1 and the second preliminary stacked structure pSTK2 may be replaced. For example, Figure 3 The slit S1 shown in FIG. 1 removes the second material layer SF and the second dummy material layer DM2, and can be removed by Figure 3 The slit S1 shown in FIG. 1 forms a third material layer CD and a third dummy material layer DL. The third material layer CD and the third dummy material layer DL may be formed of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), or polycrystalline silicon (poly-Si), or a combination of at least two thereof.

[0085] Since the second material layer SF is replaced by the third material layer CD, a first stacked structure STK1 can be formed in which the first material layer IL and the third material layer CD are alternately stacked. The first material layer IL may correspond to Figure 4A The interlayer insulating layer IL shown in FIG. 1 and the third material layer CD may correspond to FIG. 4A to FIG. 4C The conductive layer CD is shown in FIG.

[0086] Since the second dummy material layer DM2 is replaced by the third dummy material layer DL, a second stack structure STK2 can be formed in which the first dummy material layer DM1 and the third dummy material layer DL are alternately stacked. The first dummy material layer DM1 may correspond to Figure 4A The first spacer SP1 shown in FIG. 1 and the third dummy material layer DL may correspond to Figure 4A and Figure 4B A dummy layer DL is shown in FIG.

[0087] refer to Figure 5K , a second opening OP2 penetrating the spacer layer SPL may be formed. The second opening OP2 may penetrate the first stack structure STK1 and the second stack structure STK2. Figure 5J Among the spacer layers SPL formed in the second embodiment, the spacer layers SPL remaining after forming the second opening OP2 may become the second spacer SP2 or the third spacer SP3. The third material layer CD may be spaced apart from the second opening OP2 by the second spacer SP2. In addition, the third dummy material layer DL may be spaced apart from the second opening OP2 by the third spacer SP3. Therefore, the third material layer CD and the third dummy material layer DL may not be exposed through the second opening OP2.

[0088] The cover pattern CP may be exposed through the second opening OP2. For example, the inner wall of the cover pattern CP may be exposed through the second opening OP2. The width of the second opening OP2 may be greater than or equal to the width of the first opening OP1. For example, the width of the second opening OP2 penetrating the cover pattern CP may be greater than or equal to the width of the first opening OP1 penetrating the cover pattern CP.

[0089] By the third dummy material layer DL floating between the second openings OP2, the shape of the second openings OP2 may be formed relatively constant. For example, when the third dummy material layer DL exists, the cross-sectional shape of the second openings OP2 may not change at a certain level or more according to the height, or the cross-sectional size of the second openings OP2 may not change at a certain level or more according to the height, compared to when the third dummy material layer DL does not exist.

[0090] refer to Figure 5L , the covering pattern CP exposed through the second opening OP2 may be removed. The covering pattern CP contacting the top surface of the third material layer CD among the covering patterns CP on the first stacked structure STK1 may be removed. Among the first material layer IL, the first dummy material layer DM1, the second spacer SP2, the third spacer SP3, and the covering pattern CP exposed through the second opening OP2, only the covering pattern CP may be selectively etched. An isotropic wet etching process may be performed to etch the covering pattern CP.

[0091] Since the cover pattern CP is removed, a third opening OP3 may be formed. The third opening OP3 may extend from the second opening OP2. The third opening OP3 may extend from the second opening OP2 in a horizontal direction. A portion of the top surface of the third material layer CD may be exposed through the third opening OP3. For example, the top surface of the step structure of the first stacked structure STK1 may be exposed through the third opening OP3.

[0092] refer to Figure 5M , a conductive material ML may be formed in the second opening OP2 and the third opening OP3. The conductive material ML may fill the second opening OP2 and the third opening OP3. The conductive material ML may contact the top surface of the third material layer CD. Moreover, the conductive material ML may be spaced apart from the third dummy material layer DL. The third dummy material layer DL may float between the conductive materials ML. In one embodiment, the third dummy material layer DL may float between the conductive materials ML, such as Figure 5M In one embodiment, the third dummy material layer DL may be located between the conductive materials ML. In one embodiment, the third dummy material layer DL may be located between the conductive materials ML and spaced apart from the conductive materials ML. In one embodiment, the third dummy material layer DL may be located between the conductive materials ML and not in direct contact with the conductive materials ML, as shown in FIG. Figure 5M In one embodiment, the third dummy material layer DL may be located between the conductive materials ML, not in direct contact with the conductive material ML, and directly on the first dummy material layer DM1. In one embodiment, the third dummy material layer DL may be located between the conductive materials ML, not in direct contact with the conductive material ML, and directly on the first dummy material layer DM1, so as to appear to float between the conductive materials ML, as shown in FIG. Figure 5M The conductive material ML may be formed of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si) or polysilicon (poly-Si), or a combination of at least two thereof. Figure 4A and Figure 5M As shown, at least one of the third dummy material layers DL has a step shape corresponding to the step structure of the first stacked structure STK1 (ie, the dummy layer DL is located above the connection structure CSa or the connection structure CSb in the Z direction). For example, in one embodiment, Figure 4A The 'Z'-shaped dummy layer DL directly above the connection structure CSa or the connection structure CSb in FIG. 1 may be identified as one third dummy material layer DL having a stepped shape corresponding to the stepped structure of the first stacked structure STK1 among the third dummy material layers DL.

[0093] The portion of the conductive material ML filled in the second opening OP2 may be designated as FIG. 4A to FIG. 4C In addition, the portion of the conductive material ML filled in the third opening OP3 may be designated as Figure 4A and Figure 4B In one embodiment, the contact plug CT is electrically isolated from the third dummy material layer DL or the dummy layer DL.

[0094] Figure 6 is a diagram illustrating a memory card system to which the memory device of the present disclosure is applied.

[0095] refer to Figure 6 , the memory card system 3000 may include a controller 3100 , a memory device 3200 , and a connector 3300 .

[0096] The controller 3100 may be connected to the memory device 3200. The controller 3100 may access the memory device 3200. For example, the controller 3100 may control programming, reading, or erasing operations, or control background operations of the memory device 3200. The controller 3100 may provide an interface between the memory device 3200 and a host. The controller 3100 may drive firmware for controlling the memory device 3200. For example, the controller 3100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error corrector.

[0097] The controller 3100 can communicate with an external device through the connector 3300. The controller 3100 can communicate with an external device (e.g., a host) according to a specific communication protocol. For example, the controller 3100 can communicate with an external device through at least one communication protocol in various communication protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Minidisk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector 3300 can be defined by at least one communication protocol in the various communication protocols.

[0098] The memory device 3200 may include a memory unit and Figure 1 The memory devices 100 shown in FIG. 1 are configured identically.

[0099] The controller 3100 and the memory device 3200 may be integrated into a single semiconductor device to constitute a memory card. For example, the controller 3100 and the memory device 3200 may constitute a memory card such as a personal computer (PC) card (Personal Computer Memory Card International Association (PCMCIA)), a compact flash (CF) card, a smart media card (SM and SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro, and eMMC), an SD card (SD, mini SD, micro SD, and SDHC), and a universal flash storage (UFS).

[0100] Figure 7 is a diagram illustrating a solid-state drive (SSD) system to which the memory device of the present disclosure is applied.

[0101] refer to Figure 7 , the SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 may exchange signals with the host 4100 through a signal connector 4001, and receive power through a power connector 4002. The SSD 4200 may include a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0102] The controller 4210 may control the plurality of memory devices 4221 to 422n in response to a signal received from the host 4100. Exemplarily, the signal may be a signal based on an interface between the host 4100 and the SSD 4200. For example, the signal may be a signal defined by at least one of interfaces such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI Express (PCIe), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced minidisk interface (ESDI), an integrated drive electronics (IDE), a firewire, a universal flash storage (UFS), WI-FI, Bluetooth, and NVMe.

[0103] The plurality of memory devices 4221 to 422n may include a plurality of memory cells configured to store data. Each of the plurality of memory devices 4221 to 422n may be connected to Figure 1 The plurality of memory devices 4221 to 422n may communicate with the controller 4210 through channels CH1 to CHn.

[0104] The auxiliary power supply 4230 may be connected to the host 4100 through the power connector 4002. The auxiliary power supply 4230 may receive power input from the host 4100 and be charged with the power. When the supply of power from the host 4100 is not stable, the auxiliary power supply 4230 may provide power to the SSD 4200. For example, the auxiliary power supply 4230 may be located in the SSD 4200, or located outside the SSD 4200. For example, the auxiliary power supply 4230 may be located on the mainboard and provide auxiliary power to the SSD 4200.

[0105] The buffer memory 4240 may operate as a buffer memory of the SSD 4200. For example, the buffer memory 4240 may store data received from the host 4100 or data received from the plurality of memory devices 4221 to 422n, or store metadata (e.g., a mapping table) of the memory devices 4221 to 422n. The buffer memory 4240 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0106] According to an embodiment of the present disclosure, a dummy layer is formed inside an upper insulating layer formed in a contact region of a memory device, so that distortion of a shape of a contact plug can be prevented or mitigated.

[0107] Although the present disclosure has been shown and described with reference to certain examples of the embodiments of the present disclosure, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-mentioned embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0108] In the above-described embodiments, all steps may be selectively performed, or some steps in the steps may be omitted. In each embodiment, the steps are not necessarily performed in the order described, and may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are merely examples for the purpose of understanding the present disclosure, and the present disclosure is not limited thereto. That is, it should be apparent to those skilled in the art that various modifications may be made based on the technical scope of the present disclosure.

[0109] Meanwhile, embodiments of the present disclosure have been described in the accompanying drawings and the specification. Although specific terms are used herein, those specific terms are only used to explain embodiments of the present disclosure. Therefore, the present disclosure is not restricted to the above-described embodiments, and within the spirit and scope of the present disclosure, many variations are possible. It should be apparent to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications may be made based on the technical scope of the present disclosure.

Claims

1. A memory device, comprising: A first stacking structure comprising conductive layers stacked along a first direction, the first stacking structure having a step structure defined by ends of the conductive layers; contact plugs respectively connected to the conductive layers, the contact plugs extending along the first direction, and the contact plugs extending into the first stacked structure; as well as A dummy layer is located between the contact plugs. 2 . The memory device of claim 1 , wherein the dummy layer is located on the stepped structure of the first stacked structure. 3 . The memory device of claim 1 , further comprising first spacers alternately stacked with the dummy layers. 4 . The memory device of claim 3 , wherein the dummy layer and the first spacer extend along the end portions of the conductive layer, respectively. 5 . The memory device of claim 3 , wherein the dummy layer and the first spacer constitute a second stack structure, the second stack structure overlapping the stepped structure of the first stack structure. 6 . The memory device of claim 1 , wherein at least one dummy layer among the dummy layers has a stepped shape corresponding to the stepped structure. 7 . The memory device of claim 1 , wherein the first stack structure further comprises an interlayer insulating layer stacked between the conductive layers. 8 . The memory device of claim 1 , wherein the contact plugs are spaced apart from the conductive layers, respectively. 9 . The memory device of claim 1 , further comprising a second spacer between the contact plug and the conductive layer.

10. The memory device according to claim 1, further comprising connection structures respectively contacting top surfaces of the end portions of the conductive layer, The contact plugs are in contact with the connection structures respectively. 11 . The memory device of claim 10 , wherein the contact plug is connected to the conductive layer through the connection structure. 12 . The memory device of claim 10 , wherein each of the connection structures comprises a concave surface recessed from a side surface of the first stack structure.

13. The memory device of claim 1, wherein the dummy layer comprises a conductive material. 14 . The memory device of claim 1 , further comprising a third spacer between the contact plug and the dummy layer.

15. The memory device of claim 1, wherein the contact plug and the dummy layer are electrically isolated from each other.

16. A method of manufacturing a memory device, the method comprising: forming a first preliminary stacking structure, the first preliminary stacking structure comprising first material layers and second material layers stacked alternately, the first preliminary stacking structure having a step structure defined by ends of the second material layers; forming a covering pattern on a top surface of the end portion of the second material layer; forming a second preliminary stacking structure by alternately stacking a first dummy material layer and a second dummy material layer, wherein the first dummy material layer and the second dummy material layer extend along the end portion on the step structure respectively; forming a first opening, the first opening penetrating the first preliminary stacked structure and the second preliminary stacked structure; forming a recess by removing a portion of each of the second material layer and the second dummy material layer exposed through the first opening; forming a spacer layer in the first opening and the recess; forming a second opening penetrating the spacer layer; forming a third opening by removing the cover pattern through the second opening; as well as Contact plugs are formed by filling the second opening and the third opening with a conductive material.

17. The method according to claim 16, wherein forming the covering pattern comprises: forming a cover layer on a top surface and side surfaces of the first preliminary stacked structure; as well as The covering pattern is formed by removing the covering layer on the side surface of the first preliminary stacked structure among the entire covering layer.

18. The method according to claim 16, wherein forming the second preliminary stack structure comprises: forming a first dummy material layer covering the first preliminary stacked structure and the covering pattern; as well as A second dummy material layer is formed on the first dummy material layer.

19. The method according to claim 16, further comprising: After forming the spacer layer, replacing the second material layer with a third material layer; as well as The second dummy material layer is replaced with a third dummy material layer.

20. The method of claim 16, wherein the first opening penetrates the covering pattern. The method according to claim 16 , wherein the second opening exposes the capping pattern.

22. The method of claim 16, wherein a width of the second opening is greater than or equal to a width of the first opening.

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