Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate; forming a trench and a linear oxide layer located on the sidewalls and bottom surface of the trench within the substrate; modifying the linear oxide layer by incorporating modified ions into the linear oxide layer; after the modification treatment, forming an isolation structure within the trench; and after forming the isolation structure, implanting dopant ions onto the surface of the substrate to form a voltage regulation region, thereby suppressing dopant ions in the voltage regulation region from entering the isolation structure through the linear oxide layer, which facilitates precise control of the threshold voltage of the formed device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Threshold voltage is a crucial performance parameter of a metal-oxide-semiconductor field-effect transistor (MOSFET). With advancements in semiconductor manufacturing technology, the stability requirements for threshold voltage values ​​are becoming increasingly stringent.

[0003] In the prior art, the threshold voltage of NMOS devices is adjusted by ion implantation at the substrate position below the gate to adjust the threshold voltage turn-on value and meet the threshold voltage requirements of different customers.

[0004] However, existing threshold voltage adjustment methods cannot meet current technical requirements because boron atoms can easily diffuse laterally into the shallow trench isolation region, causing fluctuations in the threshold voltage value. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising: a substrate; a groove located within the substrate, wherein the sidewalls and bottom surface of the groove have a linear oxide layer, and the linear oxide layer contains modified ions; an isolation structure located within the groove and on the surface of the linear oxide layer; and a voltage adjustment region located on the surface of the substrate, wherein the voltage adjustment region contains doped ions.

[0007] Optionally, it further includes: a gate located on a portion of the voltage regulation region; source / drain regions located in the substrate on both sides of the gate; a well region located in the substrate, the well region having a P-type conductivity; and the voltage regulation region located on the well region.

[0008] Optionally, a source-drain anti-penetration region is located between the well region and the voltage regulation region, and the conductivity type of the source-drain anti-penetration region is P-type.

[0009] Optionally, the doping ion includes boron ions; the modified ion includes nitrogen ions.

[0010] Optionally, the depth of the voltage adjustment region ranges from 10 nm to 30 nm; the doping ion concentration within the voltage adjustment region ranges from 1 x 10⁻⁶. 13 atom / cm 3 Up to 6x10 13 atom / cm3 .

[0011] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a groove and a linear oxide layer located on the sidewalls and bottom surface of the groove in the substrate; modifying the linear oxide layer by incorporating modified ions into the linear oxide layer; forming an isolation structure in the groove after the modification treatment; and implanting doped ions on the surface of the substrate after forming the isolation structure to form a voltage regulation region.

[0012] Optionally, the doping ion includes boron ions; the modified ion includes nitrogen ions.

[0013] Optionally, the modification process includes ion implantation or nitriding.

[0014] Optionally, the ion implantation process includes a decoupled plasma nitriding process.

[0015] Optionally, the process parameters of the decoupled plasma nitriding process include: the reaction gas includes nitrogen, the gas flow rate ranges from 350 sccm to 500 sccm, the power ranges from 1800 W to 1950 W, the gas pressure ranges from 10 mtor to 20 mtor, and the process time ranges from 90 s to 120 s.

[0016] Optionally, the nitriding process includes: placing the linear oxide layer in a nitrogen-containing gas atmosphere and performing thermal annealing on the linear oxide layer.

[0017] Optionally, the process parameters of the nitriding process include: the nitrogen-containing gas includes one or more of NO, NO2, and N2O; the temperature range is 950℃ to 1000℃; and the process time range is 100s to 150s.

[0018] Optionally, the formation process of the voltage regulation region includes an ion implantation process.

[0019] Optionally, the substrate has a well region, and the conductivity type of the well region is P-type; the voltage regulation region is located on the well region.

[0020] Optionally, a source-drain anti-penetration region is located between the well region and the voltage regulation region, and the conductivity type of the source-drain anti-penetration region is P-type.

[0021] Optionally, the material of the linear oxide layer includes silicon oxide; the formation process of the linear oxide layer includes an in-situ water vapor growth process.

[0022] Optionally, after forming the voltage regulation region, the method further includes: forming a gate on a portion of the voltage regulation region; and forming source / drain regions in the substrate on both sides of the gate.

[0023] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0024] In the semiconductor structure formation method provided by the present invention, the linear oxide layer is modified by incorporating modified ions into the linear oxide layer. This allows the linear oxide layer to suppress dopant ions in the voltage regulation region from entering the isolation structure through the linear oxide layer, thereby improving the stability of the dopant ion concentration in the device channel. This facilitates precise control of the threshold voltage of the formed device and improves the stability of device performance.

[0025] Furthermore, the doping ions include boron ions; the modified ions include nitrogen ions. Incorporating nitrogen ions into the linear oxide layer can increase the diffusion barrier height of boron within the linear oxide layer, which helps to suppress the lateral diffusion of boron ions into the isolation structure, thereby improving the stability of the doping ion concentration in the device channel, facilitating precise control of the threshold voltage of the formed device, and improving the stability of device performance.

[0026] In the semiconductor structure provided by the present invention, the sidewalls and bottom surface of the groove have a linear oxide layer, and the linear oxide layer contains modified ions. The linear oxide layer helps to suppress doped ions in the voltage regulation region from entering the isolation structure through the linear oxide layer, thereby improving the stability of the doped ion concentration in the device channel, facilitating precise control of the threshold voltage of the formed device, and improving the stability of device performance.

[0027] Furthermore, the doping ions include boron ions; the modified ions include nitrogen ions. The nitrogen ions in the linear oxide layer give the linear oxide layer a higher boron diffusion barrier height, which helps to suppress the lateral diffusion of boron ions into the isolation structure, thereby improving the stability of the doping ion concentration in the device channel, facilitating precise control of the threshold voltage of the formed device, and improving the stability of device performance. Attached Figure Description

[0028] Figures 1 to 3 This is a schematic diagram of the steps involved in forming a semiconductor structure.

[0029] Figures 4 to 8 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0030] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0031] As described in the background section, existing threshold voltage adjustment methods are prone to fluctuations in the threshold voltage value, failing to meet current technical requirements. A method for forming a semiconductor structure will now be explained and analyzed.

[0032] Figures 1 to 3 This is a schematic diagram of the steps involved in forming a semiconductor structure.

[0033] Please refer to Figure 1 A substrate 100 is provided, wherein a P-type well region 101 is provided therein; a first mask layer is formed on the surface of the substrate 100, the first mask layer comprising a silicon oxide material layer 101 and a silicon nitride material layer 102 located on the silicon oxide material layer 101; using the first mask layer as a mask, a groove 104 is formed in the substrate 100 by etching; the sidewalls and bottom surface of the groove 104 are oxidized to form an oxide layer 105.

[0034] Please refer to Figure 2 Remove the first mask layer; form a second mask layer 106 on the surface of the substrate 100, the second mask layer 106 exposing a portion of the substrate 100; using the second mask layer 106 as a mask, implant boron ions 107 on the surface of the substrate 100 to form a threshold adjustment region 108 located on the P-type well region 101.

[0035] Please refer to Figure 3 Remove the second mask layer 106; form an isolation structure 109 in the groove 104; and form a gate 110 on the surface of a portion of the threshold adjustment region 108.

[0036] The above method is used to form an NMOS device. The boron ions 107 are used to adjust the threshold voltage of the NMOS device, and the oxide layer 105 is used to repair the etching damage generated during the formation of the groove 104. The oxide layer 105 is formed using an in-situ steam generation (ISSG) process. However, the oxide layer 105 formed by in-situ steam generation contains a large number of OH bonds. Since the OH bonds promote the lateral diffusion of boron ions 107 into the isolation structure 109, the stability of the dopant ion concentration in the formed device channel is poor, which in turn affects the threshold voltage of the device.

[0037] To address the aforementioned issues, the present invention provides a semiconductor structure and method in which the linear oxide layer is modified by incorporating modified ions into it. This allows the linear oxide layer to suppress dopant ions in the voltage regulation region from entering the isolation structure through the linear oxide layer, thereby improving the stability of the dopant ion concentration in the device channel. This facilitates precise control of the threshold voltage of the formed device and enhances the stability of device performance.

[0038] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0039] Figures 4 to 8 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0040] Please refer to Figure 4 Substrate 200 is provided.

[0041] In this embodiment, the substrate 200 has a well region 201, and the conductivity type of the well region 201 is P-type.

[0042] In this embodiment, the substrate 200 includes a first region I and a second region II. The first region I is used to form a PMOS device. Specifically, the well region 201 is located within the first region I, and the well region 201 is used to form the well region of the PMOS device.

[0043] In this embodiment, the substrate 200 further includes a source / drain punch-through region 202 located on the well region 201, and the conductivity type of the source / drain punch-through region 202 is P-type. Subsequently, a voltage adjustment region is formed on the surface of the substrate 200, which is used to adjust the threshold voltage of the device, and the conductivity type of the voltage adjustment region is P-type.

[0044] In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0045] Please refer to Figure 5 A groove 203 and a linear oxide layer 204 are formed in the substrate 200.

[0046] The formation process of the groove 203 includes a dry etching process. In this embodiment, the formation process of the groove 203 is a dry etching process.

[0047] The method for forming the groove 203 includes: forming a first mask layer on a portion of the surface of the substrate 200; using the first mask layer as a mask, etching the substrate 200 to form the groove 203 within the substrate 200.

[0048] In this embodiment, the first mask layer includes a first mask material layer 205 and a second mask material layer 206 located on the first mask material layer 205; the material of the first mask material layer 205 is silicon oxide, and the material of the second mask material layer 206 is silicon nitride.

[0049] The linear oxide layer 204 is made of silicon oxide. In this embodiment, the linear oxide layer 204 is made of silicon oxide.

[0050] In this embodiment, the linear oxide layer 204 is formed using an in-situ water vapor growth process. The linear oxide layer 204 is used to repair etching damage caused by the etching process that forms the sidewalls and bottom surface of the groove 203.

[0051] The groove 203 is used to form an isolation structure, which is used to form electrical insulation between different devices. Specifically, the groove 203 is located between the first region I and the second region II.

[0052] Please refer to Figure 6 The linear oxide layer 204 is modified by incorporating modified ions 207 into it.

[0053] Incorporating modified ions 207 into the linear oxide layer 204 helps to suppress doped ions in the voltage regulation region from entering the isolation structure through the linear oxide layer 204, thereby improving the stability of the doped ion concentration in the device channel, facilitating precise control of the threshold voltage of the formed device, and improving the stability of device performance.

[0054] In this embodiment, the modified ion 207 includes nitrogen ions.

[0055] Incorporating nitrogen ions into the linear oxide layer 204 can increase the diffusion barrier height of boron within the linear oxide layer 204, which helps to suppress the lateral diffusion of boron ions into the isolation structure. This improves the stability of the dopant ion concentration in the device channel, facilitates precise control of the threshold voltage of the formed device, and enhances the stability of device performance.

[0056] The modification process includes ion implantation or nitriding. During nitrogen ion incorporation, the linear oxide layer 204 is located on the sidewalls and bottom surface of the groove 203, which can reduce the impact of nitrogen ion incorporation on the sidewalls and bottom surface of the groove 203, and reduce the probability of interface defects between the subsequently formed isolation structure and the substrate 200.

[0057] In this embodiment, the ion implantation process includes a decoupled plasma nitriding process.

[0058] In this embodiment, the process parameters of the decoupled plasma nitriding process include: the reaction gas includes nitrogen, the gas flow rate ranges from 350 sccm to 500 sccm, the power ranges from 1800 W to 1950 W, the gas pressure ranges from 10 mtor to 20 mtor, and the process time ranges from 90 s to 120 s.

[0059] In another embodiment, the modification process is a nitriding process; the nitriding process includes: placing the linear oxide layer in a nitrogen-containing gas atmosphere and performing thermal annealing on the linear oxide layer.

[0060] In another embodiment, the process parameters of the nitriding process include: the nitrogen-containing gas includes one or more of NO, NO2, and N2O; the temperature range is 950°C to 1000°C; and the process time range is 100s to 150s.

[0061] Please refer to Figure 7 After the modification treatment, an isolation structure 208 is formed in the groove 203.

[0062] In this embodiment, the first mask layer is removed after the linear oxide layer 204 is modified and before the isolation structure 208 is formed.

[0063] In this embodiment, the method for forming the isolation structure 208 includes: forming a dielectric material layer in the groove 203 and on the surface of the substrate 200; planarizing the dielectric material layer until the surface of the substrate 200 is exposed, thereby forming the isolation structure 208.

[0064] Please refer to Figure 8 After the isolation structure 208 is formed, doped ions 209 are implanted on the bottom surface of the substrate 200 to form a voltage regulation region 210.

[0065] Specifically, the voltage regulation region 210 is located on the well region 201.

[0066] The method for forming the voltage regulation region 210 includes: forming a second mask layer (not shown in the figure) on the surface of the substrate 200, the second mask layer exposing the surface of the first region I; implanting the dopant ions 209 into the surface of the first region I to form the voltage regulation region 210; and removing the second mask layer.

[0067] In this embodiment, the voltage regulation region 210 is located on the well region 201.

[0068] In this embodiment, the dopant ion 209 includes boron ions.

[0069] In this embodiment, the formation process of the voltage regulation region 210 includes an ion implantation process.

[0070] In this embodiment, the depth range of the voltage adjustment region 210 is 10 nm to 30 nm; the doping ion concentration range within the voltage adjustment region 210 is 1 x 10⁻⁶. 13 atom / cm 3 Up to 6x10 13 atom / cm 3 .

[0071] Subsequently, after forming the voltage regulation region 210, the method further includes: forming a gate (not shown in the figure) on a portion of the voltage regulation region 210; and forming source / drain regions (not shown in the figure) in the substrate 200 on both sides of the gate.

[0072] Accordingly, the present invention also provides an embodiment of the semiconductor structure formed by the above method. Please refer to the following: Figure 8 Includes: a substrate 200; and a recess 203 located within the substrate 200 (e.g., ...). Figure 6 As shown, the groove 203 has a linear oxide layer 204 on its sidewalls and bottom surface, and the linear oxide layer 204 contains modified ions 207; an isolation structure 208 is located in the groove 203 and on the surface of the linear oxide layer 204; and a voltage adjustment region 209 is located on the surface of the substrate 200, and the voltage adjustment region 209 contains doped ions 210.

[0073] In this embodiment, the semiconductor structure further includes: a gate (not shown in the figure) located on a portion of the voltage regulation region 209; source and drain regions (not shown in the figure) located on both sides of the gate in the substrate 200; and a well region 201 located in the substrate 200, wherein the conductivity type of the well region 201 is P-type, and the voltage regulation region 210 is located on the well region 201.

[0074] In this embodiment, a source-drain anti-penetration region 202 is located between the well region 201 and the voltage regulation region 210, and the conductivity type of the source-drain anti-penetration region 202 is P-type.

[0075] In this embodiment, the dopant ion 210 includes boron ions; the modified ion 207 includes nitrogen ions.

[0076] In this embodiment, the depth range of the voltage adjustment region 210 is 10 nm to 30 nm; the doping ion concentration range within the voltage adjustment region 210 is 1 x 10⁻⁶. 13 atom / cm 3 Up to 6x10 13 atom / cm 3 .

[0077] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A groove located within the substrate, wherein the sidewalls and bottom surface of the groove have a linear oxide layer, and the linear oxide layer contains modified ions; An isolation structure located within the groove and on the surface of the linear oxide layer; A voltage regulation region located on the surface of the substrate, wherein the voltage regulation region contains doped ions; A well region located within the substrate, wherein the conductivity type of the well region is P-type, and the voltage regulation region is located on the well region; A source-drain anti-penetration region is located between the well region and the voltage regulation region, and the conductivity type of the source-drain anti-penetration region is P-type.

2. The semiconductor structure as described in claim 1, characterized in that, Also includes: The gate is located on a portion of the voltage regulation region; The source / drain regions are located in the substrate on both sides of the gate.

3. The semiconductor structure as described in claim 1, characterized in that, The doping ions include boron ions; the modified ions include nitrogen ions.

4. The semiconductor structure as described in claim 1, characterized in that, The depth range of the voltage regulation region is 10 nm to 30 nm; the doping ion concentration range within the voltage regulation region is 1 x 10⁻⁶. 13 atom / cm 3 Up to 6x10 13 atom / cm 3 .

5. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, wherein the substrate has a well region and a source / drain punch-through region, the well region being of P-type conductivity and the source / drain punch-through region being of P-type conductivity; A groove and a linear oxide layer located on the sidewalls and bottom surface of the groove are formed within the substrate; The linear oxide layer is modified by incorporating modifying ions into it. After the modification treatment, an isolation structure is formed within the groove; After the isolation structure is formed, doped ions are implanted on the substrate surface to form a voltage regulation region located on the well region, and the source-drain anti-punch-through region is located between the well region and the voltage regulation region.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The doping ions include boron ions; the modified ions include nitrogen ions.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The modification process includes ion implantation or nitriding.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The ion implantation process includes a decoupled plasma nitriding process.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The process parameters of the decoupled plasma nitriding process include: the reaction gas is nitrogen, the gas flow rate is in the range of 350 sccm to 500 sccm, the power is in the range of 1800 W to 1950 W, the gas pressure is in the range of 10 mtor to 20 mtor, and the process time is in the range of 90 s to 120 s.

10. The method for forming a semiconductor structure as described in claim 7, characterized in that, The nitriding process includes: placing the linear oxide layer in a nitrogen-containing gas atmosphere and performing thermal annealing on the linear oxide layer.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The process parameters of the nitriding process include: the nitrogen-containing gas includes one or more of NO, NO2, and N2O; the temperature range is 950℃ to 1000℃; and the process time range is 100s to 150s.

12. The method for forming a semiconductor structure as described in claim 5, characterized in that, The formation process of the voltage regulation region includes ion implantation.

13. The method for forming a semiconductor structure as described in claim 5, characterized in that, The material of the linear oxide layer includes silicon oxide; the formation process of the linear oxide layer includes an in-situ water vapor growth process.

14. The method for forming a semiconductor structure as described in claim 5, characterized in that, After forming the voltage regulation region, the method further includes: forming a gate on a portion of the voltage regulation region; and forming source / drain regions in the substrate on both sides of the gate.

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