Semiconductor structure and forming method thereof

Abstract

A method of forming a semiconductor structure includes forming a first nanostructure over a first region of a substrate; forming a second nanostructure over a second region of the substrate; forming a first gate structure around the first nanostructure; replacing the second nanostructure with an isolation region; and forming a seal ring over the substrate, where the seal ring is located between the first region and the second region. The embodiment of the invention also relates to a semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor structures and methods of forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, thereby allowing more components to be integrated into a given area. Summary of the invention

[0004] An embodiment of the present disclosure provides a method for forming a semiconductor structure, the method comprising: forming a plurality of first nanostructures above a first region of a substrate; forming a plurality of second nanostructures above a second region of the substrate; forming a first gate structure around the plurality of first nanostructures; replacing the plurality of second nanostructures with a plurality of isolation regions; and forming a sealing ring above the substrate, wherein the sealing ring is located between the first region and the second region.

[0005] Another embodiment of the present disclosure provides a method for forming a semiconductor structure, the method comprising:

[0006] forming a seal ring over the substrate, including forming a plurality of conductive features within a plurality of insulating layers; and

[0007] A buffer region is formed around the sealing ring, wherein forming the buffer region comprises: forming a stack of first nanostructures above the substrate; forming an epitaxial source / drain region adjacent to the stack of first nanostructures; forming a dummy gate structure above the stack of first nanostructures; forming a first groove extending through the dummy gate structure and the stack of first nanostructures, wherein the first groove extends deeper than the epitaxial source / drain region; filling the first groove with a dielectric material; and forming the insulating layer above the dielectric material.

[0008] Another embodiment of the present disclosure provides a semiconductor structure, which includes: a plurality of devices located on a substrate; a sealing ring surrounding the plurality of devices; and a buffer region separating the sealing ring from a scribe line region, wherein the buffer region includes: a plurality of epitaxial regions located on the substrate; and a plurality of isolation regions extending into the substrate, wherein each isolation region is sandwiched between epitaxial regions in the plurality of epitaxial regions. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] When read in conjunction with the accompanying drawings, aspects of the present disclosure are best understood from the following detailed description. It is noteworthy that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0010] Figure 1 A plan view of a device die and a seal ring therein is shown in accordance with some embodiments.

[0011] Figure 2 A plan view of a device wafer with device dies and seal rings therein is shown in accordance with some embodiments.

[0012] Figure 3 , Figure 4 , Figure 5 , Fig. 6A , Figure 6B , Figure 6C , Fig. 7A , Figure 7B , Figure 7C , Fig. 8A , Figure 8B , Figure 8C , Fig. 9A , Fig. 9B , Fig. 9C , Fig. 10A , Fig. 10B , Fig. 10C , Fig.11A , Fig. 11B , Fig. 11C , Fig. 12A , Fig. 12B , Fig. 12C , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig. 14C , Fig.15A , Fig. 15B , Fig. 15C , Fig.16A , Fig. 16B , Fig. 16C , Fig.17A , Fig. 17B , Fig. 17C , Fig.18A , Fig.18B , Fig. 18C , Fig.19 and Fig. 20 Various views are shown of intermediate steps in forming a device die in accordance with some embodiments.

[0013] Fig.21 , Fig. 22 , Fig.23 , Fig.24 , Fig.25 and Fig.26Cross-sectional views are shown of intermediate steps in forming isolation regions in accordance with some embodiments.

[0014] Fig. 27 A plan view of a device die is shown in accordance with some embodiments.

[0015] Fig.28 A cross-sectional view of a device die is shown in accordance with some embodiments.

[0016] Fig.29 , Fig.30 , Fig.31 , Fig.32 and Fig.33 Cross-sectional views are shown of intermediate steps in forming isolation regions in accordance with some embodiments.

[0017] Fig.34 A plan view of a device die is shown in accordance with some embodiments.

[0018] Fig.35 , Fig.36 and Fig.37 Cross-sectional views illustrating intermediate steps in a singulation process according to some embodiments. DETAILED DESCRIPTION

[0019] The following disclosure provides many different embodiments or examples for implementing the different components of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. As used herein, forming a first component on a second component means that the first component is in direct contact with the second component. In addition, the present disclosure may repeat reference numbers and / or letters in various instances. The repetition itself does not indicate the relationship between the embodiments and / or configurations discussed.

[0020] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0021] According to some embodiments, the buffer region between the seal ring and the scribe region is formed to include an isolation structure and / or an epitaxial structure. By forming an isolation structure in the buffer region, processing can be improved so that a smaller buffer region can be used, thereby increasing device density. For example, the presence of the isolation region can improve the flatness of the buffer region. In addition, the buffer region can be formed without metal parts, which can improve plasma cutting of the scribe region.

[0022] The disclosed nanostructured field effect transistor (NSFET) embodiments may also be applied to other nanostructured devices, such as nanosheet devices, nanowire devices, all-around gate (GAA) devices, nanoFETs, and the like. The embodiments are described below in a specific context, where the die includes a nanoFET. However, various embodiments may be applied to dies including other types of transistors (e.g., fin field effect transistors (FinFETs), planar transistors, etc.) that replace or combine with NSFETs. The embodiments discussed herein will provide examples of how the subject matter of the present disclosure can be implemented or used, and those of ordinary skill in the art will readily understand the modifications that may be made while remaining within the intended scope of the different embodiments. In the various views and illustrative embodiments, the same reference numerals are used to indicate the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0023] Figure 1 A top view of a device die 100 according to some embodiments is shown. The device die 100 can be formed on a wafer 10, as described in more detail below. The device die 100 includes one or more sealing rings 112 formed near the periphery (e.g., near the edge) of the device die 100. The sealing ring 112 can provide protection for components of the device die 100 from water, chemicals, residues, and / or contaminants that may be present during processing of the device die 100. In some embodiments, the sealing ring 112 includes one or more outer sealing rings 112 surrounding one or more inner sealing rings 112. In other embodiments, there is only one sealing ring 112. Accordingly, the term "sealing ring 112" used herein may refer to a structure including a single sealing ring or to a structure including multiple sealing rings.

[0024] The seal ring 112 may be formed along the periphery of the device die 100 and may be a continuous structure formed around the device region 111 of the device die 100. In some embodiments, the seal ring 112 is formed in a seal ring region 113 that surrounds the device region 111 of the device die 100. The device region 111 is used to form functional circuits, integrated circuit devices, and / or interconnect structures described in more detail below. In some embodiments, the seal ring 112 is formed using the same conductive materials and process steps as the conductive features within the device region 111. In some embodiments, the seal ring region 113 contains dummy devices that may or may not be electrically isolated from the seal ring 112.

[0025] In some embodiments, the seal ring region 113 is separated from the device region 111 by an internal buffer region 114. In some embodiments, the internal buffer region 114 includes dummy devices and / or dummy conductive components. Separating the device region 111 from the seal ring region 113 by the internal buffer region 114 can reduce the risk of damaging components in the device region 111 and can also improve the processing of the device region 111.

[0026] In some embodiments, seal ring region 113 is surrounded by outer buffer region 115. Outer buffer region 115 separates seal ring 112 from scribe line region 116 (described below) and reduces the risk of damaging seal ring 112 during singulation. For example, in some embodiments, outer buffer region 115 protects seal ring 112 from damage when a plasma dicing process is used to singulate device die 100. In some embodiments, outer buffer region 115 is free of conductive features (e.g., metal features), which can allow for improved plasma dicing. In some embodiments, outer buffer region 115 can include dummy devices or isolation regions (e.g., isolation regions 86, see Fig.23 ), which can reduce topography effects, improve flatness, improve processing, allow outer buffer region 115 to have a smaller width, and reduce the risk of damaging seal ring 112 during singulation. In some cases, portions of outer buffer region 115 can be removed during the singulation process.

[0027] Figure 2 1 shows a plan view of a wafer 10 including a plurality of device dies 100 according to some embodiments. The wafer 10 and / or the device dies 100 may be similar to those described elsewhere herein. The device dies 100 are separated by scribe regions 116, which are at least partially removed during a singulation process to form individual device dies 100. For example, the scribe regions 116 may be removed using a sawing process, a plasma cutting process, etc. Figure 2 As shown, each device die 100 includes a seal ring 112 located therearound.

[0028] Figures 3 to 28 1 shows an intermediate step of forming the isolation region 86 of the outer buffer region 115 of the seal ring 112 according to some embodiments. In some embodiments, Figures 3 to 18C The process steps shown in the figure can be performed in the device area 111 and the outer buffer area 115. In some embodiments, the process steps can also be performed in the seal ring area 113 and / or the inner buffer area 114. Figure 3 , showing a cross-sectional view of wafer 10. In some cases, wafer 10 may be similar to Figure 1 to Figure 2 Wafer 10 is described. Wafer 10 includes a multilayer structure including a multilayer stack 22 located on a substrate 20. According to some embodiments, substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon germanium (SiGe) substrate, etc., while other substrates and / or structures may be used, such as semiconductor on insulator (SOI), strained SOI, silicon germanium on insulator, etc.

[0029] According to some embodiments, multilayer stack 22 is formed by a series of deposition processes for depositing alternating materials. According to some embodiments, multilayer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material different from the first semiconductor material.

[0030] According to some embodiments, the first semiconductor material of the first layer 22A is formed by silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors including silicon germanium (SiGe), gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium arsenide indium, gallium phosphide and / or gallium indium arsenide phosphide; etc., or combinations thereof, or the first layer 22A contains silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors including silicon germanium (SiGe), gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium arsenide indium, gallium phosphide and / or gallium indium arsenide phosphide; etc., or combinations thereof. According to some embodiments, the deposition of the first layer 22A (e.g., SiGe) is by epitaxial growth, and the corresponding deposition method may be vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer deposition (ALD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), etc. According to some embodiments, the first layer 22A is formed at about Peace However, any suitable thickness may be utilized while remaining within the scope of the embodiments.

[0031] Once the first layer 22A is deposited over the substrate 20, the second layer 22B is deposited over the first layer 22A. According to some embodiments, the second layer 22B is formed of silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium (SiGe), gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium arsenide indium phosphide, and / or gallium indium arsenide phosphide; the like, or a combination thereof, or the second layer 22B includes silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium (SiGe), gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; the like, or a combination thereof, wherein the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, according to some embodiments where the first layer 22A is silicon germanium, the second layer 22B may be formed of silicon, or vice versa. It should be understood that any suitable material combination may be used for the first layer 22A and the second layer 22B.

[0032] According to some embodiments, the second layer 22B is epitaxially grown on the first layer 22A using a deposition technique similar to the deposition technique used to form the first layer 22A. According to some embodiments, the second layer 22B is formed to a thickness similar to the thickness of the first layer 22A. The second layer 22B can also be formed to a different thickness than the first layer 22A.

[0033] Once the second layer 22B is formed over the first layer 22A, the deposition process is repeated to form the remaining layers in the multilayer stack 22 until the desired topmost layer of the multilayer stack 22 is formed. According to some embodiments, the first layer 22A has the same or similar thickness as each other, and the second layer 22B has the same or similar thickness as each other. The first layer 22A may also have the same thickness as the thickness of the second layer 22B or a different thickness. According to some embodiments, the first layer 22A is removed in a subsequent process, and the first layer 22A is optionally referred to as a sacrificial layer 22A throughout the description. According to an optional embodiment, the second layer 22B is sacrificial and is removed in a subsequent process.

[0034] According to some embodiments, a pad layer 23 and a hard mask 24 are deposited over the multilayer stack 22. Pad layer 23 (sometimes referred to as a sacrificial layer) may be formed of a compound including silicon and another material selected from carbon, oxide, nitrogen, or a combination thereof. Hard mask 24 may be formed of or include silicon nitride.

[0035] refer to Figure 4, patterning the hard mask 24 and the pad layer 23. Next, the multilayer stack 22 and portions of the underlying substrate 20 are patterned in an etching process to form a groove 25. The groove 25 extends into the substrate 20. The remaining portion of the multilayer stack is referred to as the multilayer stack 22' hereinafter. Below the multilayer stack 22', some portions of the substrate 20 are left, and these portions of the substrate 20 are referred to as substrate strips 20' or fins 20' hereinafter. The multilayer stack 22' includes semiconductor layers 22A and 22B. Hereinafter, the semiconductor layer 22A is optionally referred to as a sacrificial layer, and the semiconductor layer 22B is optionally referred to as a nanostructure. The multilayer stack 22' and portions of the underlying substrate strip 20' are collectively referred to as semiconductor strips 27.

[0036] In the above embodiments, the nanostructure transistor structure can be patterned by any suitable method. For example, one or more photolithography processes can be used to pattern the structure, including double patterning or multiple patterning processes. Typically, a double patterning process or a multiple patterning process combines a photolithography process with a self-aligned process, thereby allowing the creation of a pattern with a spacing smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above the substrate and the sacrificial layer is patterned using a photolithography process. Using a self-aligned process, a spacer is formed next to the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the structure.

[0037] Figure 4 , Figure 5 , Fig. 6A , Figure 6B and Figure 6C The formation of isolation regions 30 is shown, and isolation regions 30 are also referred to as shallow trench isolation (STI) regions throughout the description. Figure 4 , depositing dielectric liner 26, which may be a conformal dielectric layer. Dielectric liner 26 may include silicon oxide, silicon nitride, etc., and may be formed using, for example, ALD, high density plasma chemical vapor deposition (HDPCVD), CVD, etc.

[0038] Next, refer to Figure 5 , a dielectric material 28 is deposited over the dielectric liner 26. The dielectric material 28 may include silicon oxide or other dielectric materials including carbon, nitrogen, etc., and may be formed using flowable chemical vapor deposition (FCVD), spin coating, HDPCVD, ALD, CVD, etc.

[0039] Fig. 6A , Figure 6B and FIG. 6C to FIG. 18A , Fig.18B and Fig. 18CSubsequent figure numbers in the figure may have a corresponding figure number followed by the letter A, B or C. The figure with the reference figure number including the letter A shows a stereogram. The figure with the reference figure number including the letter B shows a vertical plane XX ( Fig. 6A ). The drawings with reference numbers including the letter C show a cross-sectional view taken from a vertical plane YY ( Fig. 6A ) obtained from the cross-sectional view.

[0040] refer to Fig. 6A , Figure 6B and Figure 6C A planarization process such as a chemical mechanical polishing (CMP) process or a mechanical grinding process is performed to polish and level the top surfaces of dielectric material 28 and dielectric liner 26, and the remaining portions of dielectric material 28 and dielectric liner 26 are STI regions 30. In the planarization process, hard mask 24 or pad layer 23 may be used as a polishing stop layer.

[0041] refer to Fig. 7A , Figure 7B and Figure 7C , so that the STI region 30 is recessed, so that the semiconductor strip 27 ( Figure 7B ) protrudes higher than the top surface 30T of the remaining portion of the STI region 30 to form a protruding fin 31. The protruding fin 31 includes the top of the multilayer stack 22' and the substrate strip 20'. The recessing of the STI region 30 can be performed by a dry etching process, wherein, for example, NF3 and NH3 are used as etching gases. During the etching process, plasma can be generated. Argon can also be included. According to an optional embodiment of the present disclosure, the recessing of the STI region 30 is performed by a wet etching process. For example, the etching chemical can include HF.

[0042] refer to Fig. 8A , Figure 8B and Figure 8C , depositing a capping SiGe layer 32. The capping SiGe layer 32 may be formed by a conformal deposition process such as ALD, CVD, etc. According to an alternative embodiment, the capping SiGe layer 32 is not formed. An anisotropic etching process may then be performed to remove a horizontal portion of the capping SiGe layer 32, thereby leaving a vertical portion of the capping SiGe layer 32.

[0043] exist Fig. 9A , Fig. 9B and Fig. 9CIn the embodiment of the present invention, a dielectric liner 34 is formed, and then a dielectric layer 36 is deposited. The dielectric liner 34 may be formed of or include, for example, silicon carbonitride, silicon oxycarbide, silicon nitride, etc., and may be formed by a conformal deposition process such as ALD, CVD, etc. The dielectric layer 36 may be formed of or include silicon oxide, and may be formed by a deposition process, spin coating, etc.

[0044] Fig. 10A , Fig. 10B and Fig. 10C The etching back of dielectric layer 36 and dielectric liner 34 is shown. The remaining dielectric liner 34 and dielectric layer 36 are located in the gap between adjacent multilayer stacks 22', and the remaining dielectric liner 34 and dielectric layer 36 are collectively referred to as dielectric region 37. According to some embodiments, the top surface of dielectric layer 36 is flush with or lower than the top of multilayer stack 22'. According to some embodiments, by controlling the etching process, the top of dielectric liner 34 can be higher than the top surface of dielectric layer 36.

[0045] Fig.11A , Fig. 11B and Fig. 11C The formation of high-k dielectric region 38 is shown. According to some embodiments, dielectric region 38 is deposited by high density plasma chemical vapor deposition (HDPCVD), PECVD, ALD, CVD, etc. The material of dielectric region 38 can be selected from hafnium oxide, zirconium oxide, aluminum oxide, aluminum nitride, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, etc. According to some embodiments, a planarization process is then performed to make the top surface of dielectric region 38 flush with hard mask 24.

[0046] Next, the hard mask 24 and the pad layer 23 are removed, for example, in a dry etching process and / or a wet etching process. Fig. 12A , Fig. 12B and Fig. 12C As shown, recesses 54 are formed between high-k dielectric regions 38 , which may protrude higher than multilayer stack 22 ′.

[0047] Fig.13A and Fig. 13B The formation of a dummy gate dielectric layer 44 is shown, which is formed as a conformal layer. According to some embodiments, the dummy gate dielectric layer 44 is deposited, for example, using a conformal deposition process such as ALD, CVD, etc. According to some embodiments, the dummy gate dielectric layer 44 may be formed of or include silicon oxide. The dummy gate dielectric layer 44 extends into the recess 54 and extends over the top surface of the high-k dielectric region 38.

[0048] Fig.14A , Fig. 14Band Fig. 14C Deposition of a dummy gate electrode layer 46 is shown. According to some embodiments, the dummy gate electrode layer 46 is formed of or includes polysilicon, amorphous silicon, etc. A hard mask layer 48 is also formed over the dummy gate electrode layer 46. The hard mask layer 48 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon carbon nitride oxide, etc., or a multilayer thereof.

[0049] Next, if Fig.15A , Fig. 15B and Fig. 15C As shown, the hard mask layer 48, the dummy gate electrode layer 46, and the dummy gate dielectric layer 44 are patterned in an etching process to form a dummy gate stack 50. The remaining portions of the hard mask layer 48, the dummy gate electrode layer 46, and the dummy gate dielectric layer 44 are referred to as hard mask 48, dummy gate electrode 46, and dummy gate dielectric 44, respectively.

[0050] Next, a gate spacer layer 52 is deposited, for example, by a conformal deposition process such as ALD, CVD, or the like. According to some embodiments, the gate spacer layer 52 is formed of a dielectric material such as silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, silicon carbon nitride oxide, or the like, and may have a single-layer structure or may have a multilayer structure including a plurality of dielectric layers. After the deposition process, an anisotropic etching process may be performed to etch the horizontal portion of the gate spacer layer 52 so that the vertical portion of the gate spacer layer 52 is not removed. The remaining portion of the dielectric layer is referred to as the gate spacer 52. In subsequent figures, a gate stack 50 is shown, while the dummy gate dielectric layer 44 and the dummy gate electrode layer 46 may not (or may) be shown separately.

[0051] Fig.16A , Fig. 16B and Fig. 16C The resulting structure is shown after forming a gate spacer 52, which is located at Fig.16A and Fig. 16C Next, the protruding fin 31 ( Fig.15A , Fig. 15B and Fig. 15C ) is recessed in a portion that is not directly below the dummy gate stack 50 and the gate spacer 52 to form a recess 54, which is located between the unetched portions of the protruding fins 31. For example, a dry etching process may be performed using C2F6, CF4, SO2, a mixture of HBr, Cl2 and O2, a mixture of HBr, Cl2, O2 and CH2F2, etc. to etch the multilayer semiconductor stack 22' and the underlying substrate strip 20'. The bottom of the recess 54 is at least flush with the bottom of the multilayer semiconductor stack 22', or may be lower than the bottom of the multilayer semiconductor stack 22' (e.g., Fig. 16C). The etching may be anisotropic so that the sidewalls of the multilayer semiconductor stack 22 ′ facing the recess 54 are vertical and straight.

[0052] After forming the groove 54, Fig. 16C As shown, the sacrificial semiconductor layer 22A is recessed laterally to form a lateral groove 56, which is recessed from the edges of the corresponding upper nanostructure 22B and the lower nanostructure 22B. The lateral recessing of the sacrificial semiconductor layer 22A can be achieved by a wet etching process using an etchant that is more selective to the material of the sacrificial semiconductor layer 22A (e.g., silicon germanium (SiGe)) than to the material of the nanostructure 22B and the substrate 20 (e.g., silicon (Si)). For example, in an embodiment in which the sacrificial semiconductor layer 22A is formed of silicon germanium and the nanostructure 22B is formed of silicon, the wet etching process can be performed using an etchant such as hydrochloric acid (HCl). According to an optional embodiment, the lateral recessing of the sacrificial semiconductor layer 22A is performed by an isotropic dry etching process or a combination of a dry etching process and a wet etching process.

[0053] Fig.17A , Fig. 17B and Fig. 17C The formation of the inner spacer 58 is shown. The formation process includes depositing a spacer layer extending into the recess 56, and performing an etching process to remove the portion of the inner spacer layer located outside the recess 56, thus leaving the inner spacer 58 in the recess 56. The inner spacer 58 may be formed of silicon oxycarbonitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, etc., or the inner spacer 58 may include silicon oxycarbonitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, etc. According to some embodiments, the etching of the spacer layer may be performed by a wet etching process, wherein the etching chemistry may include H2SO4, diluted HF, ammonia solution (NH4OH, ammonia in water), etc., or a combination thereof.

[0054] refer to Fig.18A , Fig.18B and Fig. 18C, forming an epitaxial source / drain region 60 in the groove 54. The source / drain region may refer to the source or drain individually or collectively, depending on the context. According to some embodiments, the source / drain region 60 may stress the nanostructure 22B used as the channel of the corresponding nanostructure transistor, thereby improving performance. When the resulting transistor is an n-type transistor, the epitaxial source / drain region 60 is formed to be n-type by doping with an n-type dopant. For example, the n-type source / drain region 60 may be formed of silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc., or the n-type source / drain region 60 may include silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc. When the resulting transistor is a p-type transistor, the epitaxial source / drain region 60 is formed to be p-type by doping with a p-type dopant. For example, the p-type source / drain region 60 may be formed of silicon germanium boron (SiGeB), silicon boron (SiB), etc. or include silicon germanium boron (SiGeB), silicon boron (SiB), etc. Fig.18A and Fig.18B Schematically illustrated are n-type epitaxial source / drain regions 60N and p-type epitaxial source / drain regions 60P as examples. In some cases, forming epitaxial source / drain regions 60 in outer buffer regions 115 can reduce stress during the singulation process, stress due to seal ring 112, or stress from other sources. Reducing stress by forming epitaxial source / drain regions 60 in outer buffer regions 115 can improve yield and improve device reliability.

[0055] Figures 19 to 28 An intermediate step in forming the sealing ring 112 is shown in accordance with some embodiments. Fig.19 Shows 18A to 18C A perspective view after the steps shown. Figure 20 to Figure 26 A cross-sectional view taken from the vertical plane YY described previously is shown, and also as Fig.19 is shown in for reference. Figure 20 to Figure 26 Each of the diagrams shows a cross-sectional view of an outer buffer region 115 and a cross-sectional view of a device region 111 in which a device (e.g., NSFET or other device) is formed. In some embodiments, the process steps shown for the outer buffer region 115 may also be performed for the seal ring region 113 and / or the inner buffer region 114.

[0056] Fig.19 and Fig. 20A view of the structure after forming a contact etch stop layer (CESL) 62 and an interlayer dielectric (ILD) 64 is shown. The CESL 62 may be formed of silicon oxide, silicon nitride, silicon carbonitride, etc., and may be formed using CVD, ALD, etc. The ILD 64 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or any other suitable deposition method. The ILD 64 may be formed of an oxygen-containing dielectric material, which may include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. The formation of the CESL 62 and the ILD 64 includes depositing a conformal CESL 62, depositing the ILD 64, and performing a planarization process. According to some embodiments, a hard mask 66 is formed, and the hard mask 66 may be formed of silicon nitride, silicon oxynitride, silicon oxycarbide, etc., or the hard mask 66 may include silicon nitride, silicon oxynitride, silicon oxycarbide, etc. The formation process may include recessing the ILD 64 to form a groove, depositing a corresponding dielectric material into the groove, and performing a planarization process.

[0057] Fig. 20 , Fig.21 , Fig. 22 and Fig.23 The fin isolation region 84 ( Fig.21 ) and the formation of the isolation region 86 below, which cuts through and electrically isolates the adjacent protruding fins. Since the formation process involves cutting the polysilicon pseudo gate electrode on the edge of the active area, the isolation region 84 can also be referred to as the cut polysilicon on the diffusion edge (CPODE) region. Fig.21 Deposition of a hard mask 68 and an etch mask 70 is shown. According to some embodiments, the hard mask 68 is formed of silicon nitride, silicon oxynitride, or the like, or the hard mask 68 includes silicon nitride, silicon oxynitride, or the like. According to some embodiments, the etch mask 70 is a three-layer etch mask, which includes a bottom layer 70B, a middle layer 70M, and a top layer 70T. The bottom layer 70B can be formed of a cross-linked photoresist. The middle layer 70M can be formed of an inorganic dielectric material. The top layer 70T is formed of a patterned photoresist with a patterned trench 72 therein.

[0058] exist Fig. 22 In some embodiments, trenches 72 and 74 are etched. Fig. 22 As shown, etching of trenches 72 and 74 removes first layer 22A between inner spacers 58 and removes second layer 22B. In some embodiments, top layer 70T (see Fig.21) is used as an etching mask to etch the middle layer 70M and the bottom layer 70B. During the etching process, the top layer 70T (and possibly the middle layer 70M) may be consumed, leaving the patterned bottom layer 70B. In this way, the groove 72 can be transferred from the top layer 70T to the bottom layer 70B. The remaining etching mask 70 is then used to etch the hard mask 68 so that the groove 72 is further transferred into the hard mask 68. The remaining etching mask 70 is then removed, retaining the patterned hard mask 68. The patterned hard mask 68 is then used as an etching mask to etch the underlying structure to form grooves 72 and 74. First, the gate stack 50 is etched so that the groove 72 extends further downward into the gate stack 50. The portion of the groove 72 in the gate stack 50 is also referred to as a through-gate trench. The etching process is anisotropic so that the groove 72 can have substantially vertical sidewalls. When the dummy gate electrode layer 46 is formed of polycrystalline silicon or amorphous silicon, etching of the dummy gate electrode layer 46 can be performed using fluorine (F2), chlorine (Cl2), hydrogen chloride (HCl), hydrogen bromide (HBr), bromine (Br2), C2F6, CF4, SO2, etc. or a combination thereof.

[0059] After etching the gate electrode 46, the pseudo gate dielectric 44 and any native oxide formed on the surface of the multilayer stack 22' are removed by an etching process. The corresponding process may also be referred to as a dielectric breakdown process. According to some embodiments, the etching may be performed using CF4, Ar, etc., and the etching may have a low selectivity. After the dielectric breakdown process, the high-k dielectric region 38 is exposed, and the multilayer stack 22' is also exposed to the trench 72. Next, the multilayer stack 22' is etched and the semiconductor strips 20' are etched. Fig. 22 As shown, the underlying main body portion of substrate 20 below STI region 30 is also etched. According to some embodiments, the etching process includes a selective etch with high etching selectivity between semiconductor material and dielectric material. Accordingly, high-k dielectric region 38, internal spacer 58, STI region 30, etc. exposed in the etching process are not etched. Thus, trench 74, also referred to as a through-gate trench, is formed. In some cases, trench 74 can be considered as a portion of trench 72.

[0060] According to some embodiments, the etching of the multilayer stack 22', the semiconductor strips 20', and the underlying bulk portion of the substrate 20 is performed using HBr, O2, and / or Ar. In the etching of the semiconductor strips 20' and the underlying bulk portion of the substrate 20, CO2 may be added in addition to or in place of O2. The etching process may also be performed using other etching gases such as F2, Cl2, HCl, HBr, Br2, C2F6, CF4, SO2, O2, CH2F2, etc. or combinations thereof. In some embodiments, the etching is performed using plasma etching, which may be performed with an applied bias power to achieve anisotropic etching.

[0061] Fig.23 A deposition process is shown for filling trenches 72 and 74 and forming isolation regions 86 according to some embodiments. The deposition process may deposit one or more dielectric layers within trenches 72 / 74. In some embodiments, the dielectric layer includes a dielectric liner and a dielectric fill layer (not shown separately). The dielectric liner may be formed of or include silicon oxide. The dielectric fill layer may be formed of or include silicon nitride. Other materials such as silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, etc. may also be used to form the dielectric layer. In some embodiments, a planarization process (e.g., a CMP process, a grinding process, etc.) may be performed to remove excess dielectric layer material, and the remaining portion of the dielectric layer forms isolation regions 86. In some embodiments, the planarization process removes the remaining portion of the hard mask 68.

[0062] In some cases, forming the isolation region 86 in the external buffer region 115 allows the morphology and composition of the external buffer region 115 to be similar to the morphology and composition of the device region 111. This can allow the external buffer region 115 to have a flatter morphology, which can allow a smaller external buffer region 115 and also improve the processing of the device die 100. For example, a flatter external buffer region 115 can reduce the risk of morphology-related processing issues. In this way, the yield can be improved. In addition, as previously described, forming the epitaxial source / drain region 60 in the external buffer region 115 can eliminate the loading effect caused by forming the epitaxial source / drain region 60, and can also reduce the stress caused by the sealing ring 112 or the singulation process. In addition, the isolation region 86 and the epitaxial source / drain region 60 can be formed in the external buffer region 115 without the need for additional process steps.

[0063] exist Fig.24In some embodiments, the gate stack 50 and the sacrificial layer 22A in the device region 111 are removed. In some embodiments, the gate stack 50 is removed by an anisotropic dry etching process that selectively etches the material of the gate stack 50. The sacrificial layer 22A can then be removed by performing an isotropic etching process such as wet etching using an etchant that is selective to the material of the sacrificial layer 22A. The etching process forms a groove 87 that exposes the surface of the nanostructure 22B and can surround the nanostructure 22B.

[0064] exist Fig.25 , a gate dielectric 88 and a gate electrode 90 are formed to replace the gate stack 92. The gate dielectric 88 is conformally deposited in the recess 87. According to some embodiments, the gate dielectric 88 includes one or more dielectric layers, such as oxides, metal oxides, etc., or combinations thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric 88 includes a high-k dielectric material, and in these embodiments, the gate dielectric 88 may have a k value greater than about 7.0 and may include silicates or metal oxides of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The formation method of the gate dielectric 88 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0065] The gate electrode 90 is deposited over the gate dielectric 88 and fills the remaining portion of the recess 87. The gate electrode 90 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. Fig.25 , a single layer gate electrode 90 is shown, but the gate electrode 90 may include any number of liner layers, any number of work function adjustment layers, and filler materials. Any combination of layers constituting the gate electrode 90 may be deposited between adjacent nanostructures 22B. The gate dielectric 88 and the gate electrode 90 may be considered together as a replacement gate stack 92 or a replacement gate structure 92.

[0066] The replacement gate stack 92 at least partially surrounds the nanostructures 22B, and these nanostructures 22B serve as the channel region of the resulting NSFET of the device region 111. Fig.25 As shown, the presence of isolation region 86 in outer buffer region 115 blocks replacement gate stack 92 from forming on nanostructures 22B in that region. Similarly, isolation region 86 in device region 111 blocks replacement gate stack 92 from forming on some nanostructures 22B. A dielectric layer 94, which may include an etch stop layer, may be formed over replacement gate stack 92. In some embodiments, portions of replacement gate stack 92 may be removed and replaced with a dielectric “cut material” (see FIG. Fig. 27 The cut material 93 in the isolation region 86 is removed to isolate the adjacent replacement gate structure 92. The cut material can be, for example, an oxide, a nitride, a material similar to that described for the dielectric region 86, etc. In some embodiments, portions of the isolation region 86 are also removed and replaced with the cut material.

[0067] exist Fig.26 In the process, a planarization process is performed to remove excess material of the replacement gate stack 92. The planarization process may include, for example, a CMP process, a grinding process, etc. In some embodiments, the planarization process removes the hard mask 66. In this way, a NSFET may be formed in the device region 111. In some cases, the structure in the outer buffer region 115 may be considered a dummy device. An example of a dummy device is Fig.26 Indicated by the dummy device 101 in FIG.

[0068] Fig. 27 A plan view of the outer buffer region 115 and the device region 111 is shown in accordance with some embodiments. Fig. 27 The outer buffer region 115 and the device region 111 shown may be connected to Fig.26 The outer buffer region 115 is shown to be similar to the device region 111 . Fig. 27 The outer buffer region 115 is shown as being adjacent to the device region 111, but in other cases, the buffer region 115 may be separated from the device region 111 by a seal ring region 113, an inner buffer region 114, etc. Fig. 27 As shown, in the outer buffer region 115, the replacement gate stack 92 is not formed, but the isolation region 86 is formed. In this way, in some embodiments, the outer buffer region 115 can be a metal-free region. In some cases, the isolation region 86 can also be formed in the device region 111, as shown. Fig. 27 Also shown is a cut material 93 separating adjacent replacement gate stacks 92 in device region 111. In some embodiments, cut material 93 may also separate isolation regions 86 in outer buffer region 115 in some embodiments. In other embodiments, cut material may not be formed in outer buffer region 115.

[0069] Fig.28 1 shows a cross-sectional view of a device region 111, an inner buffer region 114, a seal ring region 113, an outer buffer region 115, and a scribe line region 116 of a wafer 10 according to some embodiments. Fig. 27Thereafter, an interconnect structure 106 is formed in the device region 111, and a seal ring 112 is formed in the seal ring region 113. The interconnect structure 106 and the seal ring 112 may be formed, for example, by forming a plurality of metallization layers (not separately labeled) in a plurality of insulating layers (such as an intermetallic dielectric (IMD) layer 103). The metallization layers include conductive features such as vias, contacts, and / or lines embedded in the IMD layer 103. The metallization layers may be formed using suitable techniques, such as using a damascene process, a dual damascene process, and the like. The interconnect structure 106 interconnects the devices (e.g., NSFETs and / or other devices) in the device region 111 to form an integrated circuit. The seal ring 112 may be formed using the same process steps as the interconnect structure 106. Fig.28 The seal ring 112 , interconnect structure 106 , and metallization layers thereof shown are examples, and other configurations or arrangements are possible.

[0070] In some embodiments, the inner buffer region 114 may include dummy devices similar to the dummy devices 101 of the outer buffer region 115. In other embodiments, the inner buffer region 114 may include dummy devices similar to the devices of the device region 111. The inner buffer region 114 may or may not include dummy conductive features. Fig.28 As shown, the metallization layer is not formed in the outer buffer region 115 to facilitate plasma dicing. In some embodiments, the outer buffer region 115 can have a width W in a range from about 5 μm to about 25 μm, although other widths are possible. Fig.28 are illustrative examples, and interconnect structure 106 , seal ring 112 , inner buffer region 114 , or outer buffer region 115 may have different sizes, component numbers, configurations, or arrangements than those shown.

[0071] Figure 29 to Figure 33 An intermediate step in forming isolation regions 86 is shown in accordance with some embodiments. Figure 29 to Figure 33 The process shown in is similar to that previously described for Figures 19 to 26 The process is described, except that the replacement gate stack 92 is formed before the isolation regions 86 are formed. Figure 29 to Figure 33 is similar to Figure 20 to Figure 26 Cross-sectional view of . Fig.29 , Fig.30 and Fig.31 shows a cross-sectional view of a region that may be an outer buffer region 115 or a device region 111, Fig.32 and Fig.33 Each shows a cross-sectional view of the buffer region 115 and the device region 111. In some embodiments, the processing steps shown for the buffer region 115 may also be performed for the inner buffer region 114 and / or the seal ring region 113.

[0072] Fig.29 Shows something like Fig. 20 The structure shown in FIG. 1 can be used similar to Figures 3 to 20 For example, Fig.29 The structure of FIG. 2 includes epitaxial source / drain regions 60 and a gate stack 50 formed over the multilayer stack 22 ′.

[0073] exist Fig.30 In the embodiment of the present invention, one or more etching processes are performed to remove the gate stack 50 and the first layer 22A, thereby forming a recess 87. The etching process and the recess 87 may be the same as previously described for Fig.24 For example, the gate stack 50 and the first layer 22A may be selectively removed to form the nanostructure 22B.

[0074] exist Fig.31 In some embodiments, a gate dielectric 88 and a gate electrode 90 are deposited in the recess to form a replacement gate stack 92. The gate dielectric 88 and the gate electrode 90 may be formed using the same method as previously described for the gate stack 92. Fig.25 After depositing the materials for the gate dielectric 88 and the gate electrode 90, a planarization process may be performed, similar to Fig.26 In some cases, Fig.31 The structure shown can be similar to Fig.26 The structure of the device region 111 is shown.

[0075] exist Fig.32 In some embodiments, a hard mask 68 is formed over the structure and trenches 72 / 74 are etched. Figure 21 to Figure 22 In the steps described above, hard mask 68 can be formed over outer buffer region 115 and device region 111 and patterned. One or more etching processes can then be performed to form trenches 72 and 74, which can be similar to Fig. 22 The described steps include, for example, an etching process to remove the gate stack 50 and the multilayer stack 22 ′ in the outer buffer region 115 .

[0076] exist Fig.33 In some embodiments, a deposition process is performed to fill trenches 72 and 74 and form isolation regions 86. The deposition process may be similar to that previously described for Fig.23 For example, a deposition process may deposit one or more dielectric layers within trenches 72 / 74. A planarization process such as a CMP process may be performed to remove excess dielectric layer material.

[0077] Fig.34 A plan view of the outer buffer region 115 and the device region 111 is shown in accordance with some embodiments. Fig.34 The structure shown is similar to Fig. 27 The structure shown, except that the isolation region 86 in the outer buffer region 115 is formed from cut material 93. Fig.34 The outer buffer region 115 is shown as being adjacent to the device region 111, but in other cases, the buffer region 115 may be separated from the device region 111 by a seal ring region 113, an inner buffer region 114, etc. Fig.34 As shown, in the outer buffer region 115, no replacement gate stack 92 is formed. In this way, in some embodiments, the outer buffer region 115 can be a metal-free region. In some cases, the cut material 93 in the outer buffer region 115 can be formed using the same process steps as used to form the cut material 93 in the device region 111. In some embodiments, the isolation region 86 can be formed in the device region 111 instead of in the outer buffer region 115.

[0078] Fig.35 , Fig.36 and Fig.37 An intermediate step in singulation of two device dies 100A-100B of wafer 10 according to some embodiments is shown. Device dies 100A-100B and wafer 10 may be similar to those described elsewhere herein. For example, device dies 100 each include a device region 111 and a seal ring 112, and each seal ring 112 is separated from a scribe line region 116 by an outer buffer region 115. Fig.35 1 shows a cross-sectional view of a first device die 100A and a second device die 100B of a wafer 10. Figure 2 , the first device die 100A is separated from the second device die 100B by the scribe line region 116 .

[0079] exist Fig.36 In the process, a patterned mask 150, such as a patterned photoresist layer, is formed over the wafer 10. The openings in the pattern of the patterned mask 150 correspond to the cutting paths of the singulation process. Next, a cutting process, such as a plasma cutting process, is performed along the cutting paths in the scribe area 116 to form recesses 151 (e.g., trenches in the top view). The plasma cutting process etches the portions of the wafer 10 exposed by the openings in the patterned mask 150. Fig.36As shown, recess 151 extends through dielectric layer 103 and into substrate 20. In some embodiments, the bottom of recess 151 is located between the upper surface and the lower surface of substrate 20. In other words, recess 151 extends into substrate 20 but does not extend through substrate 20. In other embodiments, recess 151 extends completely through substrate 20. In some embodiments, the plasma cutting process removes portions of outer buffer region 115 so that recess 151 extends into outer buffer region 115. In some cases, the presence of metal-free outer buffer region 115 can improve the plasma cutting process and reduce the risk of damaging device dies 100A-100B.

[0080] In some embodiments, plasma cutting includes a dry plasma process, such as a deep reactive ion etching (DRIE) process, etc. The plasma cutting process may be an etching process capable of etching narrow grooves in the substrate 20 to separate individual tube cores. The plasma cutting process can avoid problems such as tube core fragmentation or cracking when using a blade to improve the yield of the manufacturing process. Unlike cutting using a blade, plasma cutting avoids or reduces damage to the surface and / or sidewall of the wafer, thereby producing greater chip strength, improved device reliability, and improved device life. Since the cutting path of plasma cutting is narrower, the scribing area 116 can be made narrower, thereby allowing more device tube cores 100 to be formed in the wafer 10 to reduce the production cost of each tube core. In addition, plasma cutting can be performed simultaneously along multiple cutting paths, thereby increasing the yield of the manufacturing process. In addition, by the shape of the opening defined in the patterned mask 150, a non-rectangular tube core shape can be easily achieved using plasma cutting.

[0081] Next, in Fig.37 The thickness of the substrate 20 is reduced. A grinding process, such as CMP or the like, may be performed on the back side of the substrate 20 to reduce the thickness of the substrate 20. In some embodiments, the grinding process is stopped when the grooves 151 extend through the (thinned) substrate 20, thereby separating the wafer 10 into a plurality of individual device dies 100A-100B.

[0082] Advantages that may exist in the embodiments described herein. By forming an isolation region in a buffer region between a seal ring and a scribe region, the topology and flatness of the buffer region can be improved, which can improve the process and improve the yield. In some cases, this can also improve the flatness or processing of adjacent regions (such as seal rings or scribe regions). Forming an isolation region also allows the seal ring to be closer to the scribe region without significantly reducing the yield or performance. In other words, a small buffer region can be formed. Therefore, the device density can be improved. In addition, forming an epitaxial source / drain region in the buffer region can reduce the stress from the seal ring or from singulation in the structure, which can further improve the yield and device performance. In some cases, the isolation region and / or the epitaxial source / drain region can be formed without additional processing steps. The buffer region can be formed without metal parts, which can improve the plasma cutting of the scribe region.

[0083] In an embodiment of the present disclosure, a method includes forming a first nanostructure over a first region of a substrate; forming a second nanostructure over a second region of the substrate; forming a first gate structure around the first nanostructure; replacing the second nanostructure with an isolation region; and forming a seal ring over the substrate, wherein the seal ring is located between the first region and the second region. In an embodiment, the method also includes replacing at least one first nanostructure with an isolation region. In an embodiment, replacing the second nanostructure includes: forming a dummy gate structure around the second nanostructure; performing an etching process to form a groove, wherein forming the groove removes the dummy gate structure and the second nanostructure; and filling the groove with a dielectric material to form the isolation region. In an embodiment, the first gate structure is formed before replacing the second nanostructure. In an embodiment, the method also includes forming a first epitaxial source / drain region adjacent to the first nanostructure and a second epitaxial source / drain region adjacent to the second nanostructure. In an embodiment, the second region separates the seal ring from the scribe region. In an embodiment, the seal ring is formed over at least one isolation region. In an embodiment, the method also includes forming an interconnect structure over the first nanostructure, wherein the second region is free of the interconnect structure. In an embodiment, the second region has a width in the range of 5 μm to 25 μm.

[0084] In an embodiment of the present disclosure, a method includes forming a seal ring above a substrate, which includes forming a conductive feature within an insulating layer; and forming a buffer region surrounding the seal ring, wherein forming the buffer region includes: forming a stack of first nanostructures above the substrate; forming an epitaxial source / drain region adjacent to the stack of first nanostructures; forming a dummy gate structure above the stack of first nanostructures; forming a first groove extending through the dummy gate structure and the stack of first nanostructures, wherein the first groove extends deeper than the epitaxial source / drain region; filling the first groove with a dielectric material; and forming an insulating layer above the dielectric material. In an embodiment, the buffer region is free of conductive features. In an embodiment, the method further includes: forming a scribe region surrounding the buffer region; and performing a plasma cutting process on the scribe region. In an embodiment, the plasma cutting process removes a portion of the buffer region. In an embodiment, the method further includes: forming a second nanostructure above the substrate, wherein the seal ring surrounds the second nanostructure; forming a gate structure above the second nanostructure; removing a portion of the gate structure to form a second groove; and filling the second groove with a dielectric material. In an embodiment, the dielectric material is different from the material of the insulating layer.

[0085] In an embodiment of the present disclosure, a structure includes a device located on a substrate; a seal ring surrounding the device; and a buffer region separating the seal ring from a scribe region, wherein the buffer region includes: an epitaxial region located on the substrate; and an isolation region extending into the substrate, wherein each isolation region is sandwiched between the epitaxial regions. In an embodiment, the device includes a nanostructure, wherein each nanostructure is sandwiched between the epitaxial regions. In an embodiment, the buffer region includes a dummy device. In an embodiment, the buffer region is free of metal. In an embodiment, the scribe region surrounds the seal ring.

[0086] In an embodiment of the present disclosure, a method for forming a semiconductor structure is disclosed, the method comprising: forming a plurality of first nanostructures over a first region of a substrate; forming a plurality of second nanostructures over a second region of the substrate; forming a first gate structure around the plurality of first nanostructures; replacing the plurality of second nanostructures with a plurality of isolation regions; and forming a seal ring over the substrate, wherein the seal ring is located between the first region and the second region. In some embodiments, the method further comprises replacing at least one first nanostructure with an isolation region. In some embodiments, replacing the plurality of second nanostructures comprises: forming a dummy gate structure around the plurality of second nanostructures; performing an etching process to form a plurality of grooves, wherein forming the plurality of grooves removes the dummy gate structure and the plurality of second nanostructures; and filling the plurality of grooves with a dielectric material to form an isolation region. In some embodiments, the first gate structure is formed before replacing the plurality of second nanostructures. In some embodiments, the method further comprises forming a first epitaxial source / drain region adjacent to the first nanostructure and a second epitaxial source / drain region adjacent to the second nanostructure. In some embodiments, the second region separates the seal ring from the scribe region. In some embodiments, the seal ring is formed over at least one isolation region. In some embodiments, the method further comprises forming an interconnect structure over the first nanostructure, wherein the second region is free of the interconnect structure. In some embodiments, the second region has a width in a range of 5 μm to 25 μm.

[0087] In another embodiment of the present disclosure, a method of forming a semiconductor structure is disclosed, the method comprising:

[0088] forming a seal ring over the substrate, including forming a plurality of conductive features within a plurality of insulating layers; and

[0089] A buffer region is formed around the sealing ring, wherein forming the buffer region comprises: forming a stack of first nanostructures above the substrate; forming an epitaxial source / drain region adjacent to the stack of first nanostructures; forming a dummy gate structure above the stack of first nanostructures; forming a first groove extending through the dummy gate structure and the stack of first nanostructures, wherein the first groove extends deeper than the epitaxial source / drain region; filling the first groove with a dielectric material; and forming an insulating layer above the dielectric material.

[0090] In some embodiments, the buffer region is free of conductive features. In some embodiments, the method further comprises: forming a scribe region surrounding the buffer region; and performing a plasma cutting process on the scribe region. In some embodiments, the plasma cutting process removes a portion of the buffer region. In some embodiments, the method further comprises: forming a plurality of second nanostructures above the substrate, wherein a seal ring surrounds the plurality of second nanostructures; forming a gate structure above the plurality of second nanostructures; removing a portion of the gate structure to form a second groove; and filling the second groove with a dielectric material. In some embodiments, the dielectric material is different from the material of the insulating layer.

[0091] In yet another embodiment of the present disclosure, a semiconductor structure is disclosed, comprising: a plurality of devices on a substrate; a sealing ring surrounding the plurality of devices; and a buffer region separating the sealing ring from a scribe region, wherein the buffer region comprises: a plurality of epitaxial regions on the substrate; and a plurality of isolation regions extending into the substrate, wherein each isolation region is sandwiched between epitaxial regions in the plurality of epitaxial regions. In some embodiments, the plurality of devices comprises a plurality of nanostructures, wherein each nanostructure is sandwiched between epitaxial regions in the plurality of epitaxial regions. In some embodiments, the buffer region comprises a dummy device. In some embodiments, the buffer region is free of metal. In some embodiments, the scribe region surrounds the sealing ring.

[0092] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: forming a plurality of first nanostructures over a first region of a substrate; forming a plurality of second nanostructures over a second region of the substrate; forming a first gate structure around the plurality of first nanostructures; replacing the plurality of second nanostructures with a plurality of isolated regions; as well as A sealing ring is formed over the substrate, wherein the sealing ring is located between the first region and the second region. 2 . The method of claim 1 , further comprising replacing at least one first nanostructure with an isolation region.

3. The method according to claim 1, wherein: Replacing the plurality of second nanostructures comprises: forming a dummy gate structure around the plurality of second nanostructures; performing an etching process to form a plurality of grooves, wherein the plurality of grooves are formed to remove the dummy gate structure and the plurality of second nanostructures; and The plurality of recesses are filled with a dielectric material to form the isolation regions.

4. The method according to claim 1, wherein: The first gate structure is formed before replacing the plurality of second nanostructures. 5 . The method of claim 1 , further comprising forming a first epitaxial source / drain region adjacent to the first nanostructure and a second epitaxial source / drain region adjacent to the second nanostructure.

6. The method according to claim 1, wherein: The second region separates the seal ring from a scribe line region.

7. The method according to claim 1, wherein: The seal ring is formed over at least one isolation region.

8. The method according to claim 1, further comprising forming an interconnect structure over the first nanostructure, wherein The second region is free of the interconnect structure.

9. A method of forming a semiconductor structure, comprising: forming a seal ring over the substrate, including forming a plurality of conductive features within a plurality of insulating layers; as well as Forming a buffer region surrounding the sealing ring, wherein forming the buffer region comprises: forming a stack of first nanostructures over a substrate; forming an epitaxial source / drain region adjacent to the stack of the first nanostructures; forming a dummy gate structure over the stack of the first nanostructures; forming a first recess extending through the stack of the dummy gate structure and the first nanostructure, wherein the first recess extends deeper than the epitaxial source / drain region; filling the first groove with a dielectric material; and The insulating layer is formed over the dielectric material.

10. A semiconductor structure comprising: a plurality of devices disposed on a substrate; a sealing ring surrounding the plurality of devices; as well as A buffer region separating the sealing ring from the scribe line region, wherein the buffer region comprises: a plurality of epitaxial regions located on the substrate; and A plurality of isolation regions extend into the substrate, wherein each isolation region is sandwiched between epitaxial regions of the plurality of epitaxial regions.

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