Semiconductor structure and forming method thereof
By forming a combination method of insulating layer and source-drain doped layer in the semiconductor structure, the challenge of improving the performance of the fully enclosed gate structure device is solved, and effective isolation and performance improvement of leakage current are achieved.
Patent Information
- Application Number
- CN202311032203.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-15
- Publication Date
- 2025-02-25
AI Technical Summary
With the increase in semiconductor transistor element density and integration, how to further improve the performance of fully enclosed gate structure devices has become a challenge.
By forming a first groove in the semiconductor structure and forming an insulating layer on the exposed substrate side walls thereof, the source-drain doped layer of the insulating layer side walls is subsequently covered, thereby reducing the probability that the source-drain doped layer and the device gate structure generate leakage current through the substrate below the channel layer.
The performance of the semiconductor structure is improved, the isolation effect of the insulating layer on the source-drain doped layer and the device gate structure is enhanced, and the probability of leakage current is reduced.
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Figure CN119521732A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art
[0002] With the rapid development of semiconductor manufacturing technology, semiconductor transistors are moving towards higher component density and higher integration, and semiconductor process nodes are continuously decreasing in accordance with Moore's Law. Transistors, as the most basic semiconductor transistors, are currently being widely used. Therefore, with the increase in component density and integration of semiconductor transistors, in order to adapt to the reduction of process nodes, the channel length of transistors must be continuously shortened.
[0003] In order to better adapt to the requirement of proportional reduction of transistor size, semiconductor processes have gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as fin field effect transistors (FinFETs) and gate-all-around (GAA) transistors. Among them, gate-all-around transistors include vertical gate-all-around transistors and horizontal gate-all-around transistors. In a gate-all-around transistor, the gate surrounds the area where the channel is located from all sides. Compared with planar transistors, the gate of a gate-all-around transistor has a stronger control ability over the channel and can better suppress the short channel effect.
[0004] As device size continues to shrink, improving the performance of all-around gate structure devices becomes increasingly difficult and challenging. Summary of the invention
[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to further improve the performance of the semiconductor structure.
[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a channel structure layer suspended on the top of the substrate, the channel structure layer including one or more channel layers spaced apart in the vertical direction; a device gate structure located on the substrate and spanning the channel structure layer, the device gate structure covering part of the top, part of the sidewall and part of the bottom of the channel layer; a source-drain doping layer located in the channel structure layer and part of the substrate on both sides of the device gate structure; an insulating layer located between the sidewalls of the source-drain doping layer and the substrate; an inner wall layer located between the sidewalls of the device gate structure directly below the channel layer and the source-drain doping layer; an interlayer dielectric layer located on the top of the source-drain doping layer, and the interlayer dielectric layer covers the sidewalls of the device gate structure.
[0007] Optionally, the material of the inner wall layer includes one or more of silicon nitride, silicon oxide and silicon oxynitride.
[0008] Optionally, the material of the insulating layer includes one or more of silicon oxide, silicon oxynitride and silicon carbide nitride.
[0009] Optionally, with a direction parallel to the substrate and perpendicular to an extension direction of the gate structure as a lateral dimension, the lateral dimension of the insulating layer is 2 nanometers to 6 nanometers.
[0010] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, on which a channel stack structure is formed, the channel stack structure comprising one or more channel stacks stacked in sequence in the vertical direction, the channel stack comprising a sacrificial layer and a channel layer located on the sacrificial layer, a gate structure spanning the channel stack structure is formed on the substrate, the gate structure covers a portion of the top and a portion of the side walls of the channel stack structure; forming a first groove in the channel stack structure and a portion of the substrate on both sides of the gate structure; forming an insulating layer on the side walls of the substrate exposed by the first groove; and forming a source-drain doping layer covering the side walls of the insulating layer in the first groove.
[0011] Optionally, the step of forming the first groove includes: forming a hard mask layer on the top of the gate structure; performing patterning on the channel stack structure and a portion of the substrate using the hard mask layer as a mask to form a first groove in the channel stack structure and a portion of the substrate; and removing the hard mask layer.
[0012] Optionally, after forming the first groove and before performing the modification treatment, the method further includes: forming a protective layer on the sidewall of the channel stack structure exposed by the first groove; and after forming the insulating layer and before forming the source-drain doping layer, the method further includes: removing the protective layer.
[0013] Optionally, the step of forming the protective layer includes: forming a protective material layer on the sidewalls and top of the gate structure, and the bottom and sidewalls of the first groove; removing the protective material layer on the sidewalls and top of the gate structure, and the bottom of the first groove, and using the protective material layer on the sidewalls of the channel stack structure exposed by the first groove as the protective layer.
[0014] Optionally, the process of removing the sidewall and top of the gate structure and the protective material layer at the bottom of the first groove includes a plasma dry etching process.
[0015] Optionally, the material of the protective layer includes one or more of silicon nitride, silicon oxynitride and silicon carbide nitride.
[0016] Optionally, a direction parallel to the substrate surface and perpendicular to the extension direction of the gate structure is a lateral direction, and a lateral dimension of the protective layer is 2 nanometers to 4 nanometers.
[0017] Optionally, the step of forming the insulating layer includes: modifying the substrate exposed by the first groove to form an insulating material layer; removing the insulating material layer at the bottom of the first groove, and using the insulating material layer located on the side wall of the first groove as the insulating layer; or, depositing the bottom and side wall of the first groove to form an insulating material layer; removing the insulating material layer at the bottom of the first groove, and using the insulating material layer located on the side wall of the first groove as the insulating layer.
[0018] Optionally, the process of modifying the substrate exposed by the first groove includes a thermal oxidation process.
[0019] Optionally, the process parameters of the thermal oxidation process include: the process gas includes oxygen, nitrogen or hydrogen; the process temperature includes 700° C. to 850° C.; the process time includes 10 min to 30 min; and the gas flow rate includes 0.5 slm to 10 slm.
[0020] Optionally, the process of removing the insulating material layer at the bottom of the first groove includes a dry etching process.
[0021] Optionally, after forming the insulating layer and before forming the source / drain doping layer, the method further includes: laterally etching the portion of the sacrificial layer exposed by the sidewall of the first groove in a direction parallel to the substrate and perpendicular to the extension direction of the gate structure to form a second groove; forming an inner wall layer in the second groove; after forming the source / drain doping layer, the method for forming the semiconductor structure further includes: forming an interlayer dielectric layer on top of the source / drain doping layer, the interlayer dielectric layer covering the sidewall of the gate structure; removing the gate structure to form a gate opening in the interlayer dielectric layer; removing the sacrificial layer exposed by the gate opening to form a through groove connected to the gate opening below the channel layer; forming a device gate structure in the gate opening and the through groove, the device gate structure surrounding the channel layer.
[0022] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0023] An embodiment of the present invention provides a method for forming a semiconductor structure, wherein a first groove is formed in a channel stack structure and a portion of a substrate on both sides of the gate structure, and an insulating layer is formed on the sidewalls of the substrate exposed by the first groove, wherein the insulating layer has an insulating effect, and after a source-drain doping layer covering the sidewalls of the insulating layer is subsequently formed in the first groove, the insulating layer can reduce the probability of leakage current generated by the source-drain doping layer and a device gate structure formed by a subsequent process through the substrate below the channel layer, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 is a corresponding structural schematic diagram of a semiconductor structure;
[0025] Figure 2 is a schematic diagram of a structure corresponding to an embodiment of a semiconductor structure of the present invention;
[0026] Figures 3 to 15 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION
[0027] The performance of current semiconductor structures needs to be improved. The reasons why the performance needs to be improved are analyzed in combination with a semiconductor structure.
[0028] Figure 1 It is a structural schematic diagram corresponding to a semiconductor structure.
[0029] refer to Figure 1 , substrate 20; a channel structure layer 32, suspended on the top of the substrate 20, the channel structure layer 32 includes one or more channel layers 22 spaced apart in the longitudinal direction; a device gate structure 26, located on the substrate 20 and spanning the channel structure layer 32, the device gate structure 26 covers part of the top, part of the sidewall and part of the bottom of the channel layer 22; a source-drain doped layer 56, located in the channel structure layer 32 and the substrate 20 on both sides of the device gate structure 26; an interlayer dielectric layer 36, located on the top of the source-drain doped layer 56, and the interlayer dielectric layer 36 covers the sidewalls of the device gate structure 26.
[0030] Research has found that the insulating effect of the inner wall layer is not very significant, and the source-drain doping layer 56 and the device gate structure 26 can generate leakage current through the substrate below the channel structure layer 32, thereby affecting the electrical properties of the semiconductor structure.
[0031] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, on which a channel stack structure is formed, the channel stack structure including one or more channel stacks stacked in sequence in the vertical direction, the channel stack including a sacrificial layer and a channel layer located on the sacrificial layer, a gate structure spanning the channel stack structure is formed on the substrate, the gate structure covers a portion of the top and a portion of the sidewalls of the channel stack structure; forming a first groove in the channel stack structure and a portion of the substrate on both sides of the gate structure; forming an insulating layer on the sidewalls of the substrate exposed by the first groove; and forming a source-drain doping layer covering the sidewalls of the insulating layer in the first groove.
[0032] An embodiment of the present invention provides a method for forming a semiconductor structure, wherein a first groove is formed in a channel stack structure and a portion of a substrate on both sides of the gate structure, and an insulating layer is formed on the sidewalls of the substrate exposed by the first groove, wherein the insulating layer has an insulating effect, and after a source-drain doping layer covering the sidewalls of the insulating layer is subsequently formed in the first groove, the insulating layer can reduce the probability of leakage current generated by the source-drain doping layer and a device gate structure formed by a subsequent process through the substrate below the channel layer, thereby improving the performance of the semiconductor structure.
[0033] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0034] Figure 2 It is a schematic diagram of the corresponding structure in one embodiment of the semiconductor structure of the present invention.
[0035] The semiconductor structure includes: a substrate (not marked); a channel structure layer 202 suspended on the top of the substrate, the channel structure layer 202 including one or more channel layers 2022 spaced apart in the longitudinal direction; a device gate structure 289 located on the substrate and spanning the channel structure layer 202, the device gate structure 289 covering part of the top, part of the sidewall and part of the bottom of the channel layer 2022; a source-drain doped layer 297 located in the channel structure layer 202 and part of the substrate on both sides of the device gate structure 289; an insulating layer 293 located between the sidewalls of the source-drain doped layer 297 and the substrate; an inner wall layer 296 located between the sidewalls of the device gate structure 289 directly below the channel layer 2022 and the source-drain doped layer 297; an interlayer dielectric layer 298 located on the top of the source-drain doped layer 297, and the interlayer dielectric layer 298 covers the sidewalls of the device gate structure 289.
[0036] Specifically, an insulating layer 293 is provided between the side walls of the source-drain doped layer 297 and the substrate, and the insulating layer 293 has an insulating effect. After the source-drain doped layer 297 covering the side walls of the insulating layer 293 is provided in the first groove, the insulating layer 293 can reduce the probability of leakage current generated between the source-drain doped layer 297 and the device gate structure 289 through the substrate under the channel layer 2022, thereby improving the performance of the semiconductor structure.
[0037] The substrate is used to provide a process platform for forming a gate-all-around (GAA) transistor.
[0038] In this embodiment, the substrate is a three-dimensional substrate, and the substrate includes a substrate 280 and a protruding portion 281 protruding from the substrate 280 .
[0039] In this embodiment, the substrate 280 is a silicon substrate. In other embodiments, the substrate material may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.
[0040] In this embodiment, the material of the protrusion 281 is the same as that of the substrate 280, and the material of the protrusion 281 is silicon. In other embodiments, the material of the protrusion may also be a semiconductor material suitable for forming a fin, such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, and the material of the protrusion may also be different from that of the substrate.
[0041] Specifically, the channel structure layer 202 is used to provide a conductive channel for the transistor.
[0042] In this embodiment, the channel structure layer 202 includes a plurality of spaced channel layers 2022, and the stacking direction of the plurality of stacked channel layers 2022 is perpendicular to the surface of the substrate 280. In this embodiment, the number of the channel layers 2022 is two.
[0043] In other embodiments, the number of channel layers is not limited to two.
[0044] In this embodiment, the material of the channel structure layer 202 and the protrusion 281 is the same, and the material of the channel structure layer 202 is Si.
[0045] The device gate structure 289 is used to control the opening and closing of the conductive channel when the device is working.
[0046] Specifically, the device gate structure 289 is a metal gate structure.
[0047] In this embodiment, the device gate structure 289 includes a gate dielectric layer (not shown) conformally covering a portion of the top, a portion of the sidewall and a portion of the bottom of the channel layer 2022, and a gate electrode layer (not shown) covering the gate dielectric layer.
[0048] In this embodiment, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.
[0049] Specifically, the gate dielectric layer includes a gate oxide layer that conformally covers a portion of the top, a portion of the sidewall, and a portion of the bottom of the channel layer 2022, and a high-k gate dielectric layer that conformally covers the gate oxide layer. The material of the high-k gate dielectric layer is a high-k dielectric material, which refers to a dielectric material having a relative dielectric constant greater than the relative dielectric constant of silicon oxide.
[0050] The gate electrode layer is used for subsequent electrical connection with an external structure. The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC. Specifically, the gate electrode layer may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer may also include only the work function layer.
[0051] In this embodiment, the semiconductor structure further includes: a spacer layer 203 located on the sidewall of the device gate structure 289 .
[0052] In this embodiment, the spacer layer 203 is a single-layer structure, and the material of the spacer layer 203 is silicon nitride.
[0053] Specifically, the source-drain doping layer 297 is used as the source region and the drain region of the transistor.
[0054] In this embodiment, the inner wall layer 296 is located between the sidewall of the device gate structure 289 directly below the channel layer 2022 and the source-drain doping layer 297 .
[0055] Specifically, the inner wall layer 296 is located between the source-drain doped layer 297 and the device gate structure 289 . The inner wall layer 296 can isolate the source-drain doped layer 297 and the device gate structure 289 , which is beneficial to reducing the parasitic capacitance between the source-drain doped layer 297 and the device gate structure 289 .
[0056] In this embodiment, the material of the inner wall layer 296 includes one or more of silicon nitride, silicon oxide and silicon oxynitride.
[0057] Specifically, silicon nitride, silicon oxide, and silicon oxynitride are all dielectric materials that can electrically isolate the device gate structure 289 and the source-drain doped layer 297 .
[0058] The insulating layer 293 has an insulating function. The insulating layer 293 can reduce the probability of leakage current generated by the source-drain doping layer 297 and the device gate structure 289 through the substrate below the channel layer 2022, thereby improving the performance of the semiconductor structure.
[0059] It should be noted that, with the direction parallel to the substrate and perpendicular to the extension direction of the device gate structure 289 as the lateral direction, the lateral dimension of the insulating layer 293 should not be too large or too small. If the lateral dimension of the insulating layer 293 is too large, it is easy to cause the protrusion 281 at the bottom of the device gate structure 289 to be completely oxidized during the formation process of the insulating layer 293, thereby affecting the electrical performance of the semiconductor structure; if the lateral dimension of the insulating layer 293 is too small, the insulating effect of the insulating layer 293 is poor, which increases the probability of leakage current generated by the source-drain doping layer 297 and the device gate structure 289 through the substrate under the channel layer 2022, thereby improving the performance of the semiconductor structure. For this reason, in this embodiment, with the direction parallel to the substrate and perpendicular to the extension direction of the device gate structure 289 as the lateral direction, the lateral dimension of the insulating layer 293 is 2 nanometers to 6 nanometers.
[0060] In this embodiment, the material of the insulating layer 293 includes one or more of silicon oxide, silicon oxynitride and silicon carbide nitride.
[0061] Silicon oxide, silicon oxynitride and silicon carbide nitride are all dielectric materials with good insulation properties, which can reduce the probability of leakage current generated by the source-drain doping layer 297 and the device gate structure 289 through the substrate below the channel layer 2022.
[0062] The interlayer dielectric layer 298 is used to achieve electrical isolation between adjacent devices.
[0063] In this embodiment, the material of the interlayer dielectric layer 298 is silicon oxide.
[0064] Figures 3 to 15 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.
[0065] refer to Figure 3 to Figure 4 , providing a substrate 100, on which a channel stack structure 129 is formed, the channel stack structure 129 includes one or more channel stacks 102 stacked in sequence in a longitudinal direction, the channel stack 102 includes a sacrificial layer 1021 and a channel layer 1022 located on the sacrificial layer 1021, and a gate structure 104 is formed on the substrate 100 to cross the channel stack structure 129, and the gate structure 104 covers a portion of the top and a portion of the sidewalls of the channel stack structure 129.
[0066] The substrate 100 is used to provide a process platform for forming a gate-all-around (GAA) transistor.
[0067] In this embodiment, the channel stack structure 129 includes one or more channel stacks 102 stacked in sequence in the vertical direction.
[0068] Each of the channel stacks 102 includes a sacrificial layer 1021 and a channel layer 1022 located on the sacrificial layer 1021. The channel stack 102 provides a process basis for the subsequent formation of the suspended and spaced channel layer 1022. Specifically, the sacrificial layer 1021 supports the channel layer 1022, thereby providing a process basis for the subsequent realization of the spaced and suspended setting of the channel layer 1022, and also occupies a spatial position for the subsequent formation of the device gate structure 189. The channel layer 1022 is used to provide a conductive channel that fully surrounds the gate transistor.
[0069] Correspondingly, when there are multiple channel stacks 102 , there are also multiple channel layers 1022 , and the multiple channel layers 1022 are arranged at intervals.
[0070] In this embodiment, the material of the channel layer 1022 is Si, and the material of the sacrificial layer 1021 is SiGe. In the subsequent process of removing the sacrificial layer 1021, the etching selectivity of SiGe and Si is relatively high, so by setting the material of the sacrificial layer 1021 to SiGe and setting the material of the channel layer 1022 to Si, the influence of the process of removing the sacrificial layer 1021 on the channel layer 1022 can be effectively reduced, thereby improving the quality of the channel layer 1022, and further facilitating the improvement of device performance.
[0071] In this embodiment, the gate structure 104 is a dummy gate structure, and the gate structure 104 occupies a space position for the subsequent device gate structure 189. In this embodiment, the gate structure 104 includes a dummy gate layer. The material of the dummy gate layer includes polysilicon.
[0072] In this embodiment, before forming the gate structure 104 , the method for forming the semiconductor structure further includes: forming a gate oxide layer 105 on the top surface of the channel stack structure 129 .
[0073] The gate oxide layer 105 is used to protect the channel stack structure 129 . The gate oxide layer 105 can also be used as an etching stop layer in the subsequent step of removing the gate structure 104 , which helps to reduce the probability of damage to the channel stack structure 129 caused by the process of removing the gate structure 104 .
[0074] In this embodiment, the material of the gate oxide layer 105 includes silicon oxide.
[0075] In this embodiment, a spacer layer 103 is further formed on the sidewall of the gate structure 104 .
[0076] The spacer layer 103 is used as an etching mask in a subsequent etching process to define a formation region of a source / drain doping layer. The spacer layer 103 is also used to protect a sidewall of the gate structure 104 .
[0077] In this embodiment, the sidewall spacer 103 is a single-layer structure, and the material of the sidewall spacer 103 is silicon nitride.
[0078] refer to Figure 5 A first groove 107 is formed in the channel stack structure 129 and a portion of the substrate 100 on both sides of the gate structure 104 .
[0079] The first groove 107 provides a space for the subsequent formation of a protection layer and an insulating layer, and also provides a process window for the subsequent formation of a second groove.
[0080] In this embodiment, the step of forming the first groove 107 includes: forming a hard mask layer (not marked) on the top of the gate structure 104; using the hard mask layer as a mask to perform patterning on the channel stack structure 129 and a portion of the substrate 100 to form a first groove 107 in the channel stack structure 129 and a portion of the substrate 100.
[0081] In this embodiment, the process of forming the first groove 107 includes a dry etching process.
[0082] It should be noted that after a portion of the substrate 100 is patterned, the substrate 100 becomes a three-dimensional substrate 100 , and the substrate 100 includes a substrate 180 and a protruding portion 181 protruding from the substrate 180 .
[0083] In this embodiment, the substrate 180 is a silicon substrate. In other embodiments, the substrate material may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.
[0084] The protrusion 181 exposes a portion of the substrate 180 , thereby providing a process basis for the subsequent formation of an isolation layer.
[0085] In this embodiment, the material of the protrusion 181 is the same as that of the substrate 180, and the material of the protrusion 181 is silicon. In other embodiments, the material of the protrusion may also be a semiconductor material suitable for forming a fin, such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, and the material of the protrusion may also be different from that of the substrate.
[0086] In this embodiment, the channel stack structure 129 is located on the top of the protrusion 181 , and the extending direction of the channel stack structure 129 is the same as the extending direction of the protrusion 181 .
[0087] It should be noted that, after forming the first groove 107 , the method for forming the semiconductor structure further includes: removing the hard mask layer.
[0088] The process of removing the hard mask layer includes an ashing process.
[0089] refer to Figure 6 to Figure 7 After forming the first groove 107 and before subsequently forming the insulating layer, the method further includes: forming a protection layer 190 on the sidewall of the channel stack structure 129 exposed by the first groove 107 .
[0090] Specifically, in the process of subsequently forming an insulating layer, the protective layer 190 protects the channel stack structure 129 exposed by the first groove 107, thereby reducing the probability of consuming part of the channel layer 1022 in the process of subsequently forming an insulating layer, which means that the probability of forming an insulating layer on the side wall of the channel layer 1022 is greatly reduced, thereby improving the carrier mobility of the channel layer 1022.
[0091] In this embodiment, the step of forming the protective layer 190 includes: forming a protective material layer 191 on the side walls and top of the gate structure 104, and the bottom and side walls of the first groove 107; removing the protective material layer 191 on the side walls and top of the gate structure 104, and the bottom of the first groove 107, and using the protective material layer 191 on the side walls of the channel stack structure 129 exposed by the first groove 107 as the protective layer 190.
[0092] As an example, the process of forming the protective material layer 191 includes an atomic layer deposition process.
[0093] It should be noted that the protective material layer 191 at the bottom of the first groove 107 is removed to expose the top surface of the substrate 180 , thereby providing a process basis for subsequent modification treatment.
[0094] In this embodiment, the process of removing the sidewall and top of the gate structure 104 and the protective material layer 191 at the bottom of the first groove 107 includes a plasma dry etching process.
[0095] The plasma dry etching process has the characteristics of high controllability of etching direction. By using plasma to chemically and physically react with the side walls and top of the gate structure 104 and the protective material layer 191 at the bottom of the first groove 107, the purpose of completely removing the side walls and top of the gate structure 104 and the protective material layer 191 at the bottom of the first groove 107 can be achieved.
[0096] In this embodiment, the material of the protection layer 190 includes one or more of silicon nitride, silicon oxynitride and silicon carbide nitride.
[0097] Silicon nitride, silicon oxynitride and silicon carbide have an etching selectivity ratio with the material selected for the subsequently formed insulating layer, so that the insulating layer can be retained during the subsequent removal of the protective layer 190, which means that after a source-drain doping layer covering the sidewalls of the insulating layer is subsequently formed in the first groove 107, the insulating layer can reduce the probability of leakage current generated by the source-drain doping layer and the device gate structure 189 formed by the subsequent process technology through the substrate 100 under the channel layer 1022, thereby improving the performance of the semiconductor structure.
[0098] It should be noted that the direction parallel to the surface of the substrate 100 and perpendicular to the extension direction of the gate structure 104 is the lateral direction, and the lateral dimension of the protective layer 190 should not be too large or too small. If the lateral dimension of the protective layer 190 is too large, it is easy to cause the depth-to-width ratio of the remaining space of the first groove 107 to increase, resulting in a smaller process window for forming an insulating layer on the side wall of the substrate 100 exposed in the first groove 107, which increases the process difficulty of forming the insulating layer; if the lateral dimension of the protective layer 190 is too small, it is easy to cause the protective layer 190 to have an unclear protective effect on the channel layer 1022, which increases the probability of consuming part of the channel layer 1022 in the subsequent process of forming the insulating layer, which means that the probability of forming an insulating layer on the side wall of the channel layer 1022 is greatly increased, thereby increasing the probability of electrical failure of the semiconductor structure. For this reason, in this embodiment, the direction parallel to the surface of the substrate 100 and perpendicular to the extension direction of the gate structure 104 is the lateral direction, and the lateral dimension of the protective layer 190 is 2 nanometers to 4 nanometers.
[0099] refer to Figures 8 to 9 , an insulating layer 193 is formed on the sidewall of the substrate 100 exposed by the first groove 107 .
[0100] Specifically, an insulating layer 193 is formed on the side wall of the substrate 100 exposed by the first groove 107. The insulating layer 193 has an insulating effect. After a source-drain doping layer covering the side wall of the insulating layer 193 is subsequently formed in the first groove 107, the insulating layer 193 can reduce the probability of leakage current generated by the source-drain doping layer and the device gate structure 189 formed by subsequent process technology through the substrate 100 under the channel layer 1022, thereby improving the performance of the semiconductor structure.
[0101] In this embodiment, the step of forming the insulating layer 193 includes: modifying the substrate 100 exposed by the first groove 107 to form an insulating material layer 192; removing the insulating material layer 192 at the bottom of the first groove 107, and using the insulating material layer 192 located on the side wall of the first groove 107 as the insulating layer 193.
[0102] Specifically, by modifying the substrate 100 exposed by the first groove 107, part of the substrate 100 is converted into an insulating material layer 192. Compared with the solution of depositing the insulating material layer 192 on the surface of the substrate 100 exposed by the first groove 107 using a deposition process, during the modification process, there is no need to consider the influence of the aspect ratio of the first groove 107 on the formation quality of the insulating material layer 192, thereby improving the formation quality of the insulating material layer 192, reducing the probability of generating voids in the insulating material layer 192, and thereby improving the performance of the semiconductor structure.
[0103] In this embodiment, the process of modifying the substrate 100 exposed by the first groove 107 includes a thermal oxidation process.
[0104] Specifically, the thermal oxidation process has the characteristics of low process cost and high controllability. The substrate 100 at the bottom and side walls of the first groove 107 is modified by the thermal oxidation process, and the substrate 100 at the bottom and side walls of the first groove 107 can be oxidized into an insulating material layer 192.
[0105] In this embodiment, the process gas of the thermal oxidation process includes oxygen.
[0106] Specifically, the thermal oxidation process is a high-temperature process. At high temperature, oxygen atoms in the oxygen diffuse into the substrate 100 at the bottom and side walls of the first groove 107, and chemically react with silicon atoms in the substrate 100, thereby converting the portion of the substrate 100 exposed by the first groove 107 into an insulating material layer 192.
[0107] It should be noted that the process temperature of the thermal oxidation process should not be too high or too low. If the process temperature of the thermal oxidation process is too high, it is easy to cause the protrusion 181 under the gate structure 104 to be completely oxidized, thereby affecting the electrical performance of the semiconductor structure; if the process temperature of the thermal oxidation process is too low, it is easy to cause the process time of forming the insulating layer 193 to be too long, increasing the process cost. For this reason, in this embodiment, the process temperature of the thermal oxidation process is 700°C to 850°C.
[0108] It should also be noted that the process time of the thermal oxidation process should not be too long or too short. If the process time of the thermal oxidation process is too long, it is easy to cause the substrate 100 at the bottom and sidewalls of the first groove 107 to be consumed too much, which means that too much insulating material layer 192 is formed on the surface of the substrate 100 exposed by the first groove 107, increasing the process difficulty of removing the insulating material layer 192 at the bottom of the first groove 107; if the process time of the thermal oxidation process is too short, it is easy to cause the substrate 100 at the bottom and sidewalls of the first groove 107 to be consumed too little, which means that too little insulating layer 193 is formed on the sidewalls of the substrate 100 exposed by the first groove 107. After the source-drain doping layer covering the sidewalls of the insulating layer 193 is subsequently formed in the first groove 107, the insulating effect of the insulating layer 193 is not good, which increases the probability that the source-drain doping layer and the device gate structure 189 formed by the subsequent process technology will generate leakage current through the substrate 100 below the channel layer 1022, thereby improving the performance of the semiconductor structure. Therefore, in this embodiment, the process time of the thermal oxidation process is 10 minutes to 30 minutes.
[0109] Specifically, the gas flow rate of the thermal oxidation process should not be too high or too low. If the gas flow rate of the thermal oxidation process is too large, it is easy to cause the substrate 100 at the bottom and sidewall of the first groove 107 to be consumed too much, which means that too much insulating material layer 192 is formed on the surface of the substrate 100 exposed by the first groove 107, which increases the process difficulty of removing the insulating material layer 192 at the bottom of the first groove 107; if the gas flow rate of the thermal oxidation process is too small, it is easy to cause the substrate 100 at the bottom and sidewall of the first groove 107 to be consumed too little, which means that too little insulating layer 193 is formed on the sidewall of the substrate 100 exposed by the first groove 107. After the source-drain doping layer covering the sidewall of the insulating layer 193 is subsequently formed in the first groove 107, the insulating effect of the insulating layer 193 is not good, which increases the probability that the source-drain doping layer and the device gate structure 189 formed by the subsequent process generate leakage current through the substrate 100 under the channel layer 1022, thereby improving the performance of the semiconductor structure. Therefore, in this embodiment, the gas flow rate of the thermal oxidation process is 0.5 slm to 10 slm.
[0110] In this embodiment, the process of removing the insulating material layer 192 at the bottom of the first groove 107 includes a dry etching process.
[0111] It should be noted that the dry etching process is an anisotropic dry etching process. The anisotropic dry etching process has the characteristics of anisotropic etching. Its longitudinal etching rate is greater than the lateral etching rate, and the anisotropic dry etching process has better profile controllability, which is beneficial to improving the profile morphology quality of the insulating material layer 192 on the side wall of the first groove 107. In addition, the selected anisotropic dry etching process is beneficial to achieve a higher etching selectivity, thereby reducing the probability of mis-etching other film layers.
[0112] It should also be noted that, with the direction parallel to the substrate 100 and perpendicular to the extension direction of the gate structure 104 as the lateral direction, the lateral dimension of the insulating layer 193 should not be too large or too small. If the lateral dimension of the insulating layer 193 is too large, it is easy to cause the remaining space of the protrusion 181 below the gate structure 104 to become smaller, which means the spatial area of the effective channel region, thereby affecting the electrical performance of the semiconductor structure; if the lateral dimension of the insulating layer 193 is too small, after the source-drain doping layer covering the sidewall of the insulating layer 193 is subsequently formed in the first groove 107, the insulating effect of the insulating layer 193 is not good, which increases the probability of leakage current generated by the source-drain doping layer and the device gate structure 189 formed by the subsequent process through the substrate 100 below the channel layer 1022, thereby improving the performance of the semiconductor structure. For this reason, in this embodiment, with the direction parallel to the substrate 100 and perpendicular to the extension direction of the gate structure 104 as the lateral direction, the lateral dimension of the insulating layer 193 is 2 nanometers to 6 nanometers.
[0113] In this embodiment, the material of the insulating layer 193 includes one or more of silicon oxide, silicon oxynitride and silicon carbide nitride.
[0114] Silicon oxide, silicon oxynitride and silicon nitride carbide are all dielectric materials with good insulation properties. They can reduce the probability of leakage current generated by the source and drain doping layers and the device gate structure 189 formed by subsequent process technology through the substrate 100 under the channel layer 1022. At the same time, silicon oxide, silicon oxynitride and silicon nitride carbide have an etching selectivity ratio with the material selected for the protective layer 190. In the subsequent process of removing the protective layer 190, the probability of the insulating layer 193 being etched away is reduced.
[0115] In other embodiments, the step of forming the insulating layer may also include: performing deposition processing on the bottom and side walls of the first groove to form an insulating material layer; removing the insulating material layer at the bottom of the first groove, and using the insulating material layer on the side walls of the first groove as the insulating layer.
[0116] The process of performing deposition treatment on the bottom and sidewall of the first groove includes an atomic layer deposition process or a chemical vapor deposition process.
[0117] refer to Fig.10 After forming the insulating layer 193 and before subsequently forming the source-drain doping layer, the method further includes: removing the protective layer 190 .
[0118] It should be noted that, by removing the protection layer 190 , the sidewall of the channel stack structure 129 is exposed, which facilitates the subsequent etching of the exposed portion of the sacrificial layer 1021 on the sidewall of the first groove 107 .
[0119] It should also be noted that by removing the protective layer 190 after forming the anti-punch-through layer, the probability of doped ions entering the channel layer 1022 during the formation of the anti-punch-through layer is reduced, thereby reducing the risk of affecting the carrier mobility of the channel layer 1022, thereby improving the performance of the semiconductor structure.
[0120] In this embodiment, the process of removing the protective layer 190 includes a wet etching process.
[0121] refer to Fig.11 After forming the insulating layer 193 and before subsequently forming the source-drain doping layer, the method further includes: transversely etching the portion of the sacrificial layer 1021 exposed by the sidewall of the first groove 107 in a direction parallel to the substrate 100 and perpendicular to the extension direction of the gate structure 104 to form a second groove (not shown).
[0122] The second groove provides a spatial position for the subsequent formation of an inner wall layer.
[0123] As an example, the second groove is surrounded by the adjacent channel layer 1022 and the remaining sacrificial layer 1021 , or the second groove is surrounded by the substrate 100 , the channel layer 1022 adjacent to the substrate 100 , and the remaining sacrificial layer 1021 .
[0124] In this embodiment, the process of laterally etching the exposed portion of the sacrificial layer 1021 on the sidewall of the first groove 107 to form the second groove includes a wet etching process.
[0125] The wet etching process is an isotropic etching process, so that the sacrificial layer 1021 can be etched along a direction parallel to the substrate 100 and perpendicular to the extension direction of the gate structure 104, and the wet etching process can easily achieve a larger etching selectivity ratio, which is beneficial to reduce the difficulty of etching the sacrificial layer 1021 and reduce the probability of damage to other film layer structures.
[0126] In this embodiment, the material of the sacrificial layer 1021 is SiGe, the material of the channel layer 1022 is Si, and the exposed sacrificial layer 1021 is wet-etched by HCl vapor. The etching rate of HCl vapor on SiGe material is much greater than the etching rate on Si material, so the use of HCl vapor to etch the exposed part of the sacrificial layer 1021 on the sidewall of the first groove 107 can effectively reduce the probability of damage to the channel layer 1022.
[0127] In other embodiments, when the material of the channel layer is SiGe and the material of the sacrificial layer is Si, the etching solution used in the wet etching process is a tetramethylammonium hydroxide (TMAH) solution. The difference between the etching rate of the tetramethylammonium hydroxide solution on the Si material and the etching rate on the SiGe material is large, so the use of the tetramethylammonium hydroxide solution to etch the sacrificial layer can also effectively reduce the probability of the channel layer being damaged.
[0128] Continue to refer Fig.11 , an inner wall layer 196 is formed in the second groove.
[0129] Specifically, the inner wall layer 196 is located between the subsequently formed source-drain doped layer and the device gate structure 189 . The inner wall layer 196 can isolate the source-drain doped layer and the device gate structure 189 , which is beneficial to reducing the parasitic capacitance between the source-drain doped layer and the device gate structure 189 .
[0130] In this embodiment, the step of forming an inner wall layer 196 in the second groove includes: forming an inner wall material layer (not shown) on the side wall and bottom of the first groove 107, the top and side wall of the gate structure 104, and the second groove; removing the inner wall material layer at the bottom and side wall of the first groove 107, and the inner wall material layer at the top and side wall of the gate structure 104, and the remaining inner wall material layer located in the second groove serves as the inner wall layer 196.
[0131] In this embodiment, the process of forming the inner wall material layer includes an atomic layer deposition process or a chemical vapor deposition process.
[0132] Taking the atomic layer deposition process as an example, the atomic layer deposition process has good film layer step coverage, reducing the risk of voids in the inner wall material layer, thereby improving the performance of the semiconductor structure.
[0133] In this embodiment, the material of the inner wall layer 196 includes one or more of silicon nitride, silicon oxide and silicon oxynitride.
[0134] Specifically, silicon nitride, silicon oxide, and silicon oxynitride are all dielectric materials that can electrically isolate the device gate structure 189 and the source-drain doping layer that are subsequently formed.
[0135] refer to Fig.12 , a source-drain doped layer 197 is formed in the first groove 107 to cover the sidewall of the insulating layer 193 .
[0136] Specifically, the source-drain doping layer 197 is used as the source region and the drain region of the transistor.
[0137] In this embodiment, the process of forming the source-drain doping layer 197 includes an epitaxial process.
[0138] Specifically, the epitaxial process has the characteristics of fast growth rate and good filling performance. By using the epitaxial process to form the source-drain doped layer 197, the risk of generating voids in the source-drain doped layer 197 is reduced, and the performance of the source-drain doped layer 197 itself is improved.
[0139] refer to Fig.13 After forming the source-drain doping layer 197 , the method for forming the semiconductor structure further includes: forming an interlayer dielectric layer 198 on the top of the source-drain doping layer 197 , wherein the interlayer dielectric layer 198 covers the sidewalls of the gate structure 104 .
[0140] The interlayer dielectric layer 198 is used to achieve electrical isolation between adjacent devices.
[0141] In this embodiment, the material of the interlayer dielectric layer 198 is silicon oxide.
[0142] In this embodiment, the step of forming the interlayer dielectric layer 198 includes: forming a dielectric material layer (not shown) on the substrate 100 on the side wall of the gate structure 104, and the dielectric material layer also covers the top of the gate structure 104; removing the dielectric material layer above the top of the gate structure 104, and the remaining dielectric material layer serves as the interlayer dielectric layer 198.
[0143] refer to Fig.14 , the gate structure 104 is removed, and a gate opening 183 is formed in the interlayer dielectric layer 198 .
[0144] Specifically, the gate opening 183 provides a process window for the subsequent formation and removal of the sacrificial layer 1021 , and also provides a spatial position for the subsequent formation of the device gate structure 189 .
[0145] In this embodiment, the process of removing the gate structure 104 includes a dry etching process.
[0146] In this embodiment, before removing the gate structure 104 , the method for forming the semiconductor structure further includes: removing the gate mask layer.
[0147] Specifically, the gate mask layer is removed to expose the top of the gate structure 104 in preparation for removing the gate structure 104 .
[0148] Continue to refer Fig.14 , the sacrificial layer 1021 exposed by the gate opening 183 is removed, and a through groove 187 connected to the gate opening 183 is formed under the channel layer 1022 .
[0149] Specifically, the sacrificial layer 1021 is removed to form the through groove 187 , so as to provide a spatial position for the subsequent formation of the device gate structure 189 .
[0150] In this embodiment, a wet etching process is used to remove the sacrificial layer 1021. Specifically, the material of the channel layer 1022 is Si, and the material of the sacrificial layer 1021 is SiGe, so the sacrificial layer 1021 exposed by the gate opening 183 is removed by HCl vapor, and the etching rate of the sacrificial layer 1021 by the wet etching process is much greater than the etching rate of the channel layer 1022 and the protrusion 181.
[0151] The sacrificial layer 1021 is removed after the source-drain doped layer 197 is formed. Therefore, after removing the sacrificial layer 1021, the two ends of the channel layer 1022 are connected to the source-drain doped layer 197 along the extension direction of the protrusion 181, and are suspended in the gate opening 183, thereby providing a basis for the subsequent device gate structure 189 to surround the channel layer 1022.
[0152] After the sacrificial layer 1021 is removed, the channel layers 1022 are arranged at intervals, and the remaining channel layers 1022 constitute a channel structure layer, which is located on the protrusion 181 and is arranged at intervals from the protrusion 181 .
[0153] refer to Fig.15 A device gate structure 189 is formed in the gate opening 183 and the through groove 187 , and the device gate structure 189 surrounds the channel layer 1022 .
[0154] The device gate structure 189 is used to control the opening and closing of the conductive channel when the device is working.
[0155] Specifically, the device gate structure 189 is a metal gate structure.
[0156] In this embodiment, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.
[0157] Specifically, the gate dielectric layer includes a gate oxide layer that conformally covers a portion of the top, a portion of the sidewall, and a portion of the bottom of the channel layer 1022, and a high-k gate dielectric layer that conformally covers the gate oxide layer. The material of the high-k gate dielectric layer is a high-k dielectric material, which refers to a dielectric material having a relative dielectric constant greater than the relative dielectric constant of silicon oxide.
[0158] It should be noted that the gate dielectric layer also conformally covers a portion of the top of the isolation layer.
[0159] The gate electrode layer is used for subsequent electrical connection with an external structure. The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC. Specifically, the gate electrode layer may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer may also include only the work function layer.
[0160] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A semiconductor structure, characterized in that: include: substrate; A channel structure layer is suspended on the top of the substrate, and the channel structure layer includes one or more channel layers spaced apart in the longitudinal direction; A device gate structure, located on the substrate and spanning the channel structure layer, the device gate structure covering a portion of the top, a portion of the sidewall and a portion of the bottom of the channel layer; Source-drain doping layers are located in the channel structure layer and part of the substrate on both sides of the gate structure of the device; An insulating layer, located between the sidewall of the source-drain doped layer and the substrate; An inner wall layer, located between the side wall of the device gate structure and the source-drain doping layer directly below the channel layer; The interlayer dielectric layer is located on the top of the source-drain doped layer, and the interlayer dielectric layer covers the sidewalls of the device gate structure.
2. The semiconductor structure according to claim 1, wherein: The material of the inner wall layer includes one or more of silicon nitride, silicon oxide and silicon oxynitride.
3. The semiconductor structure according to claim 1, wherein: The material of the insulating layer includes one or more of silicon oxide, silicon oxynitride and silicon carbide nitride.
4. The semiconductor structure according to claim 1, wherein: With the direction parallel to the substrate and perpendicular to the extension direction of the device gate structure as the lateral direction, the lateral dimension of the insulating layer is 2 nanometers to 6 nanometers.
5. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, on which a channel stack structure is formed, the channel stack structure comprising one or more channel stacks stacked in sequence in a longitudinal direction, the channel stack comprising a sacrificial layer and a channel layer located on the sacrificial layer, and a gate structure spanning the channel stack structure is formed on the substrate, the gate structure covering a portion of the top and a portion of the sidewall of the channel stack structure; forming a first groove in the channel stack structure and a portion of the substrate on both sides of the gate structure; forming an insulating layer on the sidewall of the substrate exposed by the first groove; A source-drain doping layer is formed in the first groove to cover the sidewall of the insulating layer.
6. The method for forming a semiconductor structure according to claim 5, wherein: The step of forming the first groove includes: forming a hard mask layer on the top of the gate structure; patterning the channel stack structure and part of the substrate using the hard mask layer as a mask to form a first groove in the channel stack structure and part of the substrate; and removing the hard mask layer.
7. The method for forming a semiconductor structure according to claim 5, wherein: After forming the first groove and before forming the insulating layer, the method further includes: forming a protection layer on the sidewall of the channel stack structure exposed by the first groove; After forming the insulating layer and before forming the source-drain doping layer, the method further includes: removing the protective layer.
8. The method for forming a semiconductor structure according to claim 7, wherein: The step of forming the protective layer includes: forming a protective material layer on the sidewalls and top of the gate structure, and the bottom and sidewalls of the first groove; removing the protective material layer on the sidewalls and top of the gate structure, and the bottom of the first groove, and using the protective material layer on the sidewalls of the channel stack structure exposed by the first groove as the protective layer.
9. The method for forming a semiconductor structure according to claim 8, wherein: The process of removing the sidewall and top of the gate structure and the protective material layer at the bottom of the first groove includes a plasma dry etching process.
10. The method for forming a semiconductor structure according to claim 7, wherein: The material of the protective layer includes one or more of silicon nitride, silicon oxynitride and silicon carbide nitride.
11. The method for forming a semiconductor structure according to claim 7, wherein: The direction parallel to the substrate surface and perpendicular to the extension direction of the gate structure is a lateral direction, and the lateral dimension of the protection layer is 2 nanometers to 4 nanometers.
12. The method for forming a semiconductor structure according to claim 5, wherein: The step of forming the insulating layer includes: performing a modification process on the substrate exposed by the first groove to form an insulating material layer; removing the insulating material layer at the bottom of the first groove, and using the insulating material layer located on the side wall of the first groove as the insulating layer; or, The bottom and sidewalls of the first groove are deposited to form an insulating material layer; the insulating material layer at the bottom of the first groove is removed, and the insulating material layer located on the sidewalls of the first groove is used as the insulating layer.
13. The method for forming a semiconductor structure according to claim 12, wherein: The process of modifying the substrate exposed by the first groove includes a thermal oxidation process.
14. The method for forming a semiconductor structure according to claim 13, wherein: The process parameters of the thermal oxidation process include: the process gas includes oxygen; the process temperature is 700° C. to 850° C.; the process time is 10 min to 30 min; and the gas flow rate is 0.5 slm to 10 slm.
15. The method for forming a semiconductor structure according to claim 12, wherein: The process of removing the insulating material layer at the bottom of the first groove includes a dry etching process.
16. The method for forming a semiconductor structure according to claim 5, wherein: After forming the insulating layer and before forming the source-drain doping layer, the method further includes: laterally etching a portion of the sacrificial layer exposed by the sidewall of the first groove in a direction parallel to the substrate and perpendicular to the extension direction of the gate structure to form a second groove; forming an inner wall layer in the second groove; After forming the source-drain doping layer, the method for forming the semiconductor structure further includes: forming an interlayer dielectric layer on top of the source-drain doping layer, wherein the interlayer dielectric layer covers the sidewall of the gate structure; removing the gate structure and forming a gate opening in the interlayer dielectric layer; removing the sacrificial layer exposed by the gate opening, and forming a through groove communicating with the gate opening under the channel layer; A device gate structure is formed in the gate opening and the through-groove, and the device gate structure surrounds the channel layer.