Gallium oxide based power device with dielectric layer electric field shield ring and method of fabrication thereof

Abstract

The application discloses a gallium oxide-based power device with a dielectric layer electric field shielding ring and a preparation method thereof, and relates to the field of semiconductor devices. The device comprises a first electrode layer, a gallium oxide substrate, a gallium oxide epitaxial layer and a first dielectric layer which are sequentially stacked from bottom to top; further comprising: a p-type semiconductor layer continuously located on the surface of the gallium oxide epitaxial layer and the partial surface of the first dielectric layer, the part of the p-type semiconductor layer located on the partial surface of the first dielectric layer is a first field plate; a p-type semiconductor shielding ring located on the surface of the first dielectric layer and spaced apart from the first field plate; a second dielectric layer continuously located on the surface of the first dielectric layer, the surface of the p-type semiconductor shielding ring and the partial surface of the first field plate; a second electrode layer continuously located on the surface of the p-type semiconductor layer and the partial surface of the second dielectric layer, the part of the second electrode layer located on the partial surface of the second dielectric layer is a second field plate. The device provided by the application has a higher breakdown electric field and better voltage resistance performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and more particularly to gallium oxide-based power devices with dielectric layer electric field shielding rings and their fabrication methods. Background Technology

[0002] Gallium oxide (Ga2O3) materials can significantly improve the performance of power devices. For example, its ultra-high critical breakdown field strength of approximately 8 MV / cm greatly enhances the breakdown voltage of power devices; its ultra-wide bandgap of approximately 4.8 eV improves the reliability of power devices under extreme environments such as high temperature and strong radiation; and melt-grown substrate materials can reduce the material cost of power devices. However, due to the lack of effective p-type doping schemes for gallium oxide, current gallium oxide-based power devices cannot utilize the mature termination technologies found in silicon (Si)-based and SiC-based power devices to improve device breakdown voltage. Furthermore, the ultra-high critical breakdown field strength and large dielectric constant (k) of gallium oxide can lead to extremely high electric fields in the dielectric layer of the device, resulting in premature breakdown of the dielectric layer and limiting the optimization of device breakdown voltage. Therefore, based on the unique material properties of gallium oxide, developing suitable termination technologies and fabrication processes for gallium oxide-based power devices is of great significance for improving device performance.

[0003] Therefore, existing technologies still need to be improved and developed. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of this invention is to provide a gallium oxide-based power device with a dielectric layer electric field shielding ring and a method for fabricating the same, with the aim of providing a termination structure suitable for gallium oxide-based power devices so that the gallium oxide-based power devices have a high breakdown voltage.

[0005] The technical solution of the present invention is as follows:

[0006] In a first aspect, the present invention provides a gallium oxide-based power device having a dielectric layer electric field shielding ring, wherein the gallium oxide-based power device having a dielectric layer electric field shielding ring comprises a first electrode layer, a gallium oxide substrate, and a gallium oxide epitaxial layer stacked sequentially from bottom to top;

[0007] The gallium oxide-based power device with a dielectric layer electric field shielding ring further includes:

[0008] The first dielectric layer is located on the surface of the gallium oxide epitaxial layer;

[0009] A p-type semiconductor layer is continuously located on the surface of the gallium oxide epitaxial layer and on a portion of the surface of the first dielectric layer. The portion of the p-type semiconductor layer located on the portion of the first dielectric layer is the first field plate.

[0010] A p-type semiconductor shielding ring is located on the surface of the first dielectric layer and is spaced apart from the first field plate;

[0011] The second dielectric layer is continuously located on the surface of the first dielectric layer, the surface of the p-type semiconductor shielding ring, and a portion of the surface of the first field plate.

[0012] The second electrode layer is continuously located on the surface of the p-type semiconductor layer and on a portion of the surface of the second dielectric layer. The portion of the second electrode layer located on the portion of the surface of the second dielectric layer is the second field plate.

[0013] Optionally, the thickness of the gallium oxide substrate is 50–650 μm;

[0014] The gallium oxide substrate is a highly doped n-type gallium oxide substrate with a doping concentration of 10. 18 ~10 20 cm -3 ;

[0015] The thickness of the gallium oxide epitaxial layer is 2–20 μm;

[0016] The gallium oxide epitaxial layer is a lightly doped n-type gallium oxide epitaxial layer with a doping concentration of 10. 15 ~10 17 cm -3 .

[0017] Optionally, the thickness of the first dielectric layer is 100 nm to 1 μm; the material of the first dielectric layer includes at least one of silicon oxide, silicon nitride, aluminum oxide, and hafnium dioxide.

[0018] The thickness of the second dielectric layer is 300 nm to 2 μm; the material of the second dielectric layer includes at least one of silicon oxide, silicon nitride, aluminum oxide and hafnium dioxide.

[0019] Optionally, the material of the first electrode layer includes at least one of Ti, Ni, Ag and Au;

[0020] The materials of the second electrode layer include Ni, Mo, W, Pt, and PtO. x At least one of Al, Au and Ag.

[0021] Optionally, the thickness of the p-type semiconductor layer is 100–600 nm; the p-type semiconductor layer includes at least one of p-type NiO, p-type Cu2O, p-type gallium oxide, and p-type diamond.

[0022] The thickness of the p-type semiconductor shielding ring is 100-600 nm; the p-type semiconductor shielding ring includes at least one of p-type NiO, p-type Cu2O, p-type gallium oxide and p-type diamond.

[0023] Optionally, the distance between the first field plate and the p-type semiconductor shielding ring is 2 to 10 μm.

[0024] Optionally, when the width of the p-type semiconductor layer is the same as the width of the first dielectric layer and the width of the p-type semiconductor shielding ring in the first direction of the horizontal plane, then in the direction perpendicular to the first direction on the horizontal plane:

[0025] The width of the first field plate is 3–20 μm;

[0026] The width of the p-type semiconductor shielding ring is 3–10 μm.

[0027] Optionally, the projection of the second electrode layer on the gallium oxide epitaxial layer overlaps the projection of the p-type semiconductor layer on the gallium oxide epitaxial layer; or, the projection of the second electrode layer on the gallium oxide epitaxial layer coincides with the projection of the p-type semiconductor layer on the gallium oxide epitaxial layer.

[0028] Optionally, the projection of the end of the second field plate away from the first field plate onto the gallium oxide epitaxial layer is located in the projection of the p-type semiconductor shielding ring onto the gallium oxide epitaxial layer;

[0029] The gallium oxide-based power device with a dielectric layer electric field shielding ring further includes:

[0030] A passivation layer is continuously located on the surface of the second dielectric layer and a portion of the surface of the second electrode layer.

[0031] A second aspect of the present invention provides a method for fabricating a gallium oxide-based power device with a dielectric layer electric field shielding ring as described above, comprising the following steps:

[0032] Provide gallium oxide substrate;

[0033] A gallium oxide epitaxial layer is formed on the surface of the gallium oxide substrate;

[0034] A first dielectric layer is formed on the surface of the gallium oxide epitaxial layer;

[0035] A p-type semiconductor layer is formed on the surface of the gallium oxide epitaxial layer and on a portion of the surface of the first dielectric layer, and the portion of the p-type semiconductor layer located on the partial surface of the first dielectric layer is the first field plate.

[0036] A p-type semiconductor shielding ring is formed on the surface of the first dielectric layer, spaced apart from the first field plate;

[0037] A second dielectric layer is formed on the surface of the first dielectric layer, on the surface of the p-type semiconductor shielding ring, and on a portion of the surface of the first field plate;

[0038] A second electrode layer is formed on the surface of the p-type semiconductor layer and on a portion of the surface of the second dielectric layer, and the portion of the second electrode layer located on the partial surface of the second dielectric layer is the second field plate.

[0039] A first electrode layer is formed on the side of the gallium oxide substrate away from the gallium oxide epitaxial layer to obtain the gallium oxide-based power device with a dielectric layer electric field shielding ring.

[0040] Beneficial Effects: This invention introduces a double-layer field plate structure into gallium oxide-based power devices. By extending the p-type semiconductor layer to the surface of the first dielectric layer, a first field plate structure is formed to suppress electric field concentration at the interface edge between the p-type semiconductor layer and the gallium oxide epitaxial layer, thereby reducing the electric field peak value. By extending the second electrode layer to the surface of the second dielectric layer, a second field plate structure is formed, which can suppress electric field concentration on the surface of the first dielectric layer and the gallium oxide epitaxial layer below the edge of the first field plate structure. Therefore, the double-layer field plate structure can optimize the terminal electric field distribution, reduce the electric field peak value, and improve the device breakdown voltage. Furthermore, by introducing a p-type semiconductor shielding ring structure, the electric field peak value within the dielectric layer can be effectively reduced, suppressing premature breakdown of the dielectric layer and further improving the device breakdown voltage. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the structure of a gallium oxide-based power device with a dielectric layer electric field shielding ring in an embodiment of the present invention.

[0042] Figure 2 This is a schematic diagram of the fabrication process of a gallium oxide-based power device with a dielectric layer electric field shielding ring in an embodiment of the present invention. (a) is a schematic diagram of forming a gallium oxide epitaxial layer on the surface of a gallium oxide substrate. (b) is a schematic diagram of forming a first dielectric layer precursor layer on the surface of the gallium oxide epitaxial layer. (c) is a schematic diagram of etching the first dielectric layer precursor layer to obtain the first dielectric layer. (d) is a schematic diagram of forming a p-type semiconductor layer on the surface of the gallium oxide epitaxial layer and a portion of the surface of the first dielectric layer, and forming a p-type semiconductor shielding ring spaced apart from the first field plate on the surface of the first dielectric layer. (e) is a schematic diagram of forming a second dielectric layer on the surface of the first dielectric layer, the surface of the p-type semiconductor shielding ring, and a portion of the surface of the first field plate. (f) is a schematic diagram of forming a second electrode layer on the surface of the p-type semiconductor layer and a portion of the surface of the second dielectric layer. (g) is a schematic diagram of forming a passivation layer on the surface of the second dielectric layer and a portion of the surface of the second electrode layer. (h) is a schematic diagram of forming a first electrode layer on the side of the gallium oxide substrate away from the gallium oxide epitaxial layer.

[0043] Figure 3 This is a schematic diagram of a gallium oxide-based power device with a conventional single-field-plate structure terminal.

[0044] Figure 4 This is a schematic diagram of a gallium oxide-based power device with a double-field plate structure.

[0045] Figure 5 The graphs show the surface electric field distribution of gallium oxide-based power devices with conventional single-field plate structure terminals, gallium oxide-based power devices with dual-field plate structure terminals, and gallium oxide-based power devices with dielectric layer electric field shielding rings in Example 1.

[0046] Figure 6 The figures show the simulation results of two-dimensional electric field distribution and maximum electric field location of gallium oxide-based power devices with different structures. Among them, (a) is a gallium oxide-based power device with a conventional single-field plate structure terminal, (b) is a gallium oxide-based power device with a double-field plate structure, and (c) is a gallium oxide-based power device with a dielectric layer electric field shielding ring in Example 1.

[0047] The labels in the attached diagram:

[0048] 1. First electrode layer; 2. Gallium oxide substrate; 3. Gallium oxide epitaxial layer; 4. First dielectric layer; 4'. First dielectric layer precursor layer; 5. p-type semiconductor layer; 51. First field plate; 52. Second portion of p-type semiconductor layer; 6. p-type semiconductor shielding ring; 7. Second dielectric layer; 8. Second electrode layer; 81. Second field plate; 82. Second portion of second electrode layer; 9. Passivation layer. Detailed Implementation

[0049] This invention provides a gallium oxide-based power device with a dielectric layer electric field shielding ring and its fabrication method. To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention is further described in detail below. It should be understood that the specific embodiments described herein are only for explaining the invention and are not intended to limit the invention.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0051] The terms used in this document, such as “vertical,” “horizontal,” “up,” “down,” “left,” “right,” and similar expressions, are for illustrative purposes only and do not represent the only possible implementation.

[0052] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0053] If the embodiments of the present invention involve descriptions such as "first" or "second", such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated.

[0054] This invention provides a gallium oxide-based power device with a dielectric layer electric field shielding ring, wherein, as shown in the embodiments of the present invention, a gallium oxide-based power device is provided. Figure 1 As shown, the gallium oxide-based power device with a dielectric layer electric field shielding ring includes a first electrode layer 1, a gallium oxide substrate 2, and a gallium oxide epitaxial layer 3 stacked sequentially from bottom to top;

[0055] The gallium oxide-based power device with a dielectric layer electric field shielding ring further includes:

[0056] The first dielectric layer 4 is located on the surface of the gallium oxide epitaxial layer 3;

[0057] p-type semiconductor layer 5 is continuously located on the surface of the gallium oxide epitaxial layer 3 and on a portion of the surface of the first dielectric layer 4. The portion of the p-type semiconductor layer 5 located on the portion of the surface of the first dielectric layer 4 is the first field plate 51.

[0058] p-type semiconductor shielding ring 6 is located on a portion of the surface of the first dielectric layer 4 and is spaced apart from the first field plate 51;

[0059] The second dielectric layer 7 is continuously located on the surface of the first dielectric layer 4, the surface of the p-type semiconductor shielding ring 6, and a portion of the surface of the first field plate 51.

[0060] The second electrode layer 8 is continuously located on the surface of the p-type semiconductor layer 5 and a portion of the surface of the second dielectric layer 7. The portion of the second electrode layer 8 located on the portion of the surface of the second dielectric layer 7 is the second field plate 81.

[0061] This invention introduces a dual-layer field plate structure into gallium oxide-based power devices. By extending a p-type semiconductor layer onto the surface of a first dielectric layer, a first field plate structure is formed to suppress electric field concentration at the interface edge between the p-type semiconductor layer and the gallium oxide epitaxial layer, thereby reducing the peak electric field. By extending a second electrode layer onto the surface of a second dielectric layer, a second field plate structure is formed, which can suppress electric field concentration on the surface of the first dielectric layer and the gallium oxide epitaxial layer below the edge of the first field plate structure. Therefore, the dual-layer field plate structure can optimize the terminal electric field distribution, reduce the peak electric field, and improve the device breakdown voltage. Furthermore, by introducing a p-type semiconductor shielding ring structure to shield the high electric field in the dielectric layer, the peak electric field within the dielectric layer can be effectively reduced, suppressing premature breakdown of the dielectric layer and further improving the device breakdown voltage.

[0062] In embodiments of the present invention, such as Figure 1 As shown, the p-type semiconductor layer 5 is continuously located on the surface of the gallium oxide epitaxial layer 3 and a portion of the surface of the first dielectric layer 4. That is, the p-type semiconductor layer 5 comprises two parts: a first part and a second part. The first part of the p-type semiconductor layer, i.e., the first field plate 51, is located on a portion of the surface of the first dielectric layer 4 (in this invention, "partial surface" refers to a portion, not the entire surface). The second part 52 of the p-type semiconductor layer is located on the surface of the gallium oxide epitaxial layer 3. Specifically, in the left-right direction, the second part 52 of the p-type semiconductor layer is connected to the first dielectric layer 4.

[0063] The second electrode layer 8 is continuously located on the surface of the p-type semiconductor layer 5 and a portion of the surface of the second dielectric layer 7. That is, the second electrode layer 8 comprises two parts: a first part and a second part. The first part of the second electrode layer, i.e., the second field plate 81, is located on a portion of the surface of the second dielectric layer 7, and the second part 82 of the second electrode layer is located on the surface of the p-type semiconductor layer 5. Specifically, in the left-right direction, the second part 82 of the second electrode layer is in contact with the second dielectric layer 7.

[0064] In some embodiments, the thickness of the gallium oxide substrate is 50–650 μm, for example, it can be 50 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, 600 μm or 650 μm.

[0065] In some embodiments, the gallium oxide substrate is a highly doped n-type gallium oxide substrate with a doping concentration (i.e., electron concentration) of 10. 18 ~10 20 cm -3 The doping element is at least one of Si and Sn.

[0066] In some embodiments, the thickness of the gallium oxide epitaxial layer is 2 to 20 μm, for example, it can be 2 μm, 3 μm, 5 μm, 8 μm, 10 μm, 12 μm, 15 μm, 18 μm or 20 μm.

[0067] In some embodiments, the gallium oxide epitaxial layer is a lightly doped n-type gallium oxide epitaxial layer with a doping concentration (i.e., electron concentration) of 10. 15 ~10 17 cm -3 The doping element is at least one of Si and Sn.

[0068] In some embodiments, the thickness of the first dielectric layer is 100 nm to 1 μm, for example, it can be 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm or 1 μm, etc., with a thickness of such... Figure 1 Unless otherwise specified, the thicknesses shown in the vertical direction are all as described above in this invention. Figure 1 The thickness is shown in the vertical direction.

[0069] In some embodiments, the material of the first dielectric layer includes at least one of silicon oxide, silicon nitride, aluminum oxide, and hafnium dioxide, but is not limited thereto.

[0070] In some embodiments, the thickness of the second dielectric layer is 300 nm to 2 μm (i.e., the thickness of each part of the second dielectric layer is within this range), for example, it can be 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1 μm, 1.2 μm, 1.5 μm, 1.8 μm or 2 μm, etc.

[0071] In some embodiments, the material of the second dielectric layer includes at least one of silicon oxide, silicon nitride, aluminum oxide, and hafnium dioxide, but is not limited thereto.

[0072] In some embodiments, the material of the first electrode layer includes at least one of Ti, Ni, Ag, and Au, but is not limited thereto. In some specific embodiments, the first electrode layer is composed of a Ti layer and an Au layer stacked together, or the first electrode layer is composed of a Ti layer and an Ag layer stacked together, or the first electrode layer is composed of a Ti layer, a Ni layer, and an Ag layer stacked together.

[0073] In some embodiments, the thickness of the first electrode layer is 250 nm to 2 μm. For example, it can be 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm, 1.9 μm, or 2 μm, etc.

[0074] In some embodiments, the material of the second electrode layer includes Ni, Mo, W, Pt, and PtO. x At least one of Al, Au, and Ag. In some specific embodiments, the second electrode layer is composed of a stacked Ni layer and an Al layer; further, the Ni layer can be replaced by a Mo layer, a W layer, a Pt layer, or a PtO layer. x The Al layer can be replaced with an Au layer or an Ag layer.

[0075] In some embodiments, the thickness of the second electrode layer is 250 nm to 5 μm. For example, it can be 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm, 1.9 μm, 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, 3 μm, 3.2 μm, 3.5 μm, 3.8 μm, 4 μm, 4.2 μm, 4.5 μm, 4.8 μm, or 5 μm, etc.

[0076] In some embodiments, the thickness of the p-type semiconductor layer is 100–600 nm (i.e., the thicknesses of both the first and second portions of the p-type semiconductor layer are within this range; the thicknesses of the first and second portions of the p-type semiconductor layer can be the same or different), for example, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, or 600 nm. The hole concentration in the p-type semiconductor layer is 10. 16 ~10 19 cm -3 .

[0077] In some embodiments, the p-type semiconductor layer includes at least one of p-type NiO, p-type Cu2O, p-type gallium oxide, and p-type diamond, but is not limited thereto.

[0078] In some embodiments, the thickness of the p-type semiconductor shielding ring is 100–600 nm, for example, it can be 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, or 600 nm. The hole concentration in the p-type semiconductor shielding ring is 10. 16 ~10 19 cm -3 .

[0079] In some embodiments, the p-type semiconductor shielding ring includes at least one of p-type NiO, p-type Cu2O, p-type gallium oxide, and p-type diamond, but is not limited thereto.

[0080] In some implementations, when the width of the p-type semiconductor layer is the same as the width of the first dielectric layer and the width of the p-type semiconductor shielding ring in the first direction of the horizontal plane, then in the direction perpendicular to the first direction on the horizontal plane:

[0081] The width of the first field plate is 3 to 20 μm, for example, it can be 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, 18 μm, 19 μm or 20 μm, etc.;

[0082] The width of the p-type semiconductor shielding ring is 3 to 10 μm, for example, it can be 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm or 10 μm.

[0083] Specifically, as Figure 1 Taking the structure shown as an example, the horizontal plane is the plane containing the front-back direction (the direction perpendicular to the paper) and the left-right direction. In the front-back direction, the width of the p-type semiconductor layer is the same as the width of the first dielectric layer and the width of the p-type semiconductor shielding ring. At this time, in the left-right direction, which is perpendicular to the front-back direction, the width L1 of the first field plate is 3 to 20 μm.

[0084] The width L2 of the p-type semiconductor shielding ring is 3 to 10 μm.

[0085] In some embodiments, the projection of the second electrode layer onto the gallium oxide epitaxial layer overlaps the projection of the p-type semiconductor layer onto the gallium oxide epitaxial layer; or, the projection of the second electrode layer onto the gallium oxide epitaxial layer coincides with the projection of the p-type semiconductor layer onto the gallium oxide epitaxial layer.

[0086] Specifically, such as Figure 1As shown, the rightmost end of the projection of the second electrode layer onto the gallium oxide epitaxial layer overlaps the rightmost end of the projection of the p-type semiconductor layer onto the gallium oxide epitaxial layer. This allows the second field plate to better suppress the electric field concentration on the surface of the first dielectric layer and the gallium oxide epitaxial layer below the edge of the first field plate.

[0087] Drawing on the working principle of field limiting ring structures in Si-based or SiC-based power devices, although guard ring structures of other p-type oxides (such as p-NiO) can be applied to gallium oxide-based power devices, in the blocking state, the guard ring provides holes to assist the expansion of the depletion layer in the termination region, suppressing the peak electric field in the termination region and improving the device's breakdown voltage. However, unlike Si or SiC, gallium oxide has a higher critical breakdown field strength, resulting in a higher electron concentration in the device's epitaxial layer at the same voltage level. To achieve good results, the size of the guard ring needs to be more precisely designed, and the spacing between adjacent guard rings also needs to be closer, typically less than 1 μm, thus increasing the difficulty of device fabrication. Based on this, in some specific embodiments of the present invention, the projection of the end of the second field plate away from the first field plate on the gallium oxide epitaxial layer is located in the projection of the p-type semiconductor shielding ring on the gallium oxide epitaxial layer. Specifically, as Figure 1 As shown, the projection of the rightmost end of the second field plate 81 onto the gallium oxide epitaxial layer 3 lies between the projections of the leftmost end of the p-type semiconductor shielding ring 6 onto the gallium oxide epitaxial layer 3 and the rightmost end of the p-type semiconductor shielding ring 6 onto the gallium oxide epitaxial layer 3. That is, the projection of the rightmost end of the second field plate 81 onto the p-type semiconductor shielding ring 6 lies between the leftmost and rightmost ends of the p-type semiconductor shielding ring. Thus, the second field plate structure promotes the depletion of the region between the p-type semiconductor layer and the p-type semiconductor shielding ring, allowing the p-type semiconductor layer and the p-type semiconductor shielding ring to still function well even with a large spacing, reducing the device's dependence on processing dimensions and improving device yield. In other words, the combination of the field plate structure and the shielding ring structure allows the shielding ring in the gallium oxide-based power device provided by this invention to still have excellent performance even with a wide ring spacing, thereby simplifying the device fabrication process. Simultaneously, the p-type semiconductor shielding ring can effectively shield the electric field peaks at the edge of the second field plate, suppressing premature breakdown and improving the device's withstand voltage capability.

[0088] Therefore, in some implementations, such as Figure 1 As shown, the distance L3 between the first field plate and the p-type semiconductor shielding ring is 2 to 10 μm, for example, it can be 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm or 10 μm, etc.

[0089] In some embodiments, the gallium oxide-based power device with a dielectric layer electric field shielding ring further includes:

[0090] Passivation layer 9 is continuously located on the surface of the second dielectric layer 7 and a portion of the surface of the second electrode layer 8.

[0091] The passivation layer can be configured according to actual needs.

[0092] In some embodiments, the material of the passivation layer includes at least one of polyimide (PI), silicon nitride, silicon oxide, and SU-8 adhesive.

[0093] This invention also provides a method for fabricating a gallium oxide-based power device with a dielectric layer electric field shielding ring as described above, wherein, as... Figure 2 As shown, it includes the following steps:

[0094] S1, such as Figure 2 As shown in (a), a gallium oxide substrate 2 is provided;

[0095] S2, such as Figure 2 As shown in (a), a gallium oxide epitaxial layer 3 is formed on the surface of the gallium oxide substrate 2;

[0096] S3, such as Figure 2 As shown in (c), a first dielectric layer 4 is formed on the surface of the gallium oxide epitaxial layer 3;

[0097] S4, such as Figure 2 As shown in (d), a p-type semiconductor layer 5 is formed on the surface of the gallium oxide epitaxial layer 3 and a portion of the surface of the first dielectric layer 4, and the portion of the p-type semiconductor layer 5 located on the surface of the first dielectric layer 4 is the first field plate 51; a p-type semiconductor shielding ring 6 is formed on the surface of the first dielectric layer 4 at a distance from the first field plate 51.

[0098] S5, such as Figure 2 As shown in (e), a second dielectric layer 7 is formed on the surface of the first dielectric layer 4, the surface of the p-type semiconductor shielding ring 6, and a portion of the surface of the first field plate 51.

[0099] S6, such as Figure 2 As shown in (f), a second electrode layer 8 is formed on the surface of the p-type semiconductor layer 5 and a portion of the surface of the second dielectric layer 7. The portion of the second electrode layer 8 located on the surface of the second dielectric layer 7 is the second field plate 81.

[0100] S7, such as Figure 2 As shown in (g), a passivation layer 9 is formed on the surface of the second dielectric layer 7 and a portion of the surface of the second electrode layer 8;

[0101] S8, such as Figure 2As shown in (h), a first electrode layer 1 is formed on the side of the gallium oxide substrate 2 away from the gallium oxide epitaxial layer 3 to obtain the gallium oxide-based power device with a dielectric layer electric field shielding ring.

[0102] In this invention, in steps S1 and S2, a gallium oxide substrate with a gallium oxide epitaxial layer on its surface can be directly provided, and then inorganic and organic cleaning can be performed before proceeding to the subsequent steps.

[0103] In step S1, the selection of the gallium oxide substrate is described above and will not be repeated here.

[0104] In step S2, the material and thickness of the gallium oxide epitaxial layer are as described above and will not be repeated here.

[0105] In step S3, the material and thickness of the first dielectric layer are as described above and will not be repeated here.

[0106] In some embodiments, the step of forming a first dielectric layer on the surface of the gallium oxide epitaxial layer specifically includes:

[0107] like Figure 2 As shown in (b), a first dielectric precursor layer 4' is formed on the surface of the gallium oxide epitaxial layer by a deposition method; wherein the deposition method includes, but is not limited to, one of plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), inductively coupled plasma chemical vapor deposition (ICPCVD), and magnetron sputtering.

[0108] like Figure 2 As shown in (c), photolithography is performed on the surface of the first dielectric layer precursor layer 4', and then the first dielectric layer precursor layer 4' is patterned by a combination of dry and wet etching or wet etching to obtain the first dielectric layer 4.

[0109] In step S4, the material and thickness of the p-type semiconductor layer are as described above and will not be repeated here.

[0110] In some embodiments, a deposition method (including but not limited to magnetron sputtering deposition, pulsed laser deposition, metal-organic chemical vapor deposition, metal thermal oxidation, etc.) can be used to form a p-type semiconductor layer precursor layer (see the case of the first dielectric precursor layer);

[0111] Then, the p-type semiconductor layer precursor layer is patterned by peeling or etching to obtain the p-type semiconductor layer and the p-type semiconductor shielding ring.

[0112] For example, when the materials of the p-type semiconductor layer and the p-type semiconductor shielding ring are p-type NiO, the p-type NiO precursor layer can be prepared by Ni metal thermal oxidation method.

[0113] In step S5, the material and thickness of the second dielectric layer are as described above and will not be repeated here.

[0114] The method for forming the second dielectric layer is the same as the method for forming the first dielectric layer.

[0115] In step S6, the material and thickness of the second electrode layer are as described above and will not be repeated here.

[0116] Specifically, the deposition is performed using electron beam evaporation or magnetron sputtering, and a second electrode layer is formed using a stripping process.

[0117] In step S7, the material of the passivation layer is as described above and will not be repeated here.

[0118] Specifically, when the passivation layer is made of PI, a standard PI photolithography process can be used to form the passivation layer.

[0119] In step S8, the material and thickness of the first electrode layer are as described above and will not be repeated here.

[0120] The method for forming the first electrode layer is the same as the method for forming the second electrode layer.

[0121] The present invention will be further described below through specific embodiments.

[0122] Example 1

[0123] This invention provides a gallium oxide-based power device with a dielectric layer electric field shielding ring. The gallium oxide-based power device includes a first electrode layer 1, a gallium oxide substrate 2, and a gallium oxide epitaxial layer 3, stacked sequentially from bottom to top. The first electrode layer includes a Ti layer (100 nm thick), a Ni layer (300 nm thick), and an Ag layer (1 μm thick), stacked sequentially, with the Ti layer side attached to the gallium oxide substrate. The gallium oxide substrate has a thickness of 500 μm and is a Sn-doped β-Ga₂O₃ substrate with an electron concentration of 10⁻⁶. 20 cm -3 The thickness of the gallium oxide epitaxial layer is 10 μm. The gallium oxide epitaxial layer is a Si-doped β-Ga₂O₃ epitaxial layer with an electron concentration of 10. 16 cm -3 ;

[0124] The gallium oxide-based power device with a dielectric layer electric field shielding ring further includes:

[0125] The first dielectric layer 4 is located on the surface of the gallium oxide epitaxial layer 3; the material of the first dielectric layer is silicon nitride (grown by PECVD), and the thickness of the first dielectric layer is 300 nm;

[0126] A p-type semiconductor layer 5 is continuously located on the surface of the gallium oxide epitaxial layer 3 and a portion of the surface of the first dielectric layer 4. The portion of the p-type semiconductor layer 5 located on the surface of the first dielectric layer 4 constitutes the first field plate 51. The thickness of the p-type semiconductor layer is 500 nm (i.e., the thickness of the second portion 52 of the p-type semiconductor layer and the first field plate 51 are both 500 nm; the thickness of the second portion 52 of the p-type semiconductor layer, where it connects to the first dielectric layer in the left-right direction, is also 500 nm in the left-right direction). The p-type semiconductor layer is a p-type NiO layer with a hole concentration of 10. 18 cm -3 The width L1 of the first field plate is 10 μm.

[0127] A p-type semiconductor shielding ring 6 is located on the surface of the first dielectric layer 4 and spaced apart from the first field plate 51; the thickness of the p-type semiconductor shielding ring is 500 nm and the width L2 is 5 μm; the p-type semiconductor shielding ring is a p-type NiO layer; the distance L3 between the first field plate and the p-type semiconductor shielding ring is 5 μm.

[0128] The second dielectric layer 7 is continuously located on the surface of the first dielectric layer 4, the surface of the p-type semiconductor shielding ring 6, and a portion of the surface of the first field plate 51. In the left-right direction, the first field plate is in contact with the portion of the second dielectric layer located on the surface of the first dielectric layer. The thickness of the portion of the second dielectric layer located on the surface of the first dielectric layer is 700 nm, and the thickness of the portions of the second dielectric layer located on the surface of the first field plate and on the p-type semiconductor shielding ring is 350 nm. The material of the second dielectric layer is silicon nitride (grown using PECVD).

[0129] The second electrode layer 8 is continuously located on the surface of the p-type semiconductor layer 5 and a portion of the surface of the second dielectric layer 7. The portion of the second electrode layer 8 located on the surface of the second dielectric layer 7 constitutes the second field plate 81. The material of the second electrode layer is a stacked Ni layer and an Al layer. The Ni layer is attached to the surface of the p-type semiconductor layer 5 and a portion of the surface of the second dielectric layer 7. The maximum thickness of the second electrode layer is 3.2 μm (where the thickness of the Ni layer is 200 nm and the thickness of the Al layer is 3 μm). The rightmost end of the projection of the second electrode layer onto the gallium oxide epitaxial layer is located at the middle position of the projection of the p-type semiconductor shielding ring onto the gallium oxide epitaxial layer.

[0130] Passivation layer 9 is located on the surface of the second dielectric layer 7 and part of the surface of the second electrode layer 8; the material of the passivation layer is PI, and the maximum thickness of the passivation layer is 10 μm.

[0131] Example 1 introduces a gallium oxide power device with a dielectric layer electric field shielding ring (without a passivation layer) and a gallium oxide-based power device with a conventional single-field plate structure terminal (its structural schematic is shown in Figure 1). Figure 3 As shown, it includes, from bottom to top, a first electrode layer 1, a gallium oxide substrate 2, a gallium oxide epitaxial layer 3, and a first dielectric layer 4, and further includes a p-type semiconductor layer 5 located on the surface of the gallium oxide epitaxial layer 3 and a portion of the surface of the first dielectric layer 4, a second electrode layer 8 located on the surface of the first dielectric layer 4 and the surface of the p-type semiconductor layer 5, the portion of the p-type semiconductor layer 5 located on the surface of the first dielectric layer 4 being a field plate, and the materials of each layer being the same as in Embodiment 1), a gallium oxide-based power device with a dual field plate structure terminal (its structural schematic diagram is shown in Figure 1). Figure 4 As shown, it includes, from bottom to top, a first electrode layer 1, a gallium oxide substrate 2, a gallium oxide epitaxial layer 3, and a first dielectric layer 4, and further includes a p-type semiconductor layer 5 located on the surface of the gallium oxide epitaxial layer 3 and a portion of the surface of the first dielectric layer 4, a second dielectric layer 7 located on the surfaces of the first dielectric layer 4 and the p-type semiconductor layer 5, and a second electrode layer 8 located on the surface of the p-type semiconductor layer 5 and a portion of the surface of the second dielectric layer 7. The portion of the p-type semiconductor layer 5 located on the surface of the first dielectric layer 4 is the first field plate, and the portion of the second electrode layer 8 located on the surface of the second dielectric layer 7 is the second field plate. (The materials of each layer are the same as in Example 1.) The surface electric field distribution diagram during breakdown is shown below. Figure 5 and 6 As shown. Figure 5 As shown, compared to gallium oxide-based power devices with conventional single-field-plate structure terminals and gallium oxide-based power devices with dual-field-plate structure terminals, the terminal structure in Example 1 can achieve a more uniform electric field distribution, thus enabling a higher breakdown voltage. Figure 6The two-dimensional electric field distributions during breakdown of three terminal structures are shown. It can be seen that the maximum electric field of gallium oxide (GaO) material during breakdown in single-field plate and dual-field plate terminal structures does not reach its critical breakdown electric field (~8 MV), thus failing to fully utilize the application advantages of GaO material's high critical breakdown electric field. However, in the structure of the GaO-based power device provided in Embodiment 1 of this invention, the highest electric field within GaO reaches its critical breakdown field strength during breakdown, thus fully utilizing the material's advantages. Furthermore, it can be seen that for the single-field plate terminal structure, the electric field within the dielectric layer reaches approximately 12 MV / cm during breakdown (the breakdown electric field of PECVD-grown silicon nitride is approximately 11.6 MV / cm), while the highest electric field within GaO is only 3 MV / cm. For the dual-field plate terminal structure, the electric field within the dielectric layer (11.75 MV / cm) also reaches its critical breakdown electric field during breakdown, while the electric field within GaO is much smaller than its critical breakdown field strength. Regarding the structure of the gallium oxide-based power device provided in Embodiment 1 of the present invention, during breakdown, gallium oxide reaches its critical breakdown electric field, while the maximum electric field within the dielectric layer (11.48 MV / cm) is less than its breakdown electric field (11.6 MV / cm). Therefore, this fully demonstrates that the structure provided by the present invention can achieve effective dielectric layer electric field shielding, thereby improving the breakdown voltage of the device.

[0132] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A gallium oxide-based power device having a dielectric layer electric field shield ring, characterized by, The gallium oxide-based power device with a dielectric layer field shielding ring comprises, from bottom to top, a first electrode layer, a gallium oxide substrate and a gallium oxide epitaxial layer; The gallium oxide-based power device with a dielectric layer field shielding ring further comprises: a first dielectric layer on the surface of the gallium oxide epitaxial layer; a p-type semiconductor layer continuously on the surface of the gallium oxide epitaxial layer and part of the surface of the first dielectric layer, the part of the p-type semiconductor layer on the surface of the first dielectric layer being a first field plate; a p-type semiconductor shielding ring on the surface of the first dielectric layer and spaced apart from the first field plate; a second dielectric layer continuously on the surface of the first dielectric layer, the surface of the p-type semiconductor shielding ring and part of the surface of the first field plate; a second electrode layer continuously on the surface of the p-type semiconductor layer and part of the surface of the second dielectric layer, the part of the second electrode layer on the surface of the second dielectric layer being a second field plate.

2. The gallium oxide based power device with dielectric layer electric field shield ring of claim 1, wherein, The thickness of the gallium oxide substrate is 50-650 μm; The gallium oxide substrate is a high-doped n-type gallium oxide substrate, and the doping concentration is 10 18 10 20 cm -3 ; The thickness of the gallium oxide epitaxial layer is 2-20 μm; The gallium oxide epitaxial layer is a low-doped n-type gallium oxide epitaxial layer, and the doping concentration is 10 15 ~10 17 cm -3 .

3. The gallium oxide based power device with dielectric layer electric field shield ring of claim 1, wherein, The thickness of the first dielectric layer is 100 nm-1 μm; the material of the first dielectric layer comprises at least one of silicon oxide, silicon nitride, aluminum oxide and hafnium dioxide; The thickness of the second dielectric layer is 300 nm-2 μm; the material of the second dielectric layer comprises at least one of silicon oxide, silicon nitride, aluminum oxide and hafnium dioxide.

4. The gallium oxide based power device with dielectric layer electric field shield ring of claim 1, wherein, The material of the first electrode layer comprises at least one of Ti, Ni, Ag and Au; The material of the second electrode layer includes at least one of Ni, Mo, W, Pt, PtO x , Al, Au, and Ag.

5. The gallium oxide based power device with dielectric layer electric field shield ring of claim 1, wherein, The thickness of the p-type semiconductor layer is 100-600 nm; the p-type semiconductor layer comprises at least one of p-type NiO, p-type Cu2O, p-type gallium oxide and p-type diamond; The thickness of the p-type semiconductor shielding ring is 100-600 nm; the p-type semiconductor shielding ring comprises at least one of p-type NiO, p-type Cu2O, p-type gallium oxide and p-type diamond.

6. The gallium oxide based power device with dielectric layer electric field shield ring of claim 1, wherein, The distance between the first field plate and the p-type semiconductor shielding ring is 2-10 μm.

7. The gallium oxide based power device with dielectric layer electric field shield ring of claim 1, wherein, When the width of the p-type semiconductor layer is the same as the width of the first dielectric layer and the width of the p-type semiconductor shielding ring in the first direction of the horizontal plane, the width of the first field plate is 3-20 μm and the width of the p-type semiconductor shielding ring is 3-10 μm in the direction perpendicular to the first direction on the horizontal plane. The projection of the second electrode layer on the gallium oxide epitaxial layer covers the projection of the p-type semiconductor layer on the gallium oxide epitaxial layer; or, the projection of the second electrode layer on the gallium oxide epitaxial layer coincides with the projection of the p-type semiconductor layer on the gallium oxide epitaxial layer. The projection of the end of the second field plate away from the first field plate on the gallium oxide epitaxial layer is located in the projection of the p-type semiconductor shielding ring on the gallium oxide epitaxial layer.

8. The gallium oxide based power device with dielectric layer electric field shield ring of claim 1, wherein, The gallium oxide-based power device with a dielectric layer field shielding ring further comprises:

9. The gallium oxide based power device with dielectric layer electric field shield ring of claim 8, wherein, a passivation layer continuously on the surface of the second dielectric layer and part of the surface of the second electrode layer. The method comprises the following steps: providing a gallium oxide substrate; 10. A method of fabricating a gallium oxide-based power device with a dielectric layer electric field shield ring as claimed in claim 1, characterized in that, ​ ​ forming a gallium oxide epitaxial layer on a surface of the gallium oxide substrate; forming a first dielectric layer on a surface of the gallium oxide epitaxial layer; forming a p-type semiconductor layer on a surface of the gallium oxide epitaxial layer and on a part of the surface of the first dielectric layer, the p-type semiconductor layer on the part of the surface of the first dielectric layer being a first field plate; forming a p-type semiconductor shielding ring spaced apart from the first field plate on a surface of the first dielectric layer; forming a second dielectric layer on a surface of the first dielectric layer, on a surface of the p-type semiconductor shielding ring, and on a part of the surface of the first field plate; forming a second electrode layer on a surface of the p-type semiconductor layer and on a part of the surface of the second dielectric layer, the second electrode layer on the part of the surface of the second dielectric layer being a second field plate; forming a first electrode layer on a side of the gallium oxide substrate away from the gallium oxide epitaxial layer, to obtain the gallium oxide-based power device with a dielectric layer electric field shielding ring.

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